drivers/common/cnxk/roc_nix_debug.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(C) 2021 Marvell.
   3  */
   4
   5 #include "roc_api.h"
   6 #include "roc_priv.h"
   7
   8 #define nix_dump(fmt, ...) fprintf(stderr, fmt "\n", ##__VA_ARGS__)
   9 #define NIX_REG_INFO(reg)                                                      \
  10         {                                                                      \
  11                 reg, #reg                                                      \
  12         }
  13 #define NIX_REG_NAME_SZ 48
  14
  15 #define nix_dump_no_nl(fmt, ...) fprintf(stderr, fmt, ##__VA_ARGS__)
  16
  17 struct nix_lf_reg_info {
  18         uint32_t offset;
  19         const char *name;
  20 };
  21
  22 static const struct nix_lf_reg_info nix_lf_reg[] = {
  23         NIX_REG_INFO(NIX_LF_RX_SECRETX(0)),
  24         NIX_REG_INFO(NIX_LF_RX_SECRETX(1)),
  25         NIX_REG_INFO(NIX_LF_RX_SECRETX(2)),
  26         NIX_REG_INFO(NIX_LF_RX_SECRETX(3)),
  27         NIX_REG_INFO(NIX_LF_RX_SECRETX(4)),
  28         NIX_REG_INFO(NIX_LF_RX_SECRETX(5)),
  29         NIX_REG_INFO(NIX_LF_CFG),
  30         NIX_REG_INFO(NIX_LF_GINT),
  31         NIX_REG_INFO(NIX_LF_GINT_W1S),
  32         NIX_REG_INFO(NIX_LF_GINT_ENA_W1C),
  33         NIX_REG_INFO(NIX_LF_GINT_ENA_W1S),
  34         NIX_REG_INFO(NIX_LF_ERR_INT),
  35         NIX_REG_INFO(NIX_LF_ERR_INT_W1S),
  36         NIX_REG_INFO(NIX_LF_ERR_INT_ENA_W1C),
  37         NIX_REG_INFO(NIX_LF_ERR_INT_ENA_W1S),
  38         NIX_REG_INFO(NIX_LF_RAS),
  39         NIX_REG_INFO(NIX_LF_RAS_W1S),
  40         NIX_REG_INFO(NIX_LF_RAS_ENA_W1C),
  41         NIX_REG_INFO(NIX_LF_RAS_ENA_W1S),
  42         NIX_REG_INFO(NIX_LF_SQ_OP_ERR_DBG),
  43         NIX_REG_INFO(NIX_LF_MNQ_ERR_DBG),
  44         NIX_REG_INFO(NIX_LF_SEND_ERR_DBG),
  45 };
  46
  47 static void
  48 nix_bitmap_dump(struct plt_bitmap *bmp)
  49 {
  50         uint32_t pos = 0, start_pos;
  51         uint64_t slab = 0;
  52         int i;
  53
  54         plt_bitmap_scan_init(bmp);
  55         plt_bitmap_scan(bmp, &pos, &slab);
  56         start_pos = pos;
  57
  58         nix_dump_no_nl("  \t\t[");
  59         do {
  60                 if (!slab)
  61                         break;
  62                 i = 0;
  63
  64                 for (i = 0; i < 64; i++)
  65                         if (slab & (1ULL << i))
  66                                 nix_dump_no_nl("%d, ", i);
  67
  68                 if (!plt_bitmap_scan(bmp, &pos, &slab))
  69                         break;
  70         } while (start_pos != pos);
  71         nix_dump_no_nl(" ]");
  72 }
  73
  74 int
  75 roc_nix_lf_get_reg_count(struct roc_nix *roc_nix)
  76 {
  77         struct nix *nix = roc_nix_to_nix_priv(roc_nix);
  78         int reg_count;
  79
  80         if (roc_nix == NULL)
  81                 return NIX_ERR_PARAM;
  82
  83         reg_count = PLT_DIM(nix_lf_reg);
  84         /* NIX_LF_TX_STATX */
  85         reg_count += nix->lf_tx_stats;
  86         /* NIX_LF_RX_STATX */
  87         reg_count += nix->lf_rx_stats;
  88         /* NIX_LF_QINTX_CNT*/
  89         reg_count += nix->qints;
  90         /* NIX_LF_QINTX_INT */
  91         reg_count += nix->qints;
  92         /* NIX_LF_QINTX_ENA_W1S */
  93         reg_count += nix->qints;
  94         /* NIX_LF_QINTX_ENA_W1C */
  95         reg_count += nix->qints;
  96         /* NIX_LF_CINTX_CNT */
  97         reg_count += nix->cints;
  98         /* NIX_LF_CINTX_WAIT */
  99         reg_count += nix->cints;
 100         /* NIX_LF_CINTX_INT */
 101         reg_count += nix->cints;
 102         /* NIX_LF_CINTX_INT_W1S */
 103         reg_count += nix->cints;
 104         /* NIX_LF_CINTX_ENA_W1S */
 105         reg_count += nix->cints;
 106         /* NIX_LF_CINTX_ENA_W1C */
 107         reg_count += nix->cints;
 108
 109         return reg_count;
 110 }
 111
 112 int
 113 nix_lf_gen_reg_dump(uintptr_t nix_lf_base, uint64_t *data)
 114 {
 115         bool dump_stdout;
 116         uint64_t reg;
 117         uint32_t i;
 118
 119         dump_stdout = data ? 0 : 1;
 120
 121         for (i = 0; i < PLT_DIM(nix_lf_reg); i++) {
 122                 reg = plt_read64(nix_lf_base + nix_lf_reg[i].offset);
 123                 if (dump_stdout && reg)
 124                         nix_dump("%32s = 0x%" PRIx64, nix_lf_reg[i].name, reg);
 125                 if (data)
 126                         *data++ = reg;
 127         }
 128
 129         return i;
 130 }
 131
 132 int
 133 nix_lf_stat_reg_dump(uintptr_t nix_lf_base, uint64_t *data, uint8_t lf_tx_stats,
 134                      uint8_t lf_rx_stats)
 135 {
 136         uint32_t i, count = 0;
 137         bool dump_stdout;
 138         uint64_t reg;
 139
 140         dump_stdout = data ? 0 : 1;
 141
 142         /* NIX_LF_TX_STATX */
 143         for (i = 0; i < lf_tx_stats; i++) {
 144                 reg = plt_read64(nix_lf_base + NIX_LF_TX_STATX(i));
 145                 if (dump_stdout && reg)
 146                         nix_dump("%32s_%d = 0x%" PRIx64, "NIX_LF_TX_STATX", i,
 147                                  reg);
 148                 if (data)
 149                         *data++ = reg;
 150         }
 151         count += i;
 152
 153         /* NIX_LF_RX_STATX */
 154         for (i = 0; i < lf_rx_stats; i++) {
 155                 reg = plt_read64(nix_lf_base + NIX_LF_RX_STATX(i));
 156                 if (dump_stdout && reg)
 157                         nix_dump("%32s_%d = 0x%" PRIx64, "NIX_LF_RX_STATX", i,
 158                                  reg);
 159                 if (data)
 160                         *data++ = reg;
 161         }
 162
 163         return count + i;
 164 }
 165
 166 int
 167 nix_lf_int_reg_dump(uintptr_t nix_lf_base, uint64_t *data, uint16_t qints,
 168                     uint16_t cints)
 169 {
 170         uint32_t i, count = 0;
 171         bool dump_stdout;
 172         uint64_t reg;
 173
 174         dump_stdout = data ? 0 : 1;
 175
 176         /* NIX_LF_QINTX_CNT*/
 177         for (i = 0; i < qints; i++) {
 178                 reg = plt_read64(nix_lf_base + NIX_LF_QINTX_CNT(i));
 179                 if (dump_stdout && reg)
 180                         nix_dump("%32s_%d = 0x%" PRIx64, "NIX_LF_QINTX_CNT", i,
 181                                  reg);
 182                 if (data)
 183                         *data++ = reg;
 184         }
 185         count += i;
 186
 187         /* NIX_LF_QINTX_INT */
 188         for (i = 0; i < qints; i++) {
 189                 reg = plt_read64(nix_lf_base + NIX_LF_QINTX_INT(i));
 190                 if (dump_stdout && reg)
 191                         nix_dump("%32s_%d = 0x%" PRIx64, "NIX_LF_QINTX_INT", i,
 192                                  reg);
 193                 if (data)
 194                         *data++ = reg;
 195         }
 196         count += i;
 197
 198         /* NIX_LF_QINTX_ENA_W1S */
 199         for (i = 0; i < qints; i++) {
 200                 reg = plt_read64(nix_lf_base + NIX_LF_QINTX_ENA_W1S(i));
 201                 if (dump_stdout && reg)
 202                         nix_dump("%32s_%d = 0x%" PRIx64, "NIX_LF_QINTX_ENA_W1S",
 203                                  i, reg);
 204                 if (data)
 205                         *data++ = reg;
 206         }
 207         count += i;
 208
 209         /* NIX_LF_QINTX_ENA_W1C */
 210         for (i = 0; i < qints; i++) {
 211                 reg = plt_read64(nix_lf_base + NIX_LF_QINTX_ENA_W1C(i));
 212                 if (dump_stdout && reg)
 213                         nix_dump("%32s_%d = 0x%" PRIx64, "NIX_LF_QINTX_ENA_W1C",
 214                                  i, reg);
 215                 if (data)
 216                         *data++ = reg;
 217         }
 218         count += i;
 219
 220         /* NIX_LF_CINTX_CNT */
 221         for (i = 0; i < cints; i++) {
 222                 reg = plt_read64(nix_lf_base + NIX_LF_CINTX_CNT(i));
 223                 if (dump_stdout && reg)
 224                         nix_dump("%32s_%d = 0x%" PRIx64, "NIX_LF_CINTX_CNT", i,
 225                                  reg);
 226                 if (data)
 227                         *data++ = reg;
 228         }
 229         count += i;
 230
 231         /* NIX_LF_CINTX_WAIT */
 232         for (i = 0; i < cints; i++) {
 233                 reg = plt_read64(nix_lf_base + NIX_LF_CINTX_WAIT(i));
 234                 if (dump_stdout && reg)
 235                         nix_dump("%32s_%d = 0x%" PRIx64, "NIX_LF_CINTX_WAIT", i,
 236                                  reg);
 237                 if (data)
 238                         *data++ = reg;
 239         }
 240         count += i;
 241
 242         /* NIX_LF_CINTX_INT */
 243         for (i = 0; i < cints; i++) {
 244                 reg = plt_read64(nix_lf_base + NIX_LF_CINTX_INT(i));
 245                 if (dump_stdout && reg)
 246                         nix_dump("%32s_%d = 0x%" PRIx64, "NIX_LF_CINTX_INT", i,
 247                                  reg);
 248                 if (data)
 249                         *data++ = reg;
 250         }
 251         count += i;
 252
 253         /* NIX_LF_CINTX_INT_W1S */
 254         for (i = 0; i < cints; i++) {
 255                 reg = plt_read64(nix_lf_base + NIX_LF_CINTX_INT_W1S(i));
 256                 if (dump_stdout && reg)
 257                         nix_dump("%32s_%d = 0x%" PRIx64, "NIX_LF_CINTX_INT_W1S",
 258                                  i, reg);
 259                 if (data)
 260                         *data++ = reg;
 261         }
 262         count += i;
 263
 264         /* NIX_LF_CINTX_ENA_W1S */
 265         for (i = 0; i < cints; i++) {
 266                 reg = plt_read64(nix_lf_base + NIX_LF_CINTX_ENA_W1S(i));
 267                 if (dump_stdout && reg)
 268                         nix_dump("%32s_%d = 0x%" PRIx64, "NIX_LF_CINTX_ENA_W1S",
 269                                  i, reg);
 270                 if (data)
 271                         *data++ = reg;
 272         }
 273         count += i;
 274
 275         /* NIX_LF_CINTX_ENA_W1C */
 276         for (i = 0; i < cints; i++) {
 277                 reg = plt_read64(nix_lf_base + NIX_LF_CINTX_ENA_W1C(i));
 278                 if (dump_stdout && reg)
 279                         nix_dump("%32s_%d = 0x%" PRIx64, "NIX_LF_CINTX_ENA_W1C",
 280                                  i, reg);
 281                 if (data)
 282                         *data++ = reg;
 283         }
 284
 285         return count + i;
 286 }
 287
 288 int
 289 roc_nix_lf_reg_dump(struct roc_nix *roc_nix, uint64_t *data)
 290 {
 291         struct nix *nix = roc_nix_to_nix_priv(roc_nix);
 292         bool dump_stdout = data ? 0 : 1;
 293         uintptr_t nix_base;
 294         uint32_t i;
 295
 296         if (roc_nix == NULL)
 297                 return NIX_ERR_PARAM;
 298
 299         nix_base = nix->base;
 300         /* General registers */
 301         i = nix_lf_gen_reg_dump(nix_base, data);
 302
 303         /* Rx, Tx stat registers */
 304         i += nix_lf_stat_reg_dump(nix_base, dump_stdout ? NULL : &data[i],
 305                                   nix->lf_tx_stats, nix->lf_rx_stats);
 306
 307         /* Intr registers */
 308         i += nix_lf_int_reg_dump(nix_base, dump_stdout ? NULL : &data[i],
 309                                  nix->qints, nix->cints);
 310
 311         return 0;
 312 }
 313
 314 int
 315 nix_q_ctx_get(struct dev *dev, uint8_t ctype, uint16_t qid, __io void **ctx_p)
 316 {
 317         struct mbox *mbox = dev->mbox;
 318         int rc;
 319
 320         if (roc_model_is_cn9k()) {
 321                 struct nix_aq_enq_rsp *rsp;
 322                 struct nix_aq_enq_req *aq;
 323                 int rc;
 324
 325                 aq = mbox_alloc_msg_nix_aq_enq(mbox);
 326                 aq->qidx = qid;
 327                 aq->ctype = ctype;
 328                 aq->op = NIX_AQ_INSTOP_READ;
 329
 330                 rc = mbox_process_msg(mbox, (void *)&rsp);
 331                 if (rc)
 332                         return rc;
 333                 if (ctype == NIX_AQ_CTYPE_RQ)
 334                         *ctx_p = &rsp->rq;
 335                 else if (ctype == NIX_AQ_CTYPE_SQ)
 336                         *ctx_p = &rsp->sq;
 337                 else
 338                         *ctx_p = &rsp->cq;
 339         } else {
 340                 struct nix_cn10k_aq_enq_rsp *rsp;
 341                 struct nix_cn10k_aq_enq_req *aq;
 342
 343                 aq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);
 344                 aq->qidx = qid;
 345                 aq->ctype = ctype;
 346                 aq->op = NIX_AQ_INSTOP_READ;
 347
 348                 rc = mbox_process_msg(mbox, (void *)&rsp);
 349                 if (rc)
 350                         return rc;
 351
 352                 if (ctype == NIX_AQ_CTYPE_RQ)
 353                         *ctx_p = &rsp->rq;
 354                 else if (ctype == NIX_AQ_CTYPE_SQ)
 355                         *ctx_p = &rsp->sq;
 356                 else
 357                         *ctx_p = &rsp->cq;
 358         }
 359         return 0;
 360 }
 361
 362 static inline void
 363 nix_cn9k_lf_sq_dump(__io struct nix_sq_ctx_s *ctx, uint32_t *sqb_aura_p)
 364 {
 365         nix_dump("W0: sqe_way_mask \t\t%d\nW0: cq \t\t\t\t%d",
 366                  ctx->sqe_way_mask, ctx->cq);
 367         nix_dump("W0: sdp_mcast \t\t\t%d\nW0: substream \t\t\t0x%03x",
 368                  ctx->sdp_mcast, ctx->substream);
 369         nix_dump("W0: qint_idx \t\t\t%d\nW0: ena \t\t\t%d\n", ctx->qint_idx,
 370                  ctx->ena);
 371
 372         nix_dump("W1: sqb_count \t\t\t%d\nW1: default_chan \t\t%d",
 373                  ctx->sqb_count, ctx->default_chan);
 374         nix_dump("W1: smq_rr_quantum \t\t%d\nW1: sso_ena \t\t\t%d",
 375                  ctx->smq_rr_quantum, ctx->sso_ena);
 376         nix_dump("W1: xoff \t\t\t%d\nW1: cq_ena \t\t\t%d\nW1: smq\t\t\t\t%d\n",
 377                  ctx->xoff, ctx->cq_ena, ctx->smq);
 378
 379         nix_dump("W2: sqe_stype \t\t\t%d\nW2: sq_int_ena \t\t\t%d",
 380                  ctx->sqe_stype, ctx->sq_int_ena);
 381         nix_dump("W2: sq_int  \t\t\t%d\nW2: sqb_aura \t\t\t%d", ctx->sq_int,
 382                  ctx->sqb_aura);
 383         nix_dump("W2: smq_rr_count \t\t%d\n", ctx->smq_rr_count);
 384
 385         nix_dump("W3: smq_next_sq_vld\t\t%d\nW3: smq_pend\t\t\t%d",
 386                  ctx->smq_next_sq_vld, ctx->smq_pend);
 387         nix_dump("W3: smenq_next_sqb_vld  \t%d\nW3: head_offset\t\t\t%d",
 388                  ctx->smenq_next_sqb_vld, ctx->head_offset);
 389         nix_dump("W3: smenq_offset\t\t%d\nW3: tail_offset \t\t%d",
 390                  ctx->smenq_offset, ctx->tail_offset);
 391         nix_dump("W3: smq_lso_segnum \t\t%d\nW3: smq_next_sq \t\t%d",
 392                  ctx->smq_lso_segnum, ctx->smq_next_sq);
 393         nix_dump("W3: mnq_dis \t\t\t%d\nW3: lmt_dis \t\t\t%d", ctx->mnq_dis,
 394                  ctx->lmt_dis);
 395         nix_dump("W3: cq_limit\t\t\t%d\nW3: max_sqe_size\t\t%d\n",
 396                  ctx->cq_limit, ctx->max_sqe_size);
 397
 398         nix_dump("W4: next_sqb \t\t\t0x%" PRIx64 "", ctx->next_sqb);
 399         nix_dump("W5: tail_sqb \t\t\t0x%" PRIx64 "", ctx->tail_sqb);
 400         nix_dump("W6: smenq_sqb \t\t\t0x%" PRIx64 "", ctx->smenq_sqb);
 401         nix_dump("W7: smenq_next_sqb \t\t0x%" PRIx64 "", ctx->smenq_next_sqb);
 402         nix_dump("W8: head_sqb \t\t\t0x%" PRIx64 "", ctx->head_sqb);
 403
 404         nix_dump("W9: vfi_lso_vld \t\t%d\nW9: vfi_lso_vlan1_ins_ena\t%d",
 405                  ctx->vfi_lso_vld, ctx->vfi_lso_vlan1_ins_ena);
 406         nix_dump("W9: vfi_lso_vlan0_ins_ena\t%d\nW9: vfi_lso_mps\t\t\t%d",
 407                  ctx->vfi_lso_vlan0_ins_ena, ctx->vfi_lso_mps);
 408         nix_dump("W9: vfi_lso_sb \t\t\t%d\nW9: vfi_lso_sizem1\t\t%d",
 409                  ctx->vfi_lso_sb, ctx->vfi_lso_sizem1);
 410         nix_dump("W9: vfi_lso_total\t\t%d", ctx->vfi_lso_total);
 411
 412         nix_dump("W10: scm_lso_rem \t\t0x%" PRIx64 "",
 413                  (uint64_t)ctx->scm_lso_rem);
 414         nix_dump("W11: octs \t\t\t0x%" PRIx64 "", (uint64_t)ctx->octs);
 415         nix_dump("W12: pkts \t\t\t0x%" PRIx64 "", (uint64_t)ctx->pkts);
 416         nix_dump("W14: dropped_octs \t\t0x%" PRIx64 "",
 417                  (uint64_t)ctx->drop_octs);
 418         nix_dump("W15: dropped_pkts \t\t0x%" PRIx64 "",
 419                  (uint64_t)ctx->drop_pkts);
 420
 421         *sqb_aura_p = ctx->sqb_aura;
 422 }
 423
 424 static inline void
 425 nix_lf_sq_dump(__io struct nix_cn10k_sq_ctx_s *ctx, uint32_t *sqb_aura_p)
 426 {
 427         nix_dump("W0: sqe_way_mask \t\t%d\nW0: cq \t\t\t\t%d",
 428                  ctx->sqe_way_mask, ctx->cq);
 429         nix_dump("W0: sdp_mcast \t\t\t%d\nW0: substream \t\t\t0x%03x",
 430                  ctx->sdp_mcast, ctx->substream);
 431         nix_dump("W0: qint_idx \t\t\t%d\nW0: ena \t\t\t%d\n", ctx->qint_idx,
 432                  ctx->ena);
 433
 434         nix_dump("W1: sqb_count \t\t\t%d\nW1: default_chan \t\t%d",
 435                  ctx->sqb_count, ctx->default_chan);
 436         nix_dump("W1: smq_rr_weight \t\t%d\nW1: sso_ena \t\t\t%d",
 437                  ctx->smq_rr_weight, ctx->sso_ena);
 438         nix_dump("W1: xoff \t\t\t%d\nW1: cq_ena \t\t\t%d\nW1: smq\t\t\t\t%d\n",
 439                  ctx->xoff, ctx->cq_ena, ctx->smq);
 440
 441         nix_dump("W2: sqe_stype \t\t\t%d\nW2: sq_int_ena \t\t\t%d",
 442                  ctx->sqe_stype, ctx->sq_int_ena);
 443         nix_dump("W2: sq_int  \t\t\t%d\nW2: sqb_aura \t\t\t%d", ctx->sq_int,
 444                  ctx->sqb_aura);
 445         nix_dump("W2: smq_rr_count[ub:lb] \t\t%x:%x\n", ctx->smq_rr_count_ub,
 446                  ctx->smq_rr_count_lb);
 447
 448         nix_dump("W3: smq_next_sq_vld\t\t%d\nW3: smq_pend\t\t\t%d",
 449                  ctx->smq_next_sq_vld, ctx->smq_pend);
 450         nix_dump("W3: smenq_next_sqb_vld  \t%d\nW3: head_offset\t\t\t%d",
 451                  ctx->smenq_next_sqb_vld, ctx->head_offset);
 452         nix_dump("W3: smenq_offset\t\t%d\nW3: tail_offset \t\t%d",
 453                  ctx->smenq_offset, ctx->tail_offset);
 454         nix_dump("W3: smq_lso_segnum \t\t%d\nW3: smq_next_sq \t\t%d",
 455                  ctx->smq_lso_segnum, ctx->smq_next_sq);
 456         nix_dump("W3: mnq_dis \t\t\t%d\nW3: lmt_dis \t\t\t%d", ctx->mnq_dis,
 457                  ctx->lmt_dis);
 458         nix_dump("W3: cq_limit\t\t\t%d\nW3: max_sqe_size\t\t%d\n",
 459                  ctx->cq_limit, ctx->max_sqe_size);
 460
 461         nix_dump("W4: next_sqb \t\t\t0x%" PRIx64 "", ctx->next_sqb);
 462         nix_dump("W5: tail_sqb \t\t\t0x%" PRIx64 "", ctx->tail_sqb);
 463         nix_dump("W6: smenq_sqb \t\t\t0x%" PRIx64 "", ctx->smenq_sqb);
 464         nix_dump("W7: smenq_next_sqb \t\t0x%" PRIx64 "", ctx->smenq_next_sqb);
 465         nix_dump("W8: head_sqb \t\t\t0x%" PRIx64 "", ctx->head_sqb);
 466
 467         nix_dump("W9: vfi_lso_vld \t\t%d\nW9: vfi_lso_vlan1_ins_ena\t%d",
 468                  ctx->vfi_lso_vld, ctx->vfi_lso_vlan1_ins_ena);
 469         nix_dump("W9: vfi_lso_vlan0_ins_ena\t%d\nW9: vfi_lso_mps\t\t\t%d",
 470                  ctx->vfi_lso_vlan0_ins_ena, ctx->vfi_lso_mps);
 471         nix_dump("W9: vfi_lso_sb \t\t\t%d\nW9: vfi_lso_sizem1\t\t%d",
 472                  ctx->vfi_lso_sb, ctx->vfi_lso_sizem1);
 473         nix_dump("W9: vfi_lso_total\t\t%d", ctx->vfi_lso_total);
 474
 475         nix_dump("W10: scm_lso_rem \t\t0x%" PRIx64 "",
 476                  (uint64_t)ctx->scm_lso_rem);
 477         nix_dump("W11: octs \t\t\t0x%" PRIx64 "", (uint64_t)ctx->octs);
 478         nix_dump("W12: pkts \t\t\t0x%" PRIx64 "", (uint64_t)ctx->pkts);
 479         nix_dump("W14: dropped_octs \t\t0x%" PRIx64 "",
 480                  (uint64_t)ctx->drop_octs);
 481         nix_dump("W15: dropped_pkts \t\t0x%" PRIx64 "",
 482                  (uint64_t)ctx->drop_pkts);
 483
 484         *sqb_aura_p = ctx->sqb_aura;
 485 }
 486
 487 static inline void
 488 nix_cn9k_lf_rq_dump(__io struct nix_rq_ctx_s *ctx)
 489 {
 490         nix_dump("W0: wqe_aura \t\t\t%d\nW0: substream \t\t\t0x%03x",
 491                  ctx->wqe_aura, ctx->substream);
 492         nix_dump("W0: cq \t\t\t\t%d\nW0: ena_wqwd \t\t\t%d", ctx->cq,
 493                  ctx->ena_wqwd);
 494         nix_dump("W0: ipsech_ena \t\t\t%d\nW0: sso_ena \t\t\t%d",
 495                  ctx->ipsech_ena, ctx->sso_ena);
 496         nix_dump("W0: ena \t\t\t%d\n", ctx->ena);
 497
 498         nix_dump("W1: lpb_drop_ena \t\t%d\nW1: spb_drop_ena \t\t%d",
 499                  ctx->lpb_drop_ena, ctx->spb_drop_ena);
 500         nix_dump("W1: xqe_drop_ena \t\t%d\nW1: wqe_caching \t\t%d",
 501                  ctx->xqe_drop_ena, ctx->wqe_caching);
 502         nix_dump("W1: pb_caching \t\t\t%d\nW1: sso_tt \t\t\t%d",
 503                  ctx->pb_caching, ctx->sso_tt);
 504         nix_dump("W1: sso_grp \t\t\t%d\nW1: lpb_aura \t\t\t%d", ctx->sso_grp,
 505                  ctx->lpb_aura);
 506         nix_dump("W1: spb_aura \t\t\t%d\n", ctx->spb_aura);
 507
 508         nix_dump("W2: xqe_hdr_split \t\t%d\nW2: xqe_imm_copy \t\t%d",
 509                  ctx->xqe_hdr_split, ctx->xqe_imm_copy);
 510         nix_dump("W2: xqe_imm_size \t\t%d\nW2: later_skip \t\t\t%d",
 511                  ctx->xqe_imm_size, ctx->later_skip);
 512         nix_dump("W2: first_skip \t\t\t%d\nW2: lpb_sizem1 \t\t\t%d",
 513                  ctx->first_skip, ctx->lpb_sizem1);
 514         nix_dump("W2: spb_ena \t\t\t%d\nW2: wqe_skip \t\t\t%d", ctx->spb_ena,
 515                  ctx->wqe_skip);
 516         nix_dump("W2: spb_sizem1 \t\t\t%d\n", ctx->spb_sizem1);
 517
 518         nix_dump("W3: spb_pool_pass \t\t%d\nW3: spb_pool_drop \t\t%d",
 519                  ctx->spb_pool_pass, ctx->spb_pool_drop);
 520         nix_dump("W3: spb_aura_pass \t\t%d\nW3: spb_aura_drop \t\t%d",
 521                  ctx->spb_aura_pass, ctx->spb_aura_drop);
 522         nix_dump("W3: wqe_pool_pass \t\t%d\nW3: wqe_pool_drop \t\t%d",
 523                  ctx->wqe_pool_pass, ctx->wqe_pool_drop);
 524         nix_dump("W3: xqe_pass \t\t\t%d\nW3: xqe_drop \t\t\t%d\n",
 525                  ctx->xqe_pass, ctx->xqe_drop);
 526
 527         nix_dump("W4: qint_idx \t\t\t%d\nW4: rq_int_ena \t\t\t%d",
 528                  ctx->qint_idx, ctx->rq_int_ena);
 529         nix_dump("W4: rq_int \t\t\t%d\nW4: lpb_pool_pass \t\t%d", ctx->rq_int,
 530                  ctx->lpb_pool_pass);
 531         nix_dump("W4: lpb_pool_drop \t\t%d\nW4: lpb_aura_pass \t\t%d",
 532                  ctx->lpb_pool_drop, ctx->lpb_aura_pass);
 533         nix_dump("W4: lpb_aura_drop \t\t%d\n", ctx->lpb_aura_drop);
 534
 535         nix_dump("W5: flow_tagw \t\t\t%d\nW5: bad_utag \t\t\t%d",
 536                  ctx->flow_tagw, ctx->bad_utag);
 537         nix_dump("W5: good_utag \t\t\t%d\nW5: ltag \t\t\t%d\n", ctx->good_utag,
 538                  ctx->ltag);
 539
 540         nix_dump("W6: octs \t\t\t0x%" PRIx64 "", (uint64_t)ctx->octs);
 541         nix_dump("W7: pkts \t\t\t0x%" PRIx64 "", (uint64_t)ctx->pkts);
 542         nix_dump("W8: drop_octs \t\t\t0x%" PRIx64 "", (uint64_t)ctx->drop_octs);
 543         nix_dump("W9: drop_pkts \t\t\t0x%" PRIx64 "", (uint64_t)ctx->drop_pkts);
 544         nix_dump("W10: re_pkts \t\t\t0x%" PRIx64 "\n", (uint64_t)ctx->re_pkts);
 545 }
 546
 547 void
 548 nix_lf_rq_dump(__io struct nix_cn10k_rq_ctx_s *ctx)
 549 {
 550         nix_dump("W0: wqe_aura \t\t\t%d\nW0: len_ol3_dis \t\t\t%d",
 551                  ctx->wqe_aura, ctx->len_ol3_dis);
 552         nix_dump("W0: len_ol4_dis \t\t\t%d\nW0: len_il3_dis \t\t\t%d",
 553                  ctx->len_ol4_dis, ctx->len_il3_dis);
 554         nix_dump("W0: len_il4_dis \t\t\t%d\nW0: csum_ol4_dis \t\t\t%d",
 555                  ctx->len_il4_dis, ctx->csum_ol4_dis);
 556         nix_dump("W0: csum_ol3_dis \t\t\t%d\nW0: lenerr_dis \t\t\t%d",
 557                  ctx->csum_ol4_dis, ctx->lenerr_dis);
 558         nix_dump("W0: cq \t\t\t\t%d\nW0: ena_wqwd \t\t\t%d", ctx->cq,
 559                  ctx->ena_wqwd);
 560         nix_dump("W0: ipsech_ena \t\t\t%d\nW0: sso_ena \t\t\t%d",
 561                  ctx->ipsech_ena, ctx->sso_ena);
 562         nix_dump("W0: ena \t\t\t%d\n", ctx->ena);
 563
 564         nix_dump("W1: chi_ena \t\t%d\nW1: ipsecd_drop_en \t\t%d", ctx->chi_ena,
 565                  ctx->ipsecd_drop_en);
 566         nix_dump("W1: pb_stashing \t\t\t%d", ctx->pb_stashing);
 567         nix_dump("W1: lpb_drop_ena \t\t%d\nW1: spb_drop_ena \t\t%d",
 568                  ctx->lpb_drop_ena, ctx->spb_drop_ena);
 569         nix_dump("W1: xqe_drop_ena \t\t%d\nW1: wqe_caching \t\t%d",
 570                  ctx->xqe_drop_ena, ctx->wqe_caching);
 571         nix_dump("W1: pb_caching \t\t\t%d\nW1: sso_tt \t\t\t%d",
 572                  ctx->pb_caching, ctx->sso_tt);
 573         nix_dump("W1: sso_grp \t\t\t%d\nW1: lpb_aura \t\t\t%d", ctx->sso_grp,
 574                  ctx->lpb_aura);
 575         nix_dump("W1: spb_aura \t\t\t%d\n", ctx->spb_aura);
 576
 577         nix_dump("W2: xqe_hdr_split \t\t%d\nW2: xqe_imm_copy \t\t%d",
 578                  ctx->xqe_hdr_split, ctx->xqe_imm_copy);
 579         nix_dump("W2: xqe_imm_size \t\t%d\nW2: later_skip \t\t\t%d",
 580                  ctx->xqe_imm_size, ctx->later_skip);
 581         nix_dump("W2: first_skip \t\t\t%d\nW2: lpb_sizem1 \t\t\t%d",
 582                  ctx->first_skip, ctx->lpb_sizem1);
 583         nix_dump("W2: spb_ena \t\t\t%d\nW2: wqe_skip \t\t\t%d", ctx->spb_ena,
 584                  ctx->wqe_skip);
 585         nix_dump("W2: spb_sizem1 \t\t\t%d\nW2: policer_ena \t\t\t%d",
 586                  ctx->spb_sizem1, ctx->policer_ena);
 587         nix_dump("W2: band_prof_id \t\t\t%d", ctx->band_prof_id);
 588
 589         nix_dump("W3: spb_pool_pass \t\t%d\nW3: spb_pool_drop \t\t%d",
 590                  ctx->spb_pool_pass, ctx->spb_pool_drop);
 591         nix_dump("W3: spb_aura_pass \t\t%d\nW3: spb_aura_drop \t\t%d",
 592                  ctx->spb_aura_pass, ctx->spb_aura_drop);
 593         nix_dump("W3: wqe_pool_pass \t\t%d\nW3: wqe_pool_drop \t\t%d",
 594                  ctx->wqe_pool_pass, ctx->wqe_pool_drop);
 595         nix_dump("W3: xqe_pass \t\t\t%d\nW3: xqe_drop \t\t\t%d\n",
 596                  ctx->xqe_pass, ctx->xqe_drop);
 597
 598         nix_dump("W4: qint_idx \t\t\t%d\nW4: rq_int_ena \t\t\t%d",
 599                  ctx->qint_idx, ctx->rq_int_ena);
 600         nix_dump("W4: rq_int \t\t\t%d\nW4: lpb_pool_pass \t\t%d", ctx->rq_int,
 601                  ctx->lpb_pool_pass);
 602         nix_dump("W4: lpb_pool_drop \t\t%d\nW4: lpb_aura_pass \t\t%d",
 603                  ctx->lpb_pool_drop, ctx->lpb_aura_pass);
 604         nix_dump("W4: lpb_aura_drop \t\t%d\n", ctx->lpb_aura_drop);
 605
 606         nix_dump("W5: vwqe_skip \t\t\t%d\nW5: max_vsize_exp \t\t\t%d",
 607                  ctx->vwqe_skip, ctx->max_vsize_exp);
 608         nix_dump("W5: vtime_wait \t\t\t%d\nW5: vwqe_ena \t\t\t%d",
 609                  ctx->vtime_wait, ctx->max_vsize_exp);
 610         nix_dump("W5: ipsec_vwqe \t\t\t%d", ctx->ipsec_vwqe);
 611         nix_dump("W5: flow_tagw \t\t\t%d\nW5: bad_utag \t\t\t%d",
 612                  ctx->flow_tagw, ctx->bad_utag);
 613         nix_dump("W5: good_utag \t\t\t%d\nW5: ltag \t\t\t%d\n", ctx->good_utag,
 614                  ctx->ltag);
 615
 616         nix_dump("W6: octs \t\t\t0x%" PRIx64 "", (uint64_t)ctx->octs);
 617         nix_dump("W7: pkts \t\t\t0x%" PRIx64 "", (uint64_t)ctx->pkts);
 618         nix_dump("W8: drop_octs \t\t\t0x%" PRIx64 "", (uint64_t)ctx->drop_octs);
 619         nix_dump("W9: drop_pkts \t\t\t0x%" PRIx64 "", (uint64_t)ctx->drop_pkts);
 620         nix_dump("W10: re_pkts \t\t\t0x%" PRIx64 "\n", (uint64_t)ctx->re_pkts);
 621 }
 622
 623 static inline void
 624 nix_lf_cq_dump(__io struct nix_cq_ctx_s *ctx)
 625 {
 626         nix_dump("W0: base \t\t\t0x%" PRIx64 "\n", ctx->base);
 627
 628         nix_dump("W1: wrptr \t\t\t%" PRIx64 "", (uint64_t)ctx->wrptr);
 629         nix_dump("W1: avg_con \t\t\t%d\nW1: cint_idx \t\t\t%d", ctx->avg_con,
 630                  ctx->cint_idx);
 631         nix_dump("W1: cq_err \t\t\t%d\nW1: qint_idx \t\t\t%d", ctx->cq_err,
 632                  ctx->qint_idx);
 633         nix_dump("W1: bpid  \t\t\t%d\nW1: bp_ena \t\t\t%d\n", ctx->bpid,
 634                  ctx->bp_ena);
 635
 636         nix_dump("W2: update_time \t\t%d\nW2: avg_level \t\t\t%d",
 637                  ctx->update_time, ctx->avg_level);
 638         nix_dump("W2: head \t\t\t%d\nW2: tail \t\t\t%d\n", ctx->head,
 639                  ctx->tail);
 640
 641         nix_dump("W3: cq_err_int_ena \t\t%d\nW3: cq_err_int \t\t\t%d",
 642                  ctx->cq_err_int_ena, ctx->cq_err_int);
 643         nix_dump("W3: qsize \t\t\t%d\nW3: caching \t\t\t%d", ctx->qsize,
 644                  ctx->caching);
 645         nix_dump("W3: substream \t\t\t0x%03x\nW3: ena \t\t\t%d", ctx->substream,
 646                  ctx->ena);
 647         nix_dump("W3: drop_ena \t\t\t%d\nW3: drop \t\t\t%d", ctx->drop_ena,
 648                  ctx->drop);
 649         nix_dump("W3: bp \t\t\t\t%d\n", ctx->bp);
 650 }
 651
 652 int
 653 roc_nix_queues_ctx_dump(struct roc_nix *roc_nix)
 654 {
 655         struct nix *nix = roc_nix_to_nix_priv(roc_nix);
 656         int rc = -1, q, rq = nix->nb_rx_queues;
 657         struct npa_aq_enq_rsp *npa_rsp;
 658         struct npa_aq_enq_req *npa_aq;
 659         struct dev *dev = &nix->dev;
 660         int sq = nix->nb_tx_queues;
 661         struct npa_lf *npa_lf;
 662         volatile void *ctx;
 663         uint32_t sqb_aura;
 664
 665         npa_lf = idev_npa_obj_get();
 666         if (npa_lf == NULL)
 667                 return NPA_ERR_DEVICE_NOT_BOUNDED;
 668
 669         for (q = 0; q < rq; q++) {
 670                 rc = nix_q_ctx_get(dev, NIX_AQ_CTYPE_CQ, q, &ctx);
 671                 if (rc) {
 672                         plt_err("Failed to get cq context");
 673                         goto fail;
 674                 }
 675                 nix_dump("============== port=%d cq=%d ===============",
 676                          roc_nix->port_id, q);
 677                 nix_lf_cq_dump(ctx);
 678         }
 679
 680         for (q = 0; q < rq; q++) {
 681                 rc = nix_q_ctx_get(dev, NIX_AQ_CTYPE_RQ, q, &ctx);
 682                 if (rc) {
 683                         plt_err("Failed to get rq context");
 684                         goto fail;
 685                 }
 686                 nix_dump("============== port=%d rq=%d ===============",
 687                          roc_nix->port_id, q);
 688                 if (roc_model_is_cn9k())
 689                         nix_cn9k_lf_rq_dump(ctx);
 690                 else
 691                         nix_lf_rq_dump(ctx);
 692         }
 693
 694         for (q = 0; q < sq; q++) {
 695                 rc = nix_q_ctx_get(dev, NIX_AQ_CTYPE_SQ, q, &ctx);
 696                 if (rc) {
 697                         plt_err("Failed to get sq context");
 698                         goto fail;
 699                 }
 700                 nix_dump("============== port=%d sq=%d ===============",
 701                          roc_nix->port_id, q);
 702                 if (roc_model_is_cn9k())
 703                         nix_cn9k_lf_sq_dump(ctx, &sqb_aura);
 704                 else
 705                         nix_lf_sq_dump(ctx, &sqb_aura);
 706
 707                 if (!npa_lf) {
 708                         plt_err("NPA LF does not exist");
 709                         continue;
 710                 }
 711
 712                 /* Dump SQB Aura minimal info */
 713                 npa_aq = mbox_alloc_msg_npa_aq_enq(npa_lf->mbox);
 714                 if (npa_aq == NULL)
 715                         return -ENOSPC;
 716                 npa_aq->aura_id = sqb_aura;
 717                 npa_aq->ctype = NPA_AQ_CTYPE_AURA;
 718                 npa_aq->op = NPA_AQ_INSTOP_READ;
 719
 720                 rc = mbox_process_msg(npa_lf->mbox, (void *)&npa_rsp);
 721                 if (rc) {
 722                         plt_err("Failed to get sq's sqb_aura context");
 723                         continue;
 724                 }
 725
 726                 nix_dump("\nSQB Aura W0: Pool addr\t\t0x%" PRIx64 "",
 727                          npa_rsp->aura.pool_addr);
 728                 nix_dump("SQB Aura W1: ena\t\t\t%d", npa_rsp->aura.ena);
 729                 nix_dump("SQB Aura W2: count\t\t%" PRIx64 "",
 730                          (uint64_t)npa_rsp->aura.count);
 731                 nix_dump("SQB Aura W3: limit\t\t%" PRIx64 "",
 732                          (uint64_t)npa_rsp->aura.limit);
 733                 nix_dump("SQB Aura W3: fc_ena\t\t%d", npa_rsp->aura.fc_ena);
 734                 nix_dump("SQB Aura W4: fc_addr\t\t0x%" PRIx64 "\n",
 735                          npa_rsp->aura.fc_addr);
 736         }
 737
 738 fail:
 739         return rc;
 740 }
 741
 742 /* Dumps struct nix_cqe_hdr_s and union nix_rx_parse_u */
 743 void
 744 roc_nix_cqe_dump(const struct nix_cqe_hdr_s *cq)
 745 {
 746         const union nix_rx_parse_u *rx =
 747                 (const union nix_rx_parse_u *)((const uint64_t *)cq + 1);
 748         const uint64_t *sgs = (const uint64_t *)(rx + 1);
 749         int i;
 750
 751         nix_dump("tag \t\t0x%x\tq \t\t%d\t\tnode \t\t%d\tcqe_type \t%d",
 752                  cq->tag, cq->q, cq->node, cq->cqe_type);
 753
 754         nix_dump("W0: chan \t0x%x\t\tdesc_sizem1 \t%d", rx->chan,
 755                  rx->desc_sizem1);
 756         nix_dump("W0: imm_copy \t%d\t\texpress \t%d", rx->imm_copy,
 757                  rx->express);
 758         nix_dump("W0: wqwd \t%d\t\terrlev \t\t%d\t\terrcode \t%d", rx->wqwd,
 759                  rx->errlev, rx->errcode);
 760         nix_dump("W0: latype \t%d\t\tlbtype \t\t%d\t\tlctype \t\t%d",
 761                  rx->latype, rx->lbtype, rx->lctype);
 762         nix_dump("W0: ldtype \t%d\t\tletype \t\t%d\t\tlftype \t\t%d",
 763                  rx->ldtype, rx->letype, rx->lftype);
 764         nix_dump("W0: lgtype \t%d \t\tlhtype \t\t%d", rx->lgtype, rx->lhtype);
 765
 766         nix_dump("W1: pkt_lenm1 \t%d", rx->pkt_lenm1);
 767         nix_dump("W1: l2m \t%d\t\tl2b \t\t%d\t\tl3m \t\t%d\tl3b \t\t%d",
 768                  rx->l2m, rx->l2b, rx->l3m, rx->l3b);
 769         nix_dump("W1: vtag0_valid %d\t\tvtag0_gone \t%d", rx->vtag0_valid,
 770                  rx->vtag0_gone);
 771         nix_dump("W1: vtag1_valid %d\t\tvtag1_gone \t%d", rx->vtag1_valid,
 772                  rx->vtag1_gone);
 773         nix_dump("W1: pkind \t%d", rx->pkind);
 774         nix_dump("W1: vtag0_tci \t%d\t\tvtag1_tci \t%d", rx->vtag0_tci,
 775                  rx->vtag1_tci);
 776
 777         nix_dump("W2: laflags \t%d\t\tlbflags\t\t%d\t\tlcflags \t%d",
 778                  rx->laflags, rx->lbflags, rx->lcflags);
 779         nix_dump("W2: ldflags \t%d\t\tleflags\t\t%d\t\tlfflags \t%d",
 780                  rx->ldflags, rx->leflags, rx->lfflags);
 781         nix_dump("W2: lgflags \t%d\t\tlhflags \t%d", rx->lgflags, rx->lhflags);
 782
 783         nix_dump("W3: eoh_ptr \t%d\t\twqe_aura \t%d\t\tpb_aura \t%d",
 784                  rx->eoh_ptr, rx->wqe_aura, rx->pb_aura);
 785         nix_dump("W3: match_id \t%d", rx->match_id);
 786
 787         nix_dump("W4: laptr \t%d\t\tlbptr \t\t%d\t\tlcptr \t\t%d", rx->laptr,
 788                  rx->lbptr, rx->lcptr);
 789         nix_dump("W4: ldptr \t%d\t\tleptr \t\t%d\t\tlfptr \t\t%d", rx->ldptr,
 790                  rx->leptr, rx->lfptr);
 791         nix_dump("W4: lgptr \t%d\t\tlhptr \t\t%d", rx->lgptr, rx->lhptr);
 792
 793         nix_dump("W5: vtag0_ptr \t%d\t\tvtag1_ptr \t%d\t\tflow_key_alg \t%d",
 794                  rx->vtag0_ptr, rx->vtag1_ptr, rx->flow_key_alg);
 795
 796         for (i = 0; i < (rx->desc_sizem1 + 1) << 1; i++)
 797                 nix_dump("sg[%u] = %p", i, (void *)sgs[i]);
 798 }
 799
 800 void
 801 roc_nix_rq_dump(struct roc_nix_rq *rq)
 802 {
 803         nix_dump("nix_rq@%p", rq);
 804         nix_dump("  qid = %d", rq->qid);
 805         nix_dump("  aura_handle = 0x%" PRIx64 "", rq->aura_handle);
 806         nix_dump("  ipsec_ena = %d", rq->ipsech_ena);
 807         nix_dump("  first_skip = %d", rq->first_skip);
 808         nix_dump("  later_skip = %d", rq->later_skip);
 809         nix_dump("  lpb_size = %d", rq->lpb_size);
 810         nix_dump("  sso_ena = %d", rq->sso_ena);
 811         nix_dump("  tag_mask = %d", rq->tag_mask);
 812         nix_dump("  flow_tag_width = %d", rq->flow_tag_width);
 813         nix_dump("  tt = %d", rq->tt);
 814         nix_dump("  hwgrp = %d", rq->hwgrp);
 815         nix_dump("  vwqe_ena = %d", rq->vwqe_ena);
 816         nix_dump("  vwqe_first_skip = %d", rq->vwqe_first_skip);
 817         nix_dump("  vwqe_max_sz_exp = %d", rq->vwqe_max_sz_exp);
 818         nix_dump("  vwqe_wait_tmo = %ld", rq->vwqe_wait_tmo);
 819         nix_dump("  vwqe_aura_handle = %ld", rq->vwqe_aura_handle);
 820         nix_dump("  roc_nix = %p", rq->roc_nix);
 821         nix_dump("  inl_dev_ref = %d", rq->inl_dev_ref);
 822 }
 823
 824 void
 825 roc_nix_cq_dump(struct roc_nix_cq *cq)
 826 {
 827         nix_dump("nix_cq@%p", cq);
 828         nix_dump("  qid = %d", cq->qid);
 829         nix_dump("  qnb_desc = %d", cq->nb_desc);
 830         nix_dump("  roc_nix = %p", cq->roc_nix);
 831         nix_dump("  door = 0x%" PRIx64 "", cq->door);
 832         nix_dump("  status = %p", cq->status);
 833         nix_dump("  wdata = 0x%" PRIx64 "", cq->wdata);
 834         nix_dump("  desc_base = %p", cq->desc_base);
 835         nix_dump("  qmask = 0x%" PRIx32 "", cq->qmask);
 836 }
 837
 838 void
 839 roc_nix_sq_dump(struct roc_nix_sq *sq)
 840 {
 841         nix_dump("nix_sq@%p", sq);
 842         nix_dump("  qid = %d", sq->qid);
 843         nix_dump("  max_sqe_sz = %d", sq->max_sqe_sz);
 844         nix_dump("  nb_desc = %d", sq->nb_desc);
 845         nix_dump("  sqes_per_sqb_log2 = %d", sq->sqes_per_sqb_log2);
 846         nix_dump("  roc_nix= %p", sq->roc_nix);
 847         nix_dump("  aura_handle = 0x%" PRIx64 "", sq->aura_handle);
 848         nix_dump("  nb_sqb_bufs_adj = %d", sq->nb_sqb_bufs_adj);
 849         nix_dump("  nb_sqb_bufs = %d", sq->nb_sqb_bufs);
 850         nix_dump("  io_addr = 0x%" PRIx64 "", sq->io_addr);
 851         nix_dump("  lmt_addr = %p", sq->lmt_addr);
 852         nix_dump("  sqe_mem = %p", sq->sqe_mem);
 853         nix_dump("  fc = %p", sq->fc);
 854 };
 855
 856 static uint8_t
 857 nix_tm_reg_dump_prep(uint16_t hw_lvl, uint16_t schq, uint16_t link,
 858                      uint64_t *reg, char regstr[][NIX_REG_NAME_SZ])
 859 {
 860         uint8_t k = 0;
 861
 862         switch (hw_lvl) {
 863         case NIX_TXSCH_LVL_SMQ:
 864                 reg[k] = NIX_AF_SMQX_CFG(schq);
 865                 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_SMQ[%u]_CFG",
 866                          schq);
 867
 868                 reg[k] = NIX_AF_MDQX_PARENT(schq);
 869                 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_MDQ[%u]_PARENT",
 870                          schq);
 871
 872                 reg[k] = NIX_AF_MDQX_SCHEDULE(schq);
 873                 snprintf(regstr[k++], NIX_REG_NAME_SZ,
 874                          "NIX_AF_MDQ[%u]_SCHEDULE", schq);
 875
 876                 reg[k] = NIX_AF_MDQX_PIR(schq);
 877                 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_MDQ[%u]_PIR",
 878                          schq);
 879
 880                 reg[k] = NIX_AF_MDQX_CIR(schq);
 881                 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_MDQ[%u]_CIR",
 882                          schq);
 883
 884                 reg[k] = NIX_AF_MDQX_SHAPE(schq);
 885                 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_MDQ[%u]_SHAPE",
 886                          schq);
 887
 888                 reg[k] = NIX_AF_MDQX_SW_XOFF(schq);
 889                 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_MDQ[%u]_SW_XOFF",
 890                          schq);
 891                 break;
 892         case NIX_TXSCH_LVL_TL4:
 893                 reg[k] = NIX_AF_TL4X_PARENT(schq);
 894                 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL4[%u]_PARENT",
 895                          schq);
 896
 897                 reg[k] = NIX_AF_TL4X_TOPOLOGY(schq);
 898                 snprintf(regstr[k++], NIX_REG_NAME_SZ,
 899                          "NIX_AF_TL4[%u]_TOPOLOGY", schq);
 900
 901                 reg[k] = NIX_AF_TL4X_SDP_LINK_CFG(schq);
 902                 snprintf(regstr[k++], NIX_REG_NAME_SZ,
 903                          "NIX_AF_TL4[%u]_SDP_LINK_CFG", schq);
 904
 905                 reg[k] = NIX_AF_TL4X_SCHEDULE(schq);
 906                 snprintf(regstr[k++], NIX_REG_NAME_SZ,
 907                          "NIX_AF_TL4[%u]_SCHEDULE", schq);
 908
 909                 reg[k] = NIX_AF_TL4X_PIR(schq);
 910                 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL4[%u]_PIR",
 911                          schq);
 912
 913                 reg[k] = NIX_AF_TL4X_CIR(schq);
 914                 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL4[%u]_CIR",
 915                          schq);
 916
 917                 reg[k] = NIX_AF_TL4X_SHAPE(schq);
 918                 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL4[%u]_SHAPE",
 919                          schq);
 920
 921                 reg[k] = NIX_AF_TL4X_SW_XOFF(schq);
 922                 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL4[%u]_SW_XOFF",
 923                          schq);
 924                 break;
 925         case NIX_TXSCH_LVL_TL3:
 926                 reg[k] = NIX_AF_TL3X_PARENT(schq);
 927                 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL3[%u]_PARENT",
 928                          schq);
 929
 930                 reg[k] = NIX_AF_TL3X_TOPOLOGY(schq);
 931                 snprintf(regstr[k++], NIX_REG_NAME_SZ,
 932                          "NIX_AF_TL3[%u]_TOPOLOGY", schq);
 933
 934                 reg[k] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, link);
 935                 snprintf(regstr[k++], NIX_REG_NAME_SZ,
 936                          "NIX_AF_TL3_TL2[%u]_LINK[%u]_CFG", schq, link);
 937
 938                 reg[k] = NIX_AF_TL3X_SCHEDULE(schq);
 939                 snprintf(regstr[k++], NIX_REG_NAME_SZ,
 940                          "NIX_AF_TL3[%u]_SCHEDULE", schq);
 941
 942                 reg[k] = NIX_AF_TL3X_PIR(schq);
 943                 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL3[%u]_PIR",
 944                          schq);
 945
 946                 reg[k] = NIX_AF_TL3X_CIR(schq);
 947                 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL3[%u]_CIR",
 948                          schq);
 949
 950                 reg[k] = NIX_AF_TL3X_SHAPE(schq);
 951                 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL3[%u]_SHAPE",
 952                          schq);
 953
 954                 reg[k] = NIX_AF_TL3X_SW_XOFF(schq);
 955                 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL3[%u]_SW_XOFF",
 956                          schq);
 957                 break;
 958         case NIX_TXSCH_LVL_TL2:
 959                 reg[k] = NIX_AF_TL2X_PARENT(schq);
 960                 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL2[%u]_PARENT",
 961                          schq);
 962
 963                 reg[k] = NIX_AF_TL2X_TOPOLOGY(schq);
 964                 snprintf(regstr[k++], NIX_REG_NAME_SZ,
 965                          "NIX_AF_TL2[%u]_TOPOLOGY", schq);
 966
 967                 reg[k] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, link);
 968                 snprintf(regstr[k++], NIX_REG_NAME_SZ,
 969                          "NIX_AF_TL3_TL2[%u]_LINK[%u]_CFG", schq, link);
 970
 971                 reg[k] = NIX_AF_TL2X_SCHEDULE(schq);
 972                 snprintf(regstr[k++], NIX_REG_NAME_SZ,
 973                          "NIX_AF_TL2[%u]_SCHEDULE", schq);
 974
 975                 reg[k] = NIX_AF_TL2X_PIR(schq);
 976                 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL2[%u]_PIR",
 977                          schq);
 978
 979                 reg[k] = NIX_AF_TL2X_CIR(schq);
 980                 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL2[%u]_CIR",
 981                          schq);
 982
 983                 reg[k] = NIX_AF_TL2X_SHAPE(schq);
 984                 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL2[%u]_SHAPE",
 985                          schq);
 986
 987                 reg[k] = NIX_AF_TL2X_SW_XOFF(schq);
 988                 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL2[%u]_SW_XOFF",
 989                          schq);
 990                 break;
 991         case NIX_TXSCH_LVL_TL1:
 992
 993                 reg[k] = NIX_AF_TL1X_TOPOLOGY(schq);
 994                 snprintf(regstr[k++], NIX_REG_NAME_SZ,
 995                          "NIX_AF_TL1[%u]_TOPOLOGY", schq);
 996
 997                 reg[k] = NIX_AF_TL1X_SCHEDULE(schq);
 998                 snprintf(regstr[k++], NIX_REG_NAME_SZ,
 999                          "NIX_AF_TL1[%u]_SCHEDULE", schq);
1000
1001                 reg[k] = NIX_AF_TL1X_CIR(schq);
1002                 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL1[%u]_CIR",
1003                          schq);
1004
1005                 reg[k] = NIX_AF_TL1X_SW_XOFF(schq);
1006                 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL1[%u]_SW_XOFF",
1007                          schq);
1008
1009                 reg[k] = NIX_AF_TL1X_DROPPED_PACKETS(schq);
1010                 snprintf(regstr[k++], NIX_REG_NAME_SZ,
1011                          "NIX_AF_TL1[%u]_DROPPED_PACKETS", schq);
1012                 break;
1013         default:
1014                 break;
1015         }
1016
1017         if (k > MAX_REGS_PER_MBOX_MSG) {
1018                 nix_dump("\t!!!NIX TM Registers request overflow!!!");
1019                 return 0;
1020         }
1021         return k;
1022 }
1023
1024 static void
1025 nix_tm_dump_lvl(struct nix *nix, struct nix_tm_node_list *list, uint8_t hw_lvl)
1026 {
1027         char regstr[MAX_REGS_PER_MBOX_MSG * 2][NIX_REG_NAME_SZ];
1028         uint64_t reg[MAX_REGS_PER_MBOX_MSG * 2];
1029         struct mbox *mbox = (&nix->dev)->mbox;
1030         struct nix_txschq_config *req, *rsp;
1031         const char *lvlstr, *parent_lvlstr;
1032         struct nix_tm_node *node, *parent;
1033         struct nix_tm_node *root = NULL;
1034         uint32_t schq, parent_schq;
1035         bool found = false;
1036         uint8_t j, k, rc;
1037
1038         TAILQ_FOREACH(node, list, node) {
1039                 if (node->hw_lvl != hw_lvl)
1040                         continue;
1041
1042                 found = true;
1043                 parent = node->parent;
1044                 if (hw_lvl == NIX_TXSCH_LVL_CNT) {
1045                         lvlstr = "SQ";
1046                         schq = node->id;
1047                 } else {
1048                         lvlstr = nix_tm_hwlvl2str(node->hw_lvl);
1049                         schq = node->hw_id;
1050                 }
1051
1052                 if (parent) {
1053                         parent_schq = parent->hw_id;
1054                         parent_lvlstr = nix_tm_hwlvl2str(parent->hw_lvl);
1055                 } else if (node->hw_lvl == NIX_TXSCH_LVL_TL1) {
1056                         parent_schq = nix->tx_link;
1057                         parent_lvlstr = "LINK";
1058                 } else {
1059                         parent_schq = node->parent_hw_id;
1060                         parent_lvlstr = nix_tm_hwlvl2str(node->hw_lvl + 1);
1061                 }
1062
1063                 nix_dump("\t(%p%s) %s_%d->%s_%d", node,
1064                          node->child_realloc ? "[CR]" : "", lvlstr, schq,
1065                          parent_lvlstr, parent_schq);
1066
1067                 if (!(node->flags & NIX_TM_NODE_HWRES))
1068                         continue;
1069
1070                 /* Need to dump TL1 when root is TL2 */
1071                 if (node->hw_lvl == nix->tm_root_lvl)
1072                         root = node;
1073
1074                 /* Dump registers only when HWRES is present */
1075                 k = nix_tm_reg_dump_prep(node->hw_lvl, schq, nix->tx_link, reg,
1076                                          regstr);
1077                 if (!k)
1078                         continue;
1079
1080                 req = mbox_alloc_msg_nix_txschq_cfg(mbox);
1081                 req->read = 1;
1082                 req->lvl = node->hw_lvl;
1083                 req->num_regs = k;
1084                 mbox_memcpy(req->reg, reg, sizeof(uint64_t) * k);
1085                 rc = mbox_process_msg(mbox, (void **)&rsp);
1086                 if (!rc) {
1087                         for (j = 0; j < k; j++)
1088                                 nix_dump("\t\t%s=0x%016" PRIx64, regstr[j],
1089                                          rsp->regval[j]);
1090                 } else {
1091                         nix_dump("\t!!!Failed to dump registers!!!");
1092                 }
1093         }
1094
1095         if (found)
1096                 nix_dump("\n");
1097
1098         /* Dump TL1 node data when root level is TL2 */
1099         if (root && root->hw_lvl == NIX_TXSCH_LVL_TL2) {
1100                 k = nix_tm_reg_dump_prep(NIX_TXSCH_LVL_TL1, root->parent_hw_id,
1101                                          nix->tx_link, reg, regstr);
1102                 if (!k)
1103                         return;
1104
1105                 req = mbox_alloc_msg_nix_txschq_cfg(mbox);
1106                 req->read = 1;
1107                 req->lvl = NIX_TXSCH_LVL_TL1;
1108                 req->num_regs = k;
1109                 mbox_memcpy(req->reg, reg, sizeof(uint64_t) * k);
1110                 rc = mbox_process_msg(mbox, (void **)&rsp);
1111                 if (!rc) {
1112                         for (j = 0; j < k; j++)
1113                                 nix_dump("\t\t%s=0x%016" PRIx64, regstr[j],
1114                                          rsp->regval[j]);
1115                 } else {
1116                         nix_dump("\t!!!Failed to dump registers!!!");
1117                 }
1118                 nix_dump("\n");
1119         }
1120 }
1121
1122 void
1123 roc_nix_tm_dump(struct roc_nix *roc_nix)
1124 {
1125         struct nix *nix = roc_nix_to_nix_priv(roc_nix);
1126         struct dev *dev = &nix->dev;
1127         uint8_t hw_lvl, i;
1128
1129         nix_dump("===TM hierarchy and registers dump of %s (pf:vf) (%d:%d)===",
1130                  nix->pci_dev->name, dev_get_pf(dev->pf_func),
1131                  dev_get_vf(dev->pf_func));
1132
1133         /* Dump all trees */
1134         for (i = 0; i < ROC_NIX_TM_TREE_MAX; i++) {
1135                 nix_dump("\tTM %s:", nix_tm_tree2str(i));
1136                 for (hw_lvl = 0; hw_lvl <= NIX_TXSCH_LVL_CNT; hw_lvl++)
1137                         nix_tm_dump_lvl(nix, &nix->trees[i], hw_lvl);
1138         }
1139
1140         /* Dump unused resources */
1141         nix_dump("\tTM unused resources:");
1142         hw_lvl = NIX_TXSCH_LVL_SMQ;
1143         for (; hw_lvl < NIX_TXSCH_LVL_CNT; hw_lvl++) {
1144                 nix_dump("\t\ttxschq        %7s num = %d",
1145                          nix_tm_hwlvl2str(hw_lvl),
1146                          nix_tm_resource_avail(nix, hw_lvl, false));
1147
1148                 nix_bitmap_dump(nix->schq_bmp[hw_lvl]);
1149                 nix_dump("\n");
1150
1151                 nix_dump("\t\ttxschq_contig %7s num = %d",
1152                          nix_tm_hwlvl2str(hw_lvl),
1153                          nix_tm_resource_avail(nix, hw_lvl, true));
1154                 nix_bitmap_dump(nix->schq_contig_bmp[hw_lvl]);
1155                 nix_dump("\n");
1156         }
1157 }
1158
1159 void
1160 roc_nix_dump(struct roc_nix *roc_nix)
1161 {
1162         struct nix *nix = roc_nix_to_nix_priv(roc_nix);
1163         struct dev *dev = &nix->dev;
1164         int i;
1165
1166         nix_dump("nix@%p", nix);
1167         nix_dump("  pf = %d", dev_get_pf(dev->pf_func));
1168         nix_dump("  vf = %d", dev_get_vf(dev->pf_func));
1169         nix_dump("  bar2 = 0x%" PRIx64, dev->bar2);
1170         nix_dump("  bar4 = 0x%" PRIx64, dev->bar4);
1171         nix_dump("  port_id = %d", roc_nix->port_id);
1172         nix_dump("  rss_tag_as_xor = %d", roc_nix->rss_tag_as_xor);
1173         nix_dump("  rss_tag_as_xor = %d", roc_nix->max_sqb_count);
1174         nix_dump("  outb_nb_desc = %u", roc_nix->outb_nb_desc);
1175
1176         nix_dump("  \tpci_dev = %p", nix->pci_dev);
1177         nix_dump("  \tbase = 0x%" PRIxPTR "", nix->base);
1178         nix_dump("  \tlmt_base = 0x%" PRIxPTR "", nix->lmt_base);
1179         nix_dump("  \treta_size = %d", nix->reta_sz);
1180         nix_dump("  \ttx_chan_base = %d", nix->tx_chan_base);
1181         nix_dump("  \trx_chan_base = %d", nix->rx_chan_base);
1182         nix_dump("  \tnb_rx_queues = %d", nix->nb_rx_queues);
1183         nix_dump("  \tnb_tx_queues = %d", nix->nb_tx_queues);
1184         nix_dump("  \tlso_tsov6_idx = %d", nix->lso_tsov6_idx);
1185         nix_dump("  \tlso_tsov4_idx = %d", nix->lso_tsov4_idx);
1186         nix_dump("  \tlso_udp_tun_v4v4 = %d",
1187                  nix->lso_udp_tun_idx[ROC_NIX_LSO_TUN_V4V4]);
1188         nix_dump("  \tlso_udp_tun_v4v6 = %d",
1189                  nix->lso_udp_tun_idx[ROC_NIX_LSO_TUN_V4V6]);
1190         nix_dump("  \tlso_udp_tun_v6v4 = %d",
1191                  nix->lso_udp_tun_idx[ROC_NIX_LSO_TUN_V6V4]);
1192         nix_dump("  \tlso_udp_tun_v6v6 = %d",
1193                  nix->lso_udp_tun_idx[ROC_NIX_LSO_TUN_V6V6]);
1194         nix_dump("  \tlso_tun_v4v4 = %d",
1195                  nix->lso_tun_idx[ROC_NIX_LSO_TUN_V4V4]);
1196         nix_dump("  \tlso_tun_v4v6 = %d",
1197                  nix->lso_tun_idx[ROC_NIX_LSO_TUN_V4V6]);
1198         nix_dump("  \tlso_tun_v6v4 = %d",
1199                  nix->lso_tun_idx[ROC_NIX_LSO_TUN_V6V4]);
1200         nix_dump("  \tlso_tun_v6v6 = %d",
1201                  nix->lso_tun_idx[ROC_NIX_LSO_TUN_V6V6]);
1202         nix_dump("  \tlf_rx_stats = %d", nix->lf_rx_stats);
1203         nix_dump("  \tlf_tx_stats = %d", nix->lf_tx_stats);
1204         nix_dump("  \trx_chan_cnt = %d", nix->rx_chan_cnt);
1205         nix_dump("  \ttx_chan_cnt = %d", nix->tx_chan_cnt);
1206         nix_dump("  \tcgx_links = %d", nix->cgx_links);
1207         nix_dump("  \tlbk_links = %d", nix->lbk_links);
1208         nix_dump("  \tsdp_links = %d", nix->sdp_links);
1209         nix_dump("  \ttx_link = %d", nix->tx_link);
1210         nix_dump("  \tsqb_size = %d", nix->sqb_size);
1211         nix_dump("  \tmsixoff = %d", nix->msixoff);
1212         for (i = 0; i < nix->nb_cpt_lf; i++)
1213                 nix_dump("  \tcpt_msixoff[%d] = %d", i, nix->cpt_msixoff[i]);
1214         nix_dump("  \tcints = %d", nix->cints);
1215         nix_dump("  \tqints = %d", nix->qints);
1216         nix_dump("  \tsdp_link = %d", nix->sdp_link);
1217         nix_dump("  \tptp_en = %d", nix->ptp_en);
1218         nix_dump("  \trss_alg_idx = %d", nix->rss_alg_idx);
1219         nix_dump("  \ttx_pause = %d", nix->tx_pause);
1220         nix_dump("  \tinl_inb_ena = %d", nix->inl_inb_ena);
1221         nix_dump("  \tinl_outb_ena = %d", nix->inl_outb_ena);
1222         nix_dump("  \tinb_sa_base = 0x%p", nix->inb_sa_base);
1223         nix_dump("  \tinb_sa_sz = %" PRIu64, nix->inb_sa_sz);
1224         nix_dump("  \toutb_sa_base = 0x%p", nix->outb_sa_base);
1225         nix_dump("  \toutb_sa_sz = %" PRIu64, nix->outb_sa_sz);
1226         nix_dump("  \toutb_err_sso_pffunc = 0x%x", nix->outb_err_sso_pffunc);
1227         nix_dump("  \tcpt_lf_base = 0x%p", nix->cpt_lf_base);
1228         nix_dump("  \tnb_cpt_lf = %d", nix->nb_cpt_lf);
1229         nix_dump("  \tinb_inl_dev = %d", nix->inb_inl_dev);
1230 }
1231
1232 void
1233 roc_nix_inl_dev_dump(struct roc_nix_inl_dev *roc_inl_dev)
1234 {
1235         struct nix_inl_dev *inl_dev =
1236                 (struct nix_inl_dev *)&roc_inl_dev->reserved;
1237         struct dev *dev = &inl_dev->dev;
1238
1239         nix_dump("nix_inl_dev@%p", inl_dev);
1240         nix_dump("  pf = %d", dev_get_pf(dev->pf_func));
1241         nix_dump("  vf = %d", dev_get_vf(dev->pf_func));
1242         nix_dump("  bar2 = 0x%" PRIx64, dev->bar2);
1243         nix_dump("  bar4 = 0x%" PRIx64, dev->bar4);
1244
1245         nix_dump("  \tpci_dev = %p", inl_dev->pci_dev);
1246         nix_dump("  \tnix_base = 0x%" PRIxPTR "", inl_dev->nix_base);
1247         nix_dump("  \tsso_base = 0x%" PRIxPTR "", inl_dev->sso_base);
1248         nix_dump("  \tssow_base = 0x%" PRIxPTR "", inl_dev->ssow_base);
1249         nix_dump("  \tnix_msixoff = %d", inl_dev->nix_msixoff);
1250         nix_dump("  \tsso_msixoff = %d", inl_dev->sso_msixoff);
1251         nix_dump("  \tssow_msixoff = %d", inl_dev->ssow_msixoff);
1252         nix_dump("  \tnix_cints = %d", inl_dev->cints);
1253         nix_dump("  \tnix_qints = %d", inl_dev->qints);
1254         nix_dump("  \trq_refs = %d", inl_dev->rq_refs);
1255         nix_dump("  \tinb_sa_base = 0x%p", inl_dev->inb_sa_base);
1256         nix_dump("  \tinb_sa_sz = %d", inl_dev->inb_sa_sz);
1257         nix_dump("  \txaq_buf_size = %u", inl_dev->xaq_buf_size);
1258         nix_dump("  \txae_waes = %u", inl_dev->xae_waes);
1259         nix_dump("  \tiue = %u", inl_dev->iue);
1260         nix_dump("  \txaq_aura = 0x%" PRIx64, inl_dev->xaq_aura);
1261         nix_dump("  \txaq_mem = 0x%p", inl_dev->xaq_mem);
1262
1263         nix_dump("  \tinl_dev_rq:");
1264         roc_nix_rq_dump(&inl_dev->rq);
1265 }