drivers/common/cnxk/roc_nix_debug.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(C) 2021 Marvell.
   3  */
   4
   5 #include "roc_api.h"
   6 #include "roc_priv.h"
   7
   8 #define nix_dump(fmt, ...) fprintf(stderr, fmt "\n", ##__VA_ARGS__)
   9 #define NIX_REG_INFO(reg)                                                      \
  10         {                                                                      \
  11                 reg, #reg                                                      \
  12         }
  13 #define NIX_REG_NAME_SZ 48
  14
  15 #define nix_dump_no_nl(fmt, ...) fprintf(stderr, fmt, ##__VA_ARGS__)
  16
  17 struct nix_lf_reg_info {
  18         uint32_t offset;
  19         const char *name;
  20 };
  21
  22 static const struct nix_lf_reg_info nix_lf_reg[] = {
  23         NIX_REG_INFO(NIX_LF_RX_SECRETX(0)),
  24         NIX_REG_INFO(NIX_LF_RX_SECRETX(1)),
  25         NIX_REG_INFO(NIX_LF_RX_SECRETX(2)),
  26         NIX_REG_INFO(NIX_LF_RX_SECRETX(3)),
  27         NIX_REG_INFO(NIX_LF_RX_SECRETX(4)),
  28         NIX_REG_INFO(NIX_LF_RX_SECRETX(5)),
  29         NIX_REG_INFO(NIX_LF_CFG),
  30         NIX_REG_INFO(NIX_LF_GINT),
  31         NIX_REG_INFO(NIX_LF_GINT_W1S),
  32         NIX_REG_INFO(NIX_LF_GINT_ENA_W1C),
  33         NIX_REG_INFO(NIX_LF_GINT_ENA_W1S),
  34         NIX_REG_INFO(NIX_LF_ERR_INT),
  35         NIX_REG_INFO(NIX_LF_ERR_INT_W1S),
  36         NIX_REG_INFO(NIX_LF_ERR_INT_ENA_W1C),
  37         NIX_REG_INFO(NIX_LF_ERR_INT_ENA_W1S),
  38         NIX_REG_INFO(NIX_LF_RAS),
  39         NIX_REG_INFO(NIX_LF_RAS_W1S),
  40         NIX_REG_INFO(NIX_LF_RAS_ENA_W1C),
  41         NIX_REG_INFO(NIX_LF_RAS_ENA_W1S),
  42         NIX_REG_INFO(NIX_LF_SQ_OP_ERR_DBG),
  43         NIX_REG_INFO(NIX_LF_MNQ_ERR_DBG),
  44         NIX_REG_INFO(NIX_LF_SEND_ERR_DBG),
  45 };
  46
  47 static void
  48 nix_bitmap_dump(struct plt_bitmap *bmp)
  49 {
  50         uint32_t pos = 0, start_pos;
  51         uint64_t slab = 0;
  52         int i;
  53
  54         plt_bitmap_scan_init(bmp);
  55         plt_bitmap_scan(bmp, &pos, &slab);
  56         start_pos = pos;
  57
  58         nix_dump_no_nl("  \t\t[");
  59         do {
  60                 if (!slab)
  61                         break;
  62                 i = 0;
  63
  64                 for (i = 0; i < 64; i++)
  65                         if (slab & (1ULL << i))
  66                                 nix_dump_no_nl("%d, ", i);
  67
  68                 if (!plt_bitmap_scan(bmp, &pos, &slab))
  69                         break;
  70         } while (start_pos != pos);
  71         nix_dump_no_nl(" ]");
  72 }
  73
  74 int
  75 roc_nix_lf_get_reg_count(struct roc_nix *roc_nix)
  76 {
  77         struct nix *nix = roc_nix_to_nix_priv(roc_nix);
  78         int reg_count;
  79
  80         if (roc_nix == NULL)
  81                 return NIX_ERR_PARAM;
  82
  83         reg_count = PLT_DIM(nix_lf_reg);
  84         /* NIX_LF_TX_STATX */
  85         reg_count += nix->lf_tx_stats;
  86         /* NIX_LF_RX_STATX */
  87         reg_count += nix->lf_rx_stats;
  88         /* NIX_LF_QINTX_CNT*/
  89         reg_count += nix->qints;
  90         /* NIX_LF_QINTX_INT */
  91         reg_count += nix->qints;
  92         /* NIX_LF_QINTX_ENA_W1S */
  93         reg_count += nix->qints;
  94         /* NIX_LF_QINTX_ENA_W1C */
  95         reg_count += nix->qints;
  96         /* NIX_LF_CINTX_CNT */
  97         reg_count += nix->cints;
  98         /* NIX_LF_CINTX_WAIT */
  99         reg_count += nix->cints;
 100         /* NIX_LF_CINTX_INT */
 101         reg_count += nix->cints;
 102         /* NIX_LF_CINTX_INT_W1S */
 103         reg_count += nix->cints;
 104         /* NIX_LF_CINTX_ENA_W1S */
 105         reg_count += nix->cints;
 106         /* NIX_LF_CINTX_ENA_W1C */
 107         reg_count += nix->cints;
 108
 109         return reg_count;
 110 }
 111
 112 int
 113 roc_nix_lf_reg_dump(struct roc_nix *roc_nix, uint64_t *data)
 114 {
 115         struct nix *nix = roc_nix_to_nix_priv(roc_nix);
 116         uintptr_t nix_lf_base = nix->base;
 117         bool dump_stdout;
 118         uint64_t reg;
 119         uint32_t i;
 120
 121         if (roc_nix == NULL)
 122                 return NIX_ERR_PARAM;
 123
 124         dump_stdout = data ? 0 : 1;
 125
 126         for (i = 0; i < PLT_DIM(nix_lf_reg); i++) {
 127                 reg = plt_read64(nix_lf_base + nix_lf_reg[i].offset);
 128                 if (dump_stdout && reg)
 129                         nix_dump("%32s = 0x%" PRIx64, nix_lf_reg[i].name, reg);
 130                 if (data)
 131                         *data++ = reg;
 132         }
 133
 134         /* NIX_LF_TX_STATX */
 135         for (i = 0; i < nix->lf_tx_stats; i++) {
 136                 reg = plt_read64(nix_lf_base + NIX_LF_TX_STATX(i));
 137                 if (dump_stdout && reg)
 138                         nix_dump("%32s_%d = 0x%" PRIx64, "NIX_LF_TX_STATX", i,
 139                                  reg);
 140                 if (data)
 141                         *data++ = reg;
 142         }
 143
 144         /* NIX_LF_RX_STATX */
 145         for (i = 0; i < nix->lf_rx_stats; i++) {
 146                 reg = plt_read64(nix_lf_base + NIX_LF_RX_STATX(i));
 147                 if (dump_stdout && reg)
 148                         nix_dump("%32s_%d = 0x%" PRIx64, "NIX_LF_RX_STATX", i,
 149                                  reg);
 150                 if (data)
 151                         *data++ = reg;
 152         }
 153
 154         /* NIX_LF_QINTX_CNT*/
 155         for (i = 0; i < nix->qints; i++) {
 156                 reg = plt_read64(nix_lf_base + NIX_LF_QINTX_CNT(i));
 157                 if (dump_stdout && reg)
 158                         nix_dump("%32s_%d = 0x%" PRIx64, "NIX_LF_QINTX_CNT", i,
 159                                  reg);
 160                 if (data)
 161                         *data++ = reg;
 162         }
 163
 164         /* NIX_LF_QINTX_INT */
 165         for (i = 0; i < nix->qints; i++) {
 166                 reg = plt_read64(nix_lf_base + NIX_LF_QINTX_INT(i));
 167                 if (dump_stdout && reg)
 168                         nix_dump("%32s_%d = 0x%" PRIx64, "NIX_LF_QINTX_INT", i,
 169                                  reg);
 170                 if (data)
 171                         *data++ = reg;
 172         }
 173
 174         /* NIX_LF_QINTX_ENA_W1S */
 175         for (i = 0; i < nix->qints; i++) {
 176                 reg = plt_read64(nix_lf_base + NIX_LF_QINTX_ENA_W1S(i));
 177                 if (dump_stdout && reg)
 178                         nix_dump("%32s_%d = 0x%" PRIx64, "NIX_LF_QINTX_ENA_W1S",
 179                                  i, reg);
 180                 if (data)
 181                         *data++ = reg;
 182         }
 183
 184         /* NIX_LF_QINTX_ENA_W1C */
 185         for (i = 0; i < nix->qints; i++) {
 186                 reg = plt_read64(nix_lf_base + NIX_LF_QINTX_ENA_W1C(i));
 187                 if (dump_stdout && reg)
 188                         nix_dump("%32s_%d = 0x%" PRIx64, "NIX_LF_QINTX_ENA_W1C",
 189                                  i, reg);
 190                 if (data)
 191                         *data++ = reg;
 192         }
 193
 194         /* NIX_LF_CINTX_CNT */
 195         for (i = 0; i < nix->cints; i++) {
 196                 reg = plt_read64(nix_lf_base + NIX_LF_CINTX_CNT(i));
 197                 if (dump_stdout && reg)
 198                         nix_dump("%32s_%d = 0x%" PRIx64, "NIX_LF_CINTX_CNT", i,
 199                                  reg);
 200                 if (data)
 201                         *data++ = reg;
 202         }
 203
 204         /* NIX_LF_CINTX_WAIT */
 205         for (i = 0; i < nix->cints; i++) {
 206                 reg = plt_read64(nix_lf_base + NIX_LF_CINTX_WAIT(i));
 207                 if (dump_stdout && reg)
 208                         nix_dump("%32s_%d = 0x%" PRIx64, "NIX_LF_CINTX_WAIT", i,
 209                                  reg);
 210                 if (data)
 211                         *data++ = reg;
 212         }
 213
 214         /* NIX_LF_CINTX_INT */
 215         for (i = 0; i < nix->cints; i++) {
 216                 reg = plt_read64(nix_lf_base + NIX_LF_CINTX_INT(i));
 217                 if (dump_stdout && reg)
 218                         nix_dump("%32s_%d = 0x%" PRIx64, "NIX_LF_CINTX_INT", i,
 219                                  reg);
 220                 if (data)
 221                         *data++ = reg;
 222         }
 223
 224         /* NIX_LF_CINTX_INT_W1S */
 225         for (i = 0; i < nix->cints; i++) {
 226                 reg = plt_read64(nix_lf_base + NIX_LF_CINTX_INT_W1S(i));
 227                 if (dump_stdout && reg)
 228                         nix_dump("%32s_%d = 0x%" PRIx64, "NIX_LF_CINTX_INT_W1S",
 229                                  i, reg);
 230                 if (data)
 231                         *data++ = reg;
 232         }
 233
 234         /* NIX_LF_CINTX_ENA_W1S */
 235         for (i = 0; i < nix->cints; i++) {
 236                 reg = plt_read64(nix_lf_base + NIX_LF_CINTX_ENA_W1S(i));
 237                 if (dump_stdout && reg)
 238                         nix_dump("%32s_%d = 0x%" PRIx64, "NIX_LF_CINTX_ENA_W1S",
 239                                  i, reg);
 240                 if (data)
 241                         *data++ = reg;
 242         }
 243
 244         /* NIX_LF_CINTX_ENA_W1C */
 245         for (i = 0; i < nix->cints; i++) {
 246                 reg = plt_read64(nix_lf_base + NIX_LF_CINTX_ENA_W1C(i));
 247                 if (dump_stdout && reg)
 248                         nix_dump("%32s_%d = 0x%" PRIx64, "NIX_LF_CINTX_ENA_W1C",
 249                                  i, reg);
 250                 if (data)
 251                         *data++ = reg;
 252         }
 253         return 0;
 254 }
 255
 256 static int
 257 nix_q_ctx_get(struct mbox *mbox, uint8_t ctype, uint16_t qid, __io void **ctx_p)
 258 {
 259         int rc;
 260
 261         if (roc_model_is_cn9k()) {
 262                 struct nix_aq_enq_rsp *rsp;
 263                 struct nix_aq_enq_req *aq;
 264                 int rc;
 265
 266                 aq = mbox_alloc_msg_nix_aq_enq(mbox);
 267                 aq->qidx = qid;
 268                 aq->ctype = ctype;
 269                 aq->op = NIX_AQ_INSTOP_READ;
 270
 271                 rc = mbox_process_msg(mbox, (void *)&rsp);
 272                 if (rc)
 273                         return rc;
 274                 if (ctype == NIX_AQ_CTYPE_RQ)
 275                         *ctx_p = &rsp->rq;
 276                 else if (ctype == NIX_AQ_CTYPE_SQ)
 277                         *ctx_p = &rsp->sq;
 278                 else
 279                         *ctx_p = &rsp->cq;
 280         } else {
 281                 struct nix_cn10k_aq_enq_rsp *rsp;
 282                 struct nix_cn10k_aq_enq_req *aq;
 283
 284                 aq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);
 285                 aq->qidx = qid;
 286                 aq->ctype = ctype;
 287                 aq->op = NIX_AQ_INSTOP_READ;
 288
 289                 rc = mbox_process_msg(mbox, (void *)&rsp);
 290                 if (rc)
 291                         return rc;
 292
 293                 if (ctype == NIX_AQ_CTYPE_RQ)
 294                         *ctx_p = &rsp->rq;
 295                 else if (ctype == NIX_AQ_CTYPE_SQ)
 296                         *ctx_p = &rsp->sq;
 297                 else
 298                         *ctx_p = &rsp->cq;
 299         }
 300         return 0;
 301 }
 302
 303 static inline void
 304 nix_cn9k_lf_sq_dump(__io struct nix_sq_ctx_s *ctx, uint32_t *sqb_aura_p)
 305 {
 306         nix_dump("W0: sqe_way_mask \t\t%d\nW0: cq \t\t\t\t%d",
 307                  ctx->sqe_way_mask, ctx->cq);
 308         nix_dump("W0: sdp_mcast \t\t\t%d\nW0: substream \t\t\t0x%03x",
 309                  ctx->sdp_mcast, ctx->substream);
 310         nix_dump("W0: qint_idx \t\t\t%d\nW0: ena \t\t\t%d\n", ctx->qint_idx,
 311                  ctx->ena);
 312
 313         nix_dump("W1: sqb_count \t\t\t%d\nW1: default_chan \t\t%d",
 314                  ctx->sqb_count, ctx->default_chan);
 315         nix_dump("W1: smq_rr_quantum \t\t%d\nW1: sso_ena \t\t\t%d",
 316                  ctx->smq_rr_quantum, ctx->sso_ena);
 317         nix_dump("W1: xoff \t\t\t%d\nW1: cq_ena \t\t\t%d\nW1: smq\t\t\t\t%d\n",
 318                  ctx->xoff, ctx->cq_ena, ctx->smq);
 319
 320         nix_dump("W2: sqe_stype \t\t\t%d\nW2: sq_int_ena \t\t\t%d",
 321                  ctx->sqe_stype, ctx->sq_int_ena);
 322         nix_dump("W2: sq_int  \t\t\t%d\nW2: sqb_aura \t\t\t%d", ctx->sq_int,
 323                  ctx->sqb_aura);
 324         nix_dump("W2: smq_rr_count \t\t%d\n", ctx->smq_rr_count);
 325
 326         nix_dump("W3: smq_next_sq_vld\t\t%d\nW3: smq_pend\t\t\t%d",
 327                  ctx->smq_next_sq_vld, ctx->smq_pend);
 328         nix_dump("W3: smenq_next_sqb_vld  \t%d\nW3: head_offset\t\t\t%d",
 329                  ctx->smenq_next_sqb_vld, ctx->head_offset);
 330         nix_dump("W3: smenq_offset\t\t%d\nW3: tail_offset \t\t%d",
 331                  ctx->smenq_offset, ctx->tail_offset);
 332         nix_dump("W3: smq_lso_segnum \t\t%d\nW3: smq_next_sq \t\t%d",
 333                  ctx->smq_lso_segnum, ctx->smq_next_sq);
 334         nix_dump("W3: mnq_dis \t\t\t%d\nW3: lmt_dis \t\t\t%d", ctx->mnq_dis,
 335                  ctx->lmt_dis);
 336         nix_dump("W3: cq_limit\t\t\t%d\nW3: max_sqe_size\t\t%d\n",
 337                  ctx->cq_limit, ctx->max_sqe_size);
 338
 339         nix_dump("W4: next_sqb \t\t\t0x%" PRIx64 "", ctx->next_sqb);
 340         nix_dump("W5: tail_sqb \t\t\t0x%" PRIx64 "", ctx->tail_sqb);
 341         nix_dump("W6: smenq_sqb \t\t\t0x%" PRIx64 "", ctx->smenq_sqb);
 342         nix_dump("W7: smenq_next_sqb \t\t0x%" PRIx64 "", ctx->smenq_next_sqb);
 343         nix_dump("W8: head_sqb \t\t\t0x%" PRIx64 "", ctx->head_sqb);
 344
 345         nix_dump("W9: vfi_lso_vld \t\t%d\nW9: vfi_lso_vlan1_ins_ena\t%d",
 346                  ctx->vfi_lso_vld, ctx->vfi_lso_vlan1_ins_ena);
 347         nix_dump("W9: vfi_lso_vlan0_ins_ena\t%d\nW9: vfi_lso_mps\t\t\t%d",
 348                  ctx->vfi_lso_vlan0_ins_ena, ctx->vfi_lso_mps);
 349         nix_dump("W9: vfi_lso_sb \t\t\t%d\nW9: vfi_lso_sizem1\t\t%d",
 350                  ctx->vfi_lso_sb, ctx->vfi_lso_sizem1);
 351         nix_dump("W9: vfi_lso_total\t\t%d", ctx->vfi_lso_total);
 352
 353         nix_dump("W10: scm_lso_rem \t\t0x%" PRIx64 "",
 354                  (uint64_t)ctx->scm_lso_rem);
 355         nix_dump("W11: octs \t\t\t0x%" PRIx64 "", (uint64_t)ctx->octs);
 356         nix_dump("W12: pkts \t\t\t0x%" PRIx64 "", (uint64_t)ctx->pkts);
 357         nix_dump("W14: dropped_octs \t\t0x%" PRIx64 "",
 358                  (uint64_t)ctx->drop_octs);
 359         nix_dump("W15: dropped_pkts \t\t0x%" PRIx64 "",
 360                  (uint64_t)ctx->drop_pkts);
 361
 362         *sqb_aura_p = ctx->sqb_aura;
 363 }
 364
 365 static inline void
 366 nix_lf_sq_dump(__io struct nix_cn10k_sq_ctx_s *ctx, uint32_t *sqb_aura_p)
 367 {
 368         nix_dump("W0: sqe_way_mask \t\t%d\nW0: cq \t\t\t\t%d",
 369                  ctx->sqe_way_mask, ctx->cq);
 370         nix_dump("W0: sdp_mcast \t\t\t%d\nW0: substream \t\t\t0x%03x",
 371                  ctx->sdp_mcast, ctx->substream);
 372         nix_dump("W0: qint_idx \t\t\t%d\nW0: ena \t\t\t%d\n", ctx->qint_idx,
 373                  ctx->ena);
 374
 375         nix_dump("W1: sqb_count \t\t\t%d\nW1: default_chan \t\t%d",
 376                  ctx->sqb_count, ctx->default_chan);
 377         nix_dump("W1: smq_rr_weight \t\t%d\nW1: sso_ena \t\t\t%d",
 378                  ctx->smq_rr_weight, ctx->sso_ena);
 379         nix_dump("W1: xoff \t\t\t%d\nW1: cq_ena \t\t\t%d\nW1: smq\t\t\t\t%d\n",
 380                  ctx->xoff, ctx->cq_ena, ctx->smq);
 381
 382         nix_dump("W2: sqe_stype \t\t\t%d\nW2: sq_int_ena \t\t\t%d",
 383                  ctx->sqe_stype, ctx->sq_int_ena);
 384         nix_dump("W2: sq_int  \t\t\t%d\nW2: sqb_aura \t\t\t%d", ctx->sq_int,
 385                  ctx->sqb_aura);
 386         nix_dump("W2: smq_rr_count[ub:lb] \t\t%x:%x\n", ctx->smq_rr_count_ub,
 387                  ctx->smq_rr_count_lb);
 388
 389         nix_dump("W3: smq_next_sq_vld\t\t%d\nW3: smq_pend\t\t\t%d",
 390                  ctx->smq_next_sq_vld, ctx->smq_pend);
 391         nix_dump("W3: smenq_next_sqb_vld  \t%d\nW3: head_offset\t\t\t%d",
 392                  ctx->smenq_next_sqb_vld, ctx->head_offset);
 393         nix_dump("W3: smenq_offset\t\t%d\nW3: tail_offset \t\t%d",
 394                  ctx->smenq_offset, ctx->tail_offset);
 395         nix_dump("W3: smq_lso_segnum \t\t%d\nW3: smq_next_sq \t\t%d",
 396                  ctx->smq_lso_segnum, ctx->smq_next_sq);
 397         nix_dump("W3: mnq_dis \t\t\t%d\nW3: lmt_dis \t\t\t%d", ctx->mnq_dis,
 398                  ctx->lmt_dis);
 399         nix_dump("W3: cq_limit\t\t\t%d\nW3: max_sqe_size\t\t%d\n",
 400                  ctx->cq_limit, ctx->max_sqe_size);
 401
 402         nix_dump("W4: next_sqb \t\t\t0x%" PRIx64 "", ctx->next_sqb);
 403         nix_dump("W5: tail_sqb \t\t\t0x%" PRIx64 "", ctx->tail_sqb);
 404         nix_dump("W6: smenq_sqb \t\t\t0x%" PRIx64 "", ctx->smenq_sqb);
 405         nix_dump("W7: smenq_next_sqb \t\t0x%" PRIx64 "", ctx->smenq_next_sqb);
 406         nix_dump("W8: head_sqb \t\t\t0x%" PRIx64 "", ctx->head_sqb);
 407
 408         nix_dump("W9: vfi_lso_vld \t\t%d\nW9: vfi_lso_vlan1_ins_ena\t%d",
 409                  ctx->vfi_lso_vld, ctx->vfi_lso_vlan1_ins_ena);
 410         nix_dump("W9: vfi_lso_vlan0_ins_ena\t%d\nW9: vfi_lso_mps\t\t\t%d",
 411                  ctx->vfi_lso_vlan0_ins_ena, ctx->vfi_lso_mps);
 412         nix_dump("W9: vfi_lso_sb \t\t\t%d\nW9: vfi_lso_sizem1\t\t%d",
 413                  ctx->vfi_lso_sb, ctx->vfi_lso_sizem1);
 414         nix_dump("W9: vfi_lso_total\t\t%d", ctx->vfi_lso_total);
 415
 416         nix_dump("W10: scm_lso_rem \t\t0x%" PRIx64 "",
 417                  (uint64_t)ctx->scm_lso_rem);
 418         nix_dump("W11: octs \t\t\t0x%" PRIx64 "", (uint64_t)ctx->octs);
 419         nix_dump("W12: pkts \t\t\t0x%" PRIx64 "", (uint64_t)ctx->pkts);
 420         nix_dump("W14: dropped_octs \t\t0x%" PRIx64 "",
 421                  (uint64_t)ctx->drop_octs);
 422         nix_dump("W15: dropped_pkts \t\t0x%" PRIx64 "",
 423                  (uint64_t)ctx->drop_pkts);
 424
 425         *sqb_aura_p = ctx->sqb_aura;
 426 }
 427
 428 static inline void
 429 nix_cn9k_lf_rq_dump(__io struct nix_rq_ctx_s *ctx)
 430 {
 431         nix_dump("W0: wqe_aura \t\t\t%d\nW0: substream \t\t\t0x%03x",
 432                  ctx->wqe_aura, ctx->substream);
 433         nix_dump("W0: cq \t\t\t\t%d\nW0: ena_wqwd \t\t\t%d", ctx->cq,
 434                  ctx->ena_wqwd);
 435         nix_dump("W0: ipsech_ena \t\t\t%d\nW0: sso_ena \t\t\t%d",
 436                  ctx->ipsech_ena, ctx->sso_ena);
 437         nix_dump("W0: ena \t\t\t%d\n", ctx->ena);
 438
 439         nix_dump("W1: lpb_drop_ena \t\t%d\nW1: spb_drop_ena \t\t%d",
 440                  ctx->lpb_drop_ena, ctx->spb_drop_ena);
 441         nix_dump("W1: xqe_drop_ena \t\t%d\nW1: wqe_caching \t\t%d",
 442                  ctx->xqe_drop_ena, ctx->wqe_caching);
 443         nix_dump("W1: pb_caching \t\t\t%d\nW1: sso_tt \t\t\t%d",
 444                  ctx->pb_caching, ctx->sso_tt);
 445         nix_dump("W1: sso_grp \t\t\t%d\nW1: lpb_aura \t\t\t%d", ctx->sso_grp,
 446                  ctx->lpb_aura);
 447         nix_dump("W1: spb_aura \t\t\t%d\n", ctx->spb_aura);
 448
 449         nix_dump("W2: xqe_hdr_split \t\t%d\nW2: xqe_imm_copy \t\t%d",
 450                  ctx->xqe_hdr_split, ctx->xqe_imm_copy);
 451         nix_dump("W2: xqe_imm_size \t\t%d\nW2: later_skip \t\t\t%d",
 452                  ctx->xqe_imm_size, ctx->later_skip);
 453         nix_dump("W2: first_skip \t\t\t%d\nW2: lpb_sizem1 \t\t\t%d",
 454                  ctx->first_skip, ctx->lpb_sizem1);
 455         nix_dump("W2: spb_ena \t\t\t%d\nW2: wqe_skip \t\t\t%d", ctx->spb_ena,
 456                  ctx->wqe_skip);
 457         nix_dump("W2: spb_sizem1 \t\t\t%d\n", ctx->spb_sizem1);
 458
 459         nix_dump("W3: spb_pool_pass \t\t%d\nW3: spb_pool_drop \t\t%d",
 460                  ctx->spb_pool_pass, ctx->spb_pool_drop);
 461         nix_dump("W3: spb_aura_pass \t\t%d\nW3: spb_aura_drop \t\t%d",
 462                  ctx->spb_aura_pass, ctx->spb_aura_drop);
 463         nix_dump("W3: wqe_pool_pass \t\t%d\nW3: wqe_pool_drop \t\t%d",
 464                  ctx->wqe_pool_pass, ctx->wqe_pool_drop);
 465         nix_dump("W3: xqe_pass \t\t\t%d\nW3: xqe_drop \t\t\t%d\n",
 466                  ctx->xqe_pass, ctx->xqe_drop);
 467
 468         nix_dump("W4: qint_idx \t\t\t%d\nW4: rq_int_ena \t\t\t%d",
 469                  ctx->qint_idx, ctx->rq_int_ena);
 470         nix_dump("W4: rq_int \t\t\t%d\nW4: lpb_pool_pass \t\t%d", ctx->rq_int,
 471                  ctx->lpb_pool_pass);
 472         nix_dump("W4: lpb_pool_drop \t\t%d\nW4: lpb_aura_pass \t\t%d",
 473                  ctx->lpb_pool_drop, ctx->lpb_aura_pass);
 474         nix_dump("W4: lpb_aura_drop \t\t%d\n", ctx->lpb_aura_drop);
 475
 476         nix_dump("W5: flow_tagw \t\t\t%d\nW5: bad_utag \t\t\t%d",
 477                  ctx->flow_tagw, ctx->bad_utag);
 478         nix_dump("W5: good_utag \t\t\t%d\nW5: ltag \t\t\t%d\n", ctx->good_utag,
 479                  ctx->ltag);
 480
 481         nix_dump("W6: octs \t\t\t0x%" PRIx64 "", (uint64_t)ctx->octs);
 482         nix_dump("W7: pkts \t\t\t0x%" PRIx64 "", (uint64_t)ctx->pkts);
 483         nix_dump("W8: drop_octs \t\t\t0x%" PRIx64 "", (uint64_t)ctx->drop_octs);
 484         nix_dump("W9: drop_pkts \t\t\t0x%" PRIx64 "", (uint64_t)ctx->drop_pkts);
 485         nix_dump("W10: re_pkts \t\t\t0x%" PRIx64 "\n", (uint64_t)ctx->re_pkts);
 486 }
 487
 488 static inline void
 489 nix_lf_rq_dump(__io struct nix_cn10k_rq_ctx_s *ctx)
 490 {
 491         nix_dump("W0: wqe_aura \t\t\t%d\nW0: len_ol3_dis \t\t\t%d",
 492                  ctx->wqe_aura, ctx->len_ol3_dis);
 493         nix_dump("W0: len_ol4_dis \t\t\t%d\nW0: len_il3_dis \t\t\t%d",
 494                  ctx->len_ol4_dis, ctx->len_il3_dis);
 495         nix_dump("W0: len_il4_dis \t\t\t%d\nW0: csum_ol4_dis \t\t\t%d",
 496                  ctx->len_il4_dis, ctx->csum_ol4_dis);
 497         nix_dump("W0: csum_ol3_dis \t\t\t%d\nW0: lenerr_dis \t\t\t%d",
 498                  ctx->csum_ol4_dis, ctx->lenerr_dis);
 499         nix_dump("W0: cq \t\t\t\t%d\nW0: ena_wqwd \t\t\t%d", ctx->cq,
 500                  ctx->ena_wqwd);
 501         nix_dump("W0: ipsech_ena \t\t\t%d\nW0: sso_ena \t\t\t%d",
 502                  ctx->ipsech_ena, ctx->sso_ena);
 503         nix_dump("W0: ena \t\t\t%d\n", ctx->ena);
 504
 505         nix_dump("W1: chi_ena \t\t%d\nW1: ipsecd_drop_en \t\t%d", ctx->chi_ena,
 506                  ctx->ipsecd_drop_en);
 507         nix_dump("W1: pb_stashing \t\t\t%d", ctx->pb_stashing);
 508         nix_dump("W1: lpb_drop_ena \t\t%d\nW1: spb_drop_ena \t\t%d",
 509                  ctx->lpb_drop_ena, ctx->spb_drop_ena);
 510         nix_dump("W1: xqe_drop_ena \t\t%d\nW1: wqe_caching \t\t%d",
 511                  ctx->xqe_drop_ena, ctx->wqe_caching);
 512         nix_dump("W1: pb_caching \t\t\t%d\nW1: sso_tt \t\t\t%d",
 513                  ctx->pb_caching, ctx->sso_tt);
 514         nix_dump("W1: sso_grp \t\t\t%d\nW1: lpb_aura \t\t\t%d", ctx->sso_grp,
 515                  ctx->lpb_aura);
 516         nix_dump("W1: spb_aura \t\t\t%d\n", ctx->spb_aura);
 517
 518         nix_dump("W2: xqe_hdr_split \t\t%d\nW2: xqe_imm_copy \t\t%d",
 519                  ctx->xqe_hdr_split, ctx->xqe_imm_copy);
 520         nix_dump("W2: xqe_imm_size \t\t%d\nW2: later_skip \t\t\t%d",
 521                  ctx->xqe_imm_size, ctx->later_skip);
 522         nix_dump("W2: first_skip \t\t\t%d\nW2: lpb_sizem1 \t\t\t%d",
 523                  ctx->first_skip, ctx->lpb_sizem1);
 524         nix_dump("W2: spb_ena \t\t\t%d\nW2: wqe_skip \t\t\t%d", ctx->spb_ena,
 525                  ctx->wqe_skip);
 526         nix_dump("W2: spb_sizem1 \t\t\t%d\nW2: policer_ena \t\t\t%d",
 527                  ctx->spb_sizem1, ctx->policer_ena);
 528         nix_dump("W2: band_prof_id \t\t\t%d", ctx->band_prof_id);
 529
 530         nix_dump("W3: spb_pool_pass \t\t%d\nW3: spb_pool_drop \t\t%d",
 531                  ctx->spb_pool_pass, ctx->spb_pool_drop);
 532         nix_dump("W3: spb_aura_pass \t\t%d\nW3: spb_aura_drop \t\t%d",
 533                  ctx->spb_aura_pass, ctx->spb_aura_drop);
 534         nix_dump("W3: wqe_pool_pass \t\t%d\nW3: wqe_pool_drop \t\t%d",
 535                  ctx->wqe_pool_pass, ctx->wqe_pool_drop);
 536         nix_dump("W3: xqe_pass \t\t\t%d\nW3: xqe_drop \t\t\t%d\n",
 537                  ctx->xqe_pass, ctx->xqe_drop);
 538
 539         nix_dump("W4: qint_idx \t\t\t%d\nW4: rq_int_ena \t\t\t%d",
 540                  ctx->qint_idx, ctx->rq_int_ena);
 541         nix_dump("W4: rq_int \t\t\t%d\nW4: lpb_pool_pass \t\t%d", ctx->rq_int,
 542                  ctx->lpb_pool_pass);
 543         nix_dump("W4: lpb_pool_drop \t\t%d\nW4: lpb_aura_pass \t\t%d",
 544                  ctx->lpb_pool_drop, ctx->lpb_aura_pass);
 545         nix_dump("W4: lpb_aura_drop \t\t%d\n", ctx->lpb_aura_drop);
 546
 547         nix_dump("W5: vwqe_skip \t\t\t%d\nW5: max_vsize_exp \t\t\t%d",
 548                  ctx->vwqe_skip, ctx->max_vsize_exp);
 549         nix_dump("W5: vtime_wait \t\t\t%d\nW5: vwqe_ena \t\t\t%d",
 550                  ctx->vtime_wait, ctx->max_vsize_exp);
 551         nix_dump("W5: ipsec_vwqe \t\t\t%d", ctx->ipsec_vwqe);
 552         nix_dump("W5: flow_tagw \t\t\t%d\nW5: bad_utag \t\t\t%d",
 553                  ctx->flow_tagw, ctx->bad_utag);
 554         nix_dump("W5: good_utag \t\t\t%d\nW5: ltag \t\t\t%d\n", ctx->good_utag,
 555                  ctx->ltag);
 556
 557         nix_dump("W6: octs \t\t\t0x%" PRIx64 "", (uint64_t)ctx->octs);
 558         nix_dump("W7: pkts \t\t\t0x%" PRIx64 "", (uint64_t)ctx->pkts);
 559         nix_dump("W8: drop_octs \t\t\t0x%" PRIx64 "", (uint64_t)ctx->drop_octs);
 560         nix_dump("W9: drop_pkts \t\t\t0x%" PRIx64 "", (uint64_t)ctx->drop_pkts);
 561         nix_dump("W10: re_pkts \t\t\t0x%" PRIx64 "\n", (uint64_t)ctx->re_pkts);
 562 }
 563
 564 static inline void
 565 nix_lf_cq_dump(__io struct nix_cq_ctx_s *ctx)
 566 {
 567         nix_dump("W0: base \t\t\t0x%" PRIx64 "\n", ctx->base);
 568
 569         nix_dump("W1: wrptr \t\t\t%" PRIx64 "", (uint64_t)ctx->wrptr);
 570         nix_dump("W1: avg_con \t\t\t%d\nW1: cint_idx \t\t\t%d", ctx->avg_con,
 571                  ctx->cint_idx);
 572         nix_dump("W1: cq_err \t\t\t%d\nW1: qint_idx \t\t\t%d", ctx->cq_err,
 573                  ctx->qint_idx);
 574         nix_dump("W1: bpid  \t\t\t%d\nW1: bp_ena \t\t\t%d\n", ctx->bpid,
 575                  ctx->bp_ena);
 576
 577         nix_dump("W2: update_time \t\t%d\nW2: avg_level \t\t\t%d",
 578                  ctx->update_time, ctx->avg_level);
 579         nix_dump("W2: head \t\t\t%d\nW2: tail \t\t\t%d\n", ctx->head,
 580                  ctx->tail);
 581
 582         nix_dump("W3: cq_err_int_ena \t\t%d\nW3: cq_err_int \t\t\t%d",
 583                  ctx->cq_err_int_ena, ctx->cq_err_int);
 584         nix_dump("W3: qsize \t\t\t%d\nW3: caching \t\t\t%d", ctx->qsize,
 585                  ctx->caching);
 586         nix_dump("W3: substream \t\t\t0x%03x\nW3: ena \t\t\t%d", ctx->substream,
 587                  ctx->ena);
 588         nix_dump("W3: drop_ena \t\t\t%d\nW3: drop \t\t\t%d", ctx->drop_ena,
 589                  ctx->drop);
 590         nix_dump("W3: bp \t\t\t\t%d\n", ctx->bp);
 591 }
 592
 593 int
 594 roc_nix_queues_ctx_dump(struct roc_nix *roc_nix)
 595 {
 596         struct nix *nix = roc_nix_to_nix_priv(roc_nix);
 597         int rc = -1, q, rq = nix->nb_rx_queues;
 598         struct mbox *mbox = (&nix->dev)->mbox;
 599         struct npa_aq_enq_rsp *npa_rsp;
 600         struct npa_aq_enq_req *npa_aq;
 601         volatile void *ctx;
 602         int sq = nix->nb_tx_queues;
 603         struct npa_lf *npa_lf;
 604         uint32_t sqb_aura;
 605
 606         npa_lf = idev_npa_obj_get();
 607         if (npa_lf == NULL)
 608                 return NPA_ERR_DEVICE_NOT_BOUNDED;
 609
 610         for (q = 0; q < rq; q++) {
 611                 rc = nix_q_ctx_get(mbox, NIX_AQ_CTYPE_CQ, q, &ctx);
 612                 if (rc) {
 613                         plt_err("Failed to get cq context");
 614                         goto fail;
 615                 }
 616                 nix_dump("============== port=%d cq=%d ===============",
 617                          roc_nix->port_id, q);
 618                 nix_lf_cq_dump(ctx);
 619         }
 620
 621         for (q = 0; q < rq; q++) {
 622                 rc = nix_q_ctx_get(mbox, NIX_AQ_CTYPE_RQ, q, &ctx);
 623                 if (rc) {
 624                         plt_err("Failed to get rq context");
 625                         goto fail;
 626                 }
 627                 nix_dump("============== port=%d rq=%d ===============",
 628                          roc_nix->port_id, q);
 629                 if (roc_model_is_cn9k())
 630                         nix_cn9k_lf_rq_dump(ctx);
 631                 else
 632                         nix_lf_rq_dump(ctx);
 633         }
 634
 635         for (q = 0; q < sq; q++) {
 636                 rc = nix_q_ctx_get(mbox, NIX_AQ_CTYPE_SQ, q, &ctx);
 637                 if (rc) {
 638                         plt_err("Failed to get sq context");
 639                         goto fail;
 640                 }
 641                 nix_dump("============== port=%d sq=%d ===============",
 642                          roc_nix->port_id, q);
 643                 if (roc_model_is_cn9k())
 644                         nix_cn9k_lf_sq_dump(ctx, &sqb_aura);
 645                 else
 646                         nix_lf_sq_dump(ctx, &sqb_aura);
 647
 648                 if (!npa_lf) {
 649                         plt_err("NPA LF does not exist");
 650                         continue;
 651                 }
 652
 653                 /* Dump SQB Aura minimal info */
 654                 npa_aq = mbox_alloc_msg_npa_aq_enq(npa_lf->mbox);
 655                 if (npa_aq == NULL)
 656                         return -ENOSPC;
 657                 npa_aq->aura_id = sqb_aura;
 658                 npa_aq->ctype = NPA_AQ_CTYPE_AURA;
 659                 npa_aq->op = NPA_AQ_INSTOP_READ;
 660
 661                 rc = mbox_process_msg(npa_lf->mbox, (void *)&npa_rsp);
 662                 if (rc) {
 663                         plt_err("Failed to get sq's sqb_aura context");
 664                         continue;
 665                 }
 666
 667                 nix_dump("\nSQB Aura W0: Pool addr\t\t0x%" PRIx64 "",
 668                          npa_rsp->aura.pool_addr);
 669                 nix_dump("SQB Aura W1: ena\t\t\t%d", npa_rsp->aura.ena);
 670                 nix_dump("SQB Aura W2: count\t\t%" PRIx64 "",
 671                          (uint64_t)npa_rsp->aura.count);
 672                 nix_dump("SQB Aura W3: limit\t\t%" PRIx64 "",
 673                          (uint64_t)npa_rsp->aura.limit);
 674                 nix_dump("SQB Aura W3: fc_ena\t\t%d", npa_rsp->aura.fc_ena);
 675                 nix_dump("SQB Aura W4: fc_addr\t\t0x%" PRIx64 "\n",
 676                          npa_rsp->aura.fc_addr);
 677         }
 678
 679 fail:
 680         return rc;
 681 }
 682
 683 /* Dumps struct nix_cqe_hdr_s and union nix_rx_parse_u */
 684 void
 685 roc_nix_cqe_dump(const struct nix_cqe_hdr_s *cq)
 686 {
 687         const union nix_rx_parse_u *rx =
 688                 (const union nix_rx_parse_u *)((const uint64_t *)cq + 1);
 689
 690         nix_dump("tag \t\t0x%x\tq \t\t%d\t\tnode \t\t%d\tcqe_type \t%d",
 691                  cq->tag, cq->q, cq->node, cq->cqe_type);
 692
 693         nix_dump("W0: chan \t%d\t\tdesc_sizem1 \t%d", rx->chan,
 694                  rx->desc_sizem1);
 695         nix_dump("W0: imm_copy \t%d\t\texpress \t%d", rx->imm_copy,
 696                  rx->express);
 697         nix_dump("W0: wqwd \t%d\t\terrlev \t\t%d\t\terrcode \t%d", rx->wqwd,
 698                  rx->errlev, rx->errcode);
 699         nix_dump("W0: latype \t%d\t\tlbtype \t\t%d\t\tlctype \t\t%d",
 700                  rx->latype, rx->lbtype, rx->lctype);
 701         nix_dump("W0: ldtype \t%d\t\tletype \t\t%d\t\tlftype \t\t%d",
 702                  rx->ldtype, rx->letype, rx->lftype);
 703         nix_dump("W0: lgtype \t%d \t\tlhtype \t\t%d", rx->lgtype, rx->lhtype);
 704
 705         nix_dump("W1: pkt_lenm1 \t%d", rx->pkt_lenm1);
 706         nix_dump("W1: l2m \t%d\t\tl2b \t\t%d\t\tl3m \t\t%d\tl3b \t\t%d",
 707                  rx->l2m, rx->l2b, rx->l3m, rx->l3b);
 708         nix_dump("W1: vtag0_valid %d\t\tvtag0_gone \t%d", rx->vtag0_valid,
 709                  rx->vtag0_gone);
 710         nix_dump("W1: vtag1_valid %d\t\tvtag1_gone \t%d", rx->vtag1_valid,
 711                  rx->vtag1_gone);
 712         nix_dump("W1: pkind \t%d", rx->pkind);
 713         nix_dump("W1: vtag0_tci \t%d\t\tvtag1_tci \t%d", rx->vtag0_tci,
 714                  rx->vtag1_tci);
 715
 716         nix_dump("W2: laflags \t%d\t\tlbflags\t\t%d\t\tlcflags \t%d",
 717                  rx->laflags, rx->lbflags, rx->lcflags);
 718         nix_dump("W2: ldflags \t%d\t\tleflags\t\t%d\t\tlfflags \t%d",
 719                  rx->ldflags, rx->leflags, rx->lfflags);
 720         nix_dump("W2: lgflags \t%d\t\tlhflags \t%d", rx->lgflags, rx->lhflags);
 721
 722         nix_dump("W3: eoh_ptr \t%d\t\twqe_aura \t%d\t\tpb_aura \t%d",
 723                  rx->eoh_ptr, rx->wqe_aura, rx->pb_aura);
 724         nix_dump("W3: match_id \t%d", rx->match_id);
 725
 726         nix_dump("W4: laptr \t%d\t\tlbptr \t\t%d\t\tlcptr \t\t%d", rx->laptr,
 727                  rx->lbptr, rx->lcptr);
 728         nix_dump("W4: ldptr \t%d\t\tleptr \t\t%d\t\tlfptr \t\t%d", rx->ldptr,
 729                  rx->leptr, rx->lfptr);
 730         nix_dump("W4: lgptr \t%d\t\tlhptr \t\t%d", rx->lgptr, rx->lhptr);
 731
 732         nix_dump("W5: vtag0_ptr \t%d\t\tvtag1_ptr \t%d\t\tflow_key_alg \t%d",
 733                  rx->vtag0_ptr, rx->vtag1_ptr, rx->flow_key_alg);
 734 }
 735
 736 void
 737 roc_nix_rq_dump(struct roc_nix_rq *rq)
 738 {
 739         nix_dump("nix_rq@%p", rq);
 740         nix_dump("  qid = %d", rq->qid);
 741         nix_dump("  aura_handle = 0x%" PRIx64 "", rq->aura_handle);
 742         nix_dump("  ipsec_ena = %d", rq->ipsech_ena);
 743         nix_dump("  first_skip = %d", rq->first_skip);
 744         nix_dump("  later_skip = %d", rq->later_skip);
 745         nix_dump("  lpb_size = %d", rq->lpb_size);
 746         nix_dump("  sso_ena = %d", rq->sso_ena);
 747         nix_dump("  tag_mask = %d", rq->tag_mask);
 748         nix_dump("  flow_tag_width = %d", rq->flow_tag_width);
 749         nix_dump("  tt = %d", rq->tt);
 750         nix_dump("  hwgrp = %d", rq->hwgrp);
 751         nix_dump("  vwqe_ena = %d", rq->vwqe_ena);
 752         nix_dump("  vwqe_first_skip = %d", rq->vwqe_first_skip);
 753         nix_dump("  vwqe_max_sz_exp = %d", rq->vwqe_max_sz_exp);
 754         nix_dump("  vwqe_wait_tmo = %ld", rq->vwqe_wait_tmo);
 755         nix_dump("  vwqe_aura_handle = %ld", rq->vwqe_aura_handle);
 756         nix_dump("  roc_nix = %p", rq->roc_nix);
 757 }
 758
 759 void
 760 roc_nix_cq_dump(struct roc_nix_cq *cq)
 761 {
 762         nix_dump("nix_cq@%p", cq);
 763         nix_dump("  qid = %d", cq->qid);
 764         nix_dump("  qnb_desc = %d", cq->nb_desc);
 765         nix_dump("  roc_nix = %p", cq->roc_nix);
 766         nix_dump("  door = 0x%" PRIx64 "", cq->door);
 767         nix_dump("  status = %p", cq->status);
 768         nix_dump("  wdata = 0x%" PRIx64 "", cq->wdata);
 769         nix_dump("  desc_base = %p", cq->desc_base);
 770         nix_dump("  qmask = 0x%" PRIx32 "", cq->qmask);
 771 }
 772
 773 void
 774 roc_nix_sq_dump(struct roc_nix_sq *sq)
 775 {
 776         nix_dump("nix_sq@%p", sq);
 777         nix_dump("  qid = %d", sq->qid);
 778         nix_dump("  max_sqe_sz = %d", sq->max_sqe_sz);
 779         nix_dump("  nb_desc = %d", sq->nb_desc);
 780         nix_dump("  sqes_per_sqb_log2 = %d", sq->sqes_per_sqb_log2);
 781         nix_dump("  roc_nix= %p", sq->roc_nix);
 782         nix_dump("  aura_handle = 0x%" PRIx64 "", sq->aura_handle);
 783         nix_dump("  nb_sqb_bufs_adj = %d", sq->nb_sqb_bufs_adj);
 784         nix_dump("  nb_sqb_bufs = %d", sq->nb_sqb_bufs);
 785         nix_dump("  io_addr = 0x%" PRIx64 "", sq->io_addr);
 786         nix_dump("  lmt_addr = %p", sq->lmt_addr);
 787         nix_dump("  sqe_mem = %p", sq->sqe_mem);
 788         nix_dump("  fc = %p", sq->fc);
 789 };
 790
 791 static uint8_t
 792 nix_tm_reg_dump_prep(uint16_t hw_lvl, uint16_t schq, uint16_t link,
 793                      uint64_t *reg, char regstr[][NIX_REG_NAME_SZ])
 794 {
 795         uint8_t k = 0;
 796
 797         switch (hw_lvl) {
 798         case NIX_TXSCH_LVL_SMQ:
 799                 reg[k] = NIX_AF_SMQX_CFG(schq);
 800                 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_SMQ[%u]_CFG",
 801                          schq);
 802
 803                 reg[k] = NIX_AF_MDQX_PARENT(schq);
 804                 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_MDQ[%u]_PARENT",
 805                          schq);
 806
 807                 reg[k] = NIX_AF_MDQX_SCHEDULE(schq);
 808                 snprintf(regstr[k++], NIX_REG_NAME_SZ,
 809                          "NIX_AF_MDQ[%u]_SCHEDULE", schq);
 810
 811                 reg[k] = NIX_AF_MDQX_PIR(schq);
 812                 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_MDQ[%u]_PIR",
 813                          schq);
 814
 815                 reg[k] = NIX_AF_MDQX_CIR(schq);
 816                 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_MDQ[%u]_CIR",
 817                          schq);
 818
 819                 reg[k] = NIX_AF_MDQX_SHAPE(schq);
 820                 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_MDQ[%u]_SHAPE",
 821                          schq);
 822
 823                 reg[k] = NIX_AF_MDQX_SW_XOFF(schq);
 824                 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_MDQ[%u]_SW_XOFF",
 825                          schq);
 826                 break;
 827         case NIX_TXSCH_LVL_TL4:
 828                 reg[k] = NIX_AF_TL4X_PARENT(schq);
 829                 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL4[%u]_PARENT",
 830                          schq);
 831
 832                 reg[k] = NIX_AF_TL4X_TOPOLOGY(schq);
 833                 snprintf(regstr[k++], NIX_REG_NAME_SZ,
 834                          "NIX_AF_TL4[%u]_TOPOLOGY", schq);
 835
 836                 reg[k] = NIX_AF_TL4X_SDP_LINK_CFG(schq);
 837                 snprintf(regstr[k++], NIX_REG_NAME_SZ,
 838                          "NIX_AF_TL4[%u]_SDP_LINK_CFG", schq);
 839
 840                 reg[k] = NIX_AF_TL4X_SCHEDULE(schq);
 841                 snprintf(regstr[k++], NIX_REG_NAME_SZ,
 842                          "NIX_AF_TL4[%u]_SCHEDULE", schq);
 843
 844                 reg[k] = NIX_AF_TL4X_PIR(schq);
 845                 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL4[%u]_PIR",
 846                          schq);
 847
 848                 reg[k] = NIX_AF_TL4X_CIR(schq);
 849                 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL4[%u]_CIR",
 850                          schq);
 851
 852                 reg[k] = NIX_AF_TL4X_SHAPE(schq);
 853                 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL4[%u]_SHAPE",
 854                          schq);
 855
 856                 reg[k] = NIX_AF_TL4X_SW_XOFF(schq);
 857                 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL4[%u]_SW_XOFF",
 858                          schq);
 859                 break;
 860         case NIX_TXSCH_LVL_TL3:
 861                 reg[k] = NIX_AF_TL3X_PARENT(schq);
 862                 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL3[%u]_PARENT",
 863                          schq);
 864
 865                 reg[k] = NIX_AF_TL3X_TOPOLOGY(schq);
 866                 snprintf(regstr[k++], NIX_REG_NAME_SZ,
 867                          "NIX_AF_TL3[%u]_TOPOLOGY", schq);
 868
 869                 reg[k] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, link);
 870                 snprintf(regstr[k++], NIX_REG_NAME_SZ,
 871                          "NIX_AF_TL3_TL2[%u]_LINK[%u]_CFG", schq, link);
 872
 873                 reg[k] = NIX_AF_TL3X_SCHEDULE(schq);
 874                 snprintf(regstr[k++], NIX_REG_NAME_SZ,
 875                          "NIX_AF_TL3[%u]_SCHEDULE", schq);
 876
 877                 reg[k] = NIX_AF_TL3X_PIR(schq);
 878                 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL3[%u]_PIR",
 879                          schq);
 880
 881                 reg[k] = NIX_AF_TL3X_CIR(schq);
 882                 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL3[%u]_CIR",
 883                          schq);
 884
 885                 reg[k] = NIX_AF_TL3X_SHAPE(schq);
 886                 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL3[%u]_SHAPE",
 887                          schq);
 888
 889                 reg[k] = NIX_AF_TL3X_SW_XOFF(schq);
 890                 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL3[%u]_SW_XOFF",
 891                          schq);
 892                 break;
 893         case NIX_TXSCH_LVL_TL2:
 894                 reg[k] = NIX_AF_TL2X_PARENT(schq);
 895                 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL2[%u]_PARENT",
 896                          schq);
 897
 898                 reg[k] = NIX_AF_TL2X_TOPOLOGY(schq);
 899                 snprintf(regstr[k++], NIX_REG_NAME_SZ,
 900                          "NIX_AF_TL2[%u]_TOPOLOGY", schq);
 901
 902                 reg[k] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, link);
 903                 snprintf(regstr[k++], NIX_REG_NAME_SZ,
 904                          "NIX_AF_TL3_TL2[%u]_LINK[%u]_CFG", schq, link);
 905
 906                 reg[k] = NIX_AF_TL2X_SCHEDULE(schq);
 907                 snprintf(regstr[k++], NIX_REG_NAME_SZ,
 908                          "NIX_AF_TL2[%u]_SCHEDULE", schq);
 909
 910                 reg[k] = NIX_AF_TL2X_PIR(schq);
 911                 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL2[%u]_PIR",
 912                          schq);
 913
 914                 reg[k] = NIX_AF_TL2X_CIR(schq);
 915                 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL2[%u]_CIR",
 916                          schq);
 917
 918                 reg[k] = NIX_AF_TL2X_SHAPE(schq);
 919                 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL2[%u]_SHAPE",
 920                          schq);
 921
 922                 reg[k] = NIX_AF_TL2X_SW_XOFF(schq);
 923                 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL2[%u]_SW_XOFF",
 924                          schq);
 925                 break;
 926         case NIX_TXSCH_LVL_TL1:
 927
 928                 reg[k] = NIX_AF_TL1X_TOPOLOGY(schq);
 929                 snprintf(regstr[k++], NIX_REG_NAME_SZ,
 930                          "NIX_AF_TL1[%u]_TOPOLOGY", schq);
 931
 932                 reg[k] = NIX_AF_TL1X_SCHEDULE(schq);
 933                 snprintf(regstr[k++], NIX_REG_NAME_SZ,
 934                          "NIX_AF_TL1[%u]_SCHEDULE", schq);
 935
 936                 reg[k] = NIX_AF_TL1X_CIR(schq);
 937                 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL1[%u]_CIR",
 938                          schq);
 939
 940                 reg[k] = NIX_AF_TL1X_SW_XOFF(schq);
 941                 snprintf(regstr[k++], NIX_REG_NAME_SZ, "NIX_AF_TL1[%u]_SW_XOFF",
 942                          schq);
 943
 944                 reg[k] = NIX_AF_TL1X_DROPPED_PACKETS(schq);
 945                 snprintf(regstr[k++], NIX_REG_NAME_SZ,
 946                          "NIX_AF_TL1[%u]_DROPPED_PACKETS", schq);
 947                 break;
 948         default:
 949                 break;
 950         }
 951
 952         if (k > MAX_REGS_PER_MBOX_MSG) {
 953                 nix_dump("\t!!!NIX TM Registers request overflow!!!");
 954                 return 0;
 955         }
 956         return k;
 957 }
 958
 959 static void
 960 nix_tm_dump_lvl(struct nix *nix, struct nix_tm_node_list *list, uint8_t hw_lvl)
 961 {
 962         char regstr[MAX_REGS_PER_MBOX_MSG * 2][NIX_REG_NAME_SZ];
 963         uint64_t reg[MAX_REGS_PER_MBOX_MSG * 2];
 964         struct mbox *mbox = (&nix->dev)->mbox;
 965         struct nix_txschq_config *req, *rsp;
 966         const char *lvlstr, *parent_lvlstr;
 967         struct nix_tm_node *node, *parent;
 968         struct nix_tm_node *root = NULL;
 969         uint32_t schq, parent_schq;
 970         bool found = false;
 971         uint8_t j, k, rc;
 972
 973         TAILQ_FOREACH(node, list, node) {
 974                 if (node->hw_lvl != hw_lvl)
 975                         continue;
 976
 977                 found = true;
 978                 parent = node->parent;
 979                 if (hw_lvl == NIX_TXSCH_LVL_CNT) {
 980                         lvlstr = "SQ";
 981                         schq = node->id;
 982                 } else {
 983                         lvlstr = nix_tm_hwlvl2str(node->hw_lvl);
 984                         schq = node->hw_id;
 985                 }
 986
 987                 if (parent) {
 988                         parent_schq = parent->hw_id;
 989                         parent_lvlstr = nix_tm_hwlvl2str(parent->hw_lvl);
 990                 } else if (node->hw_lvl == NIX_TXSCH_LVL_TL1) {
 991                         parent_schq = nix->tx_link;
 992                         parent_lvlstr = "LINK";
 993                 } else {
 994                         parent_schq = node->parent_hw_id;
 995                         parent_lvlstr = nix_tm_hwlvl2str(node->hw_lvl + 1);
 996                 }
 997
 998                 nix_dump("\t(%p%s) %s_%d->%s_%d", node,
 999                          node->child_realloc ? "[CR]" : "", lvlstr, schq,
1000                          parent_lvlstr, parent_schq);
1001
1002                 if (!(node->flags & NIX_TM_NODE_HWRES))
1003                         continue;
1004
1005                 /* Need to dump TL1 when root is TL2 */
1006                 if (node->hw_lvl == nix->tm_root_lvl)
1007                         root = node;
1008
1009                 /* Dump registers only when HWRES is present */
1010                 k = nix_tm_reg_dump_prep(node->hw_lvl, schq, nix->tx_link, reg,
1011                                          regstr);
1012                 if (!k)
1013                         continue;
1014
1015                 req = mbox_alloc_msg_nix_txschq_cfg(mbox);
1016                 req->read = 1;
1017                 req->lvl = node->hw_lvl;
1018                 req->num_regs = k;
1019                 mbox_memcpy(req->reg, reg, sizeof(uint64_t) * k);
1020                 rc = mbox_process_msg(mbox, (void **)&rsp);
1021                 if (!rc) {
1022                         for (j = 0; j < k; j++)
1023                                 nix_dump("\t\t%s=0x%016" PRIx64, regstr[j],
1024                                          rsp->regval[j]);
1025                 } else {
1026                         nix_dump("\t!!!Failed to dump registers!!!");
1027                 }
1028         }
1029
1030         if (found)
1031                 nix_dump("\n");
1032
1033         /* Dump TL1 node data when root level is TL2 */
1034         if (root && root->hw_lvl == NIX_TXSCH_LVL_TL2) {
1035                 k = nix_tm_reg_dump_prep(NIX_TXSCH_LVL_TL1, root->parent_hw_id,
1036                                          nix->tx_link, reg, regstr);
1037                 if (!k)
1038                         return;
1039
1040                 req = mbox_alloc_msg_nix_txschq_cfg(mbox);
1041                 req->read = 1;
1042                 req->lvl = NIX_TXSCH_LVL_TL1;
1043                 req->num_regs = k;
1044                 mbox_memcpy(req->reg, reg, sizeof(uint64_t) * k);
1045                 rc = mbox_process_msg(mbox, (void **)&rsp);
1046                 if (!rc) {
1047                         for (j = 0; j < k; j++)
1048                                 nix_dump("\t\t%s=0x%016" PRIx64, regstr[j],
1049                                          rsp->regval[j]);
1050                 } else {
1051                         nix_dump("\t!!!Failed to dump registers!!!");
1052                 }
1053                 nix_dump("\n");
1054         }
1055 }
1056
1057 void
1058 roc_nix_tm_dump(struct roc_nix *roc_nix)
1059 {
1060         struct nix *nix = roc_nix_to_nix_priv(roc_nix);
1061         struct dev *dev = &nix->dev;
1062         uint8_t hw_lvl, i;
1063
1064         nix_dump("===TM hierarchy and registers dump of %s (pf:vf) (%d:%d)===",
1065                  nix->pci_dev->name, dev_get_pf(dev->pf_func),
1066                  dev_get_vf(dev->pf_func));
1067
1068         /* Dump all trees */
1069         for (i = 0; i < ROC_NIX_TM_TREE_MAX; i++) {
1070                 nix_dump("\tTM %s:", nix_tm_tree2str(i));
1071                 for (hw_lvl = 0; hw_lvl <= NIX_TXSCH_LVL_CNT; hw_lvl++)
1072                         nix_tm_dump_lvl(nix, &nix->trees[i], hw_lvl);
1073         }
1074
1075         /* Dump unused resources */
1076         nix_dump("\tTM unused resources:");
1077         hw_lvl = NIX_TXSCH_LVL_SMQ;
1078         for (; hw_lvl < NIX_TXSCH_LVL_CNT; hw_lvl++) {
1079                 nix_dump("\t\ttxschq        %7s num = %d",
1080                          nix_tm_hwlvl2str(hw_lvl),
1081                          nix_tm_resource_avail(nix, hw_lvl, false));
1082
1083                 nix_bitmap_dump(nix->schq_bmp[hw_lvl]);
1084                 nix_dump("\n");
1085
1086                 nix_dump("\t\ttxschq_contig %7s num = %d",
1087                          nix_tm_hwlvl2str(hw_lvl),
1088                          nix_tm_resource_avail(nix, hw_lvl, true));
1089                 nix_bitmap_dump(nix->schq_contig_bmp[hw_lvl]);
1090                 nix_dump("\n");
1091         }
1092 }
1093
1094 void
1095 roc_nix_dump(struct roc_nix *roc_nix)
1096 {
1097         struct nix *nix = roc_nix_to_nix_priv(roc_nix);
1098         struct dev *dev = &nix->dev;
1099
1100         nix_dump("nix@%p", nix);
1101         nix_dump("  pf = %d", dev_get_pf(dev->pf_func));
1102         nix_dump("  vf = %d", dev_get_vf(dev->pf_func));
1103         nix_dump("  bar2 = 0x%" PRIx64, dev->bar2);
1104         nix_dump("  bar4 = 0x%" PRIx64, dev->bar4);
1105         nix_dump("  port_id = %d", roc_nix->port_id);
1106         nix_dump("  rss_tag_as_xor = %d", roc_nix->rss_tag_as_xor);
1107         nix_dump("  rss_tag_as_xor = %d", roc_nix->max_sqb_count);
1108
1109         nix_dump("  \tpci_dev = %p", nix->pci_dev);
1110         nix_dump("  \tbase = 0x%" PRIxPTR "", nix->base);
1111         nix_dump("  \tlmt_base = 0x%" PRIxPTR "", nix->lmt_base);
1112         nix_dump("  \treta_size = %d", nix->reta_sz);
1113         nix_dump("  \ttx_chan_base = %d", nix->tx_chan_base);
1114         nix_dump("  \trx_chan_base = %d", nix->rx_chan_base);
1115         nix_dump("  \tnb_rx_queues = %d", nix->nb_rx_queues);
1116         nix_dump("  \tnb_tx_queues = %d", nix->nb_tx_queues);
1117         nix_dump("  \tlso_tsov6_idx = %d", nix->lso_tsov6_idx);
1118         nix_dump("  \tlso_tsov4_idx = %d", nix->lso_tsov4_idx);
1119         nix_dump("  \tlso_udp_tun_v4v4 = %d",
1120                  nix->lso_udp_tun_idx[ROC_NIX_LSO_TUN_V4V4]);
1121         nix_dump("  \tlso_udp_tun_v4v6 = %d",
1122                  nix->lso_udp_tun_idx[ROC_NIX_LSO_TUN_V4V6]);
1123         nix_dump("  \tlso_udp_tun_v6v4 = %d",
1124                  nix->lso_udp_tun_idx[ROC_NIX_LSO_TUN_V6V4]);
1125         nix_dump("  \tlso_udp_tun_v6v6 = %d",
1126                  nix->lso_udp_tun_idx[ROC_NIX_LSO_TUN_V6V6]);
1127         nix_dump("  \tlso_tun_v4v4 = %d",
1128                  nix->lso_tun_idx[ROC_NIX_LSO_TUN_V4V4]);
1129         nix_dump("  \tlso_tun_v4v6 = %d",
1130                  nix->lso_tun_idx[ROC_NIX_LSO_TUN_V4V6]);
1131         nix_dump("  \tlso_tun_v6v4 = %d",
1132                  nix->lso_tun_idx[ROC_NIX_LSO_TUN_V6V4]);
1133         nix_dump("  \tlso_tun_v6v6 = %d",
1134                  nix->lso_tun_idx[ROC_NIX_LSO_TUN_V6V6]);
1135         nix_dump("  \tlf_rx_stats = %d", nix->lf_rx_stats);
1136         nix_dump("  \tlf_tx_stats = %d", nix->lf_tx_stats);
1137         nix_dump("  \trx_chan_cnt = %d", nix->rx_chan_cnt);
1138         nix_dump("  \ttx_chan_cnt = %d", nix->tx_chan_cnt);
1139         nix_dump("  \tcgx_links = %d", nix->cgx_links);
1140         nix_dump("  \tlbk_links = %d", nix->lbk_links);
1141         nix_dump("  \tsdp_links = %d", nix->sdp_links);
1142         nix_dump("  \ttx_link = %d", nix->tx_link);
1143         nix_dump("  \tsqb_size = %d", nix->sqb_size);
1144         nix_dump("  \tmsixoff = %d", nix->msixoff);
1145         nix_dump("  \tcints = %d", nix->cints);
1146         nix_dump("  \tqints = %d", nix->qints);
1147         nix_dump("  \tsdp_link = %d", nix->sdp_link);
1148         nix_dump("  \tptp_en = %d", nix->ptp_en);
1149         nix_dump("  \trss_alg_idx = %d", nix->rss_alg_idx);
1150         nix_dump("  \ttx_pause = %d", nix->tx_pause);
1151 }