1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
8 uint32_t soft_exp_consumer_cnt;
10 PLT_STATIC_ASSERT(ROC_NIX_INL_ONF_IPSEC_INB_SA_SZ ==
11 1UL << ROC_NIX_INL_ONF_IPSEC_INB_SA_SZ_LOG2);
12 PLT_STATIC_ASSERT(ROC_NIX_INL_ONF_IPSEC_INB_SA_SZ == 512);
13 PLT_STATIC_ASSERT(ROC_NIX_INL_ONF_IPSEC_OUTB_SA_SZ ==
14 1UL << ROC_NIX_INL_ONF_IPSEC_OUTB_SA_SZ_LOG2);
15 PLT_STATIC_ASSERT(ROC_NIX_INL_OT_IPSEC_INB_SA_SZ ==
16 1UL << ROC_NIX_INL_OT_IPSEC_INB_SA_SZ_LOG2);
17 PLT_STATIC_ASSERT(ROC_NIX_INL_OT_IPSEC_INB_SA_SZ == 1024);
18 PLT_STATIC_ASSERT(ROC_NIX_INL_OT_IPSEC_OUTB_SA_SZ ==
19 1UL << ROC_NIX_INL_OT_IPSEC_OUTB_SA_SZ_LOG2);
22 nix_inl_inb_sa_tbl_setup(struct roc_nix *roc_nix)
24 uint32_t ipsec_in_min_spi = roc_nix->ipsec_in_min_spi;
25 uint32_t ipsec_in_max_spi = roc_nix->ipsec_in_max_spi;
26 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
27 struct roc_nix_ipsec_cfg cfg;
33 max_sa = plt_align32pow2(ipsec_in_max_spi - ipsec_in_min_spi + 1);
35 /* CN9K SA size is different */
36 if (roc_model_is_cn9k())
37 inb_sa_sz = ROC_NIX_INL_ONF_IPSEC_INB_SA_SZ;
39 inb_sa_sz = ROC_NIX_INL_OT_IPSEC_INB_SA_SZ;
41 /* Alloc contiguous memory for Inbound SA's */
42 nix->inb_sa_sz = inb_sa_sz;
43 nix->inb_spi_mask = max_sa - 1;
44 nix->inb_sa_base = plt_zmalloc(inb_sa_sz * max_sa,
45 ROC_NIX_INL_SA_BASE_ALIGN);
46 if (!nix->inb_sa_base) {
47 plt_err("Failed to allocate memory for Inbound SA");
50 if (roc_model_is_cn10k()) {
51 for (i = 0; i < max_sa; i++) {
52 sa = ((uint8_t *)nix->inb_sa_base) + (i * inb_sa_sz);
53 roc_ot_ipsec_inb_sa_init(sa, true);
57 memset(&cfg, 0, sizeof(cfg));
58 cfg.sa_size = inb_sa_sz;
59 cfg.iova = (uintptr_t)nix->inb_sa_base;
61 cfg.tt = SSO_TT_ORDERED;
63 /* Setup device specific inb SA table */
64 rc = roc_nix_lf_inl_ipsec_cfg(roc_nix, &cfg, true);
66 plt_err("Failed to setup NIX Inbound SA conf, rc=%d", rc);
72 plt_free(nix->inb_sa_base);
73 nix->inb_sa_base = NULL;
78 nix_inl_sa_tbl_release(struct roc_nix *roc_nix)
80 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
83 rc = roc_nix_lf_inl_ipsec_cfg(roc_nix, NULL, false);
85 plt_err("Failed to disable Inbound inline ipsec, rc=%d", rc);
89 plt_free(nix->inb_sa_base);
90 nix->inb_sa_base = NULL;
95 roc_nix_inl_outb_lf_base_get(struct roc_nix *roc_nix)
97 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
99 /* NIX Inline config needs to be done */
100 if (!nix->inl_outb_ena || !nix->cpt_lf_base)
103 return (struct roc_cpt_lf *)nix->cpt_lf_base;
107 roc_nix_inl_outb_sa_base_get(struct roc_nix *roc_nix)
109 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
111 return (uintptr_t)nix->outb_sa_base;
115 roc_nix_inl_inb_sa_base_get(struct roc_nix *roc_nix, bool inb_inl_dev)
117 struct idev_cfg *idev = idev_get_cfg();
118 struct nix_inl_dev *inl_dev;
119 struct nix *nix = NULL;
124 if (!inb_inl_dev && roc_nix == NULL)
128 nix = roc_nix_to_nix_priv(roc_nix);
129 if (!nix->inl_inb_ena)
134 inl_dev = idev->nix_inl_dev;
135 /* Return inline dev sa base */
137 return (uintptr_t)inl_dev->inb_sa_base;
141 return (uintptr_t)nix->inb_sa_base;
145 roc_nix_inl_inb_spi_range(struct roc_nix *roc_nix, bool inb_inl_dev,
146 uint32_t *min_spi, uint32_t *max_spi)
148 struct idev_cfg *idev = idev_get_cfg();
149 uint32_t min = 0, max = 0, mask = 0;
150 struct nix_inl_dev *inl_dev;
151 struct nix *nix = NULL;
156 if (!inb_inl_dev && roc_nix == NULL)
159 inl_dev = idev->nix_inl_dev;
163 min = inl_dev->ipsec_in_min_spi;
164 max = inl_dev->ipsec_in_max_spi;
165 mask = inl_dev->inb_spi_mask;
167 nix = roc_nix_to_nix_priv(roc_nix);
168 if (!nix->inl_inb_ena)
170 min = roc_nix->ipsec_in_min_spi;
171 max = roc_nix->ipsec_in_max_spi;
172 mask = nix->inb_spi_mask;
183 roc_nix_inl_inb_sa_sz(struct roc_nix *roc_nix, bool inl_dev_sa)
185 struct idev_cfg *idev = idev_get_cfg();
186 struct nix_inl_dev *inl_dev;
192 if (!inl_dev_sa && roc_nix == NULL)
196 nix = roc_nix_to_nix_priv(roc_nix);
198 return nix->inb_sa_sz;
202 inl_dev = idev->nix_inl_dev;
204 return inl_dev->inb_sa_sz;
211 roc_nix_inl_inb_sa_get(struct roc_nix *roc_nix, bool inb_inl_dev, uint32_t spi)
213 uint32_t max_spi, min_spi, mask;
217 sa_base = roc_nix_inl_inb_sa_base_get(roc_nix, inb_inl_dev);
218 /* Check if SA base exists */
222 /* Check if SPI is in range */
223 mask = roc_nix_inl_inb_spi_range(roc_nix, inb_inl_dev, &min_spi,
225 if (spi > max_spi || spi < min_spi)
226 plt_warn("Inbound SA SPI %u not in range (%u..%u)", spi,
230 sz = roc_nix_inl_inb_sa_sz(roc_nix, inb_inl_dev);
234 /* Basic logic of SPI->SA for now */
235 return (sa_base + ((spi & mask) * sz));
239 roc_nix_reassembly_configure(uint32_t max_wait_time, uint16_t max_frags)
241 struct idev_cfg *idev = idev_get_cfg();
242 struct roc_cpt *roc_cpt;
243 struct roc_cpt_rxc_time_cfg cfg;
245 PLT_SET_USED(max_frags);
248 plt_err("Cannot support inline inbound, cryptodev not probed");
252 cfg.step = (max_wait_time * 1000 / ROC_NIX_INL_REAS_ACTIVE_LIMIT);
253 cfg.zombie_limit = ROC_NIX_INL_REAS_ZOMBIE_LIMIT;
254 cfg.zombie_thres = ROC_NIX_INL_REAS_ZOMBIE_THRESHOLD;
255 cfg.active_limit = ROC_NIX_INL_REAS_ACTIVE_LIMIT;
256 cfg.active_thres = ROC_NIX_INL_REAS_ACTIVE_THRESHOLD;
258 return roc_cpt_rxc_time_cfg(roc_cpt, &cfg);
262 roc_nix_inl_inb_init(struct roc_nix *roc_nix)
264 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
265 struct idev_cfg *idev = idev_get_cfg();
266 struct roc_cpt *roc_cpt;
273 /* Unless we have another mechanism to trigger
274 * onetime Inline config in CPTPF, we cannot
275 * support without CPT being probed.
279 plt_err("Cannot support inline inbound, cryptodev not probed");
283 if (roc_model_is_cn9k()) {
284 param1 = ROC_ONF_IPSEC_INB_MAX_L2_SZ;
286 union roc_ot_ipsec_inb_param1 u;
289 u.s.esp_trailer_disable = 1;
293 /* Do onetime Inbound Inline config in CPTPF */
294 rc = roc_cpt_inline_ipsec_inb_cfg(roc_cpt, param1, 0);
295 if (rc && rc != -EEXIST) {
296 plt_err("Failed to setup inbound lf, rc=%d", rc);
300 /* Setup Inbound SA table */
301 rc = nix_inl_inb_sa_tbl_setup(roc_nix);
305 nix->inl_inb_ena = true;
310 roc_nix_inl_inb_fini(struct roc_nix *roc_nix)
312 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
314 if (!nix->inl_inb_ena)
317 nix->inl_inb_ena = false;
319 /* Flush Inbound CTX cache entries */
320 roc_nix_cpt_ctx_cache_sync(roc_nix);
322 /* Disable Inbound SA */
323 return nix_inl_sa_tbl_release(roc_nix);
327 roc_nix_inl_outb_init(struct roc_nix *roc_nix)
329 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
330 struct idev_cfg *idev = idev_get_cfg();
331 struct roc_cpt_lf *lf_base, *lf;
332 struct dev *dev = &nix->dev;
333 struct msix_offset_rsp *rsp;
334 struct nix_inl_dev *inl_dev;
335 size_t sa_sz, ring_sz;
348 nb_lf = roc_nix->outb_nb_crypto_qs;
349 blkaddr = nix->is_nix1 ? RVU_BLOCK_ADDR_CPT1 : RVU_BLOCK_ADDR_CPT0;
351 /* Retrieve inline device if present */
352 inl_dev = idev->nix_inl_dev;
353 sso_pffunc = inl_dev ? inl_dev->dev.pf_func : idev_sso_pffunc_get();
354 /* Use sso_pffunc if explicitly requested */
355 if (roc_nix->ipsec_out_sso_pffunc)
356 sso_pffunc = idev_sso_pffunc_get();
359 plt_err("Failed to setup inline outb, need either "
360 "inline device or sso device");
364 /* Attach CPT LF for outbound */
365 rc = cpt_lfs_attach(dev, blkaddr, true, nb_lf);
367 plt_err("Failed to attach CPT LF for inline outb, rc=%d", rc);
372 eng_grpmask = (1ULL << ROC_CPT_DFLT_ENG_GRP_SE |
373 1ULL << ROC_CPT_DFLT_ENG_GRP_SE_IE |
374 1ULL << ROC_CPT_DFLT_ENG_GRP_AE);
375 rc = cpt_lfs_alloc(dev, eng_grpmask, blkaddr,
376 !roc_nix->ipsec_out_sso_pffunc);
378 plt_err("Failed to alloc CPT LF resources, rc=%d", rc);
382 /* Get msix offsets */
383 rc = cpt_get_msix_offset(dev, &rsp);
385 plt_err("Failed to get CPT LF msix offset, rc=%d", rc);
389 mbox_memcpy(nix->cpt_msixoff,
390 nix->is_nix1 ? rsp->cpt1_lf_msixoff : rsp->cptlf_msixoff,
391 sizeof(nix->cpt_msixoff));
393 /* Alloc required num of cpt lfs */
394 lf_base = plt_zmalloc(nb_lf * sizeof(struct roc_cpt_lf), 0);
396 plt_err("Failed to alloc cpt lf memory");
401 /* Initialize CPT LF's */
402 for (i = 0; i < nb_lf; i++) {
406 lf->nb_desc = roc_nix->outb_nb_desc;
408 lf->msixoff = nix->cpt_msixoff[i];
409 lf->pci_dev = nix->pci_dev;
411 /* Setup CPT LF instruction queue */
412 rc = cpt_lf_init(lf);
414 plt_err("Failed to initialize CPT LF, rc=%d", rc);
418 /* Associate this CPT LF with NIX PFFUNC */
419 rc = cpt_lf_outb_cfg(dev, sso_pffunc, nix->dev.pf_func, i,
422 plt_err("Failed to setup CPT LF->(NIX,SSO) link, rc=%d",
428 roc_cpt_iq_enable(lf);
431 if (!roc_nix->ipsec_out_max_sa)
434 /* CN9K SA size is different */
435 if (roc_model_is_cn9k())
436 sa_sz = ROC_NIX_INL_ONF_IPSEC_OUTB_SA_SZ;
438 sa_sz = ROC_NIX_INL_OT_IPSEC_OUTB_SA_SZ;
439 /* Alloc contiguous memory of outbound SA */
440 sa_base = plt_zmalloc(sa_sz * roc_nix->ipsec_out_max_sa,
441 ROC_NIX_INL_SA_BASE_ALIGN);
443 plt_err("Outbound SA base alloc failed");
446 if (roc_model_is_cn10k()) {
447 for (i = 0; i < roc_nix->ipsec_out_max_sa; i++) {
448 sa = ((uint8_t *)sa_base) + (i * sa_sz);
449 roc_ot_ipsec_outb_sa_init(sa);
452 nix->outb_sa_base = sa_base;
453 nix->outb_sa_sz = sa_sz;
457 nix->cpt_lf_base = lf_base;
458 nix->nb_cpt_lf = nb_lf;
459 nix->outb_err_sso_pffunc = sso_pffunc;
460 nix->inl_outb_ena = true;
461 nix->outb_se_ring_cnt =
462 roc_nix->ipsec_out_max_sa / ROC_IPSEC_ERR_RING_MAX_ENTRY + 1;
463 nix->outb_se_ring_base =
464 roc_nix->port_id * ROC_NIX_SOFT_EXP_PER_PORT_MAX_RINGS;
466 if (inl_dev == NULL) {
467 nix->outb_se_ring_cnt = 0;
471 /* Allocate memory to be used as a ring buffer to poll for
472 * soft expiry event from ucode
474 ring_sz = (ROC_IPSEC_ERR_RING_MAX_ENTRY + 1) * sizeof(uint64_t);
475 ring_base = inl_dev->sa_soft_exp_ring;
476 for (i = 0; i < nix->outb_se_ring_cnt; i++) {
477 ring_base[nix->outb_se_ring_base + i] =
478 PLT_U64_CAST(plt_zmalloc(ring_sz, 0));
479 if (!ring_base[nix->outb_se_ring_base + i]) {
480 plt_err("Couldn't allocate memory for soft exp ring");
482 plt_free(PLT_PTR_CAST(
483 ring_base[nix->outb_se_ring_base + i]));
492 for (j = i - 1; j >= 0; j--)
493 cpt_lf_fini(&lf_base[j]);
496 rc |= cpt_lfs_free(dev);
498 rc |= cpt_lfs_detach(dev);
503 roc_nix_inl_outb_fini(struct roc_nix *roc_nix)
505 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
506 struct roc_cpt_lf *lf_base = nix->cpt_lf_base;
507 struct idev_cfg *idev = idev_get_cfg();
508 struct dev *dev = &nix->dev;
509 struct nix_inl_dev *inl_dev;
513 if (!nix->inl_outb_ena)
516 nix->inl_outb_ena = false;
518 /* Cleanup CPT LF instruction queue */
519 for (i = 0; i < nix->nb_cpt_lf; i++)
520 cpt_lf_fini(&lf_base[i]);
522 /* Free LF resources */
523 rc = cpt_lfs_free(dev);
525 plt_err("Failed to free CPT LF resources, rc=%d", rc);
529 rc = cpt_lfs_detach(dev);
531 plt_err("Failed to detach CPT LF, rc=%d", rc);
535 nix->cpt_lf_base = NULL;
538 /* Free outbound SA base */
539 plt_free(nix->outb_sa_base);
540 nix->outb_sa_base = NULL;
542 if (idev && idev->nix_inl_dev) {
543 inl_dev = idev->nix_inl_dev;
544 ring_base = inl_dev->sa_soft_exp_ring;
546 for (i = 0; i < ROC_NIX_INL_MAX_SOFT_EXP_RNGS; i++) {
548 plt_free(PLT_PTR_CAST(ring_base[i]));
557 roc_nix_inl_dev_is_probed(void)
559 struct idev_cfg *idev = idev_get_cfg();
564 return !!idev->nix_inl_dev;
568 roc_nix_inl_inb_is_enabled(struct roc_nix *roc_nix)
570 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
572 return nix->inl_inb_ena;
576 roc_nix_inl_outb_is_enabled(struct roc_nix *roc_nix)
578 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
580 return nix->inl_outb_ena;
584 roc_nix_inl_dev_rq_get(struct roc_nix_rq *rq)
586 struct idev_cfg *idev = idev_get_cfg();
587 struct nix_inl_dev *inl_dev;
588 struct roc_nix_rq *inl_rq;
595 inl_dev = idev->nix_inl_dev;
596 /* Nothing to do if no inline device */
600 /* Just take reference if already inited */
601 if (inl_dev->rq_refs) {
603 rq->inl_dev_ref = true;
608 inl_rq = &inl_dev->rq;
609 memset(inl_rq, 0, sizeof(struct roc_nix_rq));
611 /* Take RQ pool attributes from the first ethdev RQ */
613 inl_rq->aura_handle = rq->aura_handle;
614 inl_rq->first_skip = rq->first_skip;
615 inl_rq->later_skip = rq->later_skip;
616 inl_rq->lpb_size = rq->lpb_size;
617 inl_rq->lpb_drop_ena = true;
618 inl_rq->spb_ena = rq->spb_ena;
619 inl_rq->spb_aura_handle = rq->spb_aura_handle;
620 inl_rq->spb_size = rq->spb_size;
621 inl_rq->spb_drop_ena = !!rq->spb_ena;
623 if (!roc_model_is_cn9k()) {
624 uint64_t aura_limit =
625 roc_npa_aura_op_limit_get(inl_rq->aura_handle);
626 uint64_t aura_shift = plt_log2_u32(aura_limit);
627 uint64_t aura_drop, drop_pc;
632 aura_shift = aura_shift - 8;
634 /* Set first pass RQ to drop after part of buffers are in
635 * use to avoid metabuf alloc failure. This is needed as long
636 * as we cannot use different aura.
638 drop_pc = inl_dev->lpb_drop_pc;
639 aura_drop = ((aura_limit * drop_pc) / 100) >> aura_shift;
640 roc_npa_aura_drop_set(inl_rq->aura_handle, aura_drop, true);
643 if (inl_rq->spb_ena) {
644 uint64_t aura_limit =
645 roc_npa_aura_op_limit_get(inl_rq->spb_aura_handle);
646 uint64_t aura_shift = plt_log2_u32(aura_limit);
647 uint64_t aura_drop, drop_pc;
652 aura_shift = aura_shift - 8;
654 /* Set first pass RQ to drop after part of buffers are in
655 * use to avoid metabuf alloc failure. This is needed as long
656 * as we cannot use different aura.
658 drop_pc = inl_dev->spb_drop_pc;
659 aura_drop = ((aura_limit * drop_pc) / 100) >> aura_shift;
660 roc_npa_aura_drop_set(inl_rq->spb_aura_handle, aura_drop, true);
664 inl_rq->ipsech_ena = true;
666 inl_rq->flow_tag_width = 20;
667 /* Special tag mask */
668 inl_rq->tag_mask = rq->tag_mask;
669 inl_rq->tt = SSO_TT_ORDERED;
671 inl_rq->wqe_skip = inl_dev->wqe_skip;
672 inl_rq->sso_ena = true;
674 /* Prepare and send RQ init mbox */
675 if (roc_model_is_cn9k())
676 rc = nix_rq_cn9k_cfg(dev, inl_rq, inl_dev->qints, false, true);
678 rc = nix_rq_cfg(dev, inl_rq, inl_dev->qints, false, true);
680 plt_err("Failed to prepare aq_enq msg, rc=%d", rc);
684 rc = mbox_process(dev->mbox);
686 plt_err("Failed to send aq_enq msg, rc=%d", rc);
691 rq->inl_dev_ref = true;
696 roc_nix_inl_dev_rq_put(struct roc_nix_rq *rq)
698 struct idev_cfg *idev = idev_get_cfg();
699 struct nix_inl_dev *inl_dev;
700 struct roc_nix_rq *inl_rq;
707 if (!rq->inl_dev_ref)
710 inl_dev = idev->nix_inl_dev;
711 /* Inline device should be there if we have ref */
713 plt_err("Failed to find inline device with refs");
717 rq->inl_dev_ref = false;
719 if (inl_dev->rq_refs)
723 inl_rq = &inl_dev->rq;
724 /* There are no more references, disable RQ */
725 rc = nix_rq_ena_dis(dev, inl_rq, false);
727 plt_err("Failed to disable inline device rq, rc=%d", rc);
729 roc_npa_aura_drop_set(inl_rq->aura_handle, 0, false);
731 roc_npa_aura_drop_set(inl_rq->spb_aura_handle, 0, false);
733 /* Flush NIX LF for CN10K */
734 nix_rq_vwqe_flush(rq, inl_dev->vwqe_interval);
740 roc_nix_inl_dev_rq_limit_get(void)
742 struct idev_cfg *idev = idev_get_cfg();
743 struct nix_inl_dev *inl_dev;
744 struct roc_nix_rq *inl_rq;
746 if (!idev || !idev->nix_inl_dev)
749 inl_dev = idev->nix_inl_dev;
750 if (!inl_dev->rq_refs)
753 inl_rq = &inl_dev->rq;
755 return roc_npa_aura_op_limit_get(inl_rq->aura_handle);
759 roc_nix_inb_mode_set(struct roc_nix *roc_nix, bool use_inl_dev)
761 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
763 /* Info used by NPC flow rule add */
764 nix->inb_inl_dev = use_inl_dev;
768 roc_nix_inl_outb_soft_exp_poll_switch(struct roc_nix *roc_nix, bool poll)
770 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
771 struct idev_cfg *idev = idev_get_cfg();
772 struct nix_inl_dev *inl_dev;
773 uint16_t ring_idx, i;
775 if (!idev || !idev->nix_inl_dev)
778 inl_dev = idev->nix_inl_dev;
780 for (i = 0; i < nix->outb_se_ring_cnt; i++) {
781 ring_idx = nix->outb_se_ring_base + i;
784 plt_bitmap_set(inl_dev->soft_exp_ring_bmap, ring_idx);
786 plt_bitmap_clear(inl_dev->soft_exp_ring_bmap, ring_idx);
790 soft_exp_consumer_cnt++;
792 soft_exp_consumer_cnt--;
798 roc_nix_inb_is_with_inl_dev(struct roc_nix *roc_nix)
800 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
802 return nix->inb_inl_dev;
806 roc_nix_inl_dev_rq(void)
808 struct idev_cfg *idev = idev_get_cfg();
809 struct nix_inl_dev *inl_dev;
812 inl_dev = idev->nix_inl_dev;
813 if (inl_dev != NULL && inl_dev->rq_refs)
821 roc_nix_inl_outb_sso_pffunc_get(struct roc_nix *roc_nix)
823 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
825 return nix->outb_err_sso_pffunc;
829 roc_nix_inl_cb_register(roc_nix_inl_sso_work_cb_t cb, void *args)
831 struct idev_cfg *idev = idev_get_cfg();
832 struct nix_inl_dev *inl_dev;
837 inl_dev = idev->nix_inl_dev;
841 /* Be silent if registration called with same cb and args */
842 if (inl_dev->work_cb == cb && inl_dev->cb_args == args)
845 /* Don't allow registration again if registered with different cb */
846 if (inl_dev->work_cb)
849 inl_dev->work_cb = cb;
850 inl_dev->cb_args = args;
855 roc_nix_inl_cb_unregister(roc_nix_inl_sso_work_cb_t cb, void *args)
857 struct idev_cfg *idev = idev_get_cfg();
858 struct nix_inl_dev *inl_dev;
863 inl_dev = idev->nix_inl_dev;
867 if (inl_dev->work_cb != cb || inl_dev->cb_args != args)
870 inl_dev->work_cb = NULL;
871 inl_dev->cb_args = NULL;
876 roc_nix_inl_inb_tag_update(struct roc_nix *roc_nix, uint32_t tag_const,
879 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
880 struct roc_nix_ipsec_cfg cfg;
882 /* Be silent if inline inbound not enabled */
883 if (!nix->inl_inb_ena)
886 memset(&cfg, 0, sizeof(cfg));
887 cfg.sa_size = nix->inb_sa_sz;
888 cfg.iova = (uintptr_t)nix->inb_sa_base;
889 cfg.max_sa = nix->inb_spi_mask + 1;
891 cfg.tag_const = tag_const;
893 return roc_nix_lf_inl_ipsec_cfg(roc_nix, &cfg, true);
897 roc_nix_inl_sa_sync(struct roc_nix *roc_nix, void *sa, bool inb,
898 enum roc_nix_inl_sa_sync_op op)
900 struct idev_cfg *idev = idev_get_cfg();
901 struct nix_inl_dev *inl_dev = NULL;
902 struct roc_cpt_lf *outb_lf = NULL;
903 union cpt_lf_ctx_reload reload;
904 union cpt_lf_ctx_flush flush;
905 bool get_inl_lf = true;
909 /* Nothing much to do on cn9k */
910 if (roc_model_is_cn9k()) {
911 plt_atomic_thread_fence(__ATOMIC_ACQ_REL);
916 inl_dev = idev->nix_inl_dev;
918 if (!inl_dev && roc_nix == NULL)
922 nix = roc_nix_to_nix_priv(roc_nix);
923 outb_lf = nix->cpt_lf_base;
924 if (inb && !nix->inb_inl_dev)
928 if (inb && get_inl_lf) {
930 if (inl_dev && inl_dev->attach_cptlf)
931 outb_lf = &inl_dev->cpt_lf;
935 rbase = outb_lf->rbase;
940 case ROC_NIX_INL_SA_OP_FLUSH_INVAL:
943 case ROC_NIX_INL_SA_OP_FLUSH:
944 flush.s.cptr = ((uintptr_t)sa) >> 7;
945 plt_write64(flush.u, rbase + CPT_LF_CTX_FLUSH);
947 case ROC_NIX_INL_SA_OP_RELOAD:
948 reload.s.cptr = ((uintptr_t)sa) >> 7;
949 plt_write64(reload.u, rbase + CPT_LF_CTX_RELOAD);
956 plt_err("Could not get CPT LF for SA sync");
961 roc_nix_inl_ctx_write(struct roc_nix *roc_nix, void *sa_dptr, void *sa_cptr,
962 bool inb, uint16_t sa_len)
964 struct idev_cfg *idev = idev_get_cfg();
965 struct nix_inl_dev *inl_dev = NULL;
966 struct roc_cpt_lf *outb_lf = NULL;
967 union cpt_lf_ctx_flush flush;
968 bool get_inl_lf = true;
973 /* Nothing much to do on cn9k */
974 if (roc_model_is_cn9k()) {
975 plt_atomic_thread_fence(__ATOMIC_ACQ_REL);
980 inl_dev = idev->nix_inl_dev;
982 if (!inl_dev && roc_nix == NULL)
986 nix = roc_nix_to_nix_priv(roc_nix);
987 outb_lf = nix->cpt_lf_base;
989 if (inb && !nix->inb_inl_dev)
993 if (inb && get_inl_lf) {
995 if (inl_dev && inl_dev->attach_cptlf)
996 outb_lf = &inl_dev->cpt_lf;
1000 rbase = outb_lf->rbase;
1003 rc = roc_cpt_ctx_write(outb_lf, sa_dptr, sa_cptr, sa_len);
1006 /* Trigger CTX flush to write dirty data back to DRAM */
1007 flush.s.cptr = ((uintptr_t)sa_cptr) >> 7;
1008 plt_write64(flush.u, rbase + CPT_LF_CTX_FLUSH);
1012 plt_nix_dbg("Could not get CPT LF for CTX write");
1017 roc_nix_inl_dev_lock(void)
1019 struct idev_cfg *idev = idev_get_cfg();
1022 plt_spinlock_lock(&idev->nix_inl_dev_lock);
1026 roc_nix_inl_dev_unlock(void)
1028 struct idev_cfg *idev = idev_get_cfg();
1031 plt_spinlock_unlock(&idev->nix_inl_dev_lock);