1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
8 uint32_t soft_exp_consumer_cnt;
10 PLT_STATIC_ASSERT(ROC_NIX_INL_ONF_IPSEC_INB_SA_SZ ==
11 1UL << ROC_NIX_INL_ONF_IPSEC_INB_SA_SZ_LOG2);
12 PLT_STATIC_ASSERT(ROC_NIX_INL_ONF_IPSEC_INB_SA_SZ == 512);
13 PLT_STATIC_ASSERT(ROC_NIX_INL_ONF_IPSEC_OUTB_SA_SZ ==
14 1UL << ROC_NIX_INL_ONF_IPSEC_OUTB_SA_SZ_LOG2);
15 PLT_STATIC_ASSERT(ROC_NIX_INL_OT_IPSEC_INB_SA_SZ ==
16 1UL << ROC_NIX_INL_OT_IPSEC_INB_SA_SZ_LOG2);
17 PLT_STATIC_ASSERT(ROC_NIX_INL_OT_IPSEC_INB_SA_SZ == 1024);
18 PLT_STATIC_ASSERT(ROC_NIX_INL_OT_IPSEC_OUTB_SA_SZ ==
19 1UL << ROC_NIX_INL_OT_IPSEC_OUTB_SA_SZ_LOG2);
22 nix_inl_inb_sa_tbl_setup(struct roc_nix *roc_nix)
24 uint32_t ipsec_in_min_spi = roc_nix->ipsec_in_min_spi;
25 uint32_t ipsec_in_max_spi = roc_nix->ipsec_in_max_spi;
26 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
27 struct roc_nix_ipsec_cfg cfg;
33 max_sa = plt_align32pow2(ipsec_in_max_spi - ipsec_in_min_spi + 1);
35 /* CN9K SA size is different */
36 if (roc_model_is_cn9k())
37 inb_sa_sz = ROC_NIX_INL_ONF_IPSEC_INB_SA_SZ;
39 inb_sa_sz = ROC_NIX_INL_OT_IPSEC_INB_SA_SZ;
41 /* Alloc contiguous memory for Inbound SA's */
42 nix->inb_sa_sz = inb_sa_sz;
43 nix->inb_spi_mask = max_sa - 1;
44 nix->inb_sa_base = plt_zmalloc(inb_sa_sz * max_sa,
45 ROC_NIX_INL_SA_BASE_ALIGN);
46 if (!nix->inb_sa_base) {
47 plt_err("Failed to allocate memory for Inbound SA");
50 if (roc_model_is_cn10k()) {
51 for (i = 0; i < max_sa; i++) {
52 sa = ((uint8_t *)nix->inb_sa_base) + (i * inb_sa_sz);
53 roc_ot_ipsec_inb_sa_init(sa, true);
57 memset(&cfg, 0, sizeof(cfg));
58 cfg.sa_size = inb_sa_sz;
59 cfg.iova = (uintptr_t)nix->inb_sa_base;
61 cfg.tt = SSO_TT_ORDERED;
63 /* Setup device specific inb SA table */
64 rc = roc_nix_lf_inl_ipsec_cfg(roc_nix, &cfg, true);
66 plt_err("Failed to setup NIX Inbound SA conf, rc=%d", rc);
72 plt_free(nix->inb_sa_base);
73 nix->inb_sa_base = NULL;
78 nix_inl_sa_tbl_release(struct roc_nix *roc_nix)
80 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
83 rc = roc_nix_lf_inl_ipsec_cfg(roc_nix, NULL, false);
85 plt_err("Failed to disable Inbound inline ipsec, rc=%d", rc);
89 plt_free(nix->inb_sa_base);
90 nix->inb_sa_base = NULL;
95 roc_nix_inl_outb_lf_base_get(struct roc_nix *roc_nix)
97 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
99 /* NIX Inline config needs to be done */
100 if (!nix->inl_outb_ena || !nix->cpt_lf_base)
103 return (struct roc_cpt_lf *)nix->cpt_lf_base;
107 roc_nix_inl_outb_sa_base_get(struct roc_nix *roc_nix)
109 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
111 return (uintptr_t)nix->outb_sa_base;
115 roc_nix_inl_inb_sa_base_get(struct roc_nix *roc_nix, bool inb_inl_dev)
117 struct idev_cfg *idev = idev_get_cfg();
118 struct nix_inl_dev *inl_dev;
119 struct nix *nix = NULL;
124 if (!inb_inl_dev && roc_nix == NULL)
128 nix = roc_nix_to_nix_priv(roc_nix);
129 if (!nix->inl_inb_ena)
134 inl_dev = idev->nix_inl_dev;
135 /* Return inline dev sa base */
137 return (uintptr_t)inl_dev->inb_sa_base;
141 return (uintptr_t)nix->inb_sa_base;
145 roc_nix_inl_inb_spi_range(struct roc_nix *roc_nix, bool inb_inl_dev,
146 uint32_t *min_spi, uint32_t *max_spi)
148 struct idev_cfg *idev = idev_get_cfg();
149 uint32_t min = 0, max = 0, mask = 0;
150 struct nix_inl_dev *inl_dev;
151 struct nix *nix = NULL;
156 if (!inb_inl_dev && roc_nix == NULL)
159 inl_dev = idev->nix_inl_dev;
161 min = inl_dev->ipsec_in_min_spi;
162 max = inl_dev->ipsec_in_max_spi;
163 mask = inl_dev->inb_spi_mask;
165 nix = roc_nix_to_nix_priv(roc_nix);
166 if (!nix->inl_inb_ena)
168 min = roc_nix->ipsec_in_min_spi;
169 max = roc_nix->ipsec_in_max_spi;
170 mask = nix->inb_spi_mask;
181 roc_nix_inl_inb_sa_sz(struct roc_nix *roc_nix, bool inl_dev_sa)
183 struct idev_cfg *idev = idev_get_cfg();
184 struct nix_inl_dev *inl_dev;
190 if (!inl_dev_sa && roc_nix == NULL)
194 nix = roc_nix_to_nix_priv(roc_nix);
196 return nix->inb_sa_sz;
200 inl_dev = idev->nix_inl_dev;
202 return inl_dev->inb_sa_sz;
209 roc_nix_inl_inb_sa_get(struct roc_nix *roc_nix, bool inb_inl_dev, uint32_t spi)
211 uint32_t max_spi, min_spi, mask;
215 sa_base = roc_nix_inl_inb_sa_base_get(roc_nix, inb_inl_dev);
216 /* Check if SA base exists */
220 /* Check if SPI is in range */
221 mask = roc_nix_inl_inb_spi_range(roc_nix, inb_inl_dev, &min_spi,
223 if (spi > max_spi || spi < min_spi)
224 plt_warn("Inbound SA SPI %u not in range (%u..%u)", spi,
228 sz = roc_nix_inl_inb_sa_sz(roc_nix, inb_inl_dev);
232 /* Basic logic of SPI->SA for now */
233 return (sa_base + ((spi & mask) * sz));
237 roc_nix_reassembly_configure(uint32_t max_wait_time, uint16_t max_frags)
239 struct idev_cfg *idev = idev_get_cfg();
240 struct roc_cpt *roc_cpt;
241 struct roc_cpt_rxc_time_cfg cfg;
243 PLT_SET_USED(max_frags);
246 plt_err("Cannot support inline inbound, cryptodev not probed");
250 cfg.step = (max_wait_time * 1000 / ROC_NIX_INL_REAS_ACTIVE_LIMIT);
251 cfg.zombie_limit = ROC_NIX_INL_REAS_ZOMBIE_LIMIT;
252 cfg.zombie_thres = ROC_NIX_INL_REAS_ZOMBIE_THRESHOLD;
253 cfg.active_limit = ROC_NIX_INL_REAS_ACTIVE_LIMIT;
254 cfg.active_thres = ROC_NIX_INL_REAS_ACTIVE_THRESHOLD;
256 return roc_cpt_rxc_time_cfg(roc_cpt, &cfg);
260 roc_nix_inl_inb_init(struct roc_nix *roc_nix)
262 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
263 struct idev_cfg *idev = idev_get_cfg();
264 struct roc_cpt *roc_cpt;
271 /* Unless we have another mechanism to trigger
272 * onetime Inline config in CPTPF, we cannot
273 * support without CPT being probed.
277 plt_err("Cannot support inline inbound, cryptodev not probed");
281 if (roc_model_is_cn9k()) {
282 param1 = ROC_ONF_IPSEC_INB_MAX_L2_SZ;
284 union roc_ot_ipsec_inb_param1 u;
287 u.s.esp_trailer_disable = 1;
291 /* Do onetime Inbound Inline config in CPTPF */
292 rc = roc_cpt_inline_ipsec_inb_cfg(roc_cpt, param1, 0);
293 if (rc && rc != -EEXIST) {
294 plt_err("Failed to setup inbound lf, rc=%d", rc);
298 /* Setup Inbound SA table */
299 rc = nix_inl_inb_sa_tbl_setup(roc_nix);
303 nix->inl_inb_ena = true;
308 roc_nix_inl_inb_fini(struct roc_nix *roc_nix)
310 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
312 if (!nix->inl_inb_ena)
315 nix->inl_inb_ena = false;
317 /* Flush Inbound CTX cache entries */
318 roc_nix_cpt_ctx_cache_sync(roc_nix);
320 /* Disable Inbound SA */
321 return nix_inl_sa_tbl_release(roc_nix);
325 roc_nix_inl_outb_init(struct roc_nix *roc_nix)
327 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
328 struct idev_cfg *idev = idev_get_cfg();
329 struct roc_cpt_lf *lf_base, *lf;
330 struct dev *dev = &nix->dev;
331 struct msix_offset_rsp *rsp;
332 struct nix_inl_dev *inl_dev;
333 size_t sa_sz, ring_sz;
346 nb_lf = roc_nix->outb_nb_crypto_qs;
347 blkaddr = nix->is_nix1 ? RVU_BLOCK_ADDR_CPT1 : RVU_BLOCK_ADDR_CPT0;
349 /* Retrieve inline device if present */
350 inl_dev = idev->nix_inl_dev;
351 sso_pffunc = inl_dev ? inl_dev->dev.pf_func : idev_sso_pffunc_get();
352 /* Use sso_pffunc if explicitly requested */
353 if (roc_nix->ipsec_out_sso_pffunc)
354 sso_pffunc = idev_sso_pffunc_get();
357 plt_err("Failed to setup inline outb, need either "
358 "inline device or sso device");
362 /* Attach CPT LF for outbound */
363 rc = cpt_lfs_attach(dev, blkaddr, true, nb_lf);
365 plt_err("Failed to attach CPT LF for inline outb, rc=%d", rc);
370 eng_grpmask = (1ULL << ROC_CPT_DFLT_ENG_GRP_SE |
371 1ULL << ROC_CPT_DFLT_ENG_GRP_SE_IE |
372 1ULL << ROC_CPT_DFLT_ENG_GRP_AE);
373 rc = cpt_lfs_alloc(dev, eng_grpmask, blkaddr,
374 !roc_nix->ipsec_out_sso_pffunc);
376 plt_err("Failed to alloc CPT LF resources, rc=%d", rc);
380 /* Get msix offsets */
381 rc = cpt_get_msix_offset(dev, &rsp);
383 plt_err("Failed to get CPT LF msix offset, rc=%d", rc);
387 mbox_memcpy(nix->cpt_msixoff,
388 nix->is_nix1 ? rsp->cpt1_lf_msixoff : rsp->cptlf_msixoff,
389 sizeof(nix->cpt_msixoff));
391 /* Alloc required num of cpt lfs */
392 lf_base = plt_zmalloc(nb_lf * sizeof(struct roc_cpt_lf), 0);
394 plt_err("Failed to alloc cpt lf memory");
399 /* Initialize CPT LF's */
400 for (i = 0; i < nb_lf; i++) {
404 lf->nb_desc = roc_nix->outb_nb_desc;
406 lf->msixoff = nix->cpt_msixoff[i];
407 lf->pci_dev = nix->pci_dev;
409 /* Setup CPT LF instruction queue */
410 rc = cpt_lf_init(lf);
412 plt_err("Failed to initialize CPT LF, rc=%d", rc);
416 /* Associate this CPT LF with NIX PFFUNC */
417 rc = cpt_lf_outb_cfg(dev, sso_pffunc, nix->dev.pf_func, i,
420 plt_err("Failed to setup CPT LF->(NIX,SSO) link, rc=%d",
426 roc_cpt_iq_enable(lf);
429 if (!roc_nix->ipsec_out_max_sa)
432 /* CN9K SA size is different */
433 if (roc_model_is_cn9k())
434 sa_sz = ROC_NIX_INL_ONF_IPSEC_OUTB_SA_SZ;
436 sa_sz = ROC_NIX_INL_OT_IPSEC_OUTB_SA_SZ;
437 /* Alloc contiguous memory of outbound SA */
438 sa_base = plt_zmalloc(sa_sz * roc_nix->ipsec_out_max_sa,
439 ROC_NIX_INL_SA_BASE_ALIGN);
441 plt_err("Outbound SA base alloc failed");
444 if (roc_model_is_cn10k()) {
445 for (i = 0; i < roc_nix->ipsec_out_max_sa; i++) {
446 sa = ((uint8_t *)sa_base) + (i * sa_sz);
447 roc_ot_ipsec_outb_sa_init(sa);
450 nix->outb_sa_base = sa_base;
451 nix->outb_sa_sz = sa_sz;
455 nix->cpt_lf_base = lf_base;
456 nix->nb_cpt_lf = nb_lf;
457 nix->outb_err_sso_pffunc = sso_pffunc;
458 nix->inl_outb_ena = true;
459 nix->outb_se_ring_cnt =
460 roc_nix->ipsec_out_max_sa / ROC_IPSEC_ERR_RING_MAX_ENTRY + 1;
461 nix->outb_se_ring_base =
462 roc_nix->port_id * ROC_NIX_SOFT_EXP_PER_PORT_MAX_RINGS;
464 if (inl_dev == NULL) {
465 nix->outb_se_ring_cnt = 0;
469 /* Allocate memory to be used as a ring buffer to poll for
470 * soft expiry event from ucode
472 ring_sz = (ROC_IPSEC_ERR_RING_MAX_ENTRY + 1) * sizeof(uint64_t);
473 ring_base = inl_dev->sa_soft_exp_ring;
474 for (i = 0; i < nix->outb_se_ring_cnt; i++) {
475 ring_base[nix->outb_se_ring_base + i] =
476 PLT_U64_CAST(plt_zmalloc(ring_sz, 0));
477 if (!ring_base[nix->outb_se_ring_base + i]) {
478 plt_err("Couldn't allocate memory for soft exp ring");
480 plt_free(PLT_PTR_CAST(
481 ring_base[nix->outb_se_ring_base + i]));
490 for (j = i - 1; j >= 0; j--)
491 cpt_lf_fini(&lf_base[j]);
494 rc |= cpt_lfs_free(dev);
496 rc |= cpt_lfs_detach(dev);
501 roc_nix_inl_outb_fini(struct roc_nix *roc_nix)
503 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
504 struct roc_cpt_lf *lf_base = nix->cpt_lf_base;
505 struct idev_cfg *idev = idev_get_cfg();
506 struct dev *dev = &nix->dev;
507 struct nix_inl_dev *inl_dev;
511 if (!nix->inl_outb_ena)
514 nix->inl_outb_ena = false;
516 /* Cleanup CPT LF instruction queue */
517 for (i = 0; i < nix->nb_cpt_lf; i++)
518 cpt_lf_fini(&lf_base[i]);
520 /* Free LF resources */
521 rc = cpt_lfs_free(dev);
523 plt_err("Failed to free CPT LF resources, rc=%d", rc);
527 rc = cpt_lfs_detach(dev);
529 plt_err("Failed to detach CPT LF, rc=%d", rc);
533 nix->cpt_lf_base = NULL;
536 /* Free outbound SA base */
537 plt_free(nix->outb_sa_base);
538 nix->outb_sa_base = NULL;
540 if (idev && idev->nix_inl_dev) {
541 inl_dev = idev->nix_inl_dev;
542 ring_base = inl_dev->sa_soft_exp_ring;
544 for (i = 0; i < ROC_NIX_INL_MAX_SOFT_EXP_RNGS; i++) {
546 plt_free(PLT_PTR_CAST(ring_base[i]));
555 roc_nix_inl_dev_is_probed(void)
557 struct idev_cfg *idev = idev_get_cfg();
562 return !!idev->nix_inl_dev;
566 roc_nix_inl_inb_is_enabled(struct roc_nix *roc_nix)
568 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
570 return nix->inl_inb_ena;
574 roc_nix_inl_outb_is_enabled(struct roc_nix *roc_nix)
576 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
578 return nix->inl_outb_ena;
582 roc_nix_inl_dev_rq_get(struct roc_nix_rq *rq)
584 struct idev_cfg *idev = idev_get_cfg();
585 struct nix_inl_dev *inl_dev;
586 struct roc_nix_rq *inl_rq;
593 inl_dev = idev->nix_inl_dev;
594 /* Nothing to do if no inline device */
598 /* Just take reference if already inited */
599 if (inl_dev->rq_refs) {
601 rq->inl_dev_ref = true;
606 inl_rq = &inl_dev->rq;
607 memset(inl_rq, 0, sizeof(struct roc_nix_rq));
609 /* Take RQ pool attributes from the first ethdev RQ */
611 inl_rq->aura_handle = rq->aura_handle;
612 inl_rq->first_skip = rq->first_skip;
613 inl_rq->later_skip = rq->later_skip;
614 inl_rq->lpb_size = rq->lpb_size;
615 inl_rq->lpb_drop_ena = true;
616 inl_rq->spb_ena = rq->spb_ena;
617 inl_rq->spb_aura_handle = rq->spb_aura_handle;
618 inl_rq->spb_size = rq->spb_size;
619 inl_rq->spb_drop_ena = !!rq->spb_ena;
621 if (!roc_model_is_cn9k()) {
622 uint64_t aura_limit =
623 roc_npa_aura_op_limit_get(inl_rq->aura_handle);
624 uint64_t aura_shift = plt_log2_u32(aura_limit);
625 uint64_t aura_drop, drop_pc;
630 aura_shift = aura_shift - 8;
632 /* Set first pass RQ to drop after part of buffers are in
633 * use to avoid metabuf alloc failure. This is needed as long
634 * as we cannot use different aura.
636 drop_pc = inl_dev->lpb_drop_pc;
637 aura_drop = ((aura_limit * drop_pc) / 100) >> aura_shift;
638 roc_npa_aura_drop_set(inl_rq->aura_handle, aura_drop, true);
641 if (inl_rq->spb_ena) {
642 uint64_t aura_limit =
643 roc_npa_aura_op_limit_get(inl_rq->spb_aura_handle);
644 uint64_t aura_shift = plt_log2_u32(aura_limit);
645 uint64_t aura_drop, drop_pc;
650 aura_shift = aura_shift - 8;
652 /* Set first pass RQ to drop after part of buffers are in
653 * use to avoid metabuf alloc failure. This is needed as long
654 * as we cannot use different aura.
656 drop_pc = inl_dev->spb_drop_pc;
657 aura_drop = ((aura_limit * drop_pc) / 100) >> aura_shift;
658 roc_npa_aura_drop_set(inl_rq->spb_aura_handle, aura_drop, true);
662 inl_rq->ipsech_ena = true;
664 inl_rq->flow_tag_width = 20;
665 /* Special tag mask */
666 inl_rq->tag_mask = rq->tag_mask;
667 inl_rq->tt = SSO_TT_ORDERED;
669 inl_rq->wqe_skip = inl_dev->wqe_skip;
670 inl_rq->sso_ena = true;
672 /* Prepare and send RQ init mbox */
673 if (roc_model_is_cn9k())
674 rc = nix_rq_cn9k_cfg(dev, inl_rq, inl_dev->qints, false, true);
676 rc = nix_rq_cfg(dev, inl_rq, inl_dev->qints, false, true);
678 plt_err("Failed to prepare aq_enq msg, rc=%d", rc);
682 rc = mbox_process(dev->mbox);
684 plt_err("Failed to send aq_enq msg, rc=%d", rc);
689 rq->inl_dev_ref = true;
694 roc_nix_inl_dev_rq_put(struct roc_nix_rq *rq)
696 struct idev_cfg *idev = idev_get_cfg();
697 struct nix_inl_dev *inl_dev;
698 struct roc_nix_rq *inl_rq;
705 if (!rq->inl_dev_ref)
708 inl_dev = idev->nix_inl_dev;
709 /* Inline device should be there if we have ref */
711 plt_err("Failed to find inline device with refs");
715 rq->inl_dev_ref = false;
717 if (inl_dev->rq_refs)
721 inl_rq = &inl_dev->rq;
722 /* There are no more references, disable RQ */
723 rc = nix_rq_ena_dis(dev, inl_rq, false);
725 plt_err("Failed to disable inline device rq, rc=%d", rc);
727 roc_npa_aura_drop_set(inl_rq->aura_handle, 0, false);
729 roc_npa_aura_drop_set(inl_rq->spb_aura_handle, 0, false);
731 /* Flush NIX LF for CN10K */
732 nix_rq_vwqe_flush(rq, inl_dev->vwqe_interval);
738 roc_nix_inl_dev_rq_limit_get(void)
740 struct idev_cfg *idev = idev_get_cfg();
741 struct nix_inl_dev *inl_dev;
742 struct roc_nix_rq *inl_rq;
744 if (!idev || !idev->nix_inl_dev)
747 inl_dev = idev->nix_inl_dev;
748 if (!inl_dev->rq_refs)
751 inl_rq = &inl_dev->rq;
753 return roc_npa_aura_op_limit_get(inl_rq->aura_handle);
757 roc_nix_inb_mode_set(struct roc_nix *roc_nix, bool use_inl_dev)
759 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
761 /* Info used by NPC flow rule add */
762 nix->inb_inl_dev = use_inl_dev;
766 roc_nix_inl_outb_soft_exp_poll_switch(struct roc_nix *roc_nix, bool poll)
768 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
769 struct idev_cfg *idev = idev_get_cfg();
770 struct nix_inl_dev *inl_dev;
771 uint16_t ring_idx, i;
773 if (!idev || !idev->nix_inl_dev)
776 inl_dev = idev->nix_inl_dev;
778 for (i = 0; i < nix->outb_se_ring_cnt; i++) {
779 ring_idx = nix->outb_se_ring_base + i;
782 plt_bitmap_set(inl_dev->soft_exp_ring_bmap, ring_idx);
784 plt_bitmap_clear(inl_dev->soft_exp_ring_bmap, ring_idx);
788 soft_exp_consumer_cnt++;
790 soft_exp_consumer_cnt--;
796 roc_nix_inb_is_with_inl_dev(struct roc_nix *roc_nix)
798 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
800 return nix->inb_inl_dev;
804 roc_nix_inl_dev_rq(void)
806 struct idev_cfg *idev = idev_get_cfg();
807 struct nix_inl_dev *inl_dev;
810 inl_dev = idev->nix_inl_dev;
811 if (inl_dev != NULL && inl_dev->rq_refs)
819 roc_nix_inl_outb_sso_pffunc_get(struct roc_nix *roc_nix)
821 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
823 return nix->outb_err_sso_pffunc;
827 roc_nix_inl_cb_register(roc_nix_inl_sso_work_cb_t cb, void *args)
829 struct idev_cfg *idev = idev_get_cfg();
830 struct nix_inl_dev *inl_dev;
835 inl_dev = idev->nix_inl_dev;
839 /* Be silent if registration called with same cb and args */
840 if (inl_dev->work_cb == cb && inl_dev->cb_args == args)
843 /* Don't allow registration again if registered with different cb */
844 if (inl_dev->work_cb)
847 inl_dev->work_cb = cb;
848 inl_dev->cb_args = args;
853 roc_nix_inl_cb_unregister(roc_nix_inl_sso_work_cb_t cb, void *args)
855 struct idev_cfg *idev = idev_get_cfg();
856 struct nix_inl_dev *inl_dev;
861 inl_dev = idev->nix_inl_dev;
865 if (inl_dev->work_cb != cb || inl_dev->cb_args != args)
868 inl_dev->work_cb = NULL;
869 inl_dev->cb_args = NULL;
874 roc_nix_inl_inb_tag_update(struct roc_nix *roc_nix, uint32_t tag_const,
877 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
878 struct roc_nix_ipsec_cfg cfg;
880 /* Be silent if inline inbound not enabled */
881 if (!nix->inl_inb_ena)
884 memset(&cfg, 0, sizeof(cfg));
885 cfg.sa_size = nix->inb_sa_sz;
886 cfg.iova = (uintptr_t)nix->inb_sa_base;
887 cfg.max_sa = nix->inb_spi_mask + 1;
889 cfg.tag_const = tag_const;
891 return roc_nix_lf_inl_ipsec_cfg(roc_nix, &cfg, true);
895 roc_nix_inl_sa_sync(struct roc_nix *roc_nix, void *sa, bool inb,
896 enum roc_nix_inl_sa_sync_op op)
898 struct idev_cfg *idev = idev_get_cfg();
899 struct nix_inl_dev *inl_dev = NULL;
900 struct roc_cpt_lf *outb_lf = NULL;
901 union cpt_lf_ctx_reload reload;
902 union cpt_lf_ctx_flush flush;
903 bool get_inl_lf = true;
907 /* Nothing much to do on cn9k */
908 if (roc_model_is_cn9k()) {
909 plt_atomic_thread_fence(__ATOMIC_ACQ_REL);
914 inl_dev = idev->nix_inl_dev;
916 if (!inl_dev && roc_nix == NULL)
920 nix = roc_nix_to_nix_priv(roc_nix);
921 outb_lf = nix->cpt_lf_base;
922 if (inb && !nix->inb_inl_dev)
926 if (inb && get_inl_lf) {
928 if (inl_dev && inl_dev->attach_cptlf)
929 outb_lf = &inl_dev->cpt_lf;
933 rbase = outb_lf->rbase;
938 case ROC_NIX_INL_SA_OP_FLUSH_INVAL:
941 case ROC_NIX_INL_SA_OP_FLUSH:
942 flush.s.cptr = ((uintptr_t)sa) >> 7;
943 plt_write64(flush.u, rbase + CPT_LF_CTX_FLUSH);
945 case ROC_NIX_INL_SA_OP_RELOAD:
946 reload.s.cptr = ((uintptr_t)sa) >> 7;
947 plt_write64(reload.u, rbase + CPT_LF_CTX_RELOAD);
954 plt_err("Could not get CPT LF for SA sync");
959 roc_nix_inl_ctx_write(struct roc_nix *roc_nix, void *sa_dptr, void *sa_cptr,
960 bool inb, uint16_t sa_len)
962 struct idev_cfg *idev = idev_get_cfg();
963 struct nix_inl_dev *inl_dev = NULL;
964 struct roc_cpt_lf *outb_lf = NULL;
965 union cpt_lf_ctx_flush flush;
966 bool get_inl_lf = true;
971 /* Nothing much to do on cn9k */
972 if (roc_model_is_cn9k()) {
973 plt_atomic_thread_fence(__ATOMIC_ACQ_REL);
978 inl_dev = idev->nix_inl_dev;
980 if (!inl_dev && roc_nix == NULL)
984 nix = roc_nix_to_nix_priv(roc_nix);
985 outb_lf = nix->cpt_lf_base;
987 if (inb && !nix->inb_inl_dev)
991 if (inb && get_inl_lf) {
993 if (inl_dev && inl_dev->attach_cptlf)
994 outb_lf = &inl_dev->cpt_lf;
998 rbase = outb_lf->rbase;
1001 rc = roc_cpt_ctx_write(outb_lf, sa_dptr, sa_cptr, sa_len);
1004 /* Trigger CTX flush to write dirty data back to DRAM */
1005 flush.s.cptr = ((uintptr_t)sa_cptr) >> 7;
1006 plt_write64(flush.u, rbase + CPT_LF_CTX_FLUSH);
1010 plt_nix_dbg("Could not get CPT LF for CTX write");
1015 roc_nix_inl_dev_lock(void)
1017 struct idev_cfg *idev = idev_get_cfg();
1020 plt_spinlock_lock(&idev->nix_inl_dev_lock);
1024 roc_nix_inl_dev_unlock(void)
1026 struct idev_cfg *idev = idev_get_cfg();
1029 plt_spinlock_unlock(&idev->nix_inl_dev_lock);