1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
8 PLT_STATIC_ASSERT(ROC_NIX_INL_ONF_IPSEC_INB_SA_SZ ==
9 1UL << ROC_NIX_INL_ONF_IPSEC_INB_SA_SZ_LOG2);
10 PLT_STATIC_ASSERT(ROC_NIX_INL_ONF_IPSEC_INB_SA_SZ == 512);
11 PLT_STATIC_ASSERT(ROC_NIX_INL_ONF_IPSEC_OUTB_SA_SZ ==
12 1UL << ROC_NIX_INL_ONF_IPSEC_OUTB_SA_SZ_LOG2);
13 PLT_STATIC_ASSERT(ROC_NIX_INL_OT_IPSEC_INB_SA_SZ ==
14 1UL << ROC_NIX_INL_OT_IPSEC_INB_SA_SZ_LOG2);
15 PLT_STATIC_ASSERT(ROC_NIX_INL_OT_IPSEC_INB_SA_SZ == 1024);
16 PLT_STATIC_ASSERT(ROC_NIX_INL_OT_IPSEC_OUTB_SA_SZ ==
17 1UL << ROC_NIX_INL_OT_IPSEC_OUTB_SA_SZ_LOG2);
20 nix_inl_inb_sa_tbl_setup(struct roc_nix *roc_nix)
22 uint16_t ipsec_in_max_spi = roc_nix->ipsec_in_max_spi;
23 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
24 struct roc_nix_ipsec_cfg cfg;
29 /* CN9K SA size is different */
30 if (roc_model_is_cn9k())
31 inb_sa_sz = ROC_NIX_INL_ONF_IPSEC_INB_SA_SZ;
33 inb_sa_sz = ROC_NIX_INL_OT_IPSEC_INB_SA_SZ;
35 /* Alloc contiguous memory for Inbound SA's */
36 nix->inb_sa_sz = inb_sa_sz;
37 nix->inb_sa_base = plt_zmalloc(inb_sa_sz * ipsec_in_max_spi,
38 ROC_NIX_INL_SA_BASE_ALIGN);
39 if (!nix->inb_sa_base) {
40 plt_err("Failed to allocate memory for Inbound SA");
43 if (roc_model_is_cn10k()) {
44 for (i = 0; i < ipsec_in_max_spi; i++) {
45 sa = ((uint8_t *)nix->inb_sa_base) + (i * inb_sa_sz);
46 roc_ot_ipsec_inb_sa_init(sa, true);
50 memset(&cfg, 0, sizeof(cfg));
51 cfg.sa_size = inb_sa_sz;
52 cfg.iova = (uintptr_t)nix->inb_sa_base;
53 cfg.max_sa = ipsec_in_max_spi + 1;
54 cfg.tt = SSO_TT_ORDERED;
56 /* Setup device specific inb SA table */
57 rc = roc_nix_lf_inl_ipsec_cfg(roc_nix, &cfg, true);
59 plt_err("Failed to setup NIX Inbound SA conf, rc=%d", rc);
65 plt_free(nix->inb_sa_base);
66 nix->inb_sa_base = NULL;
71 nix_inl_sa_tbl_release(struct roc_nix *roc_nix)
73 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
76 rc = roc_nix_lf_inl_ipsec_cfg(roc_nix, NULL, false);
78 plt_err("Failed to disable Inbound inline ipsec, rc=%d", rc);
82 plt_free(nix->inb_sa_base);
83 nix->inb_sa_base = NULL;
88 roc_nix_inl_outb_lf_base_get(struct roc_nix *roc_nix)
90 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
92 /* NIX Inline config needs to be done */
93 if (!nix->inl_outb_ena || !nix->cpt_lf_base)
96 return (struct roc_cpt_lf *)nix->cpt_lf_base;
100 roc_nix_inl_outb_sa_base_get(struct roc_nix *roc_nix)
102 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
104 return (uintptr_t)nix->outb_sa_base;
108 roc_nix_inl_inb_sa_base_get(struct roc_nix *roc_nix, bool inb_inl_dev)
110 struct idev_cfg *idev = idev_get_cfg();
111 struct nix_inl_dev *inl_dev;
112 struct nix *nix = NULL;
117 if (!inb_inl_dev && roc_nix == NULL)
121 nix = roc_nix_to_nix_priv(roc_nix);
122 if (!nix->inl_inb_ena)
127 inl_dev = idev->nix_inl_dev;
128 /* Return inline dev sa base */
130 return (uintptr_t)inl_dev->inb_sa_base;
134 return (uintptr_t)nix->inb_sa_base;
138 roc_nix_inl_inb_sa_max_spi(struct roc_nix *roc_nix, bool inb_inl_dev)
140 struct idev_cfg *idev = idev_get_cfg();
141 struct nix_inl_dev *inl_dev;
147 if (!inb_inl_dev && roc_nix == NULL)
151 nix = roc_nix_to_nix_priv(roc_nix);
152 if (!nix->inl_inb_ena)
157 inl_dev = idev->nix_inl_dev;
159 return inl_dev->ipsec_in_max_spi;
163 return roc_nix->ipsec_in_max_spi;
167 roc_nix_inl_inb_sa_sz(struct roc_nix *roc_nix, bool inl_dev_sa)
169 struct idev_cfg *idev = idev_get_cfg();
170 struct nix_inl_dev *inl_dev;
176 if (!inl_dev_sa && roc_nix == NULL)
180 nix = roc_nix_to_nix_priv(roc_nix);
182 return nix->inb_sa_sz;
186 inl_dev = idev->nix_inl_dev;
188 return inl_dev->inb_sa_sz;
195 roc_nix_inl_inb_sa_get(struct roc_nix *roc_nix, bool inb_inl_dev, uint32_t spi)
201 sa_base = roc_nix_inl_inb_sa_base_get(roc_nix, inb_inl_dev);
202 /* Check if SA base exists */
206 /* Check if SPI is in range */
207 max_spi = roc_nix_inl_inb_sa_max_spi(roc_nix, inb_inl_dev);
209 plt_err("Inbound SA SPI %u exceeds max %u", spi, max_spi);
214 sz = roc_nix_inl_inb_sa_sz(roc_nix, inb_inl_dev);
218 /* Basic logic of SPI->SA for now */
219 return (sa_base + (spi * sz));
223 roc_nix_inl_inb_init(struct roc_nix *roc_nix)
225 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
226 struct idev_cfg *idev = idev_get_cfg();
227 struct roc_cpt *roc_cpt;
234 /* Unless we have another mechanism to trigger
235 * onetime Inline config in CPTPF, we cannot
236 * support without CPT being probed.
240 plt_err("Cannot support inline inbound, cryptodev not probed");
244 if (roc_model_is_cn9k()) {
245 param1 = ROC_ONF_IPSEC_INB_MAX_L2_SZ;
247 union roc_ot_ipsec_inb_param1 u;
250 u.s.esp_trailer_disable = 1;
254 /* Do onetime Inbound Inline config in CPTPF */
255 rc = roc_cpt_inline_ipsec_inb_cfg(roc_cpt, param1, 0);
256 if (rc && rc != -EEXIST) {
257 plt_err("Failed to setup inbound lf, rc=%d", rc);
261 /* Setup Inbound SA table */
262 rc = nix_inl_inb_sa_tbl_setup(roc_nix);
266 nix->inl_inb_ena = true;
271 roc_nix_inl_inb_fini(struct roc_nix *roc_nix)
273 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
275 if (!nix->inl_inb_ena)
278 nix->inl_inb_ena = false;
280 /* Flush Inbound CTX cache entries */
281 roc_nix_cpt_ctx_cache_sync(roc_nix);
283 /* Disable Inbound SA */
284 return nix_inl_sa_tbl_release(roc_nix);
288 roc_nix_inl_outb_init(struct roc_nix *roc_nix)
290 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
291 struct idev_cfg *idev = idev_get_cfg();
292 struct roc_cpt_lf *lf_base, *lf;
293 struct dev *dev = &nix->dev;
294 struct msix_offset_rsp *rsp;
295 struct nix_inl_dev *inl_dev;
308 nb_lf = roc_nix->outb_nb_crypto_qs;
309 blkaddr = nix->is_nix1 ? RVU_BLOCK_ADDR_CPT1 : RVU_BLOCK_ADDR_CPT0;
311 /* Retrieve inline device if present */
312 inl_dev = idev->nix_inl_dev;
313 sso_pffunc = inl_dev ? inl_dev->dev.pf_func : idev_sso_pffunc_get();
315 plt_err("Failed to setup inline outb, need either "
316 "inline device or sso device");
320 /* Attach CPT LF for outbound */
321 rc = cpt_lfs_attach(dev, blkaddr, true, nb_lf);
323 plt_err("Failed to attach CPT LF for inline outb, rc=%d", rc);
328 eng_grpmask = (1ULL << ROC_CPT_DFLT_ENG_GRP_SE |
329 1ULL << ROC_CPT_DFLT_ENG_GRP_SE_IE |
330 1ULL << ROC_CPT_DFLT_ENG_GRP_AE);
331 rc = cpt_lfs_alloc(dev, eng_grpmask, blkaddr, true);
333 plt_err("Failed to alloc CPT LF resources, rc=%d", rc);
337 /* Get msix offsets */
338 rc = cpt_get_msix_offset(dev, &rsp);
340 plt_err("Failed to get CPT LF msix offset, rc=%d", rc);
344 mbox_memcpy(nix->cpt_msixoff,
345 nix->is_nix1 ? rsp->cpt1_lf_msixoff : rsp->cptlf_msixoff,
346 sizeof(nix->cpt_msixoff));
348 /* Alloc required num of cpt lfs */
349 lf_base = plt_zmalloc(nb_lf * sizeof(struct roc_cpt_lf), 0);
351 plt_err("Failed to alloc cpt lf memory");
356 /* Initialize CPT LF's */
357 for (i = 0; i < nb_lf; i++) {
361 lf->nb_desc = roc_nix->outb_nb_desc;
363 lf->msixoff = nix->cpt_msixoff[i];
364 lf->pci_dev = nix->pci_dev;
366 /* Setup CPT LF instruction queue */
367 rc = cpt_lf_init(lf);
369 plt_err("Failed to initialize CPT LF, rc=%d", rc);
373 /* Associate this CPT LF with NIX PFFUNC */
374 rc = cpt_lf_outb_cfg(dev, sso_pffunc, nix->dev.pf_func, i,
377 plt_err("Failed to setup CPT LF->(NIX,SSO) link, rc=%d",
383 roc_cpt_iq_enable(lf);
386 if (!roc_nix->ipsec_out_max_sa)
389 /* CN9K SA size is different */
390 if (roc_model_is_cn9k())
391 sa_sz = ROC_NIX_INL_ONF_IPSEC_OUTB_SA_SZ;
393 sa_sz = ROC_NIX_INL_OT_IPSEC_OUTB_SA_SZ;
394 /* Alloc contiguous memory of outbound SA */
395 sa_base = plt_zmalloc(sa_sz * roc_nix->ipsec_out_max_sa,
396 ROC_NIX_INL_SA_BASE_ALIGN);
398 plt_err("Outbound SA base alloc failed");
401 if (roc_model_is_cn10k()) {
402 for (i = 0; i < roc_nix->ipsec_out_max_sa; i++) {
403 sa = ((uint8_t *)sa_base) + (i * sa_sz);
404 roc_ot_ipsec_outb_sa_init(sa);
407 nix->outb_sa_base = sa_base;
408 nix->outb_sa_sz = sa_sz;
412 nix->cpt_lf_base = lf_base;
413 nix->nb_cpt_lf = nb_lf;
414 nix->outb_err_sso_pffunc = sso_pffunc;
415 nix->inl_outb_ena = true;
419 for (j = i - 1; j >= 0; j--)
420 cpt_lf_fini(&lf_base[j]);
423 rc |= cpt_lfs_free(dev);
425 rc |= cpt_lfs_detach(dev);
430 roc_nix_inl_outb_fini(struct roc_nix *roc_nix)
432 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
433 struct roc_cpt_lf *lf_base = nix->cpt_lf_base;
434 struct dev *dev = &nix->dev;
437 if (!nix->inl_outb_ena)
440 nix->inl_outb_ena = false;
442 /* Cleanup CPT LF instruction queue */
443 for (i = 0; i < nix->nb_cpt_lf; i++)
444 cpt_lf_fini(&lf_base[i]);
446 /* Free LF resources */
447 rc = cpt_lfs_free(dev);
449 plt_err("Failed to free CPT LF resources, rc=%d", rc);
453 rc = cpt_lfs_detach(dev);
455 plt_err("Failed to detach CPT LF, rc=%d", rc);
459 nix->cpt_lf_base = NULL;
462 /* Free outbound SA base */
463 plt_free(nix->outb_sa_base);
464 nix->outb_sa_base = NULL;
471 roc_nix_inl_dev_is_probed(void)
473 struct idev_cfg *idev = idev_get_cfg();
478 return !!idev->nix_inl_dev;
482 roc_nix_inl_inb_is_enabled(struct roc_nix *roc_nix)
484 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
486 return nix->inl_inb_ena;
490 roc_nix_inl_outb_is_enabled(struct roc_nix *roc_nix)
492 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
494 return nix->inl_outb_ena;
498 roc_nix_inl_dev_rq_get(struct roc_nix_rq *rq)
500 struct idev_cfg *idev = idev_get_cfg();
501 struct nix_inl_dev *inl_dev;
502 struct roc_nix_rq *inl_rq;
509 inl_dev = idev->nix_inl_dev;
510 /* Nothing to do if no inline device */
514 /* Just take reference if already inited */
515 if (inl_dev->rq_refs) {
517 rq->inl_dev_ref = true;
522 inl_rq = &inl_dev->rq;
523 memset(inl_rq, 0, sizeof(struct roc_nix_rq));
525 /* Take RQ pool attributes from the first ethdev RQ */
527 inl_rq->aura_handle = rq->aura_handle;
528 inl_rq->first_skip = rq->first_skip;
529 inl_rq->later_skip = rq->later_skip;
530 inl_rq->lpb_size = rq->lpb_size;
532 if (!roc_model_is_cn9k()) {
533 uint64_t aura_limit =
534 roc_npa_aura_op_limit_get(inl_rq->aura_handle);
535 uint64_t aura_shift = plt_log2_u32(aura_limit);
540 aura_shift = aura_shift - 8;
542 /* Set first pass RQ to drop when half of the buffers are in
543 * use to avoid metabuf alloc failure. This is needed as long
544 * as we cannot use different
546 inl_rq->red_pass = (aura_limit / 2) >> aura_shift;
547 inl_rq->red_drop = ((aura_limit / 2) - 1) >> aura_shift;
551 inl_rq->ipsech_ena = true;
553 inl_rq->flow_tag_width = 20;
554 /* Special tag mask */
555 inl_rq->tag_mask = 0xFFF00000;
556 inl_rq->tt = SSO_TT_ORDERED;
558 inl_rq->wqe_skip = inl_dev->wqe_skip;
559 inl_rq->sso_ena = true;
561 /* Prepare and send RQ init mbox */
562 if (roc_model_is_cn9k())
563 rc = nix_rq_cn9k_cfg(dev, inl_rq, inl_dev->qints, false, true);
565 rc = nix_rq_cfg(dev, inl_rq, inl_dev->qints, false, true);
567 plt_err("Failed to prepare aq_enq msg, rc=%d", rc);
571 rc = mbox_process(dev->mbox);
573 plt_err("Failed to send aq_enq msg, rc=%d", rc);
578 rq->inl_dev_ref = true;
583 roc_nix_inl_dev_rq_put(struct roc_nix_rq *rq)
585 struct idev_cfg *idev = idev_get_cfg();
586 struct nix_inl_dev *inl_dev;
587 struct roc_nix_rq *inl_rq;
594 if (!rq->inl_dev_ref)
597 inl_dev = idev->nix_inl_dev;
598 /* Inline device should be there if we have ref */
600 plt_err("Failed to find inline device with refs");
604 rq->inl_dev_ref = false;
606 if (inl_dev->rq_refs)
610 inl_rq = &inl_dev->rq;
611 /* There are no more references, disable RQ */
612 rc = nix_rq_ena_dis(dev, inl_rq, false);
614 plt_err("Failed to disable inline device rq, rc=%d", rc);
616 /* Flush NIX LF for CN10K */
617 nix_rq_vwqe_flush(rq, inl_dev->vwqe_interval);
623 roc_nix_inl_dev_rq_limit_get(void)
625 struct idev_cfg *idev = idev_get_cfg();
626 struct nix_inl_dev *inl_dev;
627 struct roc_nix_rq *inl_rq;
629 if (!idev || !idev->nix_inl_dev)
632 inl_dev = idev->nix_inl_dev;
633 if (!inl_dev->rq_refs)
636 inl_rq = &inl_dev->rq;
638 return roc_npa_aura_op_limit_get(inl_rq->aura_handle);
642 roc_nix_inb_mode_set(struct roc_nix *roc_nix, bool use_inl_dev)
644 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
646 /* Info used by NPC flow rule add */
647 nix->inb_inl_dev = use_inl_dev;
651 roc_nix_inb_is_with_inl_dev(struct roc_nix *roc_nix)
653 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
655 return nix->inb_inl_dev;
659 roc_nix_inl_dev_rq(void)
661 struct idev_cfg *idev = idev_get_cfg();
662 struct nix_inl_dev *inl_dev;
665 inl_dev = idev->nix_inl_dev;
666 if (inl_dev != NULL && inl_dev->rq_refs)
674 roc_nix_inl_outb_sso_pffunc_get(struct roc_nix *roc_nix)
676 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
678 return nix->outb_err_sso_pffunc;
682 roc_nix_inl_cb_register(roc_nix_inl_sso_work_cb_t cb, void *args)
684 struct idev_cfg *idev = idev_get_cfg();
685 struct nix_inl_dev *inl_dev;
690 inl_dev = idev->nix_inl_dev;
694 /* Be silent if registration called with same cb and args */
695 if (inl_dev->work_cb == cb && inl_dev->cb_args == args)
698 /* Don't allow registration again if registered with different cb */
699 if (inl_dev->work_cb)
702 inl_dev->work_cb = cb;
703 inl_dev->cb_args = args;
708 roc_nix_inl_cb_unregister(roc_nix_inl_sso_work_cb_t cb, void *args)
710 struct idev_cfg *idev = idev_get_cfg();
711 struct nix_inl_dev *inl_dev;
716 inl_dev = idev->nix_inl_dev;
720 if (inl_dev->work_cb != cb || inl_dev->cb_args != args)
723 inl_dev->work_cb = NULL;
724 inl_dev->cb_args = NULL;
729 roc_nix_inl_inb_tag_update(struct roc_nix *roc_nix, uint32_t tag_const,
732 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
733 struct roc_nix_ipsec_cfg cfg;
735 /* Be silent if inline inbound not enabled */
736 if (!nix->inl_inb_ena)
739 memset(&cfg, 0, sizeof(cfg));
740 cfg.sa_size = nix->inb_sa_sz;
741 cfg.iova = (uintptr_t)nix->inb_sa_base;
742 cfg.max_sa = roc_nix->ipsec_in_max_spi + 1;
744 cfg.tag_const = tag_const;
746 return roc_nix_lf_inl_ipsec_cfg(roc_nix, &cfg, true);
750 roc_nix_inl_sa_sync(struct roc_nix *roc_nix, void *sa, bool inb,
751 enum roc_nix_inl_sa_sync_op op)
753 struct idev_cfg *idev = idev_get_cfg();
754 struct nix_inl_dev *inl_dev = NULL;
755 struct roc_cpt_lf *outb_lf = NULL;
756 union cpt_lf_ctx_reload reload;
757 union cpt_lf_ctx_flush flush;
758 bool get_inl_lf = true;
762 /* Nothing much to do on cn9k */
763 if (roc_model_is_cn9k()) {
764 plt_atomic_thread_fence(__ATOMIC_ACQ_REL);
769 inl_dev = idev->nix_inl_dev;
771 if (!inl_dev && roc_nix == NULL)
775 nix = roc_nix_to_nix_priv(roc_nix);
776 outb_lf = nix->cpt_lf_base;
777 if (inb && !nix->inb_inl_dev)
781 if (inb && get_inl_lf) {
783 if (inl_dev && inl_dev->attach_cptlf)
784 outb_lf = &inl_dev->cpt_lf;
788 rbase = outb_lf->rbase;
793 case ROC_NIX_INL_SA_OP_FLUSH_INVAL:
796 case ROC_NIX_INL_SA_OP_FLUSH:
797 flush.s.cptr = ((uintptr_t)sa) >> 7;
798 plt_write64(flush.u, rbase + CPT_LF_CTX_FLUSH);
800 case ROC_NIX_INL_SA_OP_RELOAD:
801 reload.s.cptr = ((uintptr_t)sa) >> 7;
802 plt_write64(reload.u, rbase + CPT_LF_CTX_RELOAD);
809 plt_err("Could not get CPT LF for SA sync");
814 roc_nix_inl_ctx_write(struct roc_nix *roc_nix, void *sa_dptr, void *sa_cptr,
815 bool inb, uint16_t sa_len)
817 struct idev_cfg *idev = idev_get_cfg();
818 struct nix_inl_dev *inl_dev = NULL;
819 struct roc_cpt_lf *outb_lf = NULL;
820 union cpt_lf_ctx_flush flush;
821 bool get_inl_lf = true;
826 /* Nothing much to do on cn9k */
827 if (roc_model_is_cn9k()) {
828 plt_atomic_thread_fence(__ATOMIC_ACQ_REL);
833 inl_dev = idev->nix_inl_dev;
835 if (!inl_dev && roc_nix == NULL)
839 nix = roc_nix_to_nix_priv(roc_nix);
840 outb_lf = nix->cpt_lf_base;
842 if (inb && !nix->inb_inl_dev)
846 if (inb && get_inl_lf) {
848 if (inl_dev && inl_dev->attach_cptlf)
849 outb_lf = &inl_dev->cpt_lf;
853 rbase = outb_lf->rbase;
856 rc = roc_cpt_ctx_write(outb_lf, sa_dptr, sa_cptr, sa_len);
859 /* Trigger CTX flush to write dirty data back to DRAM */
860 flush.s.cptr = ((uintptr_t)sa_cptr) >> 7;
861 plt_write64(flush.u, rbase + CPT_LF_CTX_FLUSH);
865 plt_nix_dbg("Could not get CPT LF for CTX write");
870 roc_nix_inl_dev_lock(void)
872 struct idev_cfg *idev = idev_get_cfg();
875 plt_spinlock_lock(&idev->nix_inl_dev_lock);
879 roc_nix_inl_dev_unlock(void)
881 struct idev_cfg *idev = idev_get_cfg();
884 plt_spinlock_unlock(&idev->nix_inl_dev_lock);