1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
4 #ifndef _ROC_NIX_INL_H_
5 #define _ROC_NIX_INL_H_
8 #define ROC_NIX_INL_ONF_IPSEC_INB_HW_SZ \
9 PLT_ALIGN(sizeof(struct roc_onf_ipsec_inb_sa), ROC_ALIGN)
10 /* ONF INB SW reserved area */
11 #define ROC_NIX_INL_ONF_IPSEC_INB_SW_RSVD 384
12 #define ROC_NIX_INL_ONF_IPSEC_INB_SA_SZ \
13 (ROC_NIX_INL_ONF_IPSEC_INB_HW_SZ + ROC_NIX_INL_ONF_IPSEC_INB_SW_RSVD)
14 #define ROC_NIX_INL_ONF_IPSEC_INB_SA_SZ_LOG2 9
16 /* ONF OUTB HW area */
17 #define ROC_NIX_INL_ONF_IPSEC_OUTB_HW_SZ \
18 PLT_ALIGN(sizeof(struct roc_onf_ipsec_outb_sa), ROC_ALIGN)
19 /* ONF OUTB SW reserved area */
20 #define ROC_NIX_INL_ONF_IPSEC_OUTB_SW_RSVD 128
21 #define ROC_NIX_INL_ONF_IPSEC_OUTB_SA_SZ \
22 (ROC_NIX_INL_ONF_IPSEC_OUTB_HW_SZ + ROC_NIX_INL_ONF_IPSEC_OUTB_SW_RSVD)
23 #define ROC_NIX_INL_ONF_IPSEC_OUTB_SA_SZ_LOG2 8
26 #define ROC_NIX_INL_OT_IPSEC_INB_HW_SZ \
27 PLT_ALIGN(sizeof(struct roc_ot_ipsec_inb_sa), ROC_ALIGN)
28 /* OT INB SW reserved area */
29 #define ROC_NIX_INL_OT_IPSEC_INB_SW_RSVD 128
30 #define ROC_NIX_INL_OT_IPSEC_INB_SA_SZ \
31 (ROC_NIX_INL_OT_IPSEC_INB_HW_SZ + ROC_NIX_INL_OT_IPSEC_INB_SW_RSVD)
32 #define ROC_NIX_INL_OT_IPSEC_INB_SA_SZ_LOG2 10
35 #define ROC_NIX_INL_OT_IPSEC_OUTB_HW_SZ \
36 PLT_ALIGN(sizeof(struct roc_ot_ipsec_outb_sa), ROC_ALIGN)
37 /* OT OUTB SW reserved area */
38 #define ROC_NIX_INL_OT_IPSEC_OUTB_SW_RSVD 128
39 #define ROC_NIX_INL_OT_IPSEC_OUTB_SA_SZ \
40 (ROC_NIX_INL_OT_IPSEC_OUTB_HW_SZ + ROC_NIX_INL_OT_IPSEC_OUTB_SW_RSVD)
41 #define ROC_NIX_INL_OT_IPSEC_OUTB_SA_SZ_LOG2 9
43 /* Alignment of SA Base */
44 #define ROC_NIX_INL_SA_BASE_ALIGN BIT_ULL(16)
46 static inline struct roc_onf_ipsec_inb_sa *
47 roc_nix_inl_onf_ipsec_inb_sa(uintptr_t base, uint64_t idx)
49 uint64_t off = idx << ROC_NIX_INL_ONF_IPSEC_INB_SA_SZ_LOG2;
51 return PLT_PTR_ADD(base, off);
54 static inline struct roc_onf_ipsec_outb_sa *
55 roc_nix_inl_onf_ipsec_outb_sa(uintptr_t base, uint64_t idx)
57 uint64_t off = idx << ROC_NIX_INL_ONF_IPSEC_OUTB_SA_SZ_LOG2;
59 return PLT_PTR_ADD(base, off);
63 roc_nix_inl_onf_ipsec_inb_sa_sw_rsvd(void *sa)
65 return PLT_PTR_ADD(sa, ROC_NIX_INL_ONF_IPSEC_INB_HW_SZ);
69 roc_nix_inl_onf_ipsec_outb_sa_sw_rsvd(void *sa)
71 return PLT_PTR_ADD(sa, ROC_NIX_INL_ONF_IPSEC_OUTB_HW_SZ);
74 static inline struct roc_ot_ipsec_inb_sa *
75 roc_nix_inl_ot_ipsec_inb_sa(uintptr_t base, uint64_t idx)
77 uint64_t off = idx << ROC_NIX_INL_OT_IPSEC_INB_SA_SZ_LOG2;
79 return PLT_PTR_ADD(base, off);
82 static inline struct roc_ot_ipsec_outb_sa *
83 roc_nix_inl_ot_ipsec_outb_sa(uintptr_t base, uint64_t idx)
85 uint64_t off = idx << ROC_NIX_INL_OT_IPSEC_OUTB_SA_SZ_LOG2;
87 return PLT_PTR_ADD(base, off);
91 roc_nix_inl_ot_ipsec_inb_sa_sw_rsvd(void *sa)
93 return PLT_PTR_ADD(sa, ROC_NIX_INL_OT_IPSEC_INB_HW_SZ);
97 roc_nix_inl_ot_ipsec_outb_sa_sw_rsvd(void *sa)
99 return PLT_PTR_ADD(sa, ROC_NIX_INL_OT_IPSEC_OUTB_HW_SZ);
102 /* Inline device SSO Work callback */
103 typedef void (*roc_nix_inl_sso_work_cb_t)(uint64_t *gw, void *args);
105 struct roc_nix_inl_dev {
106 /* Input parameters */
107 struct plt_pci_device *pci_dev;
108 uint32_t ipsec_in_min_spi;
109 uint32_t ipsec_in_max_spi;
111 bool is_multi_channel;
118 /* End of input parameters */
120 #define ROC_NIX_INL_MEM_SZ (1280)
121 uint8_t reserved[ROC_NIX_INL_MEM_SZ] __plt_cache_aligned;
122 } __plt_cache_aligned;
124 /* NIX Inline Device API */
125 int __roc_api roc_nix_inl_dev_init(struct roc_nix_inl_dev *roc_inl_dev);
126 int __roc_api roc_nix_inl_dev_fini(struct roc_nix_inl_dev *roc_inl_dev);
127 void __roc_api roc_nix_inl_dev_dump(struct roc_nix_inl_dev *roc_inl_dev);
128 bool __roc_api roc_nix_inl_dev_is_probed(void);
129 void __roc_api roc_nix_inl_dev_lock(void);
130 void __roc_api roc_nix_inl_dev_unlock(void);
131 int __roc_api roc_nix_inl_dev_xaq_realloc(uint64_t aura_handle);
132 uint16_t __roc_api roc_nix_inl_dev_pffunc_get(void);
134 /* NIX Inline Inbound API */
135 int __roc_api roc_nix_inl_inb_init(struct roc_nix *roc_nix);
136 int __roc_api roc_nix_inl_inb_fini(struct roc_nix *roc_nix);
137 bool __roc_api roc_nix_inl_inb_is_enabled(struct roc_nix *roc_nix);
138 uintptr_t __roc_api roc_nix_inl_inb_sa_base_get(struct roc_nix *roc_nix,
140 uint32_t __roc_api roc_nix_inl_inb_spi_range(struct roc_nix *roc_nix,
141 bool inl_dev_sa, uint32_t *min,
143 uint32_t __roc_api roc_nix_inl_inb_sa_sz(struct roc_nix *roc_nix,
145 uintptr_t __roc_api roc_nix_inl_inb_sa_get(struct roc_nix *roc_nix,
146 bool inl_dev_sa, uint32_t spi);
147 void __roc_api roc_nix_inb_mode_set(struct roc_nix *roc_nix, bool use_inl_dev);
148 int __roc_api roc_nix_inl_dev_rq_get(struct roc_nix_rq *rq);
149 int __roc_api roc_nix_inl_dev_rq_put(struct roc_nix_rq *rq);
150 bool __roc_api roc_nix_inb_is_with_inl_dev(struct roc_nix *roc_nix);
151 struct roc_nix_rq *__roc_api roc_nix_inl_dev_rq(void);
152 int __roc_api roc_nix_inl_inb_tag_update(struct roc_nix *roc_nix,
153 uint32_t tag_const, uint8_t tt);
154 uint64_t __roc_api roc_nix_inl_dev_rq_limit_get(void);
156 /* NIX Inline Outbound API */
157 int __roc_api roc_nix_inl_outb_init(struct roc_nix *roc_nix);
158 int __roc_api roc_nix_inl_outb_fini(struct roc_nix *roc_nix);
159 bool __roc_api roc_nix_inl_outb_is_enabled(struct roc_nix *roc_nix);
160 uintptr_t __roc_api roc_nix_inl_outb_sa_base_get(struct roc_nix *roc_nix);
161 struct roc_cpt_lf *__roc_api
162 roc_nix_inl_outb_lf_base_get(struct roc_nix *roc_nix);
163 uint16_t __roc_api roc_nix_inl_outb_sso_pffunc_get(struct roc_nix *roc_nix);
164 int __roc_api roc_nix_inl_cb_register(roc_nix_inl_sso_work_cb_t cb, void *args);
165 int __roc_api roc_nix_inl_cb_unregister(roc_nix_inl_sso_work_cb_t cb,
167 /* NIX Inline/Outbound API */
168 enum roc_nix_inl_sa_sync_op {
169 ROC_NIX_INL_SA_OP_FLUSH,
170 ROC_NIX_INL_SA_OP_FLUSH_INVAL,
171 ROC_NIX_INL_SA_OP_RELOAD,
174 int __roc_api roc_nix_inl_sa_sync(struct roc_nix *roc_nix, void *sa, bool inb,
175 enum roc_nix_inl_sa_sync_op op);
176 int __roc_api roc_nix_inl_ctx_write(struct roc_nix *roc_nix, void *sa_dptr,
177 void *sa_cptr, bool inb, uint16_t sa_len);
179 #endif /* _ROC_NIX_INL_H_ */