1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
8 #define XAQ_CACHE_CNT 0x7
10 /* Default Rx Config for Inline NIX LF */
11 #define NIX_INL_LF_RX_CFG \
12 (ROC_NIX_LF_RX_CFG_DROP_RE | ROC_NIX_LF_RX_CFG_L2_LEN_ERR | \
13 ROC_NIX_LF_RX_CFG_IP6_UDP_OPT | ROC_NIX_LF_RX_CFG_DIS_APAD | \
14 ROC_NIX_LF_RX_CFG_CSUM_IL4 | ROC_NIX_LF_RX_CFG_CSUM_OL4 | \
15 ROC_NIX_LF_RX_CFG_LEN_IL4 | ROC_NIX_LF_RX_CFG_LEN_IL3 | \
16 ROC_NIX_LF_RX_CFG_LEN_OL4 | ROC_NIX_LF_RX_CFG_LEN_OL3)
19 nix_inl_dev_pffunc_get(void)
21 struct idev_cfg *idev = idev_get_cfg();
22 struct nix_inl_dev *inl_dev;
25 inl_dev = idev->nix_inl_dev;
27 return inl_dev->dev.pf_func;
33 nix_inl_selftest_work_cb(uint64_t *gw, void *args)
35 uintptr_t work = gw[1];
37 *((uintptr_t *)args + (gw[0] & 0x1)) = work;
39 plt_atomic_thread_fence(__ATOMIC_ACQ_REL);
43 nix_inl_selftest(void)
45 struct idev_cfg *idev = idev_get_cfg();
46 roc_nix_inl_sso_work_cb_t save_cb;
47 static uintptr_t work_arr[2];
48 struct nix_inl_dev *inl_dev;
56 inl_dev = idev->nix_inl_dev;
60 plt_info("Performing nix inl self test");
62 /* Save and update cb to test cb */
63 save_cb = inl_dev->work_cb;
64 save_cb_args = inl_dev->cb_args;
65 inl_dev->work_cb = nix_inl_selftest_work_cb;
66 inl_dev->cb_args = work_arr;
68 plt_atomic_thread_fence(__ATOMIC_ACQ_REL);
70 #define WORK_MAGIC1 0x335577ff0
71 #define WORK_MAGIC2 0xdeadbeef0
74 add_work0 = ((uint64_t)(SSO_TT_ORDERED) << 32) | 0x0;
75 roc_store_pair(add_work0, WORK_MAGIC1, inl_dev->sso_base);
76 add_work0 = ((uint64_t)(SSO_TT_ORDERED) << 32) | 0x1;
77 roc_store_pair(add_work0, WORK_MAGIC2, inl_dev->sso_base);
81 /* Check if we got expected work */
82 if (work_arr[0] != WORK_MAGIC1 || work_arr[1] != WORK_MAGIC2) {
83 plt_err("Failed to get expected work, [0]=%p [1]=%p",
84 (void *)work_arr[0], (void *)work_arr[1]);
89 plt_info("Work, [0]=%p [1]=%p", (void *)work_arr[0],
94 inl_dev->work_cb = save_cb;
95 inl_dev->cb_args = save_cb_args;
100 nix_inl_nix_ipsec_cfg(struct nix_inl_dev *inl_dev, bool ena)
102 struct nix_inline_ipsec_lf_cfg *lf_cfg;
103 struct mbox *mbox = (&inl_dev->dev)->mbox;
106 lf_cfg = mbox_alloc_msg_nix_inline_ipsec_lf_cfg(mbox);
111 sa_w = plt_align32pow2(inl_dev->ipsec_in_max_spi + 1);
112 sa_w = plt_log2_u32(sa_w);
115 lf_cfg->sa_base_addr = (uintptr_t)inl_dev->inb_sa_base;
116 lf_cfg->ipsec_cfg1.sa_idx_w = sa_w;
117 /* CN9K SA size is different */
118 if (roc_model_is_cn9k())
119 lf_cfg->ipsec_cfg0.lenm1_max = NIX_CN9K_MAX_HW_FRS - 1;
121 lf_cfg->ipsec_cfg0.lenm1_max = NIX_RPM_MAX_HW_FRS - 1;
122 lf_cfg->ipsec_cfg1.sa_idx_max = inl_dev->ipsec_in_max_spi;
123 lf_cfg->ipsec_cfg0.sa_pow2_size =
124 plt_log2_u32(inl_dev->inb_sa_sz);
126 lf_cfg->ipsec_cfg0.tag_const = 0;
127 lf_cfg->ipsec_cfg0.tt = SSO_TT_ORDERED;
132 return mbox_process(mbox);
136 nix_inl_cpt_setup(struct nix_inl_dev *inl_dev)
138 struct roc_cpt_lf *lf = &inl_dev->cpt_lf;
139 struct dev *dev = &inl_dev->dev;
143 if (!inl_dev->attach_cptlf)
147 eng_grpmask = (1ULL << ROC_CPT_DFLT_ENG_GRP_SE |
148 1ULL << ROC_CPT_DFLT_ENG_GRP_SE_IE |
149 1ULL << ROC_CPT_DFLT_ENG_GRP_AE);
150 rc = cpt_lfs_alloc(dev, eng_grpmask, RVU_BLOCK_ADDR_CPT0, false);
152 plt_err("Failed to alloc CPT LF resources, rc=%d", rc);
156 /* Setup CPT LF for submitting control opcode */
157 lf = &inl_dev->cpt_lf;
159 lf->nb_desc = 0; /* Set to default */
160 lf->dev = &inl_dev->dev;
161 lf->msixoff = inl_dev->cpt_msixoff;
162 lf->pci_dev = inl_dev->pci_dev;
164 rc = cpt_lf_init(lf);
166 plt_err("Failed to initialize CPT LF, rc=%d", rc);
170 roc_cpt_iq_enable(lf);
173 rc |= cpt_lfs_free(dev);
178 nix_inl_cpt_release(struct nix_inl_dev *inl_dev)
180 struct roc_cpt_lf *lf = &inl_dev->cpt_lf;
181 struct dev *dev = &inl_dev->dev;
184 if (!inl_dev->attach_cptlf)
187 /* Cleanup CPT LF queue */
190 /* Free LF resources */
191 rc = cpt_lfs_free(dev);
193 plt_err("Failed to free CPT LF resources, rc=%d", rc);
197 rc = cpt_lfs_detach(dev);
199 plt_err("Failed to detach CPT LF, rc=%d", rc);
206 nix_inl_sso_setup(struct nix_inl_dev *inl_dev)
208 struct sso_lf_alloc_rsp *sso_rsp;
209 struct dev *dev = &inl_dev->dev;
210 uint32_t xaq_cnt, count, aura;
211 uint16_t hwgrp[1] = {0};
212 struct npa_pool_s pool;
217 rc = sso_lf_alloc(dev, SSO_LF_TYPE_HWS, 1, NULL);
219 plt_err("Failed to alloc SSO HWS, rc=%d", rc);
224 rc = sso_lf_alloc(dev, SSO_LF_TYPE_HWGRP, 1, (void **)&sso_rsp);
226 plt_err("Failed to alloc SSO HWGRP, rc=%d", rc);
230 inl_dev->xaq_buf_size = sso_rsp->xaq_buf_size;
231 inl_dev->xae_waes = sso_rsp->xaq_wq_entries;
232 inl_dev->iue = sso_rsp->in_unit_entries;
234 /* Create XAQ pool */
235 xaq_cnt = XAQ_CACHE_CNT;
236 xaq_cnt += inl_dev->iue / inl_dev->xae_waes;
237 plt_sso_dbg("Configuring %d xaq buffers", xaq_cnt);
239 inl_dev->xaq_mem = plt_zmalloc(inl_dev->xaq_buf_size * xaq_cnt,
240 inl_dev->xaq_buf_size);
241 if (!inl_dev->xaq_mem) {
243 plt_err("Failed to alloc xaq buf mem");
247 memset(&pool, 0, sizeof(struct npa_pool_s));
249 rc = roc_npa_pool_create(&inl_dev->xaq_aura, inl_dev->xaq_buf_size,
250 xaq_cnt, NULL, &pool);
252 plt_err("Failed to alloc aura for XAQ, rc=%d", rc);
256 /* Fill the XAQ buffers */
257 iova = (uint64_t)inl_dev->xaq_mem;
258 for (count = 0; count < xaq_cnt; count++) {
259 roc_npa_aura_op_free(inl_dev->xaq_aura, 0, iova);
260 iova += inl_dev->xaq_buf_size;
262 roc_npa_aura_op_range_set(inl_dev->xaq_aura, (uint64_t)inl_dev->xaq_mem,
265 aura = roc_npa_aura_handle_to_aura(inl_dev->xaq_aura);
267 /* Setup xaq for hwgrps */
268 rc = sso_hwgrp_alloc_xaq(dev, aura, 1);
270 plt_err("Failed to setup hwgrp xaq aura, rc=%d", rc);
274 /* Register SSO, SSOW error and work irq's */
275 rc = nix_inl_sso_register_irqs(inl_dev);
277 plt_err("Failed to register sso irq's, rc=%d", rc);
281 /* Setup hwgrp->hws link */
282 sso_hws_link_modify(0, inl_dev->ssow_base, NULL, hwgrp, 1, true);
285 plt_write64(0x1, inl_dev->sso_base + SSO_LF_GGRP_QCTL);
290 sso_hwgrp_release_xaq(&inl_dev->dev, 1);
292 roc_npa_pool_destroy(inl_dev->xaq_aura);
293 inl_dev->xaq_aura = 0;
295 plt_free(inl_dev->xaq_mem);
296 inl_dev->xaq_mem = NULL;
298 sso_lf_free(dev, SSO_LF_TYPE_HWGRP, 1);
300 sso_lf_free(dev, SSO_LF_TYPE_HWS, 1);
305 nix_inl_sso_release(struct nix_inl_dev *inl_dev)
307 uint16_t hwgrp[1] = {0};
310 plt_write64(0, inl_dev->sso_base + SSO_LF_GGRP_QCTL);
312 /* Unregister SSO/SSOW IRQ's */
313 nix_inl_sso_unregister_irqs(inl_dev);
316 sso_hws_link_modify(0, inl_dev->ssow_base, NULL, hwgrp, 1, false);
318 /* Release XAQ aura */
319 sso_hwgrp_release_xaq(&inl_dev->dev, 1);
321 /* Free SSO, SSOW LF's */
322 sso_lf_free(&inl_dev->dev, SSO_LF_TYPE_HWS, 1);
323 sso_lf_free(&inl_dev->dev, SSO_LF_TYPE_HWGRP, 1);
329 nix_inl_nix_setup(struct nix_inl_dev *inl_dev)
331 uint16_t ipsec_in_max_spi = inl_dev->ipsec_in_max_spi;
332 struct dev *dev = &inl_dev->dev;
333 struct mbox *mbox = dev->mbox;
334 struct nix_lf_alloc_rsp *rsp;
335 struct nix_lf_alloc_req *req;
339 /* Alloc NIX LF needed for single RQ */
340 req = mbox_alloc_msg_nix_lf_alloc(mbox);
347 req->xqe_sz = NIX_XQESZ_W16;
348 /* RSS size does not matter as this RQ is only for UCAST_IPSEC action */
349 req->rss_sz = ROC_NIX_RSS_RETA_SZ_64;
350 req->rss_grps = ROC_NIX_RSS_GRPS;
351 req->npa_func = idev_npa_pffunc_get();
352 req->sso_func = dev->pf_func;
353 req->rx_cfg = NIX_INL_LF_RX_CFG;
354 req->flags = NIX_LF_RSS_TAG_LSB_AS_ADDER;
356 if (roc_model_is_cn10ka_a0() || roc_model_is_cnf10ka_a0() ||
357 roc_model_is_cnf10kb_a0())
358 req->rx_cfg &= ~ROC_NIX_LF_RX_CFG_DROP_RE;
360 rc = mbox_process_msg(mbox, (void *)&rsp);
362 plt_err("Failed to alloc lf, rc=%d", rc);
366 inl_dev->lf_tx_stats = rsp->lf_tx_stats;
367 inl_dev->lf_rx_stats = rsp->lf_rx_stats;
368 inl_dev->qints = rsp->qints;
369 inl_dev->cints = rsp->cints;
371 /* Register nix interrupts */
372 rc = nix_inl_nix_register_irqs(inl_dev);
374 plt_err("Failed to register nix irq's, rc=%d", rc);
378 /* CN9K SA is different */
379 if (roc_model_is_cn9k())
380 inb_sa_sz = ROC_NIX_INL_ONF_IPSEC_INB_SA_SZ;
382 inb_sa_sz = ROC_NIX_INL_OT_IPSEC_INB_SA_SZ;
384 /* Alloc contiguous memory for Inbound SA's */
385 inl_dev->inb_sa_sz = inb_sa_sz;
386 inl_dev->inb_sa_base = plt_zmalloc(inb_sa_sz * ipsec_in_max_spi,
387 ROC_NIX_INL_SA_BASE_ALIGN);
388 if (!inl_dev->inb_sa_base) {
389 plt_err("Failed to allocate memory for Inbound SA");
391 goto unregister_irqs;
394 /* Setup device specific inb SA table */
395 rc = nix_inl_nix_ipsec_cfg(inl_dev, true);
397 plt_err("Failed to setup NIX Inbound SA conf, rc=%d", rc);
403 plt_free(inl_dev->inb_sa_base);
404 inl_dev->inb_sa_base = NULL;
406 nix_inl_nix_unregister_irqs(inl_dev);
408 mbox_alloc_msg_nix_lf_free(mbox);
409 rc |= mbox_process(mbox);
414 nix_inl_nix_release(struct nix_inl_dev *inl_dev)
416 struct dev *dev = &inl_dev->dev;
417 struct mbox *mbox = dev->mbox;
418 struct nix_lf_free_req *req;
419 struct ndc_sync_op *ndc_req;
422 /* Disable Inbound processing */
423 rc = nix_inl_nix_ipsec_cfg(inl_dev, false);
425 plt_err("Failed to disable Inbound IPSec, rc=%d", rc);
427 /* Sync NDC-NIX for LF */
428 ndc_req = mbox_alloc_msg_ndc_sync_op(mbox);
431 ndc_req->nix_lf_rx_sync = 1;
432 rc = mbox_process(mbox);
434 plt_err("Error on NDC-NIX-RX LF sync, rc %d", rc);
436 /* Unregister IRQs */
437 nix_inl_nix_unregister_irqs(inl_dev);
439 /* By default all associated mcam rules are deleted */
440 req = mbox_alloc_msg_nix_lf_free(mbox);
444 return mbox_process(mbox);
448 nix_inl_lf_attach(struct nix_inl_dev *inl_dev)
450 struct msix_offset_rsp *msix_rsp;
451 struct dev *dev = &inl_dev->dev;
452 struct mbox *mbox = dev->mbox;
453 struct rsrc_attach_req *req;
454 uint64_t nix_blkaddr;
457 req = mbox_alloc_msg_attach_resources(mbox);
461 /* Attach 1 NIXLF, SSO HWS and SSO HWGRP */
465 if (inl_dev->attach_cptlf) {
467 req->cpt_blkaddr = RVU_BLOCK_ADDR_CPT0;
470 rc = mbox_process(dev->mbox);
474 /* Get MSIX vector offsets */
475 mbox_alloc_msg_msix_offset(mbox);
476 rc = mbox_process_msg(dev->mbox, (void **)&msix_rsp);
480 inl_dev->nix_msixoff = msix_rsp->nix_msixoff;
481 inl_dev->ssow_msixoff = msix_rsp->ssow_msixoff[0];
482 inl_dev->sso_msixoff = msix_rsp->sso_msixoff[0];
483 inl_dev->cpt_msixoff = msix_rsp->cptlf_msixoff[0];
485 nix_blkaddr = nix_get_blkaddr(dev);
486 inl_dev->is_nix1 = (nix_blkaddr == RVU_BLOCK_ADDR_NIX1);
488 /* Update base addresses for LF's */
489 inl_dev->nix_base = dev->bar2 + (nix_blkaddr << 20);
490 inl_dev->ssow_base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20);
491 inl_dev->sso_base = dev->bar2 + (RVU_BLOCK_ADDR_SSO << 20);
492 inl_dev->cpt_base = dev->bar2 + (RVU_BLOCK_ADDR_CPT0 << 20);
498 nix_inl_lf_detach(struct nix_inl_dev *inl_dev)
500 struct dev *dev = &inl_dev->dev;
501 struct mbox *mbox = dev->mbox;
502 struct rsrc_detach_req *req;
505 req = mbox_alloc_msg_detach_resources(mbox);
512 req->cptlfs = !!inl_dev->attach_cptlf;
514 return mbox_process(dev->mbox);
518 roc_nix_inl_dev_init(struct roc_nix_inl_dev *roc_inl_dev)
520 struct plt_pci_device *pci_dev;
521 struct nix_inl_dev *inl_dev;
522 struct idev_cfg *idev;
525 pci_dev = roc_inl_dev->pci_dev;
527 /* Skip probe if already done */
528 idev = idev_get_cfg();
532 if (idev->nix_inl_dev) {
533 plt_info("Skipping device %s, inline device already probed",
538 PLT_STATIC_ASSERT(sizeof(struct nix_inl_dev) <= ROC_NIX_INL_MEM_SZ);
540 inl_dev = (struct nix_inl_dev *)roc_inl_dev->reserved;
541 memset(inl_dev, 0, sizeof(*inl_dev));
543 inl_dev->pci_dev = pci_dev;
544 inl_dev->ipsec_in_max_spi = roc_inl_dev->ipsec_in_max_spi;
545 inl_dev->selftest = roc_inl_dev->selftest;
546 inl_dev->is_multi_channel = roc_inl_dev->is_multi_channel;
547 inl_dev->channel = roc_inl_dev->channel;
548 inl_dev->chan_mask = roc_inl_dev->chan_mask;
549 inl_dev->attach_cptlf = roc_inl_dev->attach_cptlf;
551 /* Initialize base device */
552 rc = dev_init(&inl_dev->dev, pci_dev);
554 plt_err("Failed to init roc device");
558 /* Attach LF resources */
559 rc = nix_inl_lf_attach(inl_dev);
561 plt_err("Failed to attach LF resources, rc=%d", rc);
566 rc = nix_inl_nix_setup(inl_dev);
571 rc = nix_inl_sso_setup(inl_dev);
576 rc = nix_inl_cpt_setup(inl_dev);
580 /* Perform selftest if asked for */
581 if (inl_dev->selftest) {
582 rc = nix_inl_selftest();
587 idev->nix_inl_dev = inl_dev;
591 rc |= nix_inl_cpt_release(inl_dev);
593 rc |= nix_inl_sso_release(inl_dev);
595 rc |= nix_inl_nix_release(inl_dev);
597 rc |= nix_inl_lf_detach(inl_dev);
599 rc |= dev_fini(&inl_dev->dev, pci_dev);
605 roc_nix_inl_dev_fini(struct roc_nix_inl_dev *roc_inl_dev)
607 struct plt_pci_device *pci_dev;
608 struct nix_inl_dev *inl_dev;
609 struct idev_cfg *idev;
612 idev = idev_get_cfg();
616 if (!idev->nix_inl_dev ||
617 PLT_PTR_DIFF(roc_inl_dev->reserved, idev->nix_inl_dev))
620 inl_dev = idev->nix_inl_dev;
621 pci_dev = inl_dev->pci_dev;
624 rc = nix_inl_sso_release(inl_dev);
627 rc |= nix_inl_nix_release(inl_dev);
630 rc |= nix_inl_lf_detach(inl_dev);
633 rc |= dev_fini(&inl_dev->dev, pci_dev);
637 idev->nix_inl_dev = NULL;