1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
8 #define WORK_LIMIT 1000
11 nix_inl_sso_work_cb(struct nix_inl_dev *inl_dev)
13 uintptr_t getwrk_op = inl_dev->ssow_base + SSOW_LF_GWS_OP_GET_WORK0;
14 uintptr_t tag_wqe_op = inl_dev->ssow_base + SSOW_LF_GWS_WQE0;
15 uint32_t wdata = BIT(16) | 1;
24 /* Try to do get work */
26 plt_write64(gw.u64[0], getwrk_op);
28 roc_load_pair(gw.u64[0], gw.u64[1], tag_wqe_op);
29 } while (gw.u64[0] & BIT_ULL(63));
32 /* Do we have any work? */
35 inl_dev->work_cb(gw.u64, inl_dev->cb_args, false);
37 plt_warn("Undelivered inl dev work gw0: %p gw1: %p",
38 (void *)gw.u64[0], (void *)gw.u64[1]);
44 plt_atomic_thread_fence(__ATOMIC_ACQ_REL);
48 nix_inl_nix_reg_dump(struct nix_inl_dev *inl_dev)
50 uintptr_t nix_base = inl_dev->nix_base;
52 /* General registers */
53 nix_lf_gen_reg_dump(nix_base, NULL);
55 /* Rx, Tx stat registers */
56 nix_lf_stat_reg_dump(nix_base, NULL, inl_dev->lf_tx_stats,
57 inl_dev->lf_rx_stats);
60 nix_lf_int_reg_dump(nix_base, NULL, inl_dev->qints, inl_dev->cints);
66 nix_inl_sso_hwgrp_irq(void *param)
68 struct nix_inl_dev *inl_dev = (struct nix_inl_dev *)param;
69 uintptr_t sso_base = inl_dev->sso_base;
72 intr = plt_read64(sso_base + SSO_LF_GGRP_INT);
76 /* Check for work executable interrupt */
78 nix_inl_sso_work_cb(inl_dev);
81 plt_err("GGRP 0 GGRP_INT=0x%" PRIx64 "", intr);
84 plt_write64(intr, sso_base + SSO_LF_GGRP_INT);
88 nix_inl_sso_hws_irq(void *param)
90 struct nix_inl_dev *inl_dev = (struct nix_inl_dev *)param;
91 uintptr_t ssow_base = inl_dev->ssow_base;
94 intr = plt_read64(ssow_base + SSOW_LF_GWS_INT);
98 plt_err("GWS 0 GWS_INT=0x%" PRIx64 "", intr);
100 /* Clear interrupt */
101 plt_write64(intr, ssow_base + SSOW_LF_GWS_INT);
105 nix_inl_sso_register_irqs(struct nix_inl_dev *inl_dev)
107 struct plt_intr_handle *handle = inl_dev->pci_dev->intr_handle;
108 uintptr_t ssow_base = inl_dev->ssow_base;
109 uintptr_t sso_base = inl_dev->sso_base;
110 uint16_t sso_msixoff, ssow_msixoff;
113 ssow_msixoff = inl_dev->ssow_msixoff;
114 sso_msixoff = inl_dev->sso_msixoff;
115 if (sso_msixoff == MSIX_VECTOR_INVALID ||
116 ssow_msixoff == MSIX_VECTOR_INVALID) {
117 plt_err("Invalid SSO/SSOW MSIX offsets (0x%x, 0x%x)",
118 sso_msixoff, ssow_msixoff);
123 * Setup SSOW interrupt
126 /* Clear SSOW interrupt enable */
127 plt_write64(~0ull, ssow_base + SSOW_LF_GWS_INT_ENA_W1C);
128 /* Register interrupt with vfio */
129 rc = dev_irq_register(handle, nix_inl_sso_hws_irq, inl_dev,
130 ssow_msixoff + SSOW_LF_INT_VEC_IOP);
131 /* Set SSOW interrupt enable */
132 plt_write64(~0ull, ssow_base + SSOW_LF_GWS_INT_ENA_W1S);
135 * Setup SSO/HWGRP interrupt
138 /* Clear SSO interrupt enable */
139 plt_write64(~0ull, sso_base + SSO_LF_GGRP_INT_ENA_W1C);
141 rc |= dev_irq_register(handle, nix_inl_sso_hwgrp_irq, (void *)inl_dev,
142 sso_msixoff + SSO_LF_INT_VEC_GRP);
143 /* Enable hw interrupt */
144 plt_write64(~0ull, sso_base + SSO_LF_GGRP_INT_ENA_W1S);
146 /* Setup threshold for work exec interrupt to 100us timeout
147 * based on time counter.
149 plt_write64(BIT_ULL(63) | 10ULL << 48, sso_base + SSO_LF_GGRP_INT_THR);
155 nix_inl_sso_unregister_irqs(struct nix_inl_dev *inl_dev)
157 struct plt_intr_handle *handle = inl_dev->pci_dev->intr_handle;
158 uintptr_t ssow_base = inl_dev->ssow_base;
159 uintptr_t sso_base = inl_dev->sso_base;
160 uint16_t sso_msixoff, ssow_msixoff;
162 ssow_msixoff = inl_dev->ssow_msixoff;
163 sso_msixoff = inl_dev->sso_msixoff;
165 /* Clear SSOW interrupt enable */
166 plt_write64(~0ull, ssow_base + SSOW_LF_GWS_INT_ENA_W1C);
167 /* Clear SSO/HWGRP interrupt enable */
168 plt_write64(~0ull, sso_base + SSO_LF_GGRP_INT_ENA_W1C);
169 /* Clear SSO threshold */
170 plt_write64(0, sso_base + SSO_LF_GGRP_INT_THR);
173 dev_irq_unregister(handle, nix_inl_sso_hws_irq, (void *)inl_dev,
174 ssow_msixoff + SSOW_LF_INT_VEC_IOP);
175 dev_irq_unregister(handle, nix_inl_sso_hwgrp_irq, (void *)inl_dev,
176 sso_msixoff + SSO_LF_INT_VEC_GRP);
180 nix_inl_nix_q_irq(void *param)
182 struct nix_inl_dev *inl_dev = (struct nix_inl_dev *)param;
183 uintptr_t nix_base = inl_dev->nix_base;
184 struct dev *dev = &inl_dev->dev;
190 intr = plt_read64(nix_base + NIX_LF_QINTX_INT(0));
194 plt_err("Queue_intr=0x%" PRIx64 " qintx 0 pf=%d, vf=%d", intr, dev->pf,
197 /* Get and clear RQ0 interrupt */
198 reg = roc_atomic64_add_nosync(0,
199 (int64_t *)(nix_base + NIX_LF_RQ_OP_INT));
200 if (reg & BIT_ULL(42) /* OP_ERR */) {
201 plt_err("Failed to get rq_int");
205 plt_write64(0 | irq, nix_base + NIX_LF_RQ_OP_INT);
207 if (irq & BIT_ULL(NIX_RQINT_DROP))
208 plt_err("RQ=0 NIX_RQINT_DROP");
210 if (irq & BIT_ULL(NIX_RQINT_RED))
211 plt_err("RQ=0 NIX_RQINT_RED");
213 /* Clear interrupt */
214 plt_write64(intr, nix_base + NIX_LF_QINTX_INT(0));
216 /* Dump registers to std out */
217 nix_inl_nix_reg_dump(inl_dev);
220 rc = nix_q_ctx_get(dev, NIX_AQ_CTYPE_RQ, 0, &ctx);
222 plt_err("Failed to get rq context");
229 nix_inl_nix_ras_irq(void *param)
231 struct nix_inl_dev *inl_dev = (struct nix_inl_dev *)param;
232 uintptr_t nix_base = inl_dev->nix_base;
233 struct dev *dev = &inl_dev->dev;
238 intr = plt_read64(nix_base + NIX_LF_RAS);
242 plt_err("Ras_intr=0x%" PRIx64 " pf=%d, vf=%d", intr, dev->pf, dev->vf);
243 /* Clear interrupt */
244 plt_write64(intr, nix_base + NIX_LF_RAS);
246 /* Dump registers to std out */
247 nix_inl_nix_reg_dump(inl_dev);
250 rc = nix_q_ctx_get(dev, NIX_AQ_CTYPE_RQ, 0, &ctx);
252 plt_err("Failed to get rq context");
259 nix_inl_nix_err_irq(void *param)
261 struct nix_inl_dev *inl_dev = (struct nix_inl_dev *)param;
262 uintptr_t nix_base = inl_dev->nix_base;
263 struct dev *dev = &inl_dev->dev;
268 intr = plt_read64(nix_base + NIX_LF_ERR_INT);
272 plt_err("Err_irq=0x%" PRIx64 " pf=%d, vf=%d", intr, dev->pf, dev->vf);
274 /* Clear interrupt */
275 plt_write64(intr, nix_base + NIX_LF_ERR_INT);
277 /* Dump registers to std out */
278 nix_inl_nix_reg_dump(inl_dev);
281 rc = nix_q_ctx_get(dev, NIX_AQ_CTYPE_RQ, 0, &ctx);
283 plt_err("Failed to get rq context");
290 nix_inl_nix_register_irqs(struct nix_inl_dev *inl_dev)
292 struct plt_intr_handle *handle = inl_dev->pci_dev->intr_handle;
293 uintptr_t nix_base = inl_dev->nix_base;
297 msixoff = inl_dev->nix_msixoff;
298 if (msixoff == MSIX_VECTOR_INVALID) {
299 plt_err("Invalid NIXLF MSIX vector offset: 0x%x", msixoff);
303 /* Disable err interrupts */
304 plt_write64(~0ull, nix_base + NIX_LF_ERR_INT_ENA_W1C);
305 /* DIsable RAS interrupts */
306 plt_write64(~0ull, nix_base + NIX_LF_RAS_ENA_W1C);
308 /* Register err irq */
309 rc = dev_irq_register(handle, nix_inl_nix_err_irq, inl_dev,
310 msixoff + NIX_LF_INT_VEC_ERR_INT);
311 rc |= dev_irq_register(handle, nix_inl_nix_ras_irq, inl_dev,
312 msixoff + NIX_LF_INT_VEC_POISON);
314 /* Enable all nix lf error irqs except RQ_DISABLED and CQ_DISABLED */
315 plt_write64(~(BIT_ULL(11) | BIT_ULL(24)),
316 nix_base + NIX_LF_ERR_INT_ENA_W1S);
317 /* Enable RAS interrupts */
318 plt_write64(~0ull, nix_base + NIX_LF_RAS_ENA_W1S);
320 /* Setup queue irq for RQ 0 */
322 /* Clear QINT CNT, interrupt */
323 plt_write64(0, nix_base + NIX_LF_QINTX_CNT(0));
324 plt_write64(~0ull, nix_base + NIX_LF_QINTX_ENA_W1C(0));
326 /* Register queue irq vector */
327 rc |= dev_irq_register(handle, nix_inl_nix_q_irq, inl_dev,
328 msixoff + NIX_LF_INT_VEC_QINT_START);
330 plt_write64(0, nix_base + NIX_LF_QINTX_CNT(0));
331 plt_write64(0, nix_base + NIX_LF_QINTX_INT(0));
332 /* Enable QINT interrupt */
333 plt_write64(~0ull, nix_base + NIX_LF_QINTX_ENA_W1S(0));
339 nix_inl_nix_unregister_irqs(struct nix_inl_dev *inl_dev)
341 struct plt_intr_handle *handle = inl_dev->pci_dev->intr_handle;
342 uintptr_t nix_base = inl_dev->nix_base;
345 msixoff = inl_dev->nix_msixoff;
346 /* Disable err interrupts */
347 plt_write64(~0ull, nix_base + NIX_LF_ERR_INT_ENA_W1C);
348 /* DIsable RAS interrupts */
349 plt_write64(~0ull, nix_base + NIX_LF_RAS_ENA_W1C);
351 dev_irq_unregister(handle, nix_inl_nix_err_irq, inl_dev,
352 msixoff + NIX_LF_INT_VEC_ERR_INT);
353 dev_irq_unregister(handle, nix_inl_nix_ras_irq, inl_dev,
354 msixoff + NIX_LF_INT_VEC_POISON);
357 plt_write64(0, nix_base + NIX_LF_QINTX_CNT(0));
358 plt_write64(0, nix_base + NIX_LF_QINTX_INT(0));
360 /* Disable QINT interrupt */
361 plt_write64(~0ull, nix_base + NIX_LF_QINTX_ENA_W1C(0));
363 /* Unregister queue irq vector */
364 dev_irq_unregister(handle, nix_inl_nix_q_irq, inl_dev,
365 msixoff + NIX_LF_INT_VEC_QINT_START);