1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
4 #ifndef _ROC_NIX_INL_PRIV_H_
5 #define _ROC_NIX_INL_PRIV_H_
8 /* Base device object */
12 struct plt_pci_device *pci_dev;
14 /* LF specific BAR2 regions */
20 /* MSIX vector offsets */
22 uint16_t ssow_msixoff;
27 uint32_t xaq_buf_size;
31 struct roc_sso_xaq_data xaq;
32 roc_nix_inl_sso_work_cb_t work_cb;
35 uint16_t pkt_pools_cnt;
40 uint16_t vwqe_interval;
54 struct roc_cpt_lf cpt_lf;
56 /* Device arguments */
60 bool is_multi_channel;
61 uint32_t ipsec_in_min_spi;
62 uint32_t ipsec_in_max_spi;
63 uint32_t inb_spi_mask;
68 int nix_inl_sso_register_irqs(struct nix_inl_dev *inl_dev);
69 void nix_inl_sso_unregister_irqs(struct nix_inl_dev *inl_dev);
71 int nix_inl_nix_register_irqs(struct nix_inl_dev *inl_dev);
72 void nix_inl_nix_unregister_irqs(struct nix_inl_dev *inl_dev);
74 uint16_t nix_inl_dev_pffunc_get(void);
76 #endif /* _ROC_NIX_INL_PRIV_H_ */