1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
9 nix_err_intr_enb_dis(struct nix *nix, bool enb)
11 /* Enable all nix lf error irqs except RQ_DISABLED and CQ_DISABLED */
13 plt_write64(~(BIT_ULL(11) | BIT_ULL(24)),
14 nix->base + NIX_LF_ERR_INT_ENA_W1S);
16 plt_write64(~0ull, nix->base + NIX_LF_ERR_INT_ENA_W1C);
20 nix_ras_intr_enb_dis(struct nix *nix, bool enb)
23 plt_write64(~0ull, nix->base + NIX_LF_RAS_ENA_W1S);
25 plt_write64(~0ull, nix->base + NIX_LF_RAS_ENA_W1C);
29 roc_nix_rx_queue_intr_enable(struct roc_nix *roc_nix, uint16_t rx_queue_id)
31 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
33 /* Enable CINT interrupt */
34 plt_write64(BIT_ULL(0), nix->base + NIX_LF_CINTX_ENA_W1S(rx_queue_id));
38 roc_nix_rx_queue_intr_disable(struct roc_nix *roc_nix, uint16_t rx_queue_id)
40 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
42 /* Clear and disable CINT interrupt */
43 plt_write64(BIT_ULL(0), nix->base + NIX_LF_CINTX_ENA_W1C(rx_queue_id));
47 roc_nix_err_intr_ena_dis(struct roc_nix *roc_nix, bool enb)
49 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
51 return nix_err_intr_enb_dis(nix, enb);
55 roc_nix_ras_intr_ena_dis(struct roc_nix *roc_nix, bool enb)
57 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
59 return nix_ras_intr_enb_dis(nix, enb);
63 nix_lf_err_irq(void *param)
65 struct nix *nix = (struct nix *)param;
66 struct dev *dev = &nix->dev;
69 intr = plt_read64(nix->base + NIX_LF_ERR_INT);
73 plt_err("Err_irq=0x%" PRIx64 " pf=%d, vf=%d", intr, dev->pf, dev->vf);
76 plt_write64(intr, nix->base + NIX_LF_ERR_INT);
77 /* Dump registers to std out */
78 roc_nix_lf_reg_dump(nix_priv_to_roc_nix(nix), NULL);
79 roc_nix_queues_ctx_dump(nix_priv_to_roc_nix(nix));
83 nix_lf_register_err_irq(struct nix *nix)
85 struct plt_intr_handle *handle = nix->pci_dev->intr_handle;
88 vec = nix->msixoff + NIX_LF_INT_VEC_ERR_INT;
89 /* Clear err interrupt */
90 nix_err_intr_enb_dis(nix, false);
91 /* Set used interrupt vectors */
92 rc = dev_irq_register(handle, nix_lf_err_irq, nix, vec);
93 /* Enable all dev interrupt except for RQ_DISABLED */
94 nix_err_intr_enb_dis(nix, true);
100 nix_lf_unregister_err_irq(struct nix *nix)
102 struct plt_intr_handle *handle = nix->pci_dev->intr_handle;
105 vec = nix->msixoff + NIX_LF_INT_VEC_ERR_INT;
106 /* Clear err interrupt */
107 nix_err_intr_enb_dis(nix, false);
108 dev_irq_unregister(handle, nix_lf_err_irq, nix, vec);
112 nix_lf_ras_irq(void *param)
114 struct nix *nix = (struct nix *)param;
115 struct dev *dev = &nix->dev;
118 intr = plt_read64(nix->base + NIX_LF_RAS);
122 plt_err("Ras_intr=0x%" PRIx64 " pf=%d, vf=%d", intr, dev->pf, dev->vf);
123 /* Clear interrupt */
124 plt_write64(intr, nix->base + NIX_LF_RAS);
126 /* Dump registers to std out */
127 roc_nix_lf_reg_dump(nix_priv_to_roc_nix(nix), NULL);
128 roc_nix_queues_ctx_dump(nix_priv_to_roc_nix(nix));
132 nix_lf_register_ras_irq(struct nix *nix)
134 struct plt_intr_handle *handle = nix->pci_dev->intr_handle;
137 vec = nix->msixoff + NIX_LF_INT_VEC_POISON;
138 /* Clear err interrupt */
139 nix_ras_intr_enb_dis(nix, false);
140 /* Set used interrupt vectors */
141 rc = dev_irq_register(handle, nix_lf_ras_irq, nix, vec);
142 /* Enable dev interrupt */
143 nix_ras_intr_enb_dis(nix, true);
149 nix_lf_unregister_ras_irq(struct nix *nix)
151 struct plt_intr_handle *handle = nix->pci_dev->intr_handle;
154 vec = nix->msixoff + NIX_LF_INT_VEC_POISON;
155 /* Clear err interrupt */
156 nix_ras_intr_enb_dis(nix, false);
157 dev_irq_unregister(handle, nix_lf_ras_irq, nix, vec);
160 static inline uint8_t
161 nix_lf_q_irq_get_and_clear(struct nix *nix, uint16_t q, uint32_t off,
167 wdata = (uint64_t)q << 44;
168 reg = roc_atomic64_add_nosync(wdata, (int64_t *)(nix->base + off));
170 if (reg & BIT_ULL(42) /* OP_ERR */) {
171 plt_err("Failed execute irq get off=0x%x", off);
176 plt_write64(wdata | qint, nix->base + off);
181 static inline uint8_t
182 nix_lf_rq_irq_get_and_clear(struct nix *nix, uint16_t rq)
184 return nix_lf_q_irq_get_and_clear(nix, rq, NIX_LF_RQ_OP_INT, ~0xff00);
187 static inline uint8_t
188 nix_lf_cq_irq_get_and_clear(struct nix *nix, uint16_t cq)
190 return nix_lf_q_irq_get_and_clear(nix, cq, NIX_LF_CQ_OP_INT, ~0xff00);
193 static inline uint8_t
194 nix_lf_sq_irq_get_and_clear(struct nix *nix, uint16_t sq)
196 return nix_lf_q_irq_get_and_clear(nix, sq, NIX_LF_SQ_OP_INT, ~0x1ff00);
200 nix_lf_sq_debug_reg(struct nix *nix, uint32_t off)
204 reg = plt_read64(nix->base + off);
205 if (reg & BIT_ULL(44))
206 plt_err("SQ=%d err_code=0x%x", (int)((reg >> 8) & 0xfffff),
207 (uint8_t)(reg & 0xff));
211 nix_lf_cq_irq(void *param)
213 struct nix_qint *cint = (struct nix_qint *)param;
214 struct nix *nix = cint->nix;
216 /* Clear interrupt */
217 plt_write64(BIT_ULL(0), nix->base + NIX_LF_CINTX_INT(cint->qintx));
221 nix_lf_q_irq(void *param)
223 struct nix_qint *qint = (struct nix_qint *)param;
224 uint8_t irq, qintx = qint->qintx;
225 struct nix *nix = qint->nix;
226 struct dev *dev = &nix->dev;
230 intr = plt_read64(nix->base + NIX_LF_QINTX_INT(qintx));
234 plt_err("Queue_intr=0x%" PRIx64 " qintx=%d pf=%d, vf=%d", intr, qintx,
237 /* Handle RQ interrupts */
238 for (q = 0; q < nix->nb_rx_queues; q++) {
240 irq = nix_lf_rq_irq_get_and_clear(nix, rq);
242 if (irq & BIT_ULL(NIX_RQINT_DROP))
243 plt_err("RQ=%d NIX_RQINT_DROP", rq);
245 if (irq & BIT_ULL(NIX_RQINT_RED))
246 plt_err("RQ=%d NIX_RQINT_RED", rq);
249 /* Handle CQ interrupts */
250 for (q = 0; q < nix->nb_rx_queues; q++) {
252 irq = nix_lf_cq_irq_get_and_clear(nix, cq);
254 if (irq & BIT_ULL(NIX_CQERRINT_DOOR_ERR))
255 plt_err("CQ=%d NIX_CQERRINT_DOOR_ERR", cq);
257 if (irq & BIT_ULL(NIX_CQERRINT_WR_FULL))
258 plt_err("CQ=%d NIX_CQERRINT_WR_FULL", cq);
260 if (irq & BIT_ULL(NIX_CQERRINT_CQE_FAULT))
261 plt_err("CQ=%d NIX_CQERRINT_CQE_FAULT", cq);
264 /* Handle SQ interrupts */
265 for (q = 0; q < nix->nb_tx_queues; q++) {
267 irq = nix_lf_sq_irq_get_and_clear(nix, sq);
269 if (irq & BIT_ULL(NIX_SQINT_LMT_ERR)) {
270 plt_err("SQ=%d NIX_SQINT_LMT_ERR", sq);
271 nix_lf_sq_debug_reg(nix, NIX_LF_SQ_OP_ERR_DBG);
273 if (irq & BIT_ULL(NIX_SQINT_MNQ_ERR)) {
274 plt_err("SQ=%d NIX_SQINT_MNQ_ERR", sq);
275 nix_lf_sq_debug_reg(nix, NIX_LF_MNQ_ERR_DBG);
277 if (irq & BIT_ULL(NIX_SQINT_SEND_ERR)) {
278 plt_err("SQ=%d NIX_SQINT_SEND_ERR", sq);
279 nix_lf_sq_debug_reg(nix, NIX_LF_SEND_ERR_DBG);
281 if (irq & BIT_ULL(NIX_SQINT_SQB_ALLOC_FAIL)) {
282 plt_err("SQ=%d NIX_SQINT_SQB_ALLOC_FAIL", sq);
283 nix_lf_sq_debug_reg(nix, NIX_LF_SEND_ERR_DBG);
287 /* Clear interrupt */
288 plt_write64(intr, nix->base + NIX_LF_QINTX_INT(qintx));
290 /* Dump registers to std out */
291 roc_nix_lf_reg_dump(nix_priv_to_roc_nix(nix), NULL);
292 roc_nix_queues_ctx_dump(nix_priv_to_roc_nix(nix));
296 roc_nix_register_queue_irqs(struct roc_nix *roc_nix)
298 int vec, q, sqs, rqs, qs, rc = 0;
299 struct plt_intr_handle *handle;
302 nix = roc_nix_to_nix_priv(roc_nix);
303 handle = nix->pci_dev->intr_handle;
305 /* Figure out max qintx required */
306 rqs = PLT_MIN(nix->qints, nix->nb_rx_queues);
307 sqs = PLT_MIN(nix->qints, nix->nb_tx_queues);
308 qs = PLT_MAX(rqs, sqs);
310 nix->configured_qints = qs;
313 plt_zmalloc(nix->configured_qints * sizeof(struct nix_qint), 0);
314 if (nix->qints_mem == NULL)
317 for (q = 0; q < qs; q++) {
318 vec = nix->msixoff + NIX_LF_INT_VEC_QINT_START + q;
321 plt_write64(0, nix->base + NIX_LF_QINTX_CNT(q));
323 /* Clear interrupt */
324 plt_write64(~0ull, nix->base + NIX_LF_QINTX_ENA_W1C(q));
326 nix->qints_mem[q].nix = nix;
327 nix->qints_mem[q].qintx = q;
329 /* Sync qints_mem update */
332 /* Register queue irq vector */
333 rc = dev_irq_register(handle, nix_lf_q_irq, &nix->qints_mem[q],
338 plt_write64(0, nix->base + NIX_LF_QINTX_CNT(q));
339 plt_write64(0, nix->base + NIX_LF_QINTX_INT(q));
340 /* Enable QINT interrupt */
341 plt_write64(~0ull, nix->base + NIX_LF_QINTX_ENA_W1S(q));
348 roc_nix_unregister_queue_irqs(struct roc_nix *roc_nix)
350 struct plt_intr_handle *handle;
354 nix = roc_nix_to_nix_priv(roc_nix);
355 handle = nix->pci_dev->intr_handle;
357 for (q = 0; q < nix->configured_qints; q++) {
358 vec = nix->msixoff + NIX_LF_INT_VEC_QINT_START + q;
361 plt_write64(0, nix->base + NIX_LF_QINTX_CNT(q));
362 plt_write64(0, nix->base + NIX_LF_QINTX_INT(q));
364 /* Clear interrupt */
365 plt_write64(~0ull, nix->base + NIX_LF_QINTX_ENA_W1C(q));
367 /* Unregister queue irq vector */
368 dev_irq_unregister(handle, nix_lf_q_irq, &nix->qints_mem[q],
371 nix->configured_qints = 0;
373 plt_free(nix->qints_mem);
374 nix->qints_mem = NULL;
378 roc_nix_register_cq_irqs(struct roc_nix *roc_nix)
380 struct plt_intr_handle *handle;
381 uint8_t rc = 0, vec, q;
384 nix = roc_nix_to_nix_priv(roc_nix);
385 handle = nix->pci_dev->intr_handle;
387 nix->configured_cints = PLT_MIN(nix->cints, nix->nb_rx_queues);
390 plt_zmalloc(nix->configured_cints * sizeof(struct nix_qint), 0);
391 if (nix->cints_mem == NULL)
394 for (q = 0; q < nix->configured_cints; q++) {
395 vec = nix->msixoff + NIX_LF_INT_VEC_CINT_START + q;
398 plt_write64(0, nix->base + NIX_LF_CINTX_CNT(q));
400 /* Clear interrupt */
401 plt_write64(BIT_ULL(0), nix->base + NIX_LF_CINTX_ENA_W1C(q));
403 nix->cints_mem[q].nix = nix;
404 nix->cints_mem[q].qintx = q;
406 /* Sync cints_mem update */
409 /* Register queue irq vector */
410 rc = dev_irq_register(handle, nix_lf_cq_irq, &nix->cints_mem[q],
413 plt_err("Fail to register CQ irq, rc=%d", rc);
417 rc = plt_intr_vec_list_alloc(handle, "cnxk",
418 nix->configured_cints);
420 plt_err("Fail to allocate intr vec list, rc=%d",
424 /* VFIO vector zero is resereved for misc interrupt so
425 * doing required adjustment. (b13bfab4cd)
427 if (plt_intr_vec_list_index_set(handle, q,
428 PLT_INTR_VEC_RXTX_OFFSET + vec))
431 /* Configure CQE interrupt coalescing parameters */
432 plt_write64(((CQ_CQE_THRESH_DEFAULT) |
433 (CQ_CQE_THRESH_DEFAULT << 32) |
434 (CQ_TIMER_THRESH_DEFAULT << 48)),
435 nix->base + NIX_LF_CINTX_WAIT((q)));
437 /* Keeping the CQ interrupt disabled as the rx interrupt
438 * feature needs to be enabled/disabled on demand.
446 roc_nix_unregister_cq_irqs(struct roc_nix *roc_nix)
448 struct plt_intr_handle *handle;
452 nix = roc_nix_to_nix_priv(roc_nix);
453 handle = nix->pci_dev->intr_handle;
455 for (q = 0; q < nix->configured_cints; q++) {
456 vec = nix->msixoff + NIX_LF_INT_VEC_CINT_START + q;
459 plt_write64(0, nix->base + NIX_LF_CINTX_CNT(q));
461 /* Clear interrupt */
462 plt_write64(BIT_ULL(0), nix->base + NIX_LF_CINTX_ENA_W1C(q));
464 /* Unregister queue irq vector */
465 dev_irq_unregister(handle, nix_lf_cq_irq, &nix->cints_mem[q],
469 plt_intr_vec_list_free(handle);
470 plt_free(nix->cints_mem);
474 nix_register_irqs(struct nix *nix)
478 if (nix->msixoff == MSIX_VECTOR_INVALID) {
479 plt_err("Invalid NIXLF MSIX vector offset vector: 0x%x",
481 return NIX_ERR_PARAM;
484 /* Register lf err interrupt */
485 rc = nix_lf_register_err_irq(nix);
486 /* Register RAS interrupt */
487 rc |= nix_lf_register_ras_irq(nix);
493 nix_unregister_irqs(struct nix *nix)
495 nix_lf_unregister_err_irq(nix);
496 nix_lf_unregister_ras_irq(nix);