1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
5 #ifndef _ROC_NIX_PRIV_H_
6 #define _ROC_NIX_PRIV_H_
9 #define NIX_CQ_ENTRY_SZ 128
10 #define NIX_CQ_ENTRY64_SZ 512
11 #define NIX_CQ_ALIGN ((uint16_t)512)
12 #define NIX_MAX_SQB ((uint16_t)512)
13 #define NIX_DEF_SQB ((uint16_t)16)
14 #define NIX_MIN_SQB ((uint16_t)8)
15 #define NIX_SQB_LIST_SPACE ((uint16_t)2)
16 #define NIX_SQB_LOWER_THRESH ((uint16_t)70)
18 /* Apply BP/DROP when CQ is 95% full */
19 #define NIX_CQ_THRESH_LEVEL (5 * 256 / 100)
20 #define NIX_CQ_FULL_ERRATA_SKID (1024ull * 256)
21 #define NIX_RQ_AURA_THRESH(x) (((x)*95) / 100)
23 /* IRQ triggered when NIX_LF_CINTX_CNT[QCOUNT] crosses this value */
24 #define CQ_CQE_THRESH_DEFAULT 0x1ULL
25 #define CQ_TIMER_THRESH_DEFAULT 0xAULL /* ~1usec i.e (0xA * 100nsec) */
26 #define CQ_TIMER_THRESH_MAX 255
34 #define NIX_TM_MAX_HW_TXSCHQ 512
35 #define NIX_TM_HW_ID_INVALID UINT32_MAX
38 #define NIX_TM_HIERARCHY_ENA BIT_ULL(0)
39 #define NIX_TM_TL1_NO_SP BIT_ULL(1)
40 #define NIX_TM_TL1_ACCESS BIT_ULL(2)
43 /** Token bucket rate (bytes per second) */
46 /** Token bucket size (bytes), a.k.a. max burst size */
51 TAILQ_ENTRY(nix_tm_node) node;
54 enum roc_nix_tm_tree tree;
60 uint32_t shaper_profile_id;
61 void (*free_fn)(void *node);
69 uint32_t parent_hw_id;
71 #define NIX_TM_NODE_HWRES BIT_ULL(0)
72 #define NIX_TM_NODE_ENABLED BIT_ULL(1)
73 /* Shaper algorithm for RED state @NIX_REDALG_E */
74 uint32_t red_algo : 2;
75 uint32_t pkt_mode : 1;
76 uint32_t pkt_mode_set : 1;
80 struct nix_tm_node *parent;
82 /* Non-leaf node sp count */
83 uint32_t n_sp_priorities;
90 struct nix_tm_shaper_profile {
91 TAILQ_ENTRY(nix_tm_shaper_profile) shaper;
92 struct nix_tm_tb commit;
93 struct nix_tm_tb peak;
98 void (*free_fn)(void *profile);
103 TAILQ_HEAD(nix_tm_node_list, nix_tm_node);
104 TAILQ_HEAD(nix_tm_shaper_profile_list, nix_tm_shaper_profile);
107 uint16_t reta[ROC_NIX_RSS_GRPS][ROC_NIX_RSS_RETA_MAX];
108 enum roc_nix_rss_reta_sz reta_sz;
109 struct plt_pci_device *pci_dev;
110 uint16_t bpid[NIX_MAX_CHAN];
111 struct nix_qint *qints_mem;
112 struct nix_qint *cints_mem;
113 uint8_t configured_qints;
114 uint8_t configured_cints;
115 struct roc_nix_sq **sqs;
116 uint16_t vwqe_interval;
117 uint16_t tx_chan_base;
118 uint16_t rx_chan_base;
119 uint16_t nb_rx_queues;
120 uint16_t nb_tx_queues;
121 uint8_t lso_tsov6_idx;
122 uint8_t lso_tsov4_idx;
123 uint8_t lso_udp_tun_idx[ROC_NIX_LSO_TUN_MAX];
124 uint8_t lso_tun_idx[ROC_NIX_LSO_TUN_MAX];
136 /* Without FCS, with L2 overhead */
152 /* Traffic manager info */
154 /* Contiguous resources per lvl */
155 struct plt_bitmap *schq_contig_bmp[NIX_TXSCH_LVL_CNT];
156 /* Dis-contiguous resources per lvl */
157 struct plt_bitmap *schq_bmp[NIX_TXSCH_LVL_CNT];
160 struct nix_tm_shaper_profile_list shaper_profile_list;
161 struct nix_tm_node_list trees[ROC_NIX_TM_TREE_MAX];
162 enum roc_nix_tm_tree tm_tree;
163 uint64_t tm_rate_min;
164 uint16_t tm_root_lvl;
166 uint16_t tm_link_cfg_lvl;
167 uint16_t contig_rsvd[NIX_TXSCH_LVL_CNT];
168 uint16_t discontig_rsvd[NIX_TXSCH_LVL_CNT];
171 uint16_t cpt_msixoff[MAX_RVU_BLKLF_CNT];
178 uint16_t outb_err_sso_pffunc;
179 struct roc_cpt_lf *cpt_lf_base;
181 /* Mode provided by driver */
184 } __plt_cache_aligned;
186 enum nix_err_status {
187 NIX_ERR_PARAM = -2048,
189 NIX_ERR_INVALID_RANGE,
193 NIX_ERR_QUEUE_INVALID_RANGE,
194 NIX_ERR_AQ_READ_FAILED,
195 NIX_ERR_AQ_WRITE_FAILED,
196 NIX_ERR_TM_LEAF_NODE_GET,
197 NIX_ERR_TM_INVALID_LVL,
198 NIX_ERR_TM_INVALID_PRIO,
199 NIX_ERR_TM_INVALID_PARENT,
200 NIX_ERR_TM_NODE_EXISTS,
201 NIX_ERR_TM_INVALID_NODE,
202 NIX_ERR_TM_INVALID_SHAPER_PROFILE,
203 NIX_ERR_TM_PKT_MODE_MISMATCH,
204 NIX_ERR_TM_WEIGHT_EXCEED,
205 NIX_ERR_TM_CHILD_EXISTS,
206 NIX_ERR_TM_INVALID_PEAK_SZ,
207 NIX_ERR_TM_INVALID_PEAK_RATE,
208 NIX_ERR_TM_INVALID_COMMIT_SZ,
209 NIX_ERR_TM_INVALID_COMMIT_RATE,
210 NIX_ERR_TM_SHAPER_PROFILE_IN_USE,
211 NIX_ERR_TM_SHAPER_PROFILE_EXISTS,
212 NIX_ERR_TM_SHAPER_PKT_LEN_ADJUST,
213 NIX_ERR_TM_INVALID_TREE,
214 NIX_ERR_TM_PARENT_PRIO_UPDATE,
215 NIX_ERR_TM_PRIO_EXCEEDED,
216 NIX_ERR_TM_PRIO_ORDER,
217 NIX_ERR_TM_MULTIPLE_RR_GROUPS,
218 NIX_ERR_TM_SQ_UPDATE_FAIL,
223 nix_q_size_16, /* 16 entries */
224 nix_q_size_64, /* 64 entries */
231 nix_q_size_1M, /* Million entries */
235 static inline struct nix *
236 roc_nix_to_nix_priv(struct roc_nix *roc_nix)
238 return (struct nix *)&roc_nix->reserved[0];
241 static inline struct roc_nix *
242 nix_priv_to_roc_nix(struct nix *nix)
244 return (struct roc_nix *)((char *)nix -
245 offsetof(struct roc_nix, reserved));
249 int nix_register_irqs(struct nix *nix);
250 void nix_unregister_irqs(struct nix *nix);
253 #define NIX_TM_TREE_MASK_ALL \
254 (BIT(ROC_NIX_TM_DEFAULT) | BIT(ROC_NIX_TM_RLIMIT) | \
255 BIT(ROC_NIX_TM_USER))
258 * NIX_TM_DFLT_RR_WT * NIX_TM_RR_QUANTUM_MAX / ROC_NIX_TM_MAX_SCHED_WT
260 #define NIX_TM_DFLT_RR_WT 71
262 /* Default TL1 priority and Quantum from AF */
263 #define NIX_TM_TL1_DFLT_RR_QTM ((1 << 24) - 1)
264 #define NIX_TM_TL1_DFLT_RR_PRIO 1
266 struct nix_tm_shaper_data {
267 uint64_t burst_exponent;
268 uint64_t burst_mantissa;
276 static inline uint64_t
277 nix_tm_weight_to_rr_quantum(uint64_t weight)
279 uint64_t max = NIX_CN9K_TM_RR_QUANTUM_MAX;
281 /* From CN10K onwards, we only configure RR weight */
282 if (!roc_model_is_cn9k())
285 weight &= (uint64_t)max;
286 return (weight * max) / ROC_NIX_CN9K_TM_RR_WEIGHT_MAX;
290 nix_tm_have_tl1_access(struct nix *nix)
292 return !!(nix->tm_flags & NIX_TM_TL1_ACCESS);
296 nix_tm_is_leaf(struct nix *nix, int lvl)
298 if (nix_tm_have_tl1_access(nix))
299 return (lvl == ROC_TM_LVL_QUEUE);
300 return (lvl == ROC_TM_LVL_SCH4);
303 static inline struct nix_tm_node_list *
304 nix_tm_node_list(struct nix *nix, enum roc_nix_tm_tree tree)
306 return &nix->trees[tree];
309 static inline const char *
310 nix_tm_hwlvl2str(uint32_t hw_lvl)
313 case NIX_TXSCH_LVL_MDQ:
315 case NIX_TXSCH_LVL_TL4:
317 case NIX_TXSCH_LVL_TL3:
319 case NIX_TXSCH_LVL_TL2:
321 case NIX_TXSCH_LVL_TL1:
330 static inline const char *
331 nix_tm_tree2str(enum roc_nix_tm_tree tree)
333 if (tree == ROC_NIX_TM_DEFAULT)
334 return "Default Tree";
335 else if (tree == ROC_NIX_TM_RLIMIT)
336 return "Rate Limit Tree";
337 else if (tree == ROC_NIX_TM_USER)
346 int nix_tm_conf_init(struct roc_nix *roc_nix);
347 void nix_tm_conf_fini(struct roc_nix *roc_nix);
348 int nix_tm_leaf_data_get(struct nix *nix, uint16_t sq, uint32_t *rr_quantum,
350 int nix_tm_sq_flush_pre(struct roc_nix_sq *sq);
351 int nix_tm_sq_flush_post(struct roc_nix_sq *sq);
352 int nix_tm_smq_xoff(struct nix *nix, struct nix_tm_node *node, bool enable);
353 int nix_tm_prepare_default_tree(struct roc_nix *roc_nix);
354 int nix_tm_node_add(struct roc_nix *roc_nix, struct nix_tm_node *node);
355 int nix_tm_node_delete(struct roc_nix *roc_nix, uint32_t node_id,
356 enum roc_nix_tm_tree tree, bool free);
357 int nix_tm_free_node_resource(struct nix *nix, struct nix_tm_node *node);
358 int nix_tm_free_resources(struct roc_nix *roc_nix, uint32_t tree_mask,
360 int nix_tm_clear_path_xoff(struct nix *nix, struct nix_tm_node *node);
361 void nix_tm_clear_shaper_profiles(struct nix *nix);
362 int nix_tm_alloc_txschq(struct nix *nix, enum roc_nix_tm_tree tree);
363 int nix_tm_assign_resources(struct nix *nix, enum roc_nix_tm_tree tree);
364 int nix_tm_release_resources(struct nix *nix, uint8_t hw_lvl, bool contig,
366 void nix_tm_copy_rsp_to_nix(struct nix *nix, struct nix_txsch_alloc_rsp *rsp);
368 int nix_tm_txsch_reg_config(struct nix *nix, enum roc_nix_tm_tree tree);
369 int nix_tm_update_parent_info(struct nix *nix, enum roc_nix_tm_tree tree);
370 int nix_tm_sq_sched_conf(struct nix *nix, struct nix_tm_node *node,
371 bool rr_quantum_only);
373 int nix_rq_cn9k_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints,
375 int nix_rq_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints, bool cfg,
377 int nix_rq_ena_dis(struct dev *dev, struct roc_nix_rq *rq, bool enable);
378 int nix_tm_bp_config_get(struct roc_nix *roc_nix, bool *is_enabled);
379 int nix_tm_bp_config_set(struct roc_nix *roc_nix, bool enable);
384 uint16_t nix_tm_lvl2nix(struct nix *nix, uint32_t lvl);
385 uint16_t nix_tm_lvl2nix_tl1_root(uint32_t lvl);
386 uint16_t nix_tm_lvl2nix_tl2_root(uint32_t lvl);
387 uint16_t nix_tm_resource_avail(struct nix *nix, uint8_t hw_lvl, bool contig);
388 int nix_tm_validate_prio(struct nix *nix, uint32_t lvl, uint32_t parent_id,
389 uint32_t priority, enum roc_nix_tm_tree tree);
390 struct nix_tm_node *nix_tm_node_search(struct nix *nix, uint32_t node_id,
391 enum roc_nix_tm_tree tree);
392 struct nix_tm_shaper_profile *nix_tm_shaper_profile_search(struct nix *nix,
394 uint8_t nix_tm_sw_xoff_prep(struct nix_tm_node *node, bool enable,
395 volatile uint64_t *reg, volatile uint64_t *regval);
396 uint32_t nix_tm_check_rr(struct nix *nix, uint32_t parent_id,
397 enum roc_nix_tm_tree tree, uint32_t *rr_prio,
399 uint64_t nix_tm_shaper_profile_rate_min(struct nix *nix);
400 uint64_t nix_tm_shaper_rate_conv(uint64_t value, uint64_t *exponent_p,
401 uint64_t *mantissa_p, uint64_t *div_exp_p);
402 uint64_t nix_tm_shaper_burst_conv(uint64_t value, uint64_t *exponent_p,
403 uint64_t *mantissa_p);
404 bool nix_tm_child_res_valid(struct nix_tm_node_list *list,
405 struct nix_tm_node *parent);
406 uint16_t nix_tm_resource_estimate(struct nix *nix, uint16_t *schq_contig,
407 uint16_t *schq, enum roc_nix_tm_tree tree);
408 uint8_t nix_tm_tl1_default_prep(uint32_t schq, volatile uint64_t *reg,
409 volatile uint64_t *regval);
410 uint8_t nix_tm_topology_reg_prep(struct nix *nix, struct nix_tm_node *node,
411 volatile uint64_t *reg,
412 volatile uint64_t *regval,
413 volatile uint64_t *regval_mask);
414 uint8_t nix_tm_sched_reg_prep(struct nix *nix, struct nix_tm_node *node,
415 volatile uint64_t *reg,
416 volatile uint64_t *regval);
417 uint8_t nix_tm_shaper_reg_prep(struct nix_tm_node *node,
418 struct nix_tm_shaper_profile *profile,
419 volatile uint64_t *reg,
420 volatile uint64_t *regval);
421 struct nix_tm_node *nix_tm_node_alloc(void);
422 void nix_tm_node_free(struct nix_tm_node *node);
423 struct nix_tm_shaper_profile *nix_tm_shaper_profile_alloc(void);
424 void nix_tm_shaper_profile_free(struct nix_tm_shaper_profile *profile);
426 uint64_t nix_get_blkaddr(struct dev *dev);
427 void nix_lf_rq_dump(__io struct nix_cn10k_rq_ctx_s *ctx);
428 int nix_lf_gen_reg_dump(uintptr_t nix_lf_base, uint64_t *data);
429 int nix_lf_stat_reg_dump(uintptr_t nix_lf_base, uint64_t *data,
430 uint8_t lf_tx_stats, uint8_t lf_rx_stats);
431 int nix_lf_int_reg_dump(uintptr_t nix_lf_base, uint64_t *data, uint16_t qints,
433 int nix_q_ctx_get(struct dev *dev, uint8_t ctype, uint16_t qid,
439 int nix_tel_node_add(struct roc_nix *roc_nix);
440 void nix_tel_node_del(struct roc_nix *roc_nix);
441 int nix_tel_node_add_rq(struct roc_nix_rq *rq);
442 int nix_tel_node_add_cq(struct roc_nix_cq *cq);
443 int nix_tel_node_add_sq(struct roc_nix_sq *sq);
445 #endif /* _ROC_NIX_PRIV_H_ */