1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
5 #ifndef _ROC_NIX_PRIV_H_
6 #define _ROC_NIX_PRIV_H_
9 #define NIX_CQ_ENTRY_SZ 128
10 #define NIX_CQ_ENTRY64_SZ 512
11 #define NIX_CQ_ALIGN ((uint16_t)512)
12 #define NIX_MAX_SQB ((uint16_t)512)
13 #define NIX_DEF_SQB ((uint16_t)16)
14 #define NIX_MIN_SQB ((uint16_t)8)
15 #define NIX_SQB_LIST_SPACE ((uint16_t)2)
16 #define NIX_SQB_LOWER_THRESH ((uint16_t)70)
18 /* Apply BP/DROP when CQ is 95% full */
19 #define NIX_CQ_THRESH_LEVEL (5 * 256 / 100)
20 #define NIX_CQ_FULL_ERRATA_SKID (1024ull * 256)
21 #define NIX_RQ_AURA_THRESH(x) (((x)*95) / 100)
23 /* IRQ triggered when NIX_LF_CINTX_CNT[QCOUNT] crosses this value */
24 #define CQ_CQE_THRESH_DEFAULT 0x1ULL
25 #define CQ_TIMER_THRESH_DEFAULT 0xAULL /* ~1usec i.e (0xA * 100nsec) */
26 #define CQ_TIMER_THRESH_MAX 255
34 #define NIX_TM_MAX_HW_TXSCHQ 1024
35 #define NIX_TM_HW_ID_INVALID UINT32_MAX
36 #define NIX_TM_CHAN_INVALID UINT16_MAX
39 #define NIX_TM_HIERARCHY_ENA BIT_ULL(0)
40 #define NIX_TM_TL1_NO_SP BIT_ULL(1)
41 #define NIX_TM_TL1_ACCESS BIT_ULL(2)
42 #define NIX_TM_MARK_VLAN_DEI_EN BIT_ULL(3)
43 #define NIX_TM_MARK_IP_DSCP_EN BIT_ULL(4)
44 #define NIX_TM_MARK_IP_ECN_EN BIT_ULL(5)
46 #define NIX_TM_MARK_EN_MASK \
47 (NIX_TM_MARK_IP_DSCP_EN | NIX_TM_MARK_IP_ECN_EN | \
48 NIX_TM_MARK_VLAN_DEI_EN)
50 #define NIX_TM_MARK_VLAN_DEI_SHIFT 0 /* Leave 16b for VLAN for FP logic */
51 #define NIX_TM_MARK_IPV4_DSCP_SHIFT 16
52 #define NIX_TM_MARK_IPV6_DSCP_SHIFT 24
53 #define NIX_TM_MARK_IPV4_ECN_SHIFT 32
54 #define NIX_TM_MARK_IPV6_ECN_SHIFT 40
57 /** Token bucket rate (bytes per second) */
60 /** Token bucket size (bytes), a.k.a. max burst size */
65 TAILQ_ENTRY(nix_tm_node) node;
68 enum roc_nix_tm_tree tree;
75 uint32_t shaper_profile_id;
76 void (*free_fn)(void *node);
84 uint32_t parent_hw_id;
86 #define NIX_TM_NODE_HWRES BIT_ULL(0)
87 #define NIX_TM_NODE_ENABLED BIT_ULL(1)
88 /* Shaper algorithm for RED state @NIX_REDALG_E */
89 uint32_t red_algo : 2;
90 uint32_t pkt_mode : 1;
91 uint32_t pkt_mode_set : 1;
95 struct nix_tm_node *parent;
97 /* Non-leaf node sp count */
98 uint32_t n_sp_priorities;
105 struct nix_tm_shaper_profile {
106 TAILQ_ENTRY(nix_tm_shaper_profile) shaper;
107 struct nix_tm_tb commit;
108 struct nix_tm_tb peak;
110 int32_t pkt_mode_adj;
114 void (*free_fn)(void *profile);
119 TAILQ_HEAD(nix_tm_node_list, nix_tm_node);
120 TAILQ_HEAD(nix_tm_shaper_profile_list, nix_tm_shaper_profile);
123 uint16_t reta[ROC_NIX_RSS_GRPS][ROC_NIX_RSS_RETA_MAX];
124 enum roc_nix_rss_reta_sz reta_sz;
125 struct plt_pci_device *pci_dev;
126 uint16_t bpid[NIX_MAX_CHAN];
127 struct nix_qint *qints_mem;
128 struct nix_qint *cints_mem;
129 uint8_t configured_qints;
130 uint8_t configured_cints;
131 struct roc_nix_sq **sqs;
132 uint16_t vwqe_interval;
133 uint16_t tx_chan_base;
134 uint16_t rx_chan_base;
135 uint16_t nb_rx_queues;
136 uint16_t nb_tx_queues;
137 uint8_t lso_tsov6_idx;
138 uint8_t lso_tsov4_idx;
139 uint8_t lso_udp_tun_idx[ROC_NIX_LSO_TUN_MAX];
140 uint8_t lso_tun_idx[ROC_NIX_LSO_TUN_MAX];
152 /* Without FCS, with L2 overhead */
169 /* Traffic manager info */
171 /* Contiguous resources per lvl */
172 struct plt_bitmap *schq_contig_bmp[NIX_TXSCH_LVL_CNT];
173 /* Dis-contiguous resources per lvl */
174 struct plt_bitmap *schq_bmp[NIX_TXSCH_LVL_CNT];
177 struct nix_tm_shaper_profile_list shaper_profile_list;
178 struct nix_tm_node_list trees[ROC_NIX_TM_TREE_MAX];
179 enum roc_nix_tm_tree tm_tree;
180 uint64_t tm_rate_min;
181 uint16_t tm_root_lvl;
183 uint16_t tm_link_cfg_lvl;
184 uint16_t contig_rsvd[NIX_TXSCH_LVL_CNT];
185 uint16_t discontig_rsvd[NIX_TXSCH_LVL_CNT];
186 uint64_t tm_markfmt_en;
187 uint8_t tm_markfmt_null;
188 uint8_t tm_markfmt[ROC_NIX_TM_MARK_MAX][ROC_NIX_TM_MARK_COLOR_MAX];
191 uint16_t cpt_msixoff[MAX_RVU_BLKLF_CNT];
196 uint32_t inb_spi_mask;
199 uint16_t outb_err_sso_pffunc;
200 struct roc_cpt_lf *cpt_lf_base;
202 uint16_t outb_se_ring_cnt;
203 uint16_t outb_se_ring_base;
204 /* Mode provided by driver */
207 } __plt_cache_aligned;
209 enum nix_err_status {
210 NIX_ERR_PARAM = -2048,
212 NIX_ERR_INVALID_RANGE,
216 NIX_ERR_QUEUE_INVALID_RANGE,
217 NIX_ERR_AQ_READ_FAILED,
218 NIX_ERR_AQ_WRITE_FAILED,
219 NIX_ERR_TM_LEAF_NODE_GET,
220 NIX_ERR_TM_INVALID_LVL,
221 NIX_ERR_TM_INVALID_PRIO,
222 NIX_ERR_TM_INVALID_PARENT,
223 NIX_ERR_TM_NODE_EXISTS,
224 NIX_ERR_TM_INVALID_NODE,
225 NIX_ERR_TM_INVALID_SHAPER_PROFILE,
226 NIX_ERR_TM_PKT_MODE_MISMATCH,
227 NIX_ERR_TM_WEIGHT_EXCEED,
228 NIX_ERR_TM_CHILD_EXISTS,
229 NIX_ERR_TM_INVALID_PEAK_SZ,
230 NIX_ERR_TM_INVALID_PEAK_RATE,
231 NIX_ERR_TM_INVALID_COMMIT_SZ,
232 NIX_ERR_TM_INVALID_COMMIT_RATE,
233 NIX_ERR_TM_SHAPER_PROFILE_IN_USE,
234 NIX_ERR_TM_SHAPER_PROFILE_EXISTS,
235 NIX_ERR_TM_SHAPER_PKT_LEN_ADJUST,
236 NIX_ERR_TM_INVALID_TREE,
237 NIX_ERR_TM_PARENT_PRIO_UPDATE,
238 NIX_ERR_TM_PRIO_EXCEEDED,
239 NIX_ERR_TM_PRIO_ORDER,
240 NIX_ERR_TM_MULTIPLE_RR_GROUPS,
241 NIX_ERR_TM_SQ_UPDATE_FAIL,
246 nix_q_size_16, /* 16 entries */
247 nix_q_size_64, /* 64 entries */
254 nix_q_size_1M, /* Million entries */
258 static inline struct nix *
259 roc_nix_to_nix_priv(struct roc_nix *roc_nix)
261 return (struct nix *)&roc_nix->reserved[0];
264 static inline struct roc_nix *
265 nix_priv_to_roc_nix(struct nix *nix)
267 return (struct roc_nix *)((char *)nix -
268 offsetof(struct roc_nix, reserved));
272 int nix_register_irqs(struct nix *nix);
273 void nix_unregister_irqs(struct nix *nix);
276 #define NIX_TM_TREE_MASK_ALL \
277 (BIT(ROC_NIX_TM_DEFAULT) | BIT(ROC_NIX_TM_RLIMIT) | \
278 BIT(ROC_NIX_TM_USER))
281 * NIX_TM_DFLT_RR_WT * NIX_TM_RR_QUANTUM_MAX / ROC_NIX_TM_MAX_SCHED_WT
283 #define NIX_TM_DFLT_RR_WT 71
285 /* Default TL1 priority and Quantum from AF */
286 #define NIX_TM_TL1_DFLT_RR_QTM ((1 << 24) - 1)
287 #define NIX_TM_TL1_DFLT_RR_PRIO 1
289 struct nix_tm_shaper_data {
290 uint64_t burst_exponent;
291 uint64_t burst_mantissa;
299 static inline uint64_t
300 nix_tm_weight_to_rr_quantum(uint64_t weight)
302 uint64_t max = NIX_CN9K_TM_RR_QUANTUM_MAX;
304 /* From CN10K onwards, we only configure RR weight */
305 if (!roc_model_is_cn9k())
308 weight &= (uint64_t)max;
309 return (weight * max) / ROC_NIX_CN9K_TM_RR_WEIGHT_MAX;
313 nix_tm_have_tl1_access(struct nix *nix)
315 return !!(nix->tm_flags & NIX_TM_TL1_ACCESS);
319 nix_tm_is_leaf(struct nix *nix, int lvl)
321 if (nix_tm_have_tl1_access(nix))
322 return (lvl == ROC_TM_LVL_QUEUE);
323 return (lvl == ROC_TM_LVL_SCH4);
326 static inline struct nix_tm_node_list *
327 nix_tm_node_list(struct nix *nix, enum roc_nix_tm_tree tree)
329 return &nix->trees[tree];
332 static inline const char *
333 nix_tm_hwlvl2str(uint32_t hw_lvl)
336 case NIX_TXSCH_LVL_MDQ:
338 case NIX_TXSCH_LVL_TL4:
340 case NIX_TXSCH_LVL_TL3:
342 case NIX_TXSCH_LVL_TL2:
344 case NIX_TXSCH_LVL_TL1:
353 static inline const char *
354 nix_tm_tree2str(enum roc_nix_tm_tree tree)
356 if (tree == ROC_NIX_TM_DEFAULT)
357 return "Default Tree";
358 else if (tree == ROC_NIX_TM_RLIMIT)
359 return "Rate Limit Tree";
360 else if (tree == ROC_NIX_TM_USER)
369 int nix_tm_conf_init(struct roc_nix *roc_nix);
370 void nix_tm_conf_fini(struct roc_nix *roc_nix);
371 int nix_tm_leaf_data_get(struct nix *nix, uint16_t sq, uint32_t *rr_quantum,
373 int nix_tm_sq_flush_pre(struct roc_nix_sq *sq);
374 int nix_tm_sq_flush_post(struct roc_nix_sq *sq);
375 int nix_tm_smq_xoff(struct nix *nix, struct nix_tm_node *node, bool enable);
376 int nix_tm_prepare_default_tree(struct roc_nix *roc_nix);
377 int nix_tm_node_add(struct roc_nix *roc_nix, struct nix_tm_node *node);
378 int nix_tm_node_delete(struct roc_nix *roc_nix, uint32_t node_id,
379 enum roc_nix_tm_tree tree, bool free);
380 int nix_tm_free_node_resource(struct nix *nix, struct nix_tm_node *node);
381 int nix_tm_free_resources(struct roc_nix *roc_nix, uint32_t tree_mask,
383 int nix_tm_clear_path_xoff(struct nix *nix, struct nix_tm_node *node);
384 void nix_tm_clear_shaper_profiles(struct nix *nix);
385 int nix_tm_alloc_txschq(struct nix *nix, enum roc_nix_tm_tree tree);
386 int nix_tm_assign_resources(struct nix *nix, enum roc_nix_tm_tree tree);
387 int nix_tm_release_resources(struct nix *nix, uint8_t hw_lvl, bool contig,
389 void nix_tm_copy_rsp_to_nix(struct nix *nix, struct nix_txsch_alloc_rsp *rsp);
391 int nix_tm_txsch_reg_config(struct nix *nix, enum roc_nix_tm_tree tree);
392 int nix_tm_update_parent_info(struct nix *nix, enum roc_nix_tm_tree tree);
393 int nix_tm_sq_sched_conf(struct nix *nix, struct nix_tm_node *node,
394 bool rr_quantum_only);
396 int nix_rq_cn9k_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints,
398 int nix_rq_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints, bool cfg,
400 int nix_rq_ena_dis(struct dev *dev, struct roc_nix_rq *rq, bool enable);
401 int nix_tm_bp_config_get(struct roc_nix *roc_nix, bool *is_enabled);
402 int nix_tm_bp_config_set(struct roc_nix *roc_nix, uint16_t sq, uint16_t tc,
404 void nix_rq_vwqe_flush(struct roc_nix_rq *rq, uint16_t vwqe_interval);
405 int nix_tm_mark_init(struct nix *nix);
410 uint16_t nix_tm_lvl2nix(struct nix *nix, uint32_t lvl);
411 uint16_t nix_tm_lvl2nix_tl1_root(uint32_t lvl);
412 uint16_t nix_tm_lvl2nix_tl2_root(uint32_t lvl);
413 uint16_t nix_tm_resource_avail(struct nix *nix, uint8_t hw_lvl, bool contig);
414 int nix_tm_validate_prio(struct nix *nix, uint32_t lvl, uint32_t parent_id,
415 uint32_t priority, enum roc_nix_tm_tree tree);
416 struct nix_tm_node *nix_tm_node_search(struct nix *nix, uint32_t node_id,
417 enum roc_nix_tm_tree tree);
418 struct nix_tm_shaper_profile *nix_tm_shaper_profile_search(struct nix *nix,
420 uint8_t nix_tm_sw_xoff_prep(struct nix_tm_node *node, bool enable,
421 volatile uint64_t *reg, volatile uint64_t *regval);
422 uint32_t nix_tm_check_rr(struct nix *nix, uint32_t parent_id,
423 enum roc_nix_tm_tree tree, uint32_t *rr_prio,
425 uint64_t nix_tm_shaper_profile_rate_min(struct nix *nix);
426 uint64_t nix_tm_shaper_rate_conv(uint64_t value, uint64_t *exponent_p,
427 uint64_t *mantissa_p, uint64_t *div_exp_p,
429 uint64_t nix_tm_shaper_burst_conv(uint64_t value, uint64_t *exponent_p,
430 uint64_t *mantissa_p);
431 bool nix_tm_child_res_valid(struct nix_tm_node_list *list,
432 struct nix_tm_node *parent);
433 uint16_t nix_tm_resource_estimate(struct nix *nix, uint16_t *schq_contig,
434 uint16_t *schq, enum roc_nix_tm_tree tree);
435 uint8_t nix_tm_tl1_default_prep(uint32_t schq, volatile uint64_t *reg,
436 volatile uint64_t *regval);
437 uint8_t nix_tm_topology_reg_prep(struct nix *nix, struct nix_tm_node *node,
438 volatile uint64_t *reg,
439 volatile uint64_t *regval,
440 volatile uint64_t *regval_mask);
441 uint8_t nix_tm_sched_reg_prep(struct nix *nix, struct nix_tm_node *node,
442 volatile uint64_t *reg,
443 volatile uint64_t *regval);
444 uint8_t nix_tm_shaper_reg_prep(struct nix_tm_node *node,
445 struct nix_tm_shaper_profile *profile,
446 volatile uint64_t *reg,
447 volatile uint64_t *regval);
448 struct nix_tm_node *nix_tm_node_alloc(void);
449 void nix_tm_node_free(struct nix_tm_node *node);
450 struct nix_tm_shaper_profile *nix_tm_shaper_profile_alloc(void);
451 void nix_tm_shaper_profile_free(struct nix_tm_shaper_profile *profile);
453 uint64_t nix_get_blkaddr(struct dev *dev);
454 void nix_lf_rq_dump(__io struct nix_cn10k_rq_ctx_s *ctx);
455 int nix_lf_gen_reg_dump(uintptr_t nix_lf_base, uint64_t *data);
456 int nix_lf_stat_reg_dump(uintptr_t nix_lf_base, uint64_t *data,
457 uint8_t lf_tx_stats, uint8_t lf_rx_stats);
458 int nix_lf_int_reg_dump(uintptr_t nix_lf_base, uint64_t *data, uint16_t qints,
460 int nix_q_ctx_get(struct dev *dev, uint8_t ctype, uint16_t qid,
466 int nix_tel_node_add(struct roc_nix *roc_nix);
467 void nix_tel_node_del(struct roc_nix *roc_nix);
468 int nix_tel_node_add_rq(struct roc_nix_rq *rq);
469 int nix_tel_node_add_cq(struct roc_nix_cq *cq);
470 int nix_tel_node_add_sq(struct roc_nix_sq *sq);
472 #endif /* _ROC_NIX_PRIV_H_ */