1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
5 #ifndef _ROC_NIX_PRIV_H_
6 #define _ROC_NIX_PRIV_H_
9 #define NIX_CQ_ENTRY_SZ 128
10 #define NIX_CQ_ENTRY64_SZ 512
11 #define NIX_CQ_ALIGN ((uint16_t)512)
12 #define NIX_MAX_SQB ((uint16_t)512)
13 #define NIX_DEF_SQB ((uint16_t)16)
14 #define NIX_MIN_SQB ((uint16_t)8)
15 #define NIX_SQB_LIST_SPACE ((uint16_t)2)
16 #define NIX_SQB_LOWER_THRESH ((uint16_t)70)
18 /* Apply BP/DROP when CQ is 95% full */
19 #define NIX_CQ_THRESH_LEVEL (5 * 256 / 100)
20 #define NIX_RQ_AURA_THRESH(x) (((x) * 95) / 100)
22 /* IRQ triggered when NIX_LF_CINTX_CNT[QCOUNT] crosses this value */
23 #define CQ_CQE_THRESH_DEFAULT 0x1ULL
24 #define CQ_TIMER_THRESH_DEFAULT 0xAULL /* ~1usec i.e (0xA * 100nsec) */
25 #define CQ_TIMER_THRESH_MAX 255
33 #define NIX_TM_MAX_HW_TXSCHQ 512
34 #define NIX_TM_HW_ID_INVALID UINT32_MAX
37 #define NIX_TM_HIERARCHY_ENA BIT_ULL(0)
38 #define NIX_TM_TL1_NO_SP BIT_ULL(1)
39 #define NIX_TM_TL1_ACCESS BIT_ULL(2)
42 /** Token bucket rate (bytes per second) */
45 /** Token bucket size (bytes), a.k.a. max burst size */
50 TAILQ_ENTRY(nix_tm_node) node;
53 enum roc_nix_tm_tree tree;
59 uint32_t shaper_profile_id;
60 void (*free_fn)(void *node);
68 uint32_t parent_hw_id;
70 #define NIX_TM_NODE_HWRES BIT_ULL(0)
71 #define NIX_TM_NODE_ENABLED BIT_ULL(1)
72 /* Shaper algorithm for RED state @NIX_REDALG_E */
73 uint32_t red_algo : 2;
74 uint32_t pkt_mode : 1;
75 uint32_t pkt_mode_set : 1;
78 struct nix_tm_node *parent;
80 /* Non-leaf node sp count */
81 uint32_t n_sp_priorities;
88 struct nix_tm_shaper_profile {
89 TAILQ_ENTRY(nix_tm_shaper_profile) shaper;
90 struct nix_tm_tb commit;
91 struct nix_tm_tb peak;
95 void (*free_fn)(void *profile);
100 TAILQ_HEAD(nix_tm_node_list, nix_tm_node);
101 TAILQ_HEAD(nix_tm_shaper_profile_list, nix_tm_shaper_profile);
104 uint16_t reta[ROC_NIX_RSS_GRPS][ROC_NIX_RSS_RETA_MAX];
105 enum roc_nix_rss_reta_sz reta_sz;
106 struct plt_pci_device *pci_dev;
107 uint16_t bpid[NIX_MAX_CHAN];
108 struct nix_qint *qints_mem;
109 struct nix_qint *cints_mem;
110 uint8_t configured_qints;
111 uint8_t configured_cints;
112 struct roc_nix_sq **sqs;
113 uint16_t vwqe_interval;
114 uint16_t tx_chan_base;
115 uint16_t rx_chan_base;
116 uint16_t nb_rx_queues;
117 uint16_t nb_tx_queues;
118 uint8_t lso_tsov6_idx;
119 uint8_t lso_tsov4_idx;
120 uint8_t lso_udp_tun_idx[ROC_NIX_LSO_TUN_MAX];
121 uint8_t lso_tun_idx[ROC_NIX_LSO_TUN_MAX];
133 /* Without FCS, with L2 overhead */
148 /* Traffic manager info */
150 /* Contiguous resources per lvl */
151 struct plt_bitmap *schq_contig_bmp[NIX_TXSCH_LVL_CNT];
152 /* Dis-contiguous resources per lvl */
153 struct plt_bitmap *schq_bmp[NIX_TXSCH_LVL_CNT];
156 struct nix_tm_shaper_profile_list shaper_profile_list;
157 struct nix_tm_node_list trees[ROC_NIX_TM_TREE_MAX];
158 enum roc_nix_tm_tree tm_tree;
159 uint64_t tm_rate_min;
160 uint16_t tm_root_lvl;
162 uint16_t tm_link_cfg_lvl;
163 uint16_t contig_rsvd[NIX_TXSCH_LVL_CNT];
164 uint16_t discontig_rsvd[NIX_TXSCH_LVL_CNT];
165 } __plt_cache_aligned;
167 enum nix_err_status {
168 NIX_ERR_PARAM = -2048,
170 NIX_ERR_INVALID_RANGE,
173 NIX_ERR_QUEUE_INVALID_RANGE,
174 NIX_ERR_AQ_READ_FAILED,
175 NIX_ERR_AQ_WRITE_FAILED,
176 NIX_ERR_TM_LEAF_NODE_GET,
177 NIX_ERR_TM_INVALID_LVL,
178 NIX_ERR_TM_INVALID_PRIO,
179 NIX_ERR_TM_INVALID_PARENT,
180 NIX_ERR_TM_NODE_EXISTS,
181 NIX_ERR_TM_INVALID_NODE,
182 NIX_ERR_TM_INVALID_SHAPER_PROFILE,
183 NIX_ERR_TM_PKT_MODE_MISMATCH,
184 NIX_ERR_TM_WEIGHT_EXCEED,
185 NIX_ERR_TM_CHILD_EXISTS,
186 NIX_ERR_TM_INVALID_PEAK_SZ,
187 NIX_ERR_TM_INVALID_PEAK_RATE,
188 NIX_ERR_TM_INVALID_COMMIT_SZ,
189 NIX_ERR_TM_INVALID_COMMIT_RATE,
190 NIX_ERR_TM_SHAPER_PROFILE_IN_USE,
191 NIX_ERR_TM_SHAPER_PROFILE_EXISTS,
192 NIX_ERR_TM_SHAPER_PKT_LEN_ADJUST,
193 NIX_ERR_TM_INVALID_TREE,
194 NIX_ERR_TM_PARENT_PRIO_UPDATE,
195 NIX_ERR_TM_PRIO_EXCEEDED,
196 NIX_ERR_TM_PRIO_ORDER,
197 NIX_ERR_TM_MULTIPLE_RR_GROUPS,
198 NIX_ERR_TM_SQ_UPDATE_FAIL,
203 nix_q_size_16, /* 16 entries */
204 nix_q_size_64, /* 64 entries */
211 nix_q_size_1M, /* Million entries */
215 static inline struct nix *
216 roc_nix_to_nix_priv(struct roc_nix *roc_nix)
218 return (struct nix *)&roc_nix->reserved[0];
221 static inline struct roc_nix *
222 nix_priv_to_roc_nix(struct nix *nix)
224 return (struct roc_nix *)((char *)nix -
225 offsetof(struct roc_nix, reserved));
229 int nix_register_irqs(struct nix *nix);
230 void nix_unregister_irqs(struct nix *nix);
233 #define NIX_TM_TREE_MASK_ALL \
234 (BIT(ROC_NIX_TM_DEFAULT) | BIT(ROC_NIX_TM_RLIMIT) | \
235 BIT(ROC_NIX_TM_USER))
238 * NIX_TM_DFLT_RR_WT * NIX_TM_RR_QUANTUM_MAX / ROC_NIX_TM_MAX_SCHED_WT
240 #define NIX_TM_DFLT_RR_WT 71
242 /* Default TL1 priority and Quantum from AF */
243 #define NIX_TM_TL1_DFLT_RR_QTM ((1 << 24) - 1)
244 #define NIX_TM_TL1_DFLT_RR_PRIO 1
246 struct nix_tm_shaper_data {
247 uint64_t burst_exponent;
248 uint64_t burst_mantissa;
256 static inline uint64_t
257 nix_tm_weight_to_rr_quantum(uint64_t weight)
259 uint64_t max = (roc_model_is_cn9k() ? NIX_CN9K_TM_RR_QUANTUM_MAX :
260 NIX_TM_RR_QUANTUM_MAX);
262 weight &= (uint64_t)ROC_NIX_TM_MAX_SCHED_WT;
263 return (weight * max) / ROC_NIX_TM_MAX_SCHED_WT;
267 nix_tm_have_tl1_access(struct nix *nix)
269 return !!(nix->tm_flags & NIX_TM_TL1_ACCESS);
273 nix_tm_is_leaf(struct nix *nix, int lvl)
275 if (nix_tm_have_tl1_access(nix))
276 return (lvl == ROC_TM_LVL_QUEUE);
277 return (lvl == ROC_TM_LVL_SCH4);
280 static inline struct nix_tm_node_list *
281 nix_tm_node_list(struct nix *nix, enum roc_nix_tm_tree tree)
283 return &nix->trees[tree];
286 static inline const char *
287 nix_tm_hwlvl2str(uint32_t hw_lvl)
290 case NIX_TXSCH_LVL_MDQ:
292 case NIX_TXSCH_LVL_TL4:
294 case NIX_TXSCH_LVL_TL3:
296 case NIX_TXSCH_LVL_TL2:
298 case NIX_TXSCH_LVL_TL1:
307 static inline const char *
308 nix_tm_tree2str(enum roc_nix_tm_tree tree)
310 if (tree == ROC_NIX_TM_DEFAULT)
311 return "Default Tree";
312 else if (tree == ROC_NIX_TM_RLIMIT)
313 return "Rate Limit Tree";
314 else if (tree == ROC_NIX_TM_USER)
323 int nix_tm_conf_init(struct roc_nix *roc_nix);
324 void nix_tm_conf_fini(struct roc_nix *roc_nix);
325 int nix_tm_leaf_data_get(struct nix *nix, uint16_t sq, uint32_t *rr_quantum,
327 int nix_tm_sq_flush_pre(struct roc_nix_sq *sq);
328 int nix_tm_sq_flush_post(struct roc_nix_sq *sq);
329 int nix_tm_smq_xoff(struct nix *nix, struct nix_tm_node *node, bool enable);
330 int nix_tm_prepare_default_tree(struct roc_nix *roc_nix);
331 int nix_tm_node_add(struct roc_nix *roc_nix, struct nix_tm_node *node);
332 int nix_tm_node_delete(struct roc_nix *roc_nix, uint32_t node_id,
333 enum roc_nix_tm_tree tree, bool free);
334 int nix_tm_free_node_resource(struct nix *nix, struct nix_tm_node *node);
335 int nix_tm_free_resources(struct roc_nix *roc_nix, uint32_t tree_mask,
337 int nix_tm_clear_path_xoff(struct nix *nix, struct nix_tm_node *node);
338 void nix_tm_clear_shaper_profiles(struct nix *nix);
339 int nix_tm_alloc_txschq(struct nix *nix, enum roc_nix_tm_tree tree);
340 int nix_tm_assign_resources(struct nix *nix, enum roc_nix_tm_tree tree);
341 int nix_tm_release_resources(struct nix *nix, uint8_t hw_lvl, bool contig,
343 void nix_tm_copy_rsp_to_nix(struct nix *nix, struct nix_txsch_alloc_rsp *rsp);
345 int nix_tm_txsch_reg_config(struct nix *nix, enum roc_nix_tm_tree tree);
346 int nix_tm_update_parent_info(struct nix *nix, enum roc_nix_tm_tree tree);
347 int nix_tm_sq_sched_conf(struct nix *nix, struct nix_tm_node *node,
348 bool rr_quantum_only);
349 int nix_tm_prepare_rate_limited_tree(struct roc_nix *roc_nix);
354 uint16_t nix_tm_lvl2nix(struct nix *nix, uint32_t lvl);
355 uint16_t nix_tm_lvl2nix_tl1_root(uint32_t lvl);
356 uint16_t nix_tm_lvl2nix_tl2_root(uint32_t lvl);
357 uint16_t nix_tm_resource_avail(struct nix *nix, uint8_t hw_lvl, bool contig);
358 int nix_tm_validate_prio(struct nix *nix, uint32_t lvl, uint32_t parent_id,
359 uint32_t priority, enum roc_nix_tm_tree tree);
360 struct nix_tm_node *nix_tm_node_search(struct nix *nix, uint32_t node_id,
361 enum roc_nix_tm_tree tree);
362 struct nix_tm_shaper_profile *nix_tm_shaper_profile_search(struct nix *nix,
364 uint8_t nix_tm_sw_xoff_prep(struct nix_tm_node *node, bool enable,
365 volatile uint64_t *reg, volatile uint64_t *regval);
366 uint32_t nix_tm_check_rr(struct nix *nix, uint32_t parent_id,
367 enum roc_nix_tm_tree tree, uint32_t *rr_prio,
369 uint64_t nix_tm_shaper_profile_rate_min(struct nix *nix);
370 uint64_t nix_tm_shaper_rate_conv(uint64_t value, uint64_t *exponent_p,
371 uint64_t *mantissa_p, uint64_t *div_exp_p);
372 uint64_t nix_tm_shaper_burst_conv(uint64_t value, uint64_t *exponent_p,
373 uint64_t *mantissa_p);
374 bool nix_tm_child_res_valid(struct nix_tm_node_list *list,
375 struct nix_tm_node *parent);
376 uint16_t nix_tm_resource_estimate(struct nix *nix, uint16_t *schq_contig,
377 uint16_t *schq, enum roc_nix_tm_tree tree);
378 uint8_t nix_tm_tl1_default_prep(uint32_t schq, volatile uint64_t *reg,
379 volatile uint64_t *regval);
380 uint8_t nix_tm_topology_reg_prep(struct nix *nix, struct nix_tm_node *node,
381 volatile uint64_t *reg,
382 volatile uint64_t *regval,
383 volatile uint64_t *regval_mask);
384 uint8_t nix_tm_sched_reg_prep(struct nix *nix, struct nix_tm_node *node,
385 volatile uint64_t *reg,
386 volatile uint64_t *regval);
387 uint8_t nix_tm_shaper_reg_prep(struct nix_tm_node *node,
388 struct nix_tm_shaper_profile *profile,
389 volatile uint64_t *reg,
390 volatile uint64_t *regval);
391 struct nix_tm_node *nix_tm_node_alloc(void);
392 void nix_tm_node_free(struct nix_tm_node *node);
393 struct nix_tm_shaper_profile *nix_tm_shaper_profile_alloc(void);
394 void nix_tm_shaper_profile_free(struct nix_tm_shaper_profile *profile);
396 #endif /* _ROC_NIX_PRIV_H_ */