1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
5 #ifndef _ROC_NIX_PRIV_H_
6 #define _ROC_NIX_PRIV_H_
9 #define NIX_CQ_ENTRY_SZ 128
10 #define NIX_CQ_ENTRY64_SZ 512
11 #define NIX_CQ_ALIGN ((uint16_t)512)
12 #define NIX_MAX_SQB ((uint16_t)512)
13 #define NIX_DEF_SQB ((uint16_t)16)
14 #define NIX_MIN_SQB ((uint16_t)8)
15 #define NIX_SQB_LIST_SPACE ((uint16_t)2)
16 #define NIX_SQB_LOWER_THRESH ((uint16_t)70)
18 /* Apply BP/DROP when CQ is 95% full */
19 #define NIX_CQ_THRESH_LEVEL (5 * 256 / 100)
20 #define NIX_RQ_AURA_THRESH(x) (((x) * 95) / 100)
22 /* IRQ triggered when NIX_LF_CINTX_CNT[QCOUNT] crosses this value */
23 #define CQ_CQE_THRESH_DEFAULT 0x1ULL
24 #define CQ_TIMER_THRESH_DEFAULT 0xAULL /* ~1usec i.e (0xA * 100nsec) */
25 #define CQ_TIMER_THRESH_MAX 255
33 #define NIX_TM_MAX_HW_TXSCHQ 512
34 #define NIX_TM_HW_ID_INVALID UINT32_MAX
37 #define NIX_TM_HIERARCHY_ENA BIT_ULL(0)
38 #define NIX_TM_TL1_NO_SP BIT_ULL(1)
39 #define NIX_TM_TL1_ACCESS BIT_ULL(2)
42 /** Token bucket rate (bytes per second) */
45 /** Token bucket size (bytes), a.k.a. max burst size */
50 TAILQ_ENTRY(nix_tm_node) node;
53 enum roc_nix_tm_tree tree;
59 uint32_t shaper_profile_id;
60 void (*free_fn)(void *node);
68 uint32_t parent_hw_id;
70 #define NIX_TM_NODE_HWRES BIT_ULL(0)
71 #define NIX_TM_NODE_ENABLED BIT_ULL(1)
72 /* Shaper algorithm for RED state @NIX_REDALG_E */
73 uint32_t red_algo : 2;
74 uint32_t pkt_mode : 1;
75 uint32_t pkt_mode_set : 1;
78 struct nix_tm_node *parent;
80 /* Non-leaf node sp count */
81 uint32_t n_sp_priorities;
88 struct nix_tm_shaper_profile {
89 TAILQ_ENTRY(nix_tm_shaper_profile) shaper;
90 struct nix_tm_tb commit;
91 struct nix_tm_tb peak;
96 void (*free_fn)(void *profile);
101 TAILQ_HEAD(nix_tm_node_list, nix_tm_node);
102 TAILQ_HEAD(nix_tm_shaper_profile_list, nix_tm_shaper_profile);
105 uint16_t reta[ROC_NIX_RSS_GRPS][ROC_NIX_RSS_RETA_MAX];
106 enum roc_nix_rss_reta_sz reta_sz;
107 struct plt_pci_device *pci_dev;
108 uint16_t bpid[NIX_MAX_CHAN];
109 struct nix_qint *qints_mem;
110 struct nix_qint *cints_mem;
111 uint8_t configured_qints;
112 uint8_t configured_cints;
113 struct roc_nix_sq **sqs;
114 uint16_t vwqe_interval;
115 uint16_t tx_chan_base;
116 uint16_t rx_chan_base;
117 uint16_t nb_rx_queues;
118 uint16_t nb_tx_queues;
119 uint8_t lso_tsov6_idx;
120 uint8_t lso_tsov4_idx;
121 uint8_t lso_udp_tun_idx[ROC_NIX_LSO_TUN_MAX];
122 uint8_t lso_tun_idx[ROC_NIX_LSO_TUN_MAX];
134 /* Without FCS, with L2 overhead */
149 /* Traffic manager info */
151 /* Contiguous resources per lvl */
152 struct plt_bitmap *schq_contig_bmp[NIX_TXSCH_LVL_CNT];
153 /* Dis-contiguous resources per lvl */
154 struct plt_bitmap *schq_bmp[NIX_TXSCH_LVL_CNT];
157 struct nix_tm_shaper_profile_list shaper_profile_list;
158 struct nix_tm_node_list trees[ROC_NIX_TM_TREE_MAX];
159 enum roc_nix_tm_tree tm_tree;
160 uint64_t tm_rate_min;
161 uint16_t tm_root_lvl;
163 uint16_t tm_link_cfg_lvl;
164 uint16_t contig_rsvd[NIX_TXSCH_LVL_CNT];
165 uint16_t discontig_rsvd[NIX_TXSCH_LVL_CNT];
166 } __plt_cache_aligned;
168 enum nix_err_status {
169 NIX_ERR_PARAM = -2048,
171 NIX_ERR_INVALID_RANGE,
174 NIX_ERR_QUEUE_INVALID_RANGE,
175 NIX_ERR_AQ_READ_FAILED,
176 NIX_ERR_AQ_WRITE_FAILED,
177 NIX_ERR_TM_LEAF_NODE_GET,
178 NIX_ERR_TM_INVALID_LVL,
179 NIX_ERR_TM_INVALID_PRIO,
180 NIX_ERR_TM_INVALID_PARENT,
181 NIX_ERR_TM_NODE_EXISTS,
182 NIX_ERR_TM_INVALID_NODE,
183 NIX_ERR_TM_INVALID_SHAPER_PROFILE,
184 NIX_ERR_TM_PKT_MODE_MISMATCH,
185 NIX_ERR_TM_WEIGHT_EXCEED,
186 NIX_ERR_TM_CHILD_EXISTS,
187 NIX_ERR_TM_INVALID_PEAK_SZ,
188 NIX_ERR_TM_INVALID_PEAK_RATE,
189 NIX_ERR_TM_INVALID_COMMIT_SZ,
190 NIX_ERR_TM_INVALID_COMMIT_RATE,
191 NIX_ERR_TM_SHAPER_PROFILE_IN_USE,
192 NIX_ERR_TM_SHAPER_PROFILE_EXISTS,
193 NIX_ERR_TM_SHAPER_PKT_LEN_ADJUST,
194 NIX_ERR_TM_INVALID_TREE,
195 NIX_ERR_TM_PARENT_PRIO_UPDATE,
196 NIX_ERR_TM_PRIO_EXCEEDED,
197 NIX_ERR_TM_PRIO_ORDER,
198 NIX_ERR_TM_MULTIPLE_RR_GROUPS,
199 NIX_ERR_TM_SQ_UPDATE_FAIL,
204 nix_q_size_16, /* 16 entries */
205 nix_q_size_64, /* 64 entries */
212 nix_q_size_1M, /* Million entries */
216 static inline struct nix *
217 roc_nix_to_nix_priv(struct roc_nix *roc_nix)
219 return (struct nix *)&roc_nix->reserved[0];
222 static inline struct roc_nix *
223 nix_priv_to_roc_nix(struct nix *nix)
225 return (struct roc_nix *)((char *)nix -
226 offsetof(struct roc_nix, reserved));
230 int nix_register_irqs(struct nix *nix);
231 void nix_unregister_irqs(struct nix *nix);
234 #define NIX_TM_TREE_MASK_ALL \
235 (BIT(ROC_NIX_TM_DEFAULT) | BIT(ROC_NIX_TM_RLIMIT) | \
236 BIT(ROC_NIX_TM_USER))
239 * NIX_TM_DFLT_RR_WT * NIX_TM_RR_QUANTUM_MAX / ROC_NIX_TM_MAX_SCHED_WT
241 #define NIX_TM_DFLT_RR_WT 71
243 /* Default TL1 priority and Quantum from AF */
244 #define NIX_TM_TL1_DFLT_RR_QTM ((1 << 24) - 1)
245 #define NIX_TM_TL1_DFLT_RR_PRIO 1
247 struct nix_tm_shaper_data {
248 uint64_t burst_exponent;
249 uint64_t burst_mantissa;
257 static inline uint64_t
258 nix_tm_weight_to_rr_quantum(uint64_t weight)
260 uint64_t max = NIX_CN9K_TM_RR_QUANTUM_MAX;
262 /* From CN10K onwards, we only configure RR weight */
263 if (!roc_model_is_cn9k())
266 weight &= (uint64_t)max;
267 return (weight * max) / ROC_NIX_CN9K_TM_RR_WEIGHT_MAX;
271 nix_tm_have_tl1_access(struct nix *nix)
273 return !!(nix->tm_flags & NIX_TM_TL1_ACCESS);
277 nix_tm_is_leaf(struct nix *nix, int lvl)
279 if (nix_tm_have_tl1_access(nix))
280 return (lvl == ROC_TM_LVL_QUEUE);
281 return (lvl == ROC_TM_LVL_SCH4);
284 static inline struct nix_tm_node_list *
285 nix_tm_node_list(struct nix *nix, enum roc_nix_tm_tree tree)
287 return &nix->trees[tree];
290 static inline const char *
291 nix_tm_hwlvl2str(uint32_t hw_lvl)
294 case NIX_TXSCH_LVL_MDQ:
296 case NIX_TXSCH_LVL_TL4:
298 case NIX_TXSCH_LVL_TL3:
300 case NIX_TXSCH_LVL_TL2:
302 case NIX_TXSCH_LVL_TL1:
311 static inline const char *
312 nix_tm_tree2str(enum roc_nix_tm_tree tree)
314 if (tree == ROC_NIX_TM_DEFAULT)
315 return "Default Tree";
316 else if (tree == ROC_NIX_TM_RLIMIT)
317 return "Rate Limit Tree";
318 else if (tree == ROC_NIX_TM_USER)
327 int nix_tm_conf_init(struct roc_nix *roc_nix);
328 void nix_tm_conf_fini(struct roc_nix *roc_nix);
329 int nix_tm_leaf_data_get(struct nix *nix, uint16_t sq, uint32_t *rr_quantum,
331 int nix_tm_sq_flush_pre(struct roc_nix_sq *sq);
332 int nix_tm_sq_flush_post(struct roc_nix_sq *sq);
333 int nix_tm_smq_xoff(struct nix *nix, struct nix_tm_node *node, bool enable);
334 int nix_tm_prepare_default_tree(struct roc_nix *roc_nix);
335 int nix_tm_node_add(struct roc_nix *roc_nix, struct nix_tm_node *node);
336 int nix_tm_node_delete(struct roc_nix *roc_nix, uint32_t node_id,
337 enum roc_nix_tm_tree tree, bool free);
338 int nix_tm_free_node_resource(struct nix *nix, struct nix_tm_node *node);
339 int nix_tm_free_resources(struct roc_nix *roc_nix, uint32_t tree_mask,
341 int nix_tm_clear_path_xoff(struct nix *nix, struct nix_tm_node *node);
342 void nix_tm_clear_shaper_profiles(struct nix *nix);
343 int nix_tm_alloc_txschq(struct nix *nix, enum roc_nix_tm_tree tree);
344 int nix_tm_assign_resources(struct nix *nix, enum roc_nix_tm_tree tree);
345 int nix_tm_release_resources(struct nix *nix, uint8_t hw_lvl, bool contig,
347 void nix_tm_copy_rsp_to_nix(struct nix *nix, struct nix_txsch_alloc_rsp *rsp);
349 int nix_tm_txsch_reg_config(struct nix *nix, enum roc_nix_tm_tree tree);
350 int nix_tm_update_parent_info(struct nix *nix, enum roc_nix_tm_tree tree);
351 int nix_tm_sq_sched_conf(struct nix *nix, struct nix_tm_node *node,
352 bool rr_quantum_only);
357 uint16_t nix_tm_lvl2nix(struct nix *nix, uint32_t lvl);
358 uint16_t nix_tm_lvl2nix_tl1_root(uint32_t lvl);
359 uint16_t nix_tm_lvl2nix_tl2_root(uint32_t lvl);
360 uint16_t nix_tm_resource_avail(struct nix *nix, uint8_t hw_lvl, bool contig);
361 int nix_tm_validate_prio(struct nix *nix, uint32_t lvl, uint32_t parent_id,
362 uint32_t priority, enum roc_nix_tm_tree tree);
363 struct nix_tm_node *nix_tm_node_search(struct nix *nix, uint32_t node_id,
364 enum roc_nix_tm_tree tree);
365 struct nix_tm_shaper_profile *nix_tm_shaper_profile_search(struct nix *nix,
367 uint8_t nix_tm_sw_xoff_prep(struct nix_tm_node *node, bool enable,
368 volatile uint64_t *reg, volatile uint64_t *regval);
369 uint32_t nix_tm_check_rr(struct nix *nix, uint32_t parent_id,
370 enum roc_nix_tm_tree tree, uint32_t *rr_prio,
372 uint64_t nix_tm_shaper_profile_rate_min(struct nix *nix);
373 uint64_t nix_tm_shaper_rate_conv(uint64_t value, uint64_t *exponent_p,
374 uint64_t *mantissa_p, uint64_t *div_exp_p);
375 uint64_t nix_tm_shaper_burst_conv(uint64_t value, uint64_t *exponent_p,
376 uint64_t *mantissa_p);
377 bool nix_tm_child_res_valid(struct nix_tm_node_list *list,
378 struct nix_tm_node *parent);
379 uint16_t nix_tm_resource_estimate(struct nix *nix, uint16_t *schq_contig,
380 uint16_t *schq, enum roc_nix_tm_tree tree);
381 uint8_t nix_tm_tl1_default_prep(uint32_t schq, volatile uint64_t *reg,
382 volatile uint64_t *regval);
383 uint8_t nix_tm_topology_reg_prep(struct nix *nix, struct nix_tm_node *node,
384 volatile uint64_t *reg,
385 volatile uint64_t *regval,
386 volatile uint64_t *regval_mask);
387 uint8_t nix_tm_sched_reg_prep(struct nix *nix, struct nix_tm_node *node,
388 volatile uint64_t *reg,
389 volatile uint64_t *regval);
390 uint8_t nix_tm_shaper_reg_prep(struct nix_tm_node *node,
391 struct nix_tm_shaper_profile *profile,
392 volatile uint64_t *reg,
393 volatile uint64_t *regval);
394 struct nix_tm_node *nix_tm_node_alloc(void);
395 void nix_tm_node_free(struct nix_tm_node *node);
396 struct nix_tm_shaper_profile *nix_tm_shaper_profile_alloc(void);
397 void nix_tm_shaper_profile_free(struct nix_tm_shaper_profile *profile);
399 #endif /* _ROC_NIX_PRIV_H_ */