1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
5 #ifndef _ROC_NIX_PRIV_H_
6 #define _ROC_NIX_PRIV_H_
9 #define NIX_CQ_ENTRY_SZ 128
10 #define NIX_CQ_ENTRY64_SZ 512
11 #define NIX_CQ_ALIGN ((uint16_t)512)
12 #define NIX_MAX_SQB ((uint16_t)512)
13 #define NIX_DEF_SQB ((uint16_t)16)
14 #define NIX_MIN_SQB ((uint16_t)8)
15 #define NIX_SQB_LIST_SPACE ((uint16_t)2)
16 #define NIX_SQB_LOWER_THRESH ((uint16_t)70)
18 /* Apply BP/DROP when CQ is 95% full */
19 #define NIX_CQ_THRESH_LEVEL (5 * 256 / 100)
21 /* IRQ triggered when NIX_LF_CINTX_CNT[QCOUNT] crosses this value */
22 #define CQ_CQE_THRESH_DEFAULT 0x1ULL
23 #define CQ_TIMER_THRESH_DEFAULT 0xAULL /* ~1usec i.e (0xA * 100nsec) */
24 #define CQ_TIMER_THRESH_MAX 255
32 uint16_t reta[ROC_NIX_RSS_GRPS][ROC_NIX_RSS_RETA_MAX];
33 enum roc_nix_rss_reta_sz reta_sz;
34 struct plt_pci_device *pci_dev;
35 uint16_t bpid[NIX_MAX_CHAN];
36 struct nix_qint *qints_mem;
37 struct nix_qint *cints_mem;
38 uint8_t configured_qints;
39 uint8_t configured_cints;
40 struct roc_nix_sq **sqs;
41 uint16_t vwqe_interval;
42 uint16_t tx_chan_base;
43 uint16_t rx_chan_base;
44 uint16_t nb_rx_queues;
45 uint16_t nb_tx_queues;
46 uint8_t lso_tsov6_idx;
47 uint8_t lso_tsov4_idx;
59 /* Without FCS, with L2 overhead */
74 } __plt_cache_aligned;
77 NIX_ERR_PARAM = -2048,
79 NIX_ERR_INVALID_RANGE,
82 NIX_ERR_QUEUE_INVALID_RANGE,
83 NIX_ERR_AQ_READ_FAILED,
84 NIX_ERR_AQ_WRITE_FAILED,
89 nix_q_size_16, /* 16 entries */
90 nix_q_size_64, /* 64 entries */
97 nix_q_size_1M, /* Million entries */
101 static inline struct nix *
102 roc_nix_to_nix_priv(struct roc_nix *roc_nix)
104 return (struct nix *)&roc_nix->reserved[0];
107 static inline struct roc_nix *
108 nix_priv_to_roc_nix(struct nix *nix)
110 return (struct roc_nix *)((char *)nix -
111 offsetof(struct roc_nix, reserved));
115 int nix_register_irqs(struct nix *nix);
116 void nix_unregister_irqs(struct nix *nix);
118 #endif /* _ROC_NIX_PRIV_H_ */