1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
5 #ifndef _ROC_NIX_PRIV_H_
6 #define _ROC_NIX_PRIV_H_
9 #define NIX_CQ_ENTRY_SZ 128
10 #define NIX_CQ_ENTRY64_SZ 512
11 #define NIX_CQ_ALIGN ((uint16_t)512)
12 #define NIX_MAX_SQB ((uint16_t)512)
13 #define NIX_DEF_SQB ((uint16_t)16)
14 #define NIX_MIN_SQB ((uint16_t)8)
15 #define NIX_SQB_LIST_SPACE ((uint16_t)2)
16 #define NIX_SQB_LOWER_THRESH ((uint16_t)70)
18 /* Apply BP/DROP when CQ is 95% full */
19 #define NIX_CQ_THRESH_LEVEL (5 * 256 / 100)
21 /* IRQ triggered when NIX_LF_CINTX_CNT[QCOUNT] crosses this value */
22 #define CQ_CQE_THRESH_DEFAULT 0x1ULL
23 #define CQ_TIMER_THRESH_DEFAULT 0xAULL /* ~1usec i.e (0xA * 100nsec) */
24 #define CQ_TIMER_THRESH_MAX 255
32 #define NIX_TM_MAX_HW_TXSCHQ 512
33 #define NIX_TM_HW_ID_INVALID UINT32_MAX
36 #define NIX_TM_HIERARCHY_ENA BIT_ULL(0)
37 #define NIX_TM_TL1_NO_SP BIT_ULL(1)
38 #define NIX_TM_TL1_ACCESS BIT_ULL(2)
41 /** Token bucket rate (bytes per second) */
44 /** Token bucket size (bytes), a.k.a. max burst size */
49 TAILQ_ENTRY(nix_tm_node) node;
52 enum roc_nix_tm_tree tree;
58 uint32_t shaper_profile_id;
59 void (*free_fn)(void *node);
67 uint32_t parent_hw_id;
69 #define NIX_TM_NODE_HWRES BIT_ULL(0)
70 #define NIX_TM_NODE_ENABLED BIT_ULL(1)
71 /* Shaper algorithm for RED state @NIX_REDALG_E */
72 uint32_t red_algo : 2;
73 uint32_t pkt_mode : 1;
74 uint32_t pkt_mode_set : 1;
77 struct nix_tm_node *parent;
79 /* Non-leaf node sp count */
80 uint32_t n_sp_priorities;
87 struct nix_tm_shaper_profile {
88 TAILQ_ENTRY(nix_tm_shaper_profile) shaper;
89 struct nix_tm_tb commit;
90 struct nix_tm_tb peak;
94 void (*free_fn)(void *profile);
99 TAILQ_HEAD(nix_tm_node_list, nix_tm_node);
100 TAILQ_HEAD(nix_tm_shaper_profile_list, nix_tm_shaper_profile);
103 uint16_t reta[ROC_NIX_RSS_GRPS][ROC_NIX_RSS_RETA_MAX];
104 enum roc_nix_rss_reta_sz reta_sz;
105 struct plt_pci_device *pci_dev;
106 uint16_t bpid[NIX_MAX_CHAN];
107 struct nix_qint *qints_mem;
108 struct nix_qint *cints_mem;
109 uint8_t configured_qints;
110 uint8_t configured_cints;
111 struct roc_nix_sq **sqs;
112 uint16_t vwqe_interval;
113 uint16_t tx_chan_base;
114 uint16_t rx_chan_base;
115 uint16_t nb_rx_queues;
116 uint16_t nb_tx_queues;
117 uint8_t lso_tsov6_idx;
118 uint8_t lso_tsov4_idx;
119 uint8_t lso_udp_tun_idx[ROC_NIX_LSO_TUN_MAX];
120 uint8_t lso_tun_idx[ROC_NIX_LSO_TUN_MAX];
132 /* Without FCS, with L2 overhead */
147 /* Traffic manager info */
149 /* Contiguous resources per lvl */
150 struct plt_bitmap *schq_contig_bmp[NIX_TXSCH_LVL_CNT];
151 /* Dis-contiguous resources per lvl */
152 struct plt_bitmap *schq_bmp[NIX_TXSCH_LVL_CNT];
155 struct nix_tm_shaper_profile_list shaper_profile_list;
156 struct nix_tm_node_list trees[ROC_NIX_TM_TREE_MAX];
157 enum roc_nix_tm_tree tm_tree;
158 uint64_t tm_rate_min;
159 uint16_t tm_root_lvl;
161 uint16_t tm_link_cfg_lvl;
162 uint16_t contig_rsvd[NIX_TXSCH_LVL_CNT];
163 uint16_t discontig_rsvd[NIX_TXSCH_LVL_CNT];
164 } __plt_cache_aligned;
166 enum nix_err_status {
167 NIX_ERR_PARAM = -2048,
169 NIX_ERR_INVALID_RANGE,
172 NIX_ERR_QUEUE_INVALID_RANGE,
173 NIX_ERR_AQ_READ_FAILED,
174 NIX_ERR_AQ_WRITE_FAILED,
175 NIX_ERR_TM_LEAF_NODE_GET,
176 NIX_ERR_TM_INVALID_LVL,
177 NIX_ERR_TM_INVALID_PRIO,
178 NIX_ERR_TM_INVALID_PARENT,
179 NIX_ERR_TM_NODE_EXISTS,
180 NIX_ERR_TM_INVALID_NODE,
181 NIX_ERR_TM_INVALID_SHAPER_PROFILE,
182 NIX_ERR_TM_PKT_MODE_MISMATCH,
183 NIX_ERR_TM_WEIGHT_EXCEED,
184 NIX_ERR_TM_CHILD_EXISTS,
185 NIX_ERR_TM_INVALID_PEAK_SZ,
186 NIX_ERR_TM_INVALID_PEAK_RATE,
187 NIX_ERR_TM_INVALID_COMMIT_SZ,
188 NIX_ERR_TM_INVALID_COMMIT_RATE,
189 NIX_ERR_TM_SHAPER_PROFILE_IN_USE,
190 NIX_ERR_TM_SHAPER_PROFILE_EXISTS,
191 NIX_ERR_TM_SHAPER_PKT_LEN_ADJUST,
192 NIX_ERR_TM_INVALID_TREE,
193 NIX_ERR_TM_PARENT_PRIO_UPDATE,
194 NIX_ERR_TM_PRIO_EXCEEDED,
195 NIX_ERR_TM_PRIO_ORDER,
196 NIX_ERR_TM_MULTIPLE_RR_GROUPS,
197 NIX_ERR_TM_SQ_UPDATE_FAIL,
202 nix_q_size_16, /* 16 entries */
203 nix_q_size_64, /* 64 entries */
210 nix_q_size_1M, /* Million entries */
214 static inline struct nix *
215 roc_nix_to_nix_priv(struct roc_nix *roc_nix)
217 return (struct nix *)&roc_nix->reserved[0];
220 static inline struct roc_nix *
221 nix_priv_to_roc_nix(struct nix *nix)
223 return (struct roc_nix *)((char *)nix -
224 offsetof(struct roc_nix, reserved));
228 int nix_register_irqs(struct nix *nix);
229 void nix_unregister_irqs(struct nix *nix);
232 #define NIX_TM_TREE_MASK_ALL \
233 (BIT(ROC_NIX_TM_DEFAULT) | BIT(ROC_NIX_TM_RLIMIT) | \
234 BIT(ROC_NIX_TM_USER))
237 * NIX_TM_DFLT_RR_WT * NIX_TM_RR_QUANTUM_MAX / ROC_NIX_TM_MAX_SCHED_WT
239 #define NIX_TM_DFLT_RR_WT 71
241 /* Default TL1 priority and Quantum from AF */
242 #define NIX_TM_TL1_DFLT_RR_QTM ((1 << 24) - 1)
243 #define NIX_TM_TL1_DFLT_RR_PRIO 1
245 struct nix_tm_shaper_data {
246 uint64_t burst_exponent;
247 uint64_t burst_mantissa;
255 static inline uint64_t
256 nix_tm_weight_to_rr_quantum(uint64_t weight)
258 uint64_t max = (roc_model_is_cn9k() ? NIX_CN9K_TM_RR_QUANTUM_MAX :
259 NIX_TM_RR_QUANTUM_MAX);
261 weight &= (uint64_t)ROC_NIX_TM_MAX_SCHED_WT;
262 return (weight * max) / ROC_NIX_TM_MAX_SCHED_WT;
266 nix_tm_have_tl1_access(struct nix *nix)
268 return !!(nix->tm_flags & NIX_TM_TL1_ACCESS);
272 nix_tm_is_leaf(struct nix *nix, int lvl)
274 if (nix_tm_have_tl1_access(nix))
275 return (lvl == ROC_TM_LVL_QUEUE);
276 return (lvl == ROC_TM_LVL_SCH4);
279 static inline struct nix_tm_node_list *
280 nix_tm_node_list(struct nix *nix, enum roc_nix_tm_tree tree)
282 return &nix->trees[tree];
285 static inline const char *
286 nix_tm_hwlvl2str(uint32_t hw_lvl)
289 case NIX_TXSCH_LVL_MDQ:
291 case NIX_TXSCH_LVL_TL4:
293 case NIX_TXSCH_LVL_TL3:
295 case NIX_TXSCH_LVL_TL2:
297 case NIX_TXSCH_LVL_TL1:
306 static inline const char *
307 nix_tm_tree2str(enum roc_nix_tm_tree tree)
309 if (tree == ROC_NIX_TM_DEFAULT)
310 return "Default Tree";
311 else if (tree == ROC_NIX_TM_RLIMIT)
312 return "Rate Limit Tree";
313 else if (tree == ROC_NIX_TM_USER)
322 int nix_tm_conf_init(struct roc_nix *roc_nix);
323 void nix_tm_conf_fini(struct roc_nix *roc_nix);
324 int nix_tm_leaf_data_get(struct nix *nix, uint16_t sq, uint32_t *rr_quantum,
326 int nix_tm_sq_flush_pre(struct roc_nix_sq *sq);
327 int nix_tm_sq_flush_post(struct roc_nix_sq *sq);
328 int nix_tm_smq_xoff(struct nix *nix, struct nix_tm_node *node, bool enable);
329 int nix_tm_node_add(struct roc_nix *roc_nix, struct nix_tm_node *node);
330 int nix_tm_node_delete(struct roc_nix *roc_nix, uint32_t node_id,
331 enum roc_nix_tm_tree tree, bool free);
332 int nix_tm_free_node_resource(struct nix *nix, struct nix_tm_node *node);
333 int nix_tm_clear_path_xoff(struct nix *nix, struct nix_tm_node *node);
338 uint16_t nix_tm_lvl2nix(struct nix *nix, uint32_t lvl);
339 uint16_t nix_tm_lvl2nix_tl1_root(uint32_t lvl);
340 uint16_t nix_tm_lvl2nix_tl2_root(uint32_t lvl);
341 uint16_t nix_tm_resource_avail(struct nix *nix, uint8_t hw_lvl, bool contig);
342 int nix_tm_validate_prio(struct nix *nix, uint32_t lvl, uint32_t parent_id,
343 uint32_t priority, enum roc_nix_tm_tree tree);
344 struct nix_tm_node *nix_tm_node_search(struct nix *nix, uint32_t node_id,
345 enum roc_nix_tm_tree tree);
346 struct nix_tm_shaper_profile *nix_tm_shaper_profile_search(struct nix *nix,
348 uint8_t nix_tm_sw_xoff_prep(struct nix_tm_node *node, bool enable,
349 volatile uint64_t *reg, volatile uint64_t *regval);
350 struct nix_tm_node *nix_tm_node_alloc(void);
351 void nix_tm_node_free(struct nix_tm_node *node);
353 #endif /* _ROC_NIX_PRIV_H_ */