1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
10 static inline uint32_t
11 nix_qsize_to_val(enum nix_q_size qsize)
13 return (16UL << (qsize * 2));
16 static inline enum nix_q_size
17 nix_qsize_clampup(uint32_t val)
19 int i = nix_q_size_16;
21 for (; i < nix_q_size_max; i++)
22 if (val <= nix_qsize_to_val(i))
25 if (i >= nix_q_size_max)
26 i = nix_q_size_max - 1;
32 nix_rq_vwqe_flush(struct roc_nix_rq *rq, uint16_t vwqe_interval)
36 if (!roc_model_is_cn10k())
38 /* Due to HW errata writes to VWQE_FLUSH might hang, so instead
39 * wait for max vwqe timeout interval.
42 wait_ns = rq->vwqe_wait_tmo * (vwqe_interval + 1) * 100;
43 plt_delay_us((wait_ns / 1E3) + 1);
48 nix_rq_ena_dis(struct dev *dev, struct roc_nix_rq *rq, bool enable)
50 struct mbox *mbox = dev->mbox;
52 /* Pkts will be dropped silently if RQ is disabled */
53 if (roc_model_is_cn9k()) {
54 struct nix_aq_enq_req *aq;
56 aq = mbox_alloc_msg_nix_aq_enq(mbox);
61 aq->ctype = NIX_AQ_CTYPE_RQ;
62 aq->op = NIX_AQ_INSTOP_WRITE;
65 aq->rq_mask.ena = ~(aq->rq_mask.ena);
67 struct nix_cn10k_aq_enq_req *aq;
69 aq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);
74 aq->ctype = NIX_AQ_CTYPE_RQ;
75 aq->op = NIX_AQ_INSTOP_WRITE;
78 aq->rq_mask.ena = ~(aq->rq_mask.ena);
81 return mbox_process(mbox);
85 roc_nix_rq_ena_dis(struct roc_nix_rq *rq, bool enable)
87 struct nix *nix = roc_nix_to_nix_priv(rq->roc_nix);
90 rc = nix_rq_ena_dis(&nix->dev, rq, enable);
91 nix_rq_vwqe_flush(rq, nix->vwqe_interval);
97 nix_rq_cn9k_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints,
100 struct mbox *mbox = dev->mbox;
101 struct nix_aq_enq_req *aq;
103 aq = mbox_alloc_msg_nix_aq_enq(mbox);
108 aq->ctype = NIX_AQ_CTYPE_RQ;
109 aq->op = cfg ? NIX_AQ_INSTOP_WRITE : NIX_AQ_INSTOP_INIT;
114 aq->rq.sso_tt = rq->tt;
115 aq->rq.sso_grp = rq->hwgrp;
117 aq->rq.wqe_skip = rq->wqe_skip;
118 aq->rq.wqe_caching = 1;
120 aq->rq.good_utag = rq->tag_mask >> 24;
121 aq->rq.bad_utag = rq->tag_mask >> 24;
122 aq->rq.ltag = rq->tag_mask & BITMASK_ULL(24, 0);
126 aq->rq.good_utag = rq->tag_mask >> 24;
127 aq->rq.bad_utag = rq->tag_mask >> 24;
128 aq->rq.ltag = rq->tag_mask & BITMASK_ULL(24, 0);
133 aq->rq.ipsech_ena = 1;
136 aq->rq.lpb_aura = roc_npa_aura_handle_to_aura(rq->aura_handle);
138 /* Sizes must be aligned to 8 bytes */
139 if (rq->first_skip & 0x7 || rq->later_skip & 0x7 || rq->lpb_size & 0x7)
142 /* Expressed in number of dwords */
143 aq->rq.first_skip = rq->first_skip / 8;
144 aq->rq.later_skip = rq->later_skip / 8;
145 aq->rq.flow_tagw = rq->flow_tag_width; /* 32-bits */
146 aq->rq.lpb_sizem1 = rq->lpb_size / 8;
147 aq->rq.lpb_sizem1 -= 1; /* Expressed in size minus one */
149 aq->rq.pb_caching = 0x2; /* First cache aligned block to LLC */
150 aq->rq.xqe_imm_size = 0; /* No pkt data copy to CQE */
151 aq->rq.rq_int_ena = 0;
152 /* Many to one reduction */
153 aq->rq.qint_idx = rq->qid % qints;
154 aq->rq.xqe_drop_ena = 1;
156 /* If RED enabled, then fill enable for all cases */
157 if (rq->red_pass && (rq->red_pass >= rq->red_drop)) {
158 aq->rq.spb_pool_pass = rq->spb_red_pass;
159 aq->rq.lpb_pool_pass = rq->red_pass;
161 aq->rq.spb_pool_drop = rq->spb_red_drop;
162 aq->rq.lpb_pool_drop = rq->red_drop;
168 aq->rq_mask.sso_ena = ~aq->rq_mask.sso_ena;
169 aq->rq_mask.sso_tt = ~aq->rq_mask.sso_tt;
170 aq->rq_mask.sso_grp = ~aq->rq_mask.sso_grp;
171 aq->rq_mask.ena_wqwd = ~aq->rq_mask.ena_wqwd;
172 aq->rq_mask.wqe_skip = ~aq->rq_mask.wqe_skip;
173 aq->rq_mask.wqe_caching = ~aq->rq_mask.wqe_caching;
174 aq->rq_mask.good_utag = ~aq->rq_mask.good_utag;
175 aq->rq_mask.bad_utag = ~aq->rq_mask.bad_utag;
176 aq->rq_mask.ltag = ~aq->rq_mask.ltag;
179 aq->rq_mask.sso_ena = ~aq->rq_mask.sso_ena;
180 aq->rq_mask.good_utag = ~aq->rq_mask.good_utag;
181 aq->rq_mask.bad_utag = ~aq->rq_mask.bad_utag;
182 aq->rq_mask.ltag = ~aq->rq_mask.ltag;
183 aq->rq_mask.cq = ~aq->rq_mask.cq;
187 aq->rq_mask.ipsech_ena = ~aq->rq_mask.ipsech_ena;
189 aq->rq_mask.spb_ena = ~aq->rq_mask.spb_ena;
190 aq->rq_mask.lpb_aura = ~aq->rq_mask.lpb_aura;
191 aq->rq_mask.first_skip = ~aq->rq_mask.first_skip;
192 aq->rq_mask.later_skip = ~aq->rq_mask.later_skip;
193 aq->rq_mask.flow_tagw = ~aq->rq_mask.flow_tagw;
194 aq->rq_mask.lpb_sizem1 = ~aq->rq_mask.lpb_sizem1;
195 aq->rq_mask.ena = ~aq->rq_mask.ena;
196 aq->rq_mask.pb_caching = ~aq->rq_mask.pb_caching;
197 aq->rq_mask.xqe_imm_size = ~aq->rq_mask.xqe_imm_size;
198 aq->rq_mask.rq_int_ena = ~aq->rq_mask.rq_int_ena;
199 aq->rq_mask.qint_idx = ~aq->rq_mask.qint_idx;
200 aq->rq_mask.xqe_drop_ena = ~aq->rq_mask.xqe_drop_ena;
202 if (rq->red_pass && (rq->red_pass >= rq->red_drop)) {
203 aq->rq_mask.spb_pool_pass = ~aq->rq_mask.spb_pool_pass;
204 aq->rq_mask.lpb_pool_pass = ~aq->rq_mask.lpb_pool_pass;
206 aq->rq_mask.spb_pool_drop = ~aq->rq_mask.spb_pool_drop;
207 aq->rq_mask.lpb_pool_drop = ~aq->rq_mask.lpb_pool_drop;
215 nix_rq_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints, bool cfg,
218 struct nix_cn10k_aq_enq_req *aq;
219 struct mbox *mbox = dev->mbox;
221 aq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);
226 aq->ctype = NIX_AQ_CTYPE_RQ;
227 aq->op = cfg ? NIX_AQ_INSTOP_WRITE : NIX_AQ_INSTOP_INIT;
232 aq->rq.sso_tt = rq->tt;
233 aq->rq.sso_grp = rq->hwgrp;
235 aq->rq.wqe_skip = rq->wqe_skip;
236 aq->rq.wqe_caching = 1;
238 aq->rq.good_utag = rq->tag_mask >> 24;
239 aq->rq.bad_utag = rq->tag_mask >> 24;
240 aq->rq.ltag = rq->tag_mask & BITMASK_ULL(24, 0);
243 aq->rq.vwqe_ena = true;
244 aq->rq.vwqe_skip = rq->vwqe_first_skip;
245 /* Maximal Vector size is (2^(MAX_VSIZE_EXP+2)) */
246 aq->rq.max_vsize_exp = rq->vwqe_max_sz_exp - 2;
247 aq->rq.vtime_wait = rq->vwqe_wait_tmo;
248 aq->rq.wqe_aura = rq->vwqe_aura_handle;
253 aq->rq.good_utag = rq->tag_mask >> 24;
254 aq->rq.bad_utag = rq->tag_mask >> 24;
255 aq->rq.ltag = rq->tag_mask & BITMASK_ULL(24, 0);
259 if (rq->ipsech_ena) {
260 aq->rq.ipsech_ena = 1;
261 aq->rq.ipsecd_drop_en = 1;
264 aq->rq.lpb_aura = roc_npa_aura_handle_to_aura(rq->aura_handle);
266 /* Sizes must be aligned to 8 bytes */
267 if (rq->first_skip & 0x7 || rq->later_skip & 0x7 || rq->lpb_size & 0x7)
270 /* Expressed in number of dwords */
271 aq->rq.first_skip = rq->first_skip / 8;
272 aq->rq.later_skip = rq->later_skip / 8;
273 aq->rq.flow_tagw = rq->flow_tag_width; /* 32-bits */
274 aq->rq.lpb_sizem1 = rq->lpb_size / 8;
275 aq->rq.lpb_sizem1 -= 1; /* Expressed in size minus one */
283 roc_npa_aura_handle_to_aura(rq->spb_aura_handle);
285 if (rq->spb_size & 0x7 ||
286 rq->spb_size > NIX_RQ_CN10K_SPB_MAX_SIZE)
289 spb_sizem1 = rq->spb_size / 8; /* Expressed in no. of dwords */
290 spb_sizem1 -= 1; /* Expressed in size minus one */
291 aq->rq.spb_sizem1 = spb_sizem1 & 0x3F;
292 aq->rq.spb_high_sizem1 = (spb_sizem1 >> 6) & 0x7;
297 aq->rq.pb_caching = 0x2; /* First cache aligned block to LLC */
298 aq->rq.xqe_imm_size = 0; /* No pkt data copy to CQE */
299 aq->rq.rq_int_ena = 0;
300 /* Many to one reduction */
301 aq->rq.qint_idx = rq->qid % qints;
302 aq->rq.xqe_drop_ena = 0;
303 aq->rq.lpb_drop_ena = rq->lpb_drop_ena;
304 aq->rq.spb_drop_ena = rq->spb_drop_ena;
306 /* If RED enabled, then fill enable for all cases */
307 if (rq->red_pass && (rq->red_pass >= rq->red_drop)) {
308 aq->rq.spb_pool_pass = rq->spb_red_pass;
309 aq->rq.lpb_pool_pass = rq->red_pass;
310 aq->rq.wqe_pool_pass = rq->red_pass;
311 aq->rq.xqe_pass = rq->red_pass;
313 aq->rq.spb_pool_drop = rq->spb_red_drop;
314 aq->rq.lpb_pool_drop = rq->red_drop;
315 aq->rq.wqe_pool_drop = rq->red_drop;
316 aq->rq.xqe_drop = rq->red_drop;
322 aq->rq_mask.sso_ena = ~aq->rq_mask.sso_ena;
323 aq->rq_mask.sso_tt = ~aq->rq_mask.sso_tt;
324 aq->rq_mask.sso_grp = ~aq->rq_mask.sso_grp;
325 aq->rq_mask.ena_wqwd = ~aq->rq_mask.ena_wqwd;
326 aq->rq_mask.wqe_skip = ~aq->rq_mask.wqe_skip;
327 aq->rq_mask.wqe_caching = ~aq->rq_mask.wqe_caching;
328 aq->rq_mask.good_utag = ~aq->rq_mask.good_utag;
329 aq->rq_mask.bad_utag = ~aq->rq_mask.bad_utag;
330 aq->rq_mask.ltag = ~aq->rq_mask.ltag;
332 aq->rq_mask.vwqe_ena = ~aq->rq_mask.vwqe_ena;
333 aq->rq_mask.vwqe_skip = ~aq->rq_mask.vwqe_skip;
334 aq->rq_mask.max_vsize_exp =
335 ~aq->rq_mask.max_vsize_exp;
336 aq->rq_mask.vtime_wait =
337 ~aq->rq_mask.vtime_wait;
338 aq->rq_mask.wqe_aura = ~aq->rq_mask.wqe_aura;
342 aq->rq_mask.sso_ena = ~aq->rq_mask.sso_ena;
343 aq->rq_mask.good_utag = ~aq->rq_mask.good_utag;
344 aq->rq_mask.bad_utag = ~aq->rq_mask.bad_utag;
345 aq->rq_mask.ltag = ~aq->rq_mask.ltag;
346 aq->rq_mask.cq = ~aq->rq_mask.cq;
350 aq->rq_mask.ipsech_ena = ~aq->rq_mask.ipsech_ena;
353 aq->rq_mask.spb_aura = ~aq->rq_mask.spb_aura;
354 aq->rq_mask.spb_sizem1 = ~aq->rq_mask.spb_sizem1;
355 aq->rq_mask.spb_high_sizem1 =
356 ~aq->rq_mask.spb_high_sizem1;
359 aq->rq_mask.spb_ena = ~aq->rq_mask.spb_ena;
360 aq->rq_mask.lpb_aura = ~aq->rq_mask.lpb_aura;
361 aq->rq_mask.first_skip = ~aq->rq_mask.first_skip;
362 aq->rq_mask.later_skip = ~aq->rq_mask.later_skip;
363 aq->rq_mask.flow_tagw = ~aq->rq_mask.flow_tagw;
364 aq->rq_mask.lpb_sizem1 = ~aq->rq_mask.lpb_sizem1;
365 aq->rq_mask.ena = ~aq->rq_mask.ena;
366 aq->rq_mask.pb_caching = ~aq->rq_mask.pb_caching;
367 aq->rq_mask.xqe_imm_size = ~aq->rq_mask.xqe_imm_size;
368 aq->rq_mask.rq_int_ena = ~aq->rq_mask.rq_int_ena;
369 aq->rq_mask.qint_idx = ~aq->rq_mask.qint_idx;
370 aq->rq_mask.xqe_drop_ena = ~aq->rq_mask.xqe_drop_ena;
371 aq->rq_mask.lpb_drop_ena = ~aq->rq_mask.lpb_drop_ena;
372 aq->rq_mask.spb_drop_ena = ~aq->rq_mask.spb_drop_ena;
374 if (rq->red_pass && (rq->red_pass >= rq->red_drop)) {
375 aq->rq_mask.spb_pool_pass = ~aq->rq_mask.spb_pool_pass;
376 aq->rq_mask.lpb_pool_pass = ~aq->rq_mask.lpb_pool_pass;
377 aq->rq_mask.wqe_pool_pass = ~aq->rq_mask.wqe_pool_pass;
378 aq->rq_mask.xqe_pass = ~aq->rq_mask.xqe_pass;
380 aq->rq_mask.spb_pool_drop = ~aq->rq_mask.spb_pool_drop;
381 aq->rq_mask.lpb_pool_drop = ~aq->rq_mask.lpb_pool_drop;
382 aq->rq_mask.wqe_pool_drop = ~aq->rq_mask.wqe_pool_drop;
383 aq->rq_mask.xqe_drop = ~aq->rq_mask.xqe_drop;
391 roc_nix_rq_init(struct roc_nix *roc_nix, struct roc_nix_rq *rq, bool ena)
393 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
394 struct mbox *mbox = (&nix->dev)->mbox;
395 bool is_cn9k = roc_model_is_cn9k();
396 struct dev *dev = &nix->dev;
399 if (roc_nix == NULL || rq == NULL)
400 return NIX_ERR_PARAM;
402 if (rq->qid >= nix->nb_rx_queues)
403 return NIX_ERR_QUEUE_INVALID_RANGE;
405 rq->roc_nix = roc_nix;
408 rc = nix_rq_cn9k_cfg(dev, rq, nix->qints, false, ena);
410 rc = nix_rq_cfg(dev, rq, nix->qints, false, ena);
415 rc = mbox_process(mbox);
419 return nix_tel_node_add_rq(rq);
423 roc_nix_rq_modify(struct roc_nix *roc_nix, struct roc_nix_rq *rq, bool ena)
425 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
426 struct mbox *mbox = (&nix->dev)->mbox;
427 bool is_cn9k = roc_model_is_cn9k();
428 struct dev *dev = &nix->dev;
431 if (roc_nix == NULL || rq == NULL)
432 return NIX_ERR_PARAM;
434 if (rq->qid >= nix->nb_rx_queues)
435 return NIX_ERR_QUEUE_INVALID_RANGE;
437 rq->roc_nix = roc_nix;
440 rc = nix_rq_cn9k_cfg(dev, rq, nix->qints, true, ena);
442 rc = nix_rq_cfg(dev, rq, nix->qints, true, ena);
447 rc = mbox_process(mbox);
451 return nix_tel_node_add_rq(rq);
455 roc_nix_rq_fini(struct roc_nix_rq *rq)
457 /* Disabling RQ is sufficient */
458 return roc_nix_rq_ena_dis(rq, false);
462 roc_nix_cq_init(struct roc_nix *roc_nix, struct roc_nix_cq *cq)
464 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
465 struct mbox *mbox = (&nix->dev)->mbox;
466 volatile struct nix_cq_ctx_s *cq_ctx;
467 enum nix_q_size qsize;
472 return NIX_ERR_PARAM;
474 if (cq->qid >= nix->nb_rx_queues)
475 return NIX_ERR_QUEUE_INVALID_RANGE;
477 qsize = nix_qsize_clampup(cq->nb_desc);
478 cq->nb_desc = nix_qsize_to_val(qsize);
479 cq->qmask = cq->nb_desc - 1;
480 cq->door = nix->base + NIX_LF_CQ_OP_DOOR;
481 cq->status = (int64_t *)(nix->base + NIX_LF_CQ_OP_STATUS);
482 cq->wdata = (uint64_t)cq->qid << 32;
483 cq->roc_nix = roc_nix;
486 desc_sz = cq->nb_desc * NIX_CQ_ENTRY_SZ;
487 cq->desc_base = plt_zmalloc(desc_sz, NIX_CQ_ALIGN);
488 if (cq->desc_base == NULL) {
493 if (roc_model_is_cn9k()) {
494 struct nix_aq_enq_req *aq;
496 aq = mbox_alloc_msg_nix_aq_enq(mbox);
501 aq->ctype = NIX_AQ_CTYPE_CQ;
502 aq->op = NIX_AQ_INSTOP_INIT;
505 struct nix_cn10k_aq_enq_req *aq;
507 aq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);
512 aq->ctype = NIX_AQ_CTYPE_CQ;
513 aq->op = NIX_AQ_INSTOP_INIT;
519 cq_ctx->qsize = qsize;
520 cq_ctx->base = (uint64_t)cq->desc_base;
521 cq_ctx->avg_level = 0xff;
522 cq_ctx->cq_err_int_ena = BIT(NIX_CQERRINT_CQE_FAULT);
523 cq_ctx->cq_err_int_ena |= BIT(NIX_CQERRINT_DOOR_ERR);
525 /* Many to one reduction */
526 cq_ctx->qint_idx = cq->qid % nix->qints;
527 /* Map CQ0 [RQ0] to CINT0 and so on till max 64 irqs */
528 cq_ctx->cint_idx = cq->qid;
530 if (roc_errata_nix_has_cq_min_size_4k()) {
531 const float rx_cq_skid = NIX_CQ_FULL_ERRATA_SKID;
532 uint16_t min_rx_drop;
534 min_rx_drop = ceil(rx_cq_skid / (float)cq->nb_desc);
535 cq_ctx->drop = min_rx_drop;
536 cq_ctx->drop_ena = 1;
537 cq->drop_thresh = min_rx_drop;
539 cq->drop_thresh = NIX_CQ_THRESH_LEVEL;
540 /* Drop processing or red drop cannot be enabled due to
541 * due to packets coming for second pass from CPT.
543 if (!roc_nix_inl_inb_is_enabled(roc_nix)) {
544 cq_ctx->drop = cq->drop_thresh;
545 cq_ctx->drop_ena = 1;
549 /* TX pause frames enable flow ctrl on RX side */
551 /* Single BPID is allocated for all rx channels for now */
552 cq_ctx->bpid = nix->bpid[0];
553 cq_ctx->bp = cq->drop_thresh;
557 rc = mbox_process(mbox);
561 return nix_tel_node_add_cq(cq);
564 plt_free(cq->desc_base);
570 roc_nix_cq_fini(struct roc_nix_cq *cq)
577 return NIX_ERR_PARAM;
579 nix = roc_nix_to_nix_priv(cq->roc_nix);
580 mbox = (&nix->dev)->mbox;
583 if (roc_model_is_cn9k()) {
584 struct nix_aq_enq_req *aq;
586 aq = mbox_alloc_msg_nix_aq_enq(mbox);
591 aq->ctype = NIX_AQ_CTYPE_CQ;
592 aq->op = NIX_AQ_INSTOP_WRITE;
595 aq->cq_mask.ena = ~aq->cq_mask.ena;
596 aq->cq_mask.bp_ena = ~aq->cq_mask.bp_ena;
598 struct nix_cn10k_aq_enq_req *aq;
600 aq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);
605 aq->ctype = NIX_AQ_CTYPE_CQ;
606 aq->op = NIX_AQ_INSTOP_WRITE;
609 aq->cq_mask.ena = ~aq->cq_mask.ena;
610 aq->cq_mask.bp_ena = ~aq->cq_mask.bp_ena;
613 rc = mbox_process(mbox);
617 plt_free(cq->desc_base);
622 sqb_pool_populate(struct roc_nix *roc_nix, struct roc_nix_sq *sq)
624 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
625 uint16_t sqes_per_sqb, count, nb_sqb_bufs;
626 struct npa_pool_s pool;
627 struct npa_aura_s aura;
632 blk_sz = nix->sqb_size;
633 if (sq->max_sqe_sz == roc_nix_maxsqesz_w16)
634 sqes_per_sqb = (blk_sz / 8) / 16;
636 sqes_per_sqb = (blk_sz / 8) / 8;
638 sq->nb_desc = PLT_MAX(256U, sq->nb_desc);
639 nb_sqb_bufs = sq->nb_desc / sqes_per_sqb;
640 nb_sqb_bufs += NIX_SQB_LIST_SPACE;
641 /* Clamp up the SQB count */
642 nb_sqb_bufs = PLT_MIN(roc_nix->max_sqb_count,
643 (uint16_t)PLT_MAX(NIX_DEF_SQB, nb_sqb_bufs));
645 sq->nb_sqb_bufs = nb_sqb_bufs;
646 sq->sqes_per_sqb_log2 = (uint16_t)plt_log2_u32(sqes_per_sqb);
647 sq->nb_sqb_bufs_adj =
649 (PLT_ALIGN_MUL_CEIL(nb_sqb_bufs, sqes_per_sqb) / sqes_per_sqb);
650 sq->nb_sqb_bufs_adj =
651 (sq->nb_sqb_bufs_adj * NIX_SQB_LOWER_THRESH) / 100;
653 /* Explicitly set nat_align alone as by default pool is with both
654 * nat_align and buf_offset = 1 which we don't want for SQB.
656 memset(&pool, 0, sizeof(struct npa_pool_s));
659 memset(&aura, 0, sizeof(aura));
661 if (roc_model_is_cn9k() || roc_errata_npa_has_no_fc_stype_ststp())
662 aura.fc_stype = 0x0; /* STF */
664 aura.fc_stype = 0x3; /* STSTP */
665 aura.fc_addr = (uint64_t)sq->fc;
666 aura.fc_hyst_bits = 0; /* Store count on all updates */
667 rc = roc_npa_pool_create(&sq->aura_handle, blk_sz, NIX_MAX_SQB, &aura,
672 sq->sqe_mem = plt_zmalloc(blk_sz * NIX_MAX_SQB, blk_sz);
673 if (sq->sqe_mem == NULL) {
678 /* Fill the initial buffers */
679 iova = (uint64_t)sq->sqe_mem;
680 for (count = 0; count < NIX_MAX_SQB; count++) {
681 roc_npa_aura_op_free(sq->aura_handle, 0, iova);
685 if (roc_npa_aura_op_available_wait(sq->aura_handle, NIX_MAX_SQB, 0) !=
687 plt_err("Failed to free all pointers to the pool");
692 roc_npa_aura_op_range_set(sq->aura_handle, (uint64_t)sq->sqe_mem, iova);
693 roc_npa_aura_limit_modify(sq->aura_handle, sq->nb_sqb_bufs);
694 sq->aura_sqb_bufs = NIX_MAX_SQB;
698 plt_free(sq->sqe_mem);
700 roc_npa_pool_destroy(sq->aura_handle);
706 sq_cn9k_init(struct nix *nix, struct roc_nix_sq *sq, uint32_t rr_quantum,
709 struct roc_nix *roc_nix = nix_priv_to_roc_nix(nix);
710 struct mbox *mbox = (&nix->dev)->mbox;
711 struct nix_aq_enq_req *aq;
713 aq = mbox_alloc_msg_nix_aq_enq(mbox);
718 aq->ctype = NIX_AQ_CTYPE_SQ;
719 aq->op = NIX_AQ_INSTOP_INIT;
720 aq->sq.max_sqe_size = sq->max_sqe_sz;
722 aq->sq.max_sqe_size = sq->max_sqe_sz;
724 aq->sq.smq_rr_quantum = rr_quantum;
725 if (roc_nix_is_sdp(roc_nix))
726 aq->sq.default_chan =
727 nix->tx_chan_base + (sq->qid % nix->tx_chan_cnt);
729 aq->sq.default_chan = nix->tx_chan_base;
730 aq->sq.sqe_stype = NIX_STYPE_STF;
732 aq->sq.sso_ena = !!sq->sso_ena;
733 aq->sq.cq_ena = !!sq->cq_ena;
734 aq->sq.cq = sq->cqid;
735 if (aq->sq.max_sqe_size == NIX_MAXSQESZ_W8)
736 aq->sq.sqe_stype = NIX_STYPE_STP;
737 aq->sq.sqb_aura = roc_npa_aura_handle_to_aura(sq->aura_handle);
738 aq->sq.sq_int_ena = BIT(NIX_SQINT_LMT_ERR);
739 aq->sq.sq_int_ena |= BIT(NIX_SQINT_SQB_ALLOC_FAIL);
740 aq->sq.sq_int_ena |= BIT(NIX_SQINT_SEND_ERR);
741 aq->sq.sq_int_ena |= BIT(NIX_SQINT_MNQ_ERR);
743 /* Many to one reduction */
744 /* Assigning QINT 0 to all the SQs, an errata exists where NIXTX can
745 * send incorrect QINT_IDX when reporting queue interrupt (QINT). This
746 * might result in software missing the interrupt.
753 sq_cn9k_fini(struct nix *nix, struct roc_nix_sq *sq)
755 struct mbox *mbox = (&nix->dev)->mbox;
756 struct nix_aq_enq_rsp *rsp;
757 struct nix_aq_enq_req *aq;
758 uint16_t sqes_per_sqb;
762 aq = mbox_alloc_msg_nix_aq_enq(mbox);
767 aq->ctype = NIX_AQ_CTYPE_SQ;
768 aq->op = NIX_AQ_INSTOP_READ;
769 rc = mbox_process_msg(mbox, (void *)&rsp);
773 /* Check if sq is already cleaned up */
778 aq = mbox_alloc_msg_nix_aq_enq(mbox);
783 aq->ctype = NIX_AQ_CTYPE_SQ;
784 aq->op = NIX_AQ_INSTOP_WRITE;
785 aq->sq_mask.ena = ~aq->sq_mask.ena;
787 rc = mbox_process(mbox);
791 /* Read SQ and free sqb's */
792 aq = mbox_alloc_msg_nix_aq_enq(mbox);
797 aq->ctype = NIX_AQ_CTYPE_SQ;
798 aq->op = NIX_AQ_INSTOP_READ;
799 rc = mbox_process_msg(mbox, (void *)&rsp);
804 plt_err("SQ has pending SQE's");
806 count = aq->sq.sqb_count;
807 sqes_per_sqb = 1 << sq->sqes_per_sqb_log2;
808 /* Free SQB's that are used */
809 sqb_buf = (void *)rsp->sq.head_sqb;
813 next_sqb = *(void **)((uintptr_t)sqb_buf +
814 (uint32_t)((sqes_per_sqb - 1) *
816 roc_npa_aura_op_free(sq->aura_handle, 1, (uint64_t)sqb_buf);
821 /* Free next to use sqb */
822 if (rsp->sq.next_sqb)
823 roc_npa_aura_op_free(sq->aura_handle, 1, rsp->sq.next_sqb);
828 sq_init(struct nix *nix, struct roc_nix_sq *sq, uint32_t rr_quantum,
831 struct mbox *mbox = (&nix->dev)->mbox;
832 struct nix_cn10k_aq_enq_req *aq;
834 aq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);
839 aq->ctype = NIX_AQ_CTYPE_SQ;
840 aq->op = NIX_AQ_INSTOP_INIT;
841 aq->sq.max_sqe_size = sq->max_sqe_sz;
843 aq->sq.max_sqe_size = sq->max_sqe_sz;
845 aq->sq.smq_rr_weight = rr_quantum;
846 aq->sq.default_chan = nix->tx_chan_base;
847 aq->sq.sqe_stype = NIX_STYPE_STF;
849 aq->sq.sso_ena = !!sq->sso_ena;
850 aq->sq.cq_ena = !!sq->cq_ena;
851 aq->sq.cq = sq->cqid;
852 if (aq->sq.max_sqe_size == NIX_MAXSQESZ_W8)
853 aq->sq.sqe_stype = NIX_STYPE_STP;
854 aq->sq.sqb_aura = roc_npa_aura_handle_to_aura(sq->aura_handle);
855 aq->sq.sq_int_ena = BIT(NIX_SQINT_LMT_ERR);
856 aq->sq.sq_int_ena |= BIT(NIX_SQINT_SQB_ALLOC_FAIL);
857 aq->sq.sq_int_ena |= BIT(NIX_SQINT_SEND_ERR);
858 aq->sq.sq_int_ena |= BIT(NIX_SQINT_MNQ_ERR);
860 /* Assigning QINT 0 to all the SQs, an errata exists where NIXTX can
861 * send incorrect QINT_IDX when reporting queue interrupt (QINT). This
862 * might result in software missing the interrupt.
869 sq_fini(struct nix *nix, struct roc_nix_sq *sq)
871 struct mbox *mbox = (&nix->dev)->mbox;
872 struct nix_cn10k_aq_enq_rsp *rsp;
873 struct nix_cn10k_aq_enq_req *aq;
874 uint16_t sqes_per_sqb;
878 aq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);
883 aq->ctype = NIX_AQ_CTYPE_SQ;
884 aq->op = NIX_AQ_INSTOP_READ;
885 rc = mbox_process_msg(mbox, (void *)&rsp);
889 /* Check if sq is already cleaned up */
894 aq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);
899 aq->ctype = NIX_AQ_CTYPE_SQ;
900 aq->op = NIX_AQ_INSTOP_WRITE;
901 aq->sq_mask.ena = ~aq->sq_mask.ena;
903 rc = mbox_process(mbox);
907 /* Read SQ and free sqb's */
908 aq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);
913 aq->ctype = NIX_AQ_CTYPE_SQ;
914 aq->op = NIX_AQ_INSTOP_READ;
915 rc = mbox_process_msg(mbox, (void *)&rsp);
920 plt_err("SQ has pending SQE's");
922 count = aq->sq.sqb_count;
923 sqes_per_sqb = 1 << sq->sqes_per_sqb_log2;
924 /* Free SQB's that are used */
925 sqb_buf = (void *)rsp->sq.head_sqb;
929 next_sqb = *(void **)((uintptr_t)sqb_buf +
930 (uint32_t)((sqes_per_sqb - 1) *
932 roc_npa_aura_op_free(sq->aura_handle, 1, (uint64_t)sqb_buf);
937 /* Free next to use sqb */
938 if (rsp->sq.next_sqb)
939 roc_npa_aura_op_free(sq->aura_handle, 1, rsp->sq.next_sqb);
944 roc_nix_sq_init(struct roc_nix *roc_nix, struct roc_nix_sq *sq)
946 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
947 struct mbox *mbox = (&nix->dev)->mbox;
948 uint16_t qid, smq = UINT16_MAX;
949 uint32_t rr_quantum = 0;
953 return NIX_ERR_PARAM;
956 if (qid >= nix->nb_tx_queues)
957 return NIX_ERR_QUEUE_INVALID_RANGE;
959 sq->roc_nix = roc_nix;
961 * Allocate memory for flow control updates from HW.
962 * Alloc one cache line, so that fits all FC_STYPE modes.
964 sq->fc = plt_zmalloc(ROC_ALIGN, ROC_ALIGN);
965 if (sq->fc == NULL) {
970 rc = sqb_pool_populate(roc_nix, sq);
974 rc = nix_tm_leaf_data_get(nix, sq->qid, &rr_quantum, &smq);
976 rc = NIX_ERR_TM_LEAF_NODE_GET;
980 /* Init SQ context */
981 if (roc_model_is_cn9k())
982 rc = sq_cn9k_init(nix, sq, rr_quantum, smq);
984 rc = sq_init(nix, sq, rr_quantum, smq);
989 rc = mbox_process(mbox);
994 sq->io_addr = nix->base + NIX_LF_OP_SENDX(0);
995 /* Evenly distribute LMT slot for each sq */
996 if (roc_model_is_cn9k()) {
997 /* Multiple cores/SQ's can use same LMTLINE safely in CN9K */
998 sq->lmt_addr = (void *)(nix->lmt_base +
999 ((qid & RVU_CN9K_LMT_SLOT_MASK) << 12));
1002 rc = nix_tel_node_add_sq(sq);
1011 roc_nix_sq_fini(struct roc_nix_sq *sq)
1015 struct ndc_sync_op *ndc_req;
1020 return NIX_ERR_PARAM;
1022 nix = roc_nix_to_nix_priv(sq->roc_nix);
1023 mbox = (&nix->dev)->mbox;
1027 rc = nix_tm_sq_flush_pre(sq);
1029 /* Release SQ context */
1030 if (roc_model_is_cn9k())
1031 rc |= sq_cn9k_fini(roc_nix_to_nix_priv(sq->roc_nix), sq);
1033 rc |= sq_fini(roc_nix_to_nix_priv(sq->roc_nix), sq);
1035 /* Sync NDC-NIX-TX for LF */
1036 ndc_req = mbox_alloc_msg_ndc_sync_op(mbox);
1037 if (ndc_req == NULL)
1039 ndc_req->nix_lf_tx_sync = 1;
1040 if (mbox_process(mbox))
1041 rc |= NIX_ERR_NDC_SYNC;
1043 rc |= nix_tm_sq_flush_post(sq);
1045 /* Restore limit to max SQB count that the pool was created
1046 * for aura drain to succeed.
1048 roc_npa_aura_limit_modify(sq->aura_handle, NIX_MAX_SQB);
1049 rc |= roc_npa_pool_destroy(sq->aura_handle);
1051 plt_free(sq->sqe_mem);
1052 nix->sqs[qid] = NULL;
1058 roc_nix_cq_head_tail_get(struct roc_nix *roc_nix, uint16_t qid, uint32_t *head,
1061 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
1065 if (head == NULL || tail == NULL)
1068 reg = (((uint64_t)qid) << 32);
1069 addr = (int64_t *)(nix->base + NIX_LF_CQ_OP_STATUS);
1070 val = roc_atomic64_add_nosync(reg, addr);
1072 (BIT_ULL(NIX_CQ_OP_STAT_OP_ERR) | BIT_ULL(NIX_CQ_OP_STAT_CQ_ERR)))
1075 *tail = (uint32_t)(val & 0xFFFFF);
1076 *head = (uint32_t)((val >> 20) & 0xFFFFF);
1080 roc_nix_sq_head_tail_get(struct roc_nix *roc_nix, uint16_t qid, uint32_t *head,
1083 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
1084 struct roc_nix_sq *sq = nix->sqs[qid];
1085 uint16_t sqes_per_sqb, sqb_cnt;
1089 if (head == NULL || tail == NULL)
1092 reg = (((uint64_t)qid) << 32);
1093 addr = (int64_t *)(nix->base + NIX_LF_SQ_OP_STATUS);
1094 val = roc_atomic64_add_nosync(reg, addr);
1095 if (val & BIT_ULL(NIX_CQ_OP_STAT_OP_ERR)) {
1100 *tail = (uint32_t)((val >> 28) & 0x3F);
1101 *head = (uint32_t)((val >> 20) & 0x3F);
1102 sqb_cnt = (uint16_t)(val & 0xFFFF);
1104 sqes_per_sqb = 1 << sq->sqes_per_sqb_log2;
1106 /* Update tail index as per used sqb count */
1107 *tail += (sqes_per_sqb * (sqb_cnt - 1));