1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
9 bitmap_ctzll(uint64_t slab)
14 return __builtin_ctzll(slab);
18 nix_tm_clear_shaper_profiles(struct nix *nix)
20 struct nix_tm_shaper_profile *shaper_profile, *tmp;
21 struct nix_tm_shaper_profile_list *list;
23 list = &nix->shaper_profile_list;
24 PLT_TAILQ_FOREACH_SAFE(shaper_profile, list, shaper, tmp) {
25 if (shaper_profile->ref_cnt)
26 plt_warn("Shaper profile %u has non zero references",
28 TAILQ_REMOVE(&nix->shaper_profile_list, shaper_profile, shaper);
29 nix_tm_shaper_profile_free(shaper_profile);
34 nix_tm_node_reg_conf(struct nix *nix, struct nix_tm_node *node)
36 uint64_t regval_mask[MAX_REGS_PER_MBOX_MSG];
37 uint64_t regval[MAX_REGS_PER_MBOX_MSG];
38 struct nix_tm_shaper_profile *profile;
39 uint64_t reg[MAX_REGS_PER_MBOX_MSG];
40 struct mbox *mbox = (&nix->dev)->mbox;
41 struct nix_txschq_config *req;
46 memset(regval, 0, sizeof(regval));
47 memset(regval_mask, 0, sizeof(regval_mask));
49 profile = nix_tm_shaper_profile_search(nix, node->shaper_profile_id);
50 hw_lvl = node->hw_lvl;
52 /* Need this trigger to configure TL1 */
53 if (!nix_tm_have_tl1_access(nix) && hw_lvl == NIX_TXSCH_LVL_TL2) {
54 /* Prepare default conf for TL1 */
55 req = mbox_alloc_msg_nix_txschq_cfg(mbox);
56 req->lvl = NIX_TXSCH_LVL_TL1;
58 k = nix_tm_tl1_default_prep(node->parent_hw_id, req->reg,
61 rc = mbox_process(mbox);
66 /* Prepare topology config */
67 k = nix_tm_topology_reg_prep(nix, node, reg, regval, regval_mask);
69 /* Prepare schedule config */
70 k += nix_tm_sched_reg_prep(nix, node, ®[k], ®val[k]);
72 /* Prepare shaping config */
73 k += nix_tm_shaper_reg_prep(node, profile, ®[k], ®val[k]);
78 /* Copy and send config mbox */
79 req = mbox_alloc_msg_nix_txschq_cfg(mbox);
83 mbox_memcpy(req->reg, reg, sizeof(uint64_t) * k);
84 mbox_memcpy(req->regval, regval, sizeof(uint64_t) * k);
85 mbox_memcpy(req->regval_mask, regval_mask, sizeof(uint64_t) * k);
87 rc = mbox_process(mbox);
93 plt_err("Txschq conf failed for node %p, rc=%d", node, rc);
98 nix_tm_txsch_reg_config(struct nix *nix, enum roc_nix_tm_tree tree)
100 struct nix_tm_node_list *list;
101 bool is_pf_or_lbk = false;
102 struct nix_tm_node *node;
103 bool skip_bp = false;
107 list = nix_tm_node_list(nix, tree);
109 if ((!dev_is_vf(&nix->dev) || nix->lbk_link) && !nix->sdp_link)
112 for (hw_lvl = 0; hw_lvl <= nix->tm_root_lvl; hw_lvl++) {
113 TAILQ_FOREACH(node, list, node) {
114 if (node->hw_lvl != hw_lvl)
117 /* Only one TL3/TL2 Link config should have BP enable
118 * set per channel only for PF or lbk vf.
121 if (is_pf_or_lbk && !skip_bp &&
122 node->hw_lvl == nix->tm_link_cfg_lvl) {
127 rc = nix_tm_node_reg_conf(nix, node);
137 nix_tm_update_parent_info(struct nix *nix, enum roc_nix_tm_tree tree)
139 struct nix_tm_node *child, *parent;
140 struct nix_tm_node_list *list;
141 uint32_t rr_prio, max_prio;
144 list = nix_tm_node_list(nix, tree);
146 /* Release all the node hw resources locally
147 * if parent marked as dirty and resource exists.
149 TAILQ_FOREACH(child, list, node) {
150 /* Release resource only if parent direct hierarchy changed */
151 if (child->flags & NIX_TM_NODE_HWRES && child->parent &&
152 child->parent->child_realloc) {
153 nix_tm_free_node_resource(nix, child);
155 child->max_prio = UINT32_MAX;
158 TAILQ_FOREACH(parent, list, node) {
159 /* Count group of children of same priority i.e are RR */
160 rr_num = nix_tm_check_rr(nix, parent->id, tree, &rr_prio,
163 /* Assuming that multiple RR groups are
164 * not configured based on capability.
166 parent->rr_prio = rr_prio;
167 parent->rr_num = rr_num;
168 parent->max_prio = max_prio;
175 nix_tm_root_node_get(struct nix *nix, int tree)
177 struct nix_tm_node_list *list = nix_tm_node_list(nix, tree);
178 struct nix_tm_node *tm_node;
180 TAILQ_FOREACH(tm_node, list, node) {
181 if (tm_node->hw_lvl == nix->tm_root_lvl)
189 nix_tm_node_add(struct roc_nix *roc_nix, struct nix_tm_node *node)
191 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
192 struct nix_tm_shaper_profile *profile;
193 uint32_t node_id, parent_id, lvl;
194 struct nix_tm_node *parent_node;
195 uint32_t priority, profile_id;
196 uint8_t hw_lvl, exp_next_lvl;
197 enum roc_nix_tm_tree tree;
201 priority = node->priority;
202 parent_id = node->parent_id;
203 profile_id = node->shaper_profile_id;
207 plt_tm_dbg("Add node %s lvl %u id %u, prio 0x%x weight 0x%x "
208 "parent %u profile 0x%x tree %u",
209 nix_tm_hwlvl2str(nix_tm_lvl2nix(nix, lvl)), lvl, node_id,
210 priority, node->weight, parent_id, profile_id, tree);
212 if (tree >= ROC_NIX_TM_TREE_MAX)
213 return NIX_ERR_PARAM;
215 /* Translate sw level id's to nix hw level id's */
216 hw_lvl = nix_tm_lvl2nix(nix, lvl);
217 if (hw_lvl == NIX_TXSCH_LVL_CNT && !nix_tm_is_leaf(nix, lvl))
218 return NIX_ERR_TM_INVALID_LVL;
220 /* Leaf nodes have to be same priority */
221 if (nix_tm_is_leaf(nix, lvl) && priority != 0)
222 return NIX_ERR_TM_INVALID_PRIO;
224 parent_node = nix_tm_node_search(nix, parent_id, tree);
226 if (node_id < nix->nb_tx_queues)
227 exp_next_lvl = NIX_TXSCH_LVL_SMQ;
229 exp_next_lvl = hw_lvl + 1;
231 /* Check if there is no parent node yet */
232 if (hw_lvl != nix->tm_root_lvl &&
233 (!parent_node || parent_node->hw_lvl != exp_next_lvl))
234 return NIX_ERR_TM_INVALID_PARENT;
236 /* Check if a node already exists */
237 if (nix_tm_node_search(nix, node_id, tree))
238 return NIX_ERR_TM_NODE_EXISTS;
240 /* Check if root node exists */
241 if (hw_lvl == nix->tm_root_lvl && nix_tm_root_node_get(nix, tree))
242 return NIX_ERR_TM_NODE_EXISTS;
244 profile = nix_tm_shaper_profile_search(nix, profile_id);
245 if (!nix_tm_is_leaf(nix, lvl)) {
246 /* Check if shaper profile exists for non leaf node */
247 if (!profile && profile_id != ROC_NIX_TM_SHAPER_PROFILE_NONE)
248 return NIX_ERR_TM_INVALID_SHAPER_PROFILE;
250 /* Packet mode in profile should match with that of tm node */
251 if (profile && profile->pkt_mode != node->pkt_mode)
252 return NIX_ERR_TM_PKT_MODE_MISMATCH;
255 /* Check if there is second DWRR already in siblings or holes in prio */
256 rc = nix_tm_validate_prio(nix, lvl, parent_id, priority, tree);
260 if (node->weight > roc_nix_tm_max_sched_wt_get())
261 return NIX_ERR_TM_WEIGHT_EXCEED;
263 /* Maintain minimum weight */
267 node->hw_lvl = nix_tm_lvl2nix(nix, lvl);
269 node->max_prio = UINT32_MAX;
270 node->hw_id = NIX_TM_HW_ID_INVALID;
276 node->parent = parent_node;
278 parent_node->child_realloc = true;
279 node->parent_hw_id = NIX_TM_HW_ID_INVALID;
281 TAILQ_INSERT_TAIL(&nix->trees[tree], node, node);
282 plt_tm_dbg("Added node %s lvl %u id %u (%p)",
283 nix_tm_hwlvl2str(node->hw_lvl), lvl, node_id, node);
288 nix_tm_clear_path_xoff(struct nix *nix, struct nix_tm_node *node)
290 struct mbox *mbox = (&nix->dev)->mbox;
291 struct nix_txschq_config *req;
292 struct nix_tm_node *p;
295 /* Enable nodes in path for flush to succeed */
296 if (!nix_tm_is_leaf(nix, node->lvl))
301 if (!(p->flags & NIX_TM_NODE_ENABLED) &&
302 (p->flags & NIX_TM_NODE_HWRES)) {
303 req = mbox_alloc_msg_nix_txschq_cfg(mbox);
304 req->lvl = p->hw_lvl;
305 req->num_regs = nix_tm_sw_xoff_prep(p, false, req->reg,
307 rc = mbox_process(mbox);
311 p->flags |= NIX_TM_NODE_ENABLED;
320 nix_tm_bp_config_set(struct roc_nix *roc_nix, bool enable)
322 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
323 enum roc_nix_tm_tree tree = nix->tm_tree;
324 struct mbox *mbox = (&nix->dev)->mbox;
325 struct nix_txschq_config *req = NULL;
326 struct nix_tm_node_list *list;
327 struct nix_tm_node *node;
332 list = nix_tm_node_list(nix, tree);
335 TAILQ_FOREACH(node, list, node) {
336 if (node->hw_lvl != nix->tm_link_cfg_lvl)
339 if (!(node->flags & NIX_TM_NODE_HWRES) || !node->bp_capa)
343 req = mbox_alloc_msg_nix_txschq_cfg(mbox);
344 req->lvl = nix->tm_link_cfg_lvl;
348 req->reg[k] = NIX_AF_TL3_TL2X_LINKX_CFG(node->hw_id, link);
349 req->regval[k] = enable ? BIT_ULL(13) : 0;
350 req->regval_mask[k] = ~BIT_ULL(13);
353 if (k >= MAX_REGS_PER_MBOX_MSG) {
355 rc = mbox_process(mbox);
364 rc = mbox_process(mbox);
371 plt_err("Failed to %s bp on link %u, rc=%d(%s)",
372 enable ? "enable" : "disable", link, rc, roc_error_msg_get(rc));
377 nix_tm_bp_config_get(struct roc_nix *roc_nix, bool *is_enabled)
379 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
380 struct nix_txschq_config *req = NULL, *rsp;
381 enum roc_nix_tm_tree tree = nix->tm_tree;
382 struct mbox *mbox = (&nix->dev)->mbox;
383 struct nix_tm_node_list *list;
384 struct nix_tm_node *node;
391 list = nix_tm_node_list(nix, tree);
394 TAILQ_FOREACH(node, list, node) {
395 if (node->hw_lvl != nix->tm_link_cfg_lvl)
398 if (!(node->flags & NIX_TM_NODE_HWRES) || !node->bp_capa)
403 req = mbox_alloc_msg_nix_txschq_cfg(mbox);
405 req->lvl = nix->tm_link_cfg_lvl;
409 req->reg[k] = NIX_AF_TL3_TL2X_LINKX_CFG(node->hw_id, link);
412 if (k >= MAX_REGS_PER_MBOX_MSG) {
414 rc = mbox_process_msg(mbox, (void **)&rsp);
415 if (rc || rsp->num_regs != k)
419 /* Report it as enabled only if enabled or all */
420 for (i = 0; i < k; i++)
421 enable &= !!(rsp->regval[i] & BIT_ULL(13));
427 rc = mbox_process_msg(mbox, (void **)&rsp);
430 /* Report it as enabled only if enabled or all */
431 for (i = 0; i < k; i++)
432 enable &= !!(rsp->regval[i] & BIT_ULL(13));
435 *is_enabled = found ? !!enable : false;
438 plt_err("Failed to get bp status on link %u, rc=%d(%s)", link, rc,
439 roc_error_msg_get(rc));
444 nix_tm_smq_xoff(struct nix *nix, struct nix_tm_node *node, bool enable)
446 struct mbox *mbox = (&nix->dev)->mbox;
447 struct nix_txschq_config *req;
452 plt_tm_dbg("Setting SMQ %u XOFF/FLUSH to %s", smq,
453 enable ? "enable" : "disable");
455 rc = nix_tm_clear_path_xoff(nix, node);
459 req = mbox_alloc_msg_nix_txschq_cfg(mbox);
460 req->lvl = NIX_TXSCH_LVL_SMQ;
463 req->reg[0] = NIX_AF_SMQX_CFG(smq);
464 req->regval[0] = enable ? (BIT_ULL(50) | BIT_ULL(49)) : 0;
465 req->regval_mask[0] =
466 enable ? ~(BIT_ULL(50) | BIT_ULL(49)) : ~BIT_ULL(50);
468 return mbox_process(mbox);
472 nix_tm_leaf_data_get(struct nix *nix, uint16_t sq, uint32_t *rr_quantum,
475 struct nix_tm_node *node;
478 node = nix_tm_node_search(nix, sq, nix->tm_tree);
480 /* Check if we found a valid leaf node */
481 if (!node || !nix_tm_is_leaf(nix, node->lvl) || !node->parent ||
482 node->parent->hw_id == NIX_TM_HW_ID_INVALID) {
486 /* Get SMQ Id of leaf node's parent */
487 *smq = node->parent->hw_id;
488 *rr_quantum = nix_tm_weight_to_rr_quantum(node->weight);
490 rc = nix_tm_smq_xoff(nix, node->parent, false);
493 node->flags |= NIX_TM_NODE_ENABLED;
498 roc_nix_tm_sq_flush_spin(struct roc_nix_sq *sq)
500 struct nix *nix = roc_nix_to_nix_priv(sq->roc_nix);
501 uint16_t sqb_cnt, head_off, tail_off;
502 uint64_t wdata, val, prev;
503 uint16_t qid = sq->qid;
505 uint64_t timeout; /* 10's of usec */
507 /* Wait for enough time based on shaper min rate */
508 timeout = (sq->nb_desc * roc_nix_max_pkt_len(sq->roc_nix) * 8 * 1E5);
509 /* Wait for worst case scenario of this SQ being last priority
510 * and so have to wait for all other SQ's drain out by their own.
512 timeout = timeout * nix->nb_tx_queues;
513 timeout = timeout / nix->tm_rate_min;
517 wdata = ((uint64_t)qid << 32);
518 regaddr = (int64_t *)(nix->base + NIX_LF_SQ_OP_STATUS);
519 val = roc_atomic64_add_nosync(wdata, regaddr);
521 /* Spin multiple iterations as "sq->fc_cache_pkts" can still
522 * have space to send pkts even though fc_mem is disabled
528 val = roc_atomic64_add_nosync(wdata, regaddr);
529 /* Continue on error */
530 if (val & BIT_ULL(63))
536 sqb_cnt = val & 0xFFFF;
537 head_off = (val >> 20) & 0x3F;
538 tail_off = (val >> 28) & 0x3F;
540 /* SQ reached quiescent state */
541 if (sqb_cnt <= 1 && head_off == tail_off &&
542 (*(volatile uint64_t *)sq->fc == sq->nb_sqb_bufs)) {
554 roc_nix_tm_dump(sq->roc_nix);
555 roc_nix_queues_ctx_dump(sq->roc_nix);
559 /* Flush and disable tx queue and its parent SMQ */
561 nix_tm_sq_flush_pre(struct roc_nix_sq *sq)
563 struct roc_nix *roc_nix = sq->roc_nix;
564 struct nix_tm_node *node, *sibling;
565 struct nix_tm_node_list *list;
566 enum roc_nix_tm_tree tree;
572 nix = roc_nix_to_nix_priv(roc_nix);
574 /* Need not do anything if tree is in disabled state */
575 if (!(nix->tm_flags & NIX_TM_HIERARCHY_ENA))
578 mbox = (&nix->dev)->mbox;
582 list = nix_tm_node_list(nix, tree);
584 /* Find the node for this SQ */
585 node = nix_tm_node_search(nix, qid, tree);
586 if (!node || !(node->flags & NIX_TM_NODE_ENABLED)) {
587 plt_err("Invalid node/state for sq %u", qid);
591 /* Enable CGX RXTX to drain pkts */
592 if (!roc_nix->io_enabled) {
593 /* Though it enables both RX MCAM Entries and CGX Link
594 * we assume all the rx queues are stopped way back.
596 mbox_alloc_msg_nix_lf_start_rx(mbox);
597 rc = mbox_process(mbox);
599 plt_err("cgx start failed, rc=%d", rc);
604 /* Disable backpressure */
605 rc = nix_tm_bp_config_set(roc_nix, false);
607 plt_err("Failed to disable backpressure for flush, rc=%d", rc);
611 /* Disable smq xoff for case it was enabled earlier */
612 rc = nix_tm_smq_xoff(nix, node->parent, false);
614 plt_err("Failed to enable smq %u, rc=%d", node->parent->hw_id,
619 /* As per HRM, to disable an SQ, all other SQ's
620 * that feed to same SMQ must be paused before SMQ flush.
622 TAILQ_FOREACH(sibling, list, node) {
623 if (sibling->parent != node->parent)
625 if (!(sibling->flags & NIX_TM_NODE_ENABLED))
633 rc = roc_nix_tm_sq_aura_fc(sq, false);
635 plt_err("Failed to disable sqb aura fc, rc=%d", rc);
639 /* Wait for sq entries to be flushed */
640 rc = roc_nix_tm_sq_flush_spin(sq);
642 plt_err("Failed to drain sq %u, rc=%d\n", sq->qid, rc);
647 node->flags &= ~NIX_TM_NODE_ENABLED;
649 /* Disable and flush */
650 rc = nix_tm_smq_xoff(nix, node->parent, true);
652 plt_err("Failed to disable smq %u, rc=%d", node->parent->hw_id,
657 /* Restore cgx state */
658 if (!roc_nix->io_enabled) {
659 mbox_alloc_msg_nix_lf_stop_rx(mbox);
660 rc |= mbox_process(mbox);
667 nix_tm_sq_flush_post(struct roc_nix_sq *sq)
669 struct roc_nix *roc_nix = sq->roc_nix;
670 struct nix_tm_node *node, *sibling;
671 struct nix_tm_node_list *list;
672 enum roc_nix_tm_tree tree;
673 struct roc_nix_sq *s_sq;
679 nix = roc_nix_to_nix_priv(roc_nix);
681 /* Need not do anything if tree is in disabled state */
682 if (!(nix->tm_flags & NIX_TM_HIERARCHY_ENA))
687 list = nix_tm_node_list(nix, tree);
689 /* Find the node for this SQ */
690 node = nix_tm_node_search(nix, qid, tree);
692 plt_err("Invalid node for sq %u", qid);
696 /* Enable all the siblings back */
697 TAILQ_FOREACH(sibling, list, node) {
698 if (sibling->parent != node->parent)
701 if (sibling->id == qid)
704 if (!(sibling->flags & NIX_TM_NODE_ENABLED))
708 s_sq = nix->sqs[s_qid];
713 /* Enable back if any SQ is still present */
714 rc = nix_tm_smq_xoff(nix, node->parent, false);
716 plt_err("Failed to enable smq %u, rc=%d",
717 node->parent->hw_id, rc);
723 rc = roc_nix_tm_sq_aura_fc(s_sq, true);
725 plt_err("Failed to enable sqb aura fc, rc=%d", rc);
733 /* Restore backpressure */
734 rc = nix_tm_bp_config_set(roc_nix, true);
736 plt_err("Failed to restore backpressure, rc=%d", rc);
744 nix_tm_sq_sched_conf(struct nix *nix, struct nix_tm_node *node,
745 bool rr_quantum_only)
747 struct mbox *mbox = (&nix->dev)->mbox;
748 uint16_t qid = node->id, smq;
752 smq = node->parent->hw_id;
753 rr_quantum = nix_tm_weight_to_rr_quantum(node->weight);
756 plt_tm_dbg("Update sq(%u) rr_quantum 0x%" PRIx64, qid,
759 plt_tm_dbg("Enabling sq(%u)->smq(%u), rr_quantum 0x%" PRIx64,
760 qid, smq, rr_quantum);
762 if (qid > nix->nb_tx_queues)
765 if (roc_model_is_cn9k()) {
766 struct nix_aq_enq_req *aq;
768 aq = mbox_alloc_msg_nix_aq_enq(mbox);
773 aq->ctype = NIX_AQ_CTYPE_SQ;
774 aq->op = NIX_AQ_INSTOP_WRITE;
776 /* smq update only when needed */
777 if (!rr_quantum_only) {
779 aq->sq_mask.smq = ~aq->sq_mask.smq;
781 aq->sq.smq_rr_quantum = rr_quantum;
782 aq->sq_mask.smq_rr_quantum = ~aq->sq_mask.smq_rr_quantum;
784 struct nix_cn10k_aq_enq_req *aq;
786 aq = mbox_alloc_msg_nix_cn10k_aq_enq(mbox);
791 aq->ctype = NIX_AQ_CTYPE_SQ;
792 aq->op = NIX_AQ_INSTOP_WRITE;
794 /* smq update only when needed */
795 if (!rr_quantum_only) {
797 aq->sq_mask.smq = ~aq->sq_mask.smq;
799 aq->sq.smq_rr_weight = rr_quantum;
800 aq->sq_mask.smq_rr_weight = ~aq->sq_mask.smq_rr_weight;
803 rc = mbox_process(mbox);
805 plt_err("Failed to set smq, rc=%d", rc);
810 nix_tm_release_resources(struct nix *nix, uint8_t hw_lvl, bool contig,
813 uint16_t avail, thresh, to_free = 0, schq;
814 struct mbox *mbox = (&nix->dev)->mbox;
815 struct nix_txsch_free_req *req;
816 struct plt_bitmap *bmp;
821 bmp = contig ? nix->schq_contig_bmp[hw_lvl] : nix->schq_bmp[hw_lvl];
823 contig ? nix->contig_rsvd[hw_lvl] : nix->discontig_rsvd[hw_lvl];
824 plt_bitmap_scan_init(bmp);
826 avail = nix_tm_resource_avail(nix, hw_lvl, contig);
829 /* Release only above threshold */
831 to_free = avail - thresh;
833 /* Release everything */
837 /* Now release resources to AF */
839 if (!slab && !plt_bitmap_scan(bmp, &pos, &slab))
842 schq = bitmap_ctzll(slab);
843 slab &= ~(1ULL << schq);
847 req = mbox_alloc_msg_nix_txsch_free(mbox);
851 req->schq_lvl = hw_lvl;
853 rc = mbox_process(mbox);
855 plt_err("failed to release hwres %s(%u) rc %d",
856 nix_tm_hwlvl2str(hw_lvl), schq, rc);
860 plt_tm_dbg("Released hwres %s(%u)", nix_tm_hwlvl2str(hw_lvl),
862 plt_bitmap_clear(bmp, schq);
867 plt_err("resource inconsistency for %s(%u)",
868 nix_tm_hwlvl2str(hw_lvl), contig);
875 nix_tm_free_node_resource(struct nix *nix, struct nix_tm_node *node)
877 struct mbox *mbox = (&nix->dev)->mbox;
878 struct nix_txsch_free_req *req;
879 struct plt_bitmap *bmp;
880 uint16_t avail, hw_id;
884 hw_lvl = node->hw_lvl;
886 bmp = nix->schq_bmp[hw_lvl];
887 /* Free specific HW resource */
888 plt_tm_dbg("Free hwres %s(%u) lvl %u id %u (%p)",
889 nix_tm_hwlvl2str(node->hw_lvl), hw_id, node->lvl, node->id,
892 avail = nix_tm_resource_avail(nix, hw_lvl, false);
893 /* Always for now free to discontiguous queue when avail
896 if (nix->discontig_rsvd[hw_lvl] &&
897 avail < nix->discontig_rsvd[hw_lvl]) {
898 PLT_ASSERT(hw_id < NIX_TM_MAX_HW_TXSCHQ);
899 PLT_ASSERT(plt_bitmap_get(bmp, hw_id) == 0);
900 plt_bitmap_set(bmp, hw_id);
901 node->hw_id = NIX_TM_HW_ID_INVALID;
902 node->flags &= ~NIX_TM_NODE_HWRES;
907 req = mbox_alloc_msg_nix_txsch_free(mbox);
911 req->schq_lvl = node->hw_lvl;
913 rc = mbox_process(mbox);
915 plt_err("failed to release hwres %s(%u) rc %d",
916 nix_tm_hwlvl2str(node->hw_lvl), hw_id, rc);
920 /* Mark parent as dirty for reallocing it's children */
922 node->parent->child_realloc = true;
924 node->hw_id = NIX_TM_HW_ID_INVALID;
925 node->flags &= ~NIX_TM_NODE_HWRES;
926 plt_tm_dbg("Released hwres %s(%u) to af",
927 nix_tm_hwlvl2str(node->hw_lvl), hw_id);
932 nix_tm_node_delete(struct roc_nix *roc_nix, uint32_t node_id,
933 enum roc_nix_tm_tree tree, bool free)
935 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
936 struct nix_tm_shaper_profile *profile;
937 struct nix_tm_node *node, *child;
938 struct nix_tm_node_list *list;
942 plt_tm_dbg("Delete node id %u tree %u", node_id, tree);
944 node = nix_tm_node_search(nix, node_id, tree);
946 return NIX_ERR_TM_INVALID_NODE;
948 list = nix_tm_node_list(nix, tree);
949 /* Check for any existing children */
950 TAILQ_FOREACH(child, list, node) {
951 if (child->parent == node)
952 return NIX_ERR_TM_CHILD_EXISTS;
955 /* Remove shaper profile reference */
956 profile_id = node->shaper_profile_id;
957 profile = nix_tm_shaper_profile_search(nix, profile_id);
959 /* Free hw resource locally */
960 if (node->flags & NIX_TM_NODE_HWRES) {
961 rc = nix_tm_free_node_resource(nix, node);
969 TAILQ_REMOVE(list, node, node);
971 plt_tm_dbg("Deleted node %s lvl %u id %u, prio 0x%x weight 0x%x "
972 "parent %u profile 0x%x tree %u (%p)",
973 nix_tm_hwlvl2str(node->hw_lvl), node->lvl, node->id,
974 node->priority, node->weight,
975 node->parent ? node->parent->id : UINT32_MAX,
976 node->shaper_profile_id, tree, node);
977 /* Free only if requested */
979 nix_tm_node_free(node);
984 nix_tm_assign_hw_id(struct nix *nix, struct nix_tm_node *parent,
985 uint16_t *contig_id, int *contig_cnt,
986 struct nix_tm_node_list *list)
988 struct nix_tm_node *child;
989 struct plt_bitmap *bmp;
990 uint8_t child_hw_lvl;
996 child_hw_lvl = parent->hw_lvl - 1;
997 bmp = nix->schq_bmp[child_hw_lvl];
998 plt_bitmap_scan_init(bmp);
1001 /* Save spare schq if it is case of RR + SP */
1002 if (parent->rr_prio != 0xf && *contig_cnt > 1)
1003 spare_schq = *contig_id + parent->rr_prio;
1005 TAILQ_FOREACH(child, list, node) {
1008 if (child->parent->id != parent->id)
1011 /* Resource never expected to be present */
1012 if (child->flags & NIX_TM_NODE_HWRES) {
1013 plt_err("Resource exists for child (%s)%u, id %u (%p)",
1014 nix_tm_hwlvl2str(child->hw_lvl), child->hw_id,
1020 plt_bitmap_scan(bmp, &pos, &slab);
1022 if (child->priority == parent->rr_prio && spare_schq != -1) {
1023 /* Use spare schq first if present */
1026 *contig_cnt = *contig_cnt - 1;
1028 } else if (child->priority == parent->rr_prio) {
1029 /* Assign a discontiguous queue */
1031 plt_err("Schq not found for Child %u "
1033 child->id, child->lvl, child);
1037 schq = bitmap_ctzll(slab);
1038 slab &= ~(1ULL << schq);
1040 plt_bitmap_clear(bmp, schq);
1042 /* Assign a contiguous queue */
1043 schq = *contig_id + child->priority;
1044 *contig_cnt = *contig_cnt - 1;
1047 plt_tm_dbg("Resource %s(%u), for lvl %u id %u(%p)",
1048 nix_tm_hwlvl2str(child->hw_lvl), schq, child->lvl,
1051 child->hw_id = schq;
1052 child->parent_hw_id = parent->hw_id;
1053 child->flags |= NIX_TM_NODE_HWRES;
1060 nix_tm_assign_resources(struct nix *nix, enum roc_nix_tm_tree tree)
1062 struct nix_tm_node *parent, *root = NULL;
1063 struct plt_bitmap *bmp, *bmp_contig;
1064 struct nix_tm_node_list *list;
1065 uint8_t child_hw_lvl, hw_lvl;
1066 uint16_t contig_id, j;
1071 list = nix_tm_node_list(nix, tree);
1072 /* Walk from TL1 to TL4 parents */
1073 for (hw_lvl = NIX_TXSCH_LVL_TL1; hw_lvl > 0; hw_lvl--) {
1074 TAILQ_FOREACH(parent, list, node) {
1075 child_hw_lvl = parent->hw_lvl - 1;
1076 if (parent->hw_lvl != hw_lvl)
1079 /* Remember root for future */
1080 if (parent->hw_lvl == nix->tm_root_lvl)
1083 if (!parent->child_realloc) {
1084 /* Skip when parent is not dirty */
1085 if (nix_tm_child_res_valid(list, parent))
1087 plt_err("Parent not dirty but invalid "
1088 "child res parent id %u(lvl %u)",
1089 parent->id, parent->lvl);
1093 bmp_contig = nix->schq_contig_bmp[child_hw_lvl];
1095 /* Prealloc contiguous indices for a parent */
1096 contig_id = NIX_TM_MAX_HW_TXSCHQ;
1097 cnt = (int)parent->max_prio + 1;
1099 plt_bitmap_scan_init(bmp_contig);
1100 if (!plt_bitmap_scan(bmp_contig, &pos, &slab)) {
1101 plt_err("Contig schq not found");
1104 contig_id = pos + bitmap_ctzll(slab);
1106 /* Check if we have enough */
1107 for (j = contig_id; j < contig_id + cnt; j++) {
1108 if (!plt_bitmap_get(bmp_contig, j))
1112 if (j != contig_id + cnt) {
1113 plt_err("Contig schq not sufficient");
1117 for (j = contig_id; j < contig_id + cnt; j++)
1118 plt_bitmap_clear(bmp_contig, j);
1121 /* Assign hw id to all children */
1122 rc = nix_tm_assign_hw_id(nix, parent, &contig_id, &cnt,
1125 plt_err("Unexpected err, contig res alloc, "
1126 "parent %u, of %s, rc=%d, cnt=%d",
1127 parent->id, nix_tm_hwlvl2str(hw_lvl),
1132 /* Clear the dirty bit as children's
1133 * resources are reallocated.
1135 parent->child_realloc = false;
1139 /* Root is always expected to be there */
1143 if (root->flags & NIX_TM_NODE_HWRES)
1146 /* Process root node */
1147 bmp = nix->schq_bmp[nix->tm_root_lvl];
1148 plt_bitmap_scan_init(bmp);
1149 if (!plt_bitmap_scan(bmp, &pos, &slab)) {
1150 plt_err("Resource not allocated for root");
1154 root->hw_id = pos + bitmap_ctzll(slab);
1155 root->flags |= NIX_TM_NODE_HWRES;
1156 plt_bitmap_clear(bmp, root->hw_id);
1158 /* Get TL1 id as well when root is not TL1 */
1159 if (!nix_tm_have_tl1_access(nix)) {
1160 bmp = nix->schq_bmp[NIX_TXSCH_LVL_TL1];
1162 plt_bitmap_scan_init(bmp);
1163 if (!plt_bitmap_scan(bmp, &pos, &slab)) {
1164 plt_err("Resource not found for TL1");
1167 root->parent_hw_id = pos + bitmap_ctzll(slab);
1168 plt_bitmap_clear(bmp, root->parent_hw_id);
1171 plt_tm_dbg("Resource %s(%u) for root(id %u) (%p)",
1172 nix_tm_hwlvl2str(root->hw_lvl), root->hw_id, root->id, root);
1178 nix_tm_copy_rsp_to_nix(struct nix *nix, struct nix_txsch_alloc_rsp *rsp)
1183 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) {
1184 for (i = 0; i < rsp->schq[lvl]; i++)
1185 plt_bitmap_set(nix->schq_bmp[lvl],
1186 rsp->schq_list[lvl][i]);
1188 for (i = 0; i < rsp->schq_contig[lvl]; i++)
1189 plt_bitmap_set(nix->schq_contig_bmp[lvl],
1190 rsp->schq_contig_list[lvl][i]);
1195 nix_tm_alloc_txschq(struct nix *nix, enum roc_nix_tm_tree tree)
1197 uint16_t schq_contig[NIX_TXSCH_LVL_CNT];
1198 struct mbox *mbox = (&nix->dev)->mbox;
1199 uint16_t schq[NIX_TXSCH_LVL_CNT];
1200 struct nix_txsch_alloc_req *req;
1201 struct nix_txsch_alloc_rsp *rsp;
1206 memset(schq, 0, sizeof(schq));
1207 memset(schq_contig, 0, sizeof(schq_contig));
1209 /* Estimate requirement */
1210 rc = nix_tm_resource_estimate(nix, schq_contig, schq, tree);
1214 /* Release existing contiguous resources when realloc requested
1215 * as there is no way to guarantee continuity of old with new.
1217 for (hw_lvl = 0; hw_lvl < NIX_TXSCH_LVL_CNT; hw_lvl++) {
1218 if (schq_contig[hw_lvl])
1219 nix_tm_release_resources(nix, hw_lvl, true, false);
1222 /* Alloc as needed */
1225 req = mbox_alloc_msg_nix_txsch_alloc(mbox);
1230 mbox_memcpy(req->schq, schq, sizeof(req->schq));
1231 mbox_memcpy(req->schq_contig, schq_contig,
1232 sizeof(req->schq_contig));
1234 /* Each alloc can be at max of MAX_TXSCHQ_PER_FUNC per level.
1235 * So split alloc to multiple requests.
1237 for (i = 0; i < NIX_TXSCH_LVL_CNT; i++) {
1238 if (req->schq[i] > MAX_TXSCHQ_PER_FUNC)
1239 req->schq[i] = MAX_TXSCHQ_PER_FUNC;
1240 schq[i] -= req->schq[i];
1242 if (req->schq_contig[i] > MAX_TXSCHQ_PER_FUNC)
1243 req->schq_contig[i] = MAX_TXSCHQ_PER_FUNC;
1244 schq_contig[i] -= req->schq_contig[i];
1246 if (schq[i] || schq_contig[i])
1250 rc = mbox_process_msg(mbox, (void *)&rsp);
1254 nix_tm_copy_rsp_to_nix(nix, rsp);
1257 nix->tm_link_cfg_lvl = rsp->link_cfg_lvl;
1260 for (i = 0; i < NIX_TXSCH_LVL_CNT; i++) {
1261 if (nix_tm_release_resources(nix, i, true, false))
1262 plt_err("Failed to release contig resources of "
1265 if (nix_tm_release_resources(nix, i, false, false))
1266 plt_err("Failed to release discontig resources of "
1274 nix_tm_prepare_default_tree(struct roc_nix *roc_nix)
1276 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
1277 uint32_t nonleaf_id = nix->nb_tx_queues;
1278 struct nix_tm_node *node = NULL;
1279 uint8_t leaf_lvl, lvl, lvl_end;
1283 /* Add ROOT, SCH1, SCH2, SCH3, [SCH4] nodes */
1284 parent = ROC_NIX_TM_NODE_ID_INVALID;
1285 /* With TL1 access we have an extra level */
1286 lvl_end = (nix_tm_have_tl1_access(nix) ? ROC_TM_LVL_SCH4 :
1289 for (lvl = ROC_TM_LVL_ROOT; lvl <= lvl_end; lvl++) {
1291 node = nix_tm_node_alloc();
1295 node->id = nonleaf_id;
1296 node->parent_id = parent;
1298 node->weight = NIX_TM_DFLT_RR_WT;
1299 node->shaper_profile_id = ROC_NIX_TM_SHAPER_PROFILE_NONE;
1301 node->tree = ROC_NIX_TM_DEFAULT;
1303 rc = nix_tm_node_add(roc_nix, node);
1306 parent = nonleaf_id;
1310 parent = nonleaf_id - 1;
1311 leaf_lvl = (nix_tm_have_tl1_access(nix) ? ROC_TM_LVL_QUEUE :
1314 /* Add leaf nodes */
1315 for (i = 0; i < nix->nb_tx_queues; i++) {
1317 node = nix_tm_node_alloc();
1322 node->parent_id = parent;
1324 node->weight = NIX_TM_DFLT_RR_WT;
1325 node->shaper_profile_id = ROC_NIX_TM_SHAPER_PROFILE_NONE;
1326 node->lvl = leaf_lvl;
1327 node->tree = ROC_NIX_TM_DEFAULT;
1329 rc = nix_tm_node_add(roc_nix, node);
1336 nix_tm_node_free(node);
1341 roc_nix_tm_prepare_rate_limited_tree(struct roc_nix *roc_nix)
1343 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
1344 uint32_t nonleaf_id = nix->nb_tx_queues;
1345 struct nix_tm_node *node = NULL;
1346 uint8_t leaf_lvl, lvl, lvl_end;
1350 /* Add ROOT, SCH1, SCH2 nodes */
1351 parent = ROC_NIX_TM_NODE_ID_INVALID;
1352 lvl_end = (nix_tm_have_tl1_access(nix) ? ROC_TM_LVL_SCH3 :
1355 for (lvl = ROC_TM_LVL_ROOT; lvl <= lvl_end; lvl++) {
1357 node = nix_tm_node_alloc();
1361 node->id = nonleaf_id;
1362 node->parent_id = parent;
1364 node->weight = NIX_TM_DFLT_RR_WT;
1365 node->shaper_profile_id = ROC_NIX_TM_SHAPER_PROFILE_NONE;
1367 node->tree = ROC_NIX_TM_RLIMIT;
1369 rc = nix_tm_node_add(roc_nix, node);
1372 parent = nonleaf_id;
1376 /* SMQ is mapped to SCH4 when we have TL1 access and SCH3 otherwise */
1377 lvl = (nix_tm_have_tl1_access(nix) ? ROC_TM_LVL_SCH4 : ROC_TM_LVL_SCH3);
1379 /* Add per queue SMQ nodes i.e SCH4 / SCH3 */
1380 for (i = 0; i < nix->nb_tx_queues; i++) {
1382 node = nix_tm_node_alloc();
1386 node->id = nonleaf_id + i;
1387 node->parent_id = parent;
1389 node->weight = NIX_TM_DFLT_RR_WT;
1390 node->shaper_profile_id = ROC_NIX_TM_SHAPER_PROFILE_NONE;
1392 node->tree = ROC_NIX_TM_RLIMIT;
1394 rc = nix_tm_node_add(roc_nix, node);
1399 parent = nonleaf_id;
1400 leaf_lvl = (nix_tm_have_tl1_access(nix) ? ROC_TM_LVL_QUEUE :
1403 /* Add leaf nodes */
1404 for (i = 0; i < nix->nb_tx_queues; i++) {
1406 node = nix_tm_node_alloc();
1411 node->parent_id = parent + i;
1413 node->weight = NIX_TM_DFLT_RR_WT;
1414 node->shaper_profile_id = ROC_NIX_TM_SHAPER_PROFILE_NONE;
1415 node->lvl = leaf_lvl;
1416 node->tree = ROC_NIX_TM_RLIMIT;
1418 rc = nix_tm_node_add(roc_nix, node);
1425 nix_tm_node_free(node);
1430 nix_tm_free_resources(struct roc_nix *roc_nix, uint32_t tree_mask, bool hw_only)
1432 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
1433 struct nix_tm_shaper_profile *profile;
1434 struct nix_tm_node *node, *next_node;
1435 struct nix_tm_node_list *list;
1436 enum roc_nix_tm_tree tree;
1437 uint32_t profile_id;
1440 for (tree = 0; tree < ROC_NIX_TM_TREE_MAX; tree++) {
1441 if (!(tree_mask & BIT(tree)))
1444 plt_tm_dbg("Freeing resources of tree %u", tree);
1446 list = nix_tm_node_list(nix, tree);
1447 next_node = TAILQ_FIRST(list);
1450 next_node = TAILQ_NEXT(node, node);
1452 if (!nix_tm_is_leaf(nix, node->lvl) &&
1453 node->flags & NIX_TM_NODE_HWRES) {
1454 /* Clear xoff in path for flush to succeed */
1455 rc = nix_tm_clear_path_xoff(nix, node);
1458 rc = nix_tm_free_node_resource(nix, node);
1464 /* Leave software elements if needed */
1468 next_node = TAILQ_FIRST(list);
1471 next_node = TAILQ_NEXT(node, node);
1473 plt_tm_dbg("Free node lvl %u id %u (%p)", node->lvl,
1476 profile_id = node->shaper_profile_id;
1477 profile = nix_tm_shaper_profile_search(nix, profile_id);
1481 TAILQ_REMOVE(list, node, node);
1482 nix_tm_node_free(node);
1489 nix_tm_conf_init(struct roc_nix *roc_nix)
1491 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
1492 uint32_t bmp_sz, hw_lvl;
1496 PLT_STATIC_ASSERT(sizeof(struct nix_tm_node) <= ROC_NIX_TM_NODE_SZ);
1497 PLT_STATIC_ASSERT(sizeof(struct nix_tm_shaper_profile) <=
1498 ROC_NIX_TM_SHAPER_PROFILE_SZ);
1501 for (i = 0; i < ROC_NIX_TM_TREE_MAX; i++)
1502 TAILQ_INIT(&nix->trees[i]);
1504 TAILQ_INIT(&nix->shaper_profile_list);
1505 nix->tm_rate_min = 1E9; /* 1Gbps */
1508 bmp_sz = plt_bitmap_get_memory_footprint(NIX_TM_MAX_HW_TXSCHQ);
1509 bmp_mem = plt_zmalloc(bmp_sz * NIX_TXSCH_LVL_CNT * 2, 0);
1512 nix->schq_bmp_mem = bmp_mem;
1514 /* Init contiguous and discontiguous bitmap per lvl */
1516 for (hw_lvl = 0; hw_lvl < NIX_TXSCH_LVL_CNT; hw_lvl++) {
1517 /* Bitmap for discontiguous resource */
1518 nix->schq_bmp[hw_lvl] =
1519 plt_bitmap_init(NIX_TM_MAX_HW_TXSCHQ, bmp_mem, bmp_sz);
1520 if (!nix->schq_bmp[hw_lvl])
1523 bmp_mem = PLT_PTR_ADD(bmp_mem, bmp_sz);
1525 /* Bitmap for contiguous resource */
1526 nix->schq_contig_bmp[hw_lvl] =
1527 plt_bitmap_init(NIX_TM_MAX_HW_TXSCHQ, bmp_mem, bmp_sz);
1528 if (!nix->schq_contig_bmp[hw_lvl])
1531 bmp_mem = PLT_PTR_ADD(bmp_mem, bmp_sz);
1534 /* Disable TL1 Static Priority when VF's are enabled
1535 * as otherwise VF's TL2 reallocation will be needed
1536 * runtime to support a specific topology of PF.
1538 if (nix->pci_dev->max_vfs)
1539 nix->tm_flags |= NIX_TM_TL1_NO_SP;
1541 /* TL1 access is only for PF's */
1542 if (roc_nix_is_pf(roc_nix)) {
1543 nix->tm_flags |= NIX_TM_TL1_ACCESS;
1544 nix->tm_root_lvl = NIX_TXSCH_LVL_TL1;
1546 nix->tm_root_lvl = NIX_TXSCH_LVL_TL2;
1551 nix_tm_conf_fini(roc_nix);
1556 nix_tm_conf_fini(struct roc_nix *roc_nix)
1558 struct nix *nix = roc_nix_to_nix_priv(roc_nix);
1561 for (hw_lvl = 0; hw_lvl < NIX_TXSCH_LVL_CNT; hw_lvl++) {
1562 plt_bitmap_free(nix->schq_bmp[hw_lvl]);
1563 plt_bitmap_free(nix->schq_contig_bmp[hw_lvl]);
1565 plt_free(nix->schq_bmp_mem);