drivers/common/cnxk/roc_nix_xstats.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(C) 2021 Marvell.
   3  */
   4 #ifndef _ROC_NIX_XSTAT_H_
   5 #define _ROC_NIX_XSTAT_H_
   6
   7 #include <inttypes.h>
   8
   9 struct cnxk_nix_xstats_name {
  10         char name[ROC_NIX_XSTATS_NAME_SIZE];
  11         uint32_t offset;
  12 };
  13
  14 static const struct cnxk_nix_xstats_name nix_tx_xstats[] = {
  15         {"tx_ucast", NIX_STAT_LF_TX_TX_UCAST},
  16         {"tx_bcast", NIX_STAT_LF_TX_TX_BCAST},
  17         {"tx_mcast", NIX_STAT_LF_TX_TX_MCAST},
  18         {"tx_drop", NIX_STAT_LF_TX_TX_DROP},
  19         {"tx_octs", NIX_STAT_LF_TX_TX_OCTS},
  20 };
  21
  22 static const struct cnxk_nix_xstats_name nix_rx_xstats[] = {
  23         {"rx_octs", NIX_STAT_LF_RX_RX_OCTS},
  24         {"rx_ucast", NIX_STAT_LF_RX_RX_UCAST},
  25         {"rx_bcast", NIX_STAT_LF_RX_RX_BCAST},
  26         {"rx_mcast", NIX_STAT_LF_RX_RX_MCAST},
  27         {"rx_drop", NIX_STAT_LF_RX_RX_DROP},
  28         {"rx_drop_octs", NIX_STAT_LF_RX_RX_DROP_OCTS},
  29         {"rx_fcs", NIX_STAT_LF_RX_RX_FCS},
  30         {"rx_err", NIX_STAT_LF_RX_RX_ERR},
  31         {"rx_drp_bcast", NIX_STAT_LF_RX_RX_DRP_BCAST},
  32         {"rx_drp_mcast", NIX_STAT_LF_RX_RX_DRP_MCAST},
  33         {"rx_drp_l3bcast", NIX_STAT_LF_RX_RX_DRP_L3BCAST},
  34         {"rx_drp_l3mcast", NIX_STAT_LF_RX_RX_DRP_L3MCAST},
  35 };
  36
  37 static const struct cnxk_nix_xstats_name nix_q_xstats[] = {
  38         {"rq_op_re_pkts", NIX_LF_RQ_OP_RE_PKTS},
  39 };
  40
  41 static const struct cnxk_nix_xstats_name nix_rx_xstats_rpm[] = {
  42         {"rpm_rx_etherStatsOctets", RPM_MTI_STAT_RX_OCT_CNT},
  43         {"rpm_rx_OctetsReceivedOK", RPM_MTI_STAT_RX_OCT_RECV_OK},
  44         {"rpm_rx_aAlignmentErrors", RPM_MTI_STAT_RX_ALIG_ERR},
  45         {"rpm_rx_aPAUSEMACCtrlFramesReceived", RPM_MTI_STAT_RX_CTRL_FRM_RECV},
  46         {"rpm_rx_aFrameTooLongErrors", RPM_MTI_STAT_RX_FRM_LONG},
  47         {"rpm_rx_aInRangeLengthErrors", RPM_MTI_STAT_RX_LEN_ERR},
  48         {"rpm_rx_aFramesReceivedOK", RPM_MTI_STAT_RX_FRM_RECV},
  49         {"rpm_rx_aFrameCheckSequenceErrors", RPM_MTI_STAT_RX_FRM_SEQ_ERR},
  50         {"rpm_rx_VLANReceivedOK", RPM_MTI_STAT_RX_VLAN_OK},
  51         {"rpm_rx_ifInErrors", RPM_MTI_STAT_RX_IN_ERR},
  52         {"rpm_rx_ifInUcastPkts", RPM_MTI_STAT_RX_IN_UCAST_PKT},
  53         {"rpm_rx_ifInMulticastPkts", RPM_MTI_STAT_RX_IN_MCAST_PKT},
  54         {"rpm_rx_ifInBroadcastPkts", RPM_MTI_STAT_RX_IN_BCAST_PKT},
  55         {"rpm_rx_etherStatsDropEvents", RPM_MTI_STAT_RX_DRP_EVENTS},
  56         {"rpm_rx_etherStatsPkts", RPM_MTI_STAT_RX_PKT},
  57         {"rpm_rx_etherStatsUndersizePkts", RPM_MTI_STAT_RX_UNDER_SIZE},
  58         {"rpm_rx_etherStatsPkts64Octets", RPM_MTI_STAT_RX_1_64_PKT_CNT},
  59         {"rpm_rx_etherStatsPkts65to127Octets", RPM_MTI_STAT_RX_65_127_PKT_CNT},
  60         {"rpm_rx_etherStatsPkts128to255Octets",
  61          RPM_MTI_STAT_RX_128_255_PKT_CNT},
  62         {"rpm_rx_etherStatsPkts256to511Octets",
  63          RPM_MTI_STAT_RX_256_511_PKT_CNT},
  64         {"rpm_rx_etherStatsPkts512to1023Octets",
  65          RPM_MTI_STAT_RX_512_1023_PKT_CNT},
  66         {"rpm_rx_etherStatsPkts1024to1518Octets",
  67          RPM_MTI_STAT_RX_1024_1518_PKT_CNT},
  68         {"rpm_rx_etherStatsPkts1519toMaxOctets",
  69          RPM_MTI_STAT_RX_1519_MAX_PKT_CNT},
  70         {"rpm_rx_etherStatsOversizePkts", RPM_MTI_STAT_RX_OVER_SIZE},
  71         {"rpm_rx_etherStatsJabbers", RPM_MTI_STAT_RX_JABBER},
  72         {"rpm_rx_etherStatsFragments", RPM_MTI_STAT_RX_ETH_FRAGS},
  73         {"rpm_rx_CBFC_pause_frames_class_0", RPM_MTI_STAT_RX_CBFC_CLASS_0},
  74         {"rpm_rx_CBFC_pause_frames_class_1", RPM_MTI_STAT_RX_CBFC_CLASS_1},
  75         {"rpm_rx_CBFC_pause_frames_class_2", RPM_MTI_STAT_RX_CBFC_CLASS_2},
  76         {"rpm_rx_CBFC_pause_frames_class_3", RPM_MTI_STAT_RX_CBFC_CLASS_3},
  77         {"rpm_rx_CBFC_pause_frames_class_4", RPM_MTI_STAT_RX_CBFC_CLASS_4},
  78         {"rpm_rx_CBFC_pause_frames_class_5", RPM_MTI_STAT_RX_CBFC_CLASS_5},
  79         {"rpm_rx_CBFC_pause_frames_class_6", RPM_MTI_STAT_RX_CBFC_CLASS_6},
  80         {"rpm_rx_CBFC_pause_frames_class_7", RPM_MTI_STAT_RX_CBFC_CLASS_7},
  81         {"rpm_rx_CBFC_pause_frames_class_8", RPM_MTI_STAT_RX_CBFC_CLASS_8},
  82         {"rpm_rx_CBFC_pause_frames_class_9", RPM_MTI_STAT_RX_CBFC_CLASS_9},
  83         {"rpm_rx_CBFC_pause_frames_class_10", RPM_MTI_STAT_RX_CBFC_CLASS_10},
  84         {"rpm_rx_CBFC_pause_frames_class_11", RPM_MTI_STAT_RX_CBFC_CLASS_11},
  85         {"rpm_rx_CBFC_pause_frames_class_12", RPM_MTI_STAT_RX_CBFC_CLASS_12},
  86         {"rpm_rx_CBFC_pause_frames_class_13", RPM_MTI_STAT_RX_CBFC_CLASS_13},
  87         {"rpm_rx_CBFC_pause_frames_class_14", RPM_MTI_STAT_RX_CBFC_CLASS_14},
  88         {"rpm_rx_CBFC_pause_frames_class_15", RPM_MTI_STAT_RX_CBFC_CLASS_15},
  89         {"rpm_rx_aMACControlFramesReceived", RPM_MTI_STAT_RX_MAC_CONTROL},
  90 };
  91
  92 static const struct cnxk_nix_xstats_name nix_tx_xstats_rpm[] = {
  93         {"rpm_tx_etherStatsOctets", RPM_MTI_STAT_TX_OCT_CNT},
  94         {"rpm_tx_OctetsTransmittedOK", RPM_MTI_STAT_TX_OCT_TX_OK},
  95         {"rpm_tx_aPAUSEMACCtrlFramesTransmitted",
  96          RPM_MTI_STAT_TX_PAUSE_MAC_CTRL},
  97         {"rpm_tx_aFramesTransmittedOK", RPM_MTI_STAT_TX_FRAMES_OK},
  98         {"rpm_tx_VLANTransmittedOK", RPM_MTI_STAT_TX_VLAN_OK},
  99         {"rpm_tx_ifOutErrors", RPM_MTI_STAT_TX_OUT_ERR},
 100         {"rpm_tx_ifOutUcastPkts", RPM_MTI_STAT_TX_UCAST_PKT_CNT},
 101         {"rpm_tx_ifOutMulticastPkts", RPM_MTI_STAT_TX_MCAST_PKT_CNT},
 102         {"rpm_tx_ifOutBroadcastPkts", RPM_MTI_STAT_TX_BCAST_PKT_CNT},
 103         {"rpm_tx_etherStatsPkts64Octets", RPM_MTI_STAT_TX_1_64_PKT_CNT},
 104         {"rpm_tx_etherStatsPkts65to127Octets", RPM_MTI_STAT_TX_65_127_PKT_CNT},
 105         {"rpm_tx_etherStatsPkts128to255Octets",
 106          RPM_MTI_STAT_TX_128_255_PKT_CNT},
 107         {"rpm_tx_etherStatsPkts256to511Octets",
 108          RPM_MTI_STAT_TX_256_511_PKT_CNT},
 109         {"rpm_tx_etherStatsPkts512to1023Octets",
 110          RPM_MTI_STAT_TX_512_1023_PKT_CNT},
 111         {"rpm_tx_etherStatsPkts1024to1518Octets",
 112          RPM_MTI_STAT_TX_1024_1518_PKT_CNT},
 113         {"rpm_tx_etherStatsPkts1519toMaxOctets",
 114          RPM_MTI_STAT_TX_1519_MAX_PKT_CNT},
 115         {"rpm_tx_CBFC_pause_frames_class_0", RPM_MTI_STAT_TX_CBFC_CLASS_0},
 116         {"rpm_tx_CBFC_pause_frames_class_1", RPM_MTI_STAT_TX_CBFC_CLASS_1},
 117         {"rpm_tx_CBFC_pause_frames_class_2", RPM_MTI_STAT_TX_CBFC_CLASS_2},
 118         {"rpm_tx_CBFC_pause_frames_class_3", RPM_MTI_STAT_TX_CBFC_CLASS_3},
 119         {"rpm_tx_CBFC_pause_frames_class_4", RPM_MTI_STAT_TX_CBFC_CLASS_4},
 120         {"rpm_tx_CBFC_pause_frames_class_5", RPM_MTI_STAT_TX_CBFC_CLASS_5},
 121         {"rpm_tx_CBFC_pause_frames_class_6", RPM_MTI_STAT_TX_CBFC_CLASS_6},
 122         {"rpm_tx_CBFC_pause_frames_class_7", RPM_MTI_STAT_TX_CBFC_CLASS_7},
 123         {"rpm_tx_CBFC_pause_frames_class_8", RPM_MTI_STAT_TX_CBFC_CLASS_8},
 124         {"rpm_tx_CBFC_pause_frames_class_9", RPM_MTI_STAT_TX_CBFC_CLASS_9},
 125         {"rpm_tx_CBFC_pause_frames_class_10", RPM_MTI_STAT_TX_CBFC_CLASS_10},
 126         {"rpm_tx_CBFC_pause_frames_class_11", RPM_MTI_STAT_TX_CBFC_CLASS_11},
 127         {"rpm_tx_CBFC_pause_frames_class_12", RPM_MTI_STAT_TX_CBFC_CLASS_12},
 128         {"rpm_tx_CBFC_pause_frames_class_13", RPM_MTI_STAT_TX_CBFC_CLASS_13},
 129         {"rpm_tx_CBFC_pause_frames_class_14", RPM_MTI_STAT_TX_CBFC_CLASS_14},
 130         {"rpm_tx_CBFC_pause_frames_class_15", RPM_MTI_STAT_TX_CBFC_CLASS_15},
 131         {"rpm_tx_aMACControlFramesTransmitted",
 132          RPM_MTI_STAT_TX_MAC_CONTROL_FRAMES},
 133         {"rpm_tx_etherStatsPkts", RPM_MTI_STAT_TX_PKT_CNT},
 134 };
 135
 136 static const struct cnxk_nix_xstats_name nix_rx_xstats_cgx[] = {
 137         {"cgx_rx_pkts", CGX_RX_PKT_CNT},
 138         {"cgx_rx_octs", CGX_RX_OCT_CNT},
 139         {"cgx_rx_pause_pkts", CGX_RX_PAUSE_PKT_CNT},
 140         {"cgx_rx_pause_octs", CGX_RX_PAUSE_OCT_CNT},
 141         {"cgx_rx_dmac_filt_pkts", CGX_RX_DMAC_FILT_PKT_CNT},
 142         {"cgx_rx_dmac_filt_octs", CGX_RX_DMAC_FILT_OCT_CNT},
 143         {"cgx_rx_fifo_drop_pkts", CGX_RX_FIFO_DROP_PKT_CNT},
 144         {"cgx_rx_fifo_drop_octs", CGX_RX_FIFO_DROP_OCT_CNT},
 145         {"cgx_rx_errors", CGX_RX_ERR_CNT},
 146 };
 147
 148 static const struct cnxk_nix_xstats_name nix_tx_xstats_cgx[] = {
 149         {"cgx_tx_collision_drop", CGX_TX_COLLISION_DROP},
 150         {"cgx_tx_frame_deferred_cnt", CGX_TX_FRAME_DEFER_CNT},
 151         {"cgx_tx_multiple_collision", CGX_TX_MULTIPLE_COLLISION},
 152         {"cgx_tx_single_collision", CGX_TX_SINGLE_COLLISION},
 153         {"cgx_tx_octs", CGX_TX_OCT_CNT},
 154         {"cgx_tx_pkts", CGX_TX_PKT_CNT},
 155         {"cgx_tx_1_to_63_oct_frames", CGX_TX_1_63_PKT_CNT},
 156         {"cgx_tx_64_oct_frames", CGX_TX_64_PKT_CNT},
 157         {"cgx_tx_65_to_127_oct_frames", CGX_TX_65_127_PKT_CNT},
 158         {"cgx_tx_128_to_255_oct_frames", CGX_TX_128_255_PKT_CNT},
 159         {"cgx_tx_256_to_511_oct_frames", CGX_TX_256_511_PKT_CNT},
 160         {"cgx_tx_512_to_1023_oct_frames", CGX_TX_512_1023_PKT_CNT},
 161         {"cgx_tx_1024_to_1518_oct_frames", CGX_TX_1024_1518_PKT_CNT},
 162         {"cgx_tx_1519_to_max_oct_frames", CGX_TX_1519_MAX_PKT_CNT},
 163         {"cgx_tx_broadcast_packets", CGX_TX_BCAST_PKTS},
 164         {"cgx_tx_multicast_packets", CGX_TX_MCAST_PKTS},
 165         {"cgx_tx_underflow_packets", CGX_TX_UFLOW_PKTS},
 166         {"cgx_tx_pause_packets", CGX_TX_PAUSE_PKTS},
 167 };
 168
 169 #define CNXK_NIX_NUM_RX_XSTATS     PLT_DIM(nix_rx_xstats)
 170 #define CNXK_NIX_NUM_TX_XSTATS     PLT_DIM(nix_tx_xstats)
 171 #define CNXK_NIX_NUM_QUEUE_XSTATS  PLT_DIM(nix_q_xstats)
 172 #define CNXK_NIX_NUM_RX_XSTATS_CGX PLT_DIM(nix_rx_xstats_cgx)
 173 #define CNXK_NIX_NUM_TX_XSTATS_CGX PLT_DIM(nix_tx_xstats_cgx)
 174 #define CNXK_NIX_NUM_RX_XSTATS_RPM PLT_DIM(nix_rx_xstats_rpm)
 175 #define CNXK_NIX_NUM_TX_XSTATS_RPM PLT_DIM(nix_tx_xstats_rpm)
 176
 177 #define CNXK_NIX_NUM_XSTATS_REG                                                \
 178         (CNXK_NIX_NUM_RX_XSTATS + CNXK_NIX_NUM_TX_XSTATS +                     \
 179          CNXK_NIX_NUM_QUEUE_XSTATS)
 180 #define CNXK_NIX_NUM_XSTATS_CGX                                                \
 181         (CNXK_NIX_NUM_XSTATS_REG + CNXK_NIX_NUM_RX_XSTATS_CGX +                \
 182          CNXK_NIX_NUM_TX_XSTATS_CGX)
 183 #define CNXK_NIX_NUM_XSTATS_RPM                                                \
 184         (CNXK_NIX_NUM_XSTATS_REG + CNXK_NIX_NUM_RX_XSTATS_RPM +                \
 185          CNXK_NIX_NUM_TX_XSTATS_RPM)
 186
 187 static inline uint64_t
 188 roc_nix_num_rx_xstats(void)
 189 {
 190         if (roc_model_is_cn9k())
 191                 return CNXK_NIX_NUM_RX_XSTATS_CGX;
 192
 193         return CNXK_NIX_NUM_RX_XSTATS_RPM;
 194 }
 195
 196 static inline uint64_t
 197 roc_nix_num_tx_xstats(void)
 198 {
 199         if (roc_model_is_cn9k())
 200                 return CNXK_NIX_NUM_TX_XSTATS_CGX;
 201
 202         return CNXK_NIX_NUM_TX_XSTATS_RPM;
 203 }
 204 #endif /* _ROC_NIX_XSTAT_H_ */