1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
9 roc_npa_aura_op_range_set(uint64_t aura_handle, uint64_t start_iova,
12 const uint64_t start = roc_npa_aura_handle_to_base(aura_handle) +
13 NPA_LF_POOL_OP_PTR_START0;
14 const uint64_t end = roc_npa_aura_handle_to_base(aura_handle) +
15 NPA_LF_POOL_OP_PTR_END0;
16 uint64_t reg = roc_npa_aura_handle_to_aura(aura_handle);
17 struct npa_lf *lf = idev_npa_obj_get();
18 struct npa_aura_lim *lim;
23 lim[reg].ptr_start = PLT_MIN(lim[reg].ptr_start, start_iova);
24 lim[reg].ptr_end = PLT_MAX(lim[reg].ptr_end, end_iova);
26 roc_store_pair(lim[reg].ptr_start, reg, start);
27 roc_store_pair(lim[reg].ptr_end, reg, end);
31 npa_aura_pool_init(struct mbox *mbox, uint32_t aura_id, struct npa_aura_s *aura,
32 struct npa_pool_s *pool)
34 struct npa_aq_enq_req *aura_init_req, *pool_init_req;
35 struct npa_aq_enq_rsp *aura_init_rsp, *pool_init_rsp;
36 struct mbox_dev *mdev = &mbox->dev[0];
37 int rc = -ENOSPC, off;
39 aura_init_req = mbox_alloc_msg_npa_aq_enq(mbox);
40 if (aura_init_req == NULL)
42 aura_init_req->aura_id = aura_id;
43 aura_init_req->ctype = NPA_AQ_CTYPE_AURA;
44 aura_init_req->op = NPA_AQ_INSTOP_INIT;
45 mbox_memcpy(&aura_init_req->aura, aura, sizeof(*aura));
47 pool_init_req = mbox_alloc_msg_npa_aq_enq(mbox);
48 if (pool_init_req == NULL)
50 pool_init_req->aura_id = aura_id;
51 pool_init_req->ctype = NPA_AQ_CTYPE_POOL;
52 pool_init_req->op = NPA_AQ_INSTOP_INIT;
53 mbox_memcpy(&pool_init_req->pool, pool, sizeof(*pool));
55 rc = mbox_process(mbox);
59 off = mbox->rx_start +
60 PLT_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);
61 aura_init_rsp = (struct npa_aq_enq_rsp *)((uintptr_t)mdev->mbase + off);
62 off = mbox->rx_start + aura_init_rsp->hdr.next_msgoff;
63 pool_init_rsp = (struct npa_aq_enq_rsp *)((uintptr_t)mdev->mbase + off);
65 if (aura_init_rsp->hdr.rc == 0 && pool_init_rsp->hdr.rc == 0)
68 return NPA_ERR_AURA_POOL_INIT;
72 npa_aura_pool_fini(struct mbox *mbox, uint32_t aura_id, uint64_t aura_handle)
74 struct npa_aq_enq_req *aura_req, *pool_req;
75 struct npa_aq_enq_rsp *aura_rsp, *pool_rsp;
76 struct mbox_dev *mdev = &mbox->dev[0];
77 struct ndc_sync_op *ndc_req;
78 int rc = -ENOSPC, off;
81 /* Procedure for disabling an aura/pool */
84 /* Clear all the pointers from the aura */
86 ptr = roc_npa_aura_op_alloc(aura_handle, 0);
89 pool_req = mbox_alloc_msg_npa_aq_enq(mbox);
92 pool_req->aura_id = aura_id;
93 pool_req->ctype = NPA_AQ_CTYPE_POOL;
94 pool_req->op = NPA_AQ_INSTOP_WRITE;
95 pool_req->pool.ena = 0;
96 pool_req->pool_mask.ena = ~pool_req->pool_mask.ena;
98 aura_req = mbox_alloc_msg_npa_aq_enq(mbox);
101 aura_req->aura_id = aura_id;
102 aura_req->ctype = NPA_AQ_CTYPE_AURA;
103 aura_req->op = NPA_AQ_INSTOP_WRITE;
104 aura_req->aura.ena = 0;
105 aura_req->aura_mask.ena = ~aura_req->aura_mask.ena;
107 rc = mbox_process(mbox);
111 off = mbox->rx_start +
112 PLT_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);
113 pool_rsp = (struct npa_aq_enq_rsp *)((uintptr_t)mdev->mbase + off);
115 off = mbox->rx_start + pool_rsp->hdr.next_msgoff;
116 aura_rsp = (struct npa_aq_enq_rsp *)((uintptr_t)mdev->mbase + off);
118 if (aura_rsp->hdr.rc != 0 || pool_rsp->hdr.rc != 0)
119 return NPA_ERR_AURA_POOL_FINI;
121 /* Sync NDC-NPA for LF */
122 ndc_req = mbox_alloc_msg_ndc_sync_op(mbox);
125 ndc_req->npa_lf_sync = 1;
126 rc = mbox_process(mbox);
128 plt_err("Error on NDC-NPA LF sync, rc %d", rc);
129 return NPA_ERR_AURA_POOL_FINI;
135 roc_npa_pool_op_pc_reset(uint64_t aura_handle)
137 struct npa_lf *lf = idev_npa_obj_get();
138 struct npa_aq_enq_req *pool_req;
139 struct npa_aq_enq_rsp *pool_rsp;
140 struct ndc_sync_op *ndc_req;
141 struct mbox_dev *mdev;
142 int rc = -ENOSPC, off;
146 return NPA_ERR_PARAM;
149 mdev = &mbox->dev[0];
150 plt_npa_dbg("lf=%p aura_handle=0x%" PRIx64, lf, aura_handle);
152 pool_req = mbox_alloc_msg_npa_aq_enq(mbox);
153 if (pool_req == NULL)
155 pool_req->aura_id = roc_npa_aura_handle_to_aura(aura_handle);
156 pool_req->ctype = NPA_AQ_CTYPE_POOL;
157 pool_req->op = NPA_AQ_INSTOP_WRITE;
158 pool_req->pool.op_pc = 0;
159 pool_req->pool_mask.op_pc = ~pool_req->pool_mask.op_pc;
161 rc = mbox_process(mbox);
165 off = mbox->rx_start +
166 PLT_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);
167 pool_rsp = (struct npa_aq_enq_rsp *)((uintptr_t)mdev->mbase + off);
169 if (pool_rsp->hdr.rc != 0)
170 return NPA_ERR_AURA_POOL_FINI;
172 /* Sync NDC-NPA for LF */
173 ndc_req = mbox_alloc_msg_ndc_sync_op(mbox);
176 ndc_req->npa_lf_sync = 1;
177 rc = mbox_process(mbox);
179 plt_err("Error on NDC-NPA LF sync, rc %d", rc);
180 return NPA_ERR_AURA_POOL_FINI;
185 npa_stack_memzone_name(struct npa_lf *lf, int pool_id, char *name)
187 snprintf(name, PLT_MEMZONE_NAMESIZE, "roc_npa_stack_%x_%d", lf->pf_func,
192 static inline const struct plt_memzone *
193 npa_stack_dma_alloc(struct npa_lf *lf, char *name, int pool_id, size_t size)
195 const char *mz_name = npa_stack_memzone_name(lf, pool_id, name);
197 return plt_memzone_reserve_aligned(mz_name, size, 0, ROC_ALIGN);
201 npa_stack_dma_free(struct npa_lf *lf, char *name, int pool_id)
203 const struct plt_memzone *mz;
205 mz = plt_memzone_lookup(npa_stack_memzone_name(lf, pool_id, name));
207 return NPA_ERR_PARAM;
209 return plt_memzone_free(mz);
213 bitmap_ctzll(uint64_t slab)
218 return __builtin_ctzll(slab);
222 npa_aura_pool_pair_alloc(struct npa_lf *lf, const uint32_t block_size,
223 const uint32_t block_count, struct npa_aura_s *aura,
224 struct npa_pool_s *pool, uint64_t *aura_handle)
226 int rc, aura_id, pool_id, stack_size, alloc_size;
227 char name[PLT_MEMZONE_NAMESIZE];
228 const struct plt_memzone *mz;
233 if (!lf || !block_size || !block_count || !pool || !aura ||
235 return NPA_ERR_PARAM;
237 /* Block size should be cache line aligned and in range of 128B-128KB */
238 if (block_size % ROC_ALIGN || block_size < 128 ||
239 block_size > ROC_NPA_MAX_BLOCK_SZ)
240 return NPA_ERR_INVALID_BLOCK_SZ;
244 /* Scan from the beginning */
245 plt_bitmap_scan_init(lf->npa_bmp);
246 /* Scan bitmap to get the free pool */
247 rc = plt_bitmap_scan(lf->npa_bmp, &pos, &slab);
250 plt_err("Mempools exhausted");
251 return NPA_ERR_AURA_ID_ALLOC;
254 /* Get aura_id from resource bitmap */
255 aura_id = pos + bitmap_ctzll(slab);
256 /* Mark pool as reserved */
257 plt_bitmap_clear(lf->npa_bmp, aura_id);
259 /* Configuration based on each aura has separate pool(aura-pool pair) */
261 rc = (aura_id < 0 || pool_id >= (int)lf->nr_pools ||
262 aura_id >= (int)BIT_ULL(6 + lf->aura_sz)) ?
263 NPA_ERR_AURA_ID_ALLOC :
268 /* Allocate stack memory */
269 stack_size = (block_count + lf->stack_pg_ptrs - 1) / lf->stack_pg_ptrs;
270 alloc_size = stack_size * lf->stack_pg_bytes;
272 mz = npa_stack_dma_alloc(lf, name, pool_id, alloc_size);
278 /* Update aura fields */
279 aura->pool_addr = pool_id; /* AF will translate to associated poolctx */
281 aura->shift = plt_log2_u32(block_count);
282 aura->shift = aura->shift < 8 ? 0 : aura->shift - 8;
283 aura->limit = block_count;
284 aura->pool_caching = 1;
285 aura->err_int_ena = BIT(NPA_AURA_ERR_INT_AURA_ADD_OVER);
286 aura->err_int_ena |= BIT(NPA_AURA_ERR_INT_AURA_ADD_UNDER);
287 aura->err_int_ena |= BIT(NPA_AURA_ERR_INT_AURA_FREE_UNDER);
288 aura->err_int_ena |= BIT(NPA_AURA_ERR_INT_POOL_DIS);
289 aura->avg_con = ROC_NPA_AVG_CONT;
290 /* Many to one reduction */
291 aura->err_qint_idx = aura_id % lf->qints;
293 /* Update pool fields */
294 pool->stack_base = mz->iova;
296 pool->buf_size = block_size / ROC_ALIGN;
297 pool->stack_max_pages = stack_size;
298 pool->shift = plt_log2_u32(block_count);
299 pool->shift = pool->shift < 8 ? 0 : pool->shift - 8;
302 pool->stack_caching = 1;
303 pool->err_int_ena = BIT(NPA_POOL_ERR_INT_OVFLS);
304 pool->err_int_ena |= BIT(NPA_POOL_ERR_INT_RANGE);
305 pool->err_int_ena |= BIT(NPA_POOL_ERR_INT_PERR);
306 pool->avg_con = ROC_NPA_AVG_CONT;
308 /* Many to one reduction */
309 pool->err_qint_idx = pool_id % lf->qints;
311 /* Issue AURA_INIT and POOL_INIT op */
312 rc = npa_aura_pool_init(lf->mbox, aura_id, aura, pool);
316 *aura_handle = roc_npa_aura_handle_gen(aura_id, lf->base);
317 /* Update aura count */
318 roc_npa_aura_op_cnt_set(*aura_handle, 0, block_count);
319 /* Read it back to make sure aura count is updated */
320 roc_npa_aura_op_cnt_get(*aura_handle);
325 plt_memzone_free(mz);
327 plt_bitmap_set(lf->npa_bmp, aura_id);
333 roc_npa_pool_create(uint64_t *aura_handle, uint32_t block_size,
334 uint32_t block_count, struct npa_aura_s *aura,
335 struct npa_pool_s *pool)
337 struct npa_aura_s defaura;
338 struct npa_pool_s defpool;
339 struct idev_cfg *idev;
343 lf = idev_npa_obj_get();
345 rc = NPA_ERR_DEVICE_NOT_BOUNDED;
349 idev = idev_get_cfg();
356 memset(&defaura, 0, sizeof(struct npa_aura_s));
360 memset(&defpool, 0, sizeof(struct npa_pool_s));
361 defpool.nat_align = 1;
362 defpool.buf_offset = 1;
366 rc = npa_aura_pool_pair_alloc(lf, block_size, block_count, aura, pool,
369 plt_err("Failed to alloc pool or aura rc=%d", rc);
373 plt_npa_dbg("lf=%p block_sz=%d block_count=%d aura_handle=0x%" PRIx64,
374 lf, block_size, block_count, *aura_handle);
376 /* Just hold the reference of the object */
377 __atomic_fetch_add(&idev->npa_refcnt, 1, __ATOMIC_SEQ_CST);
383 roc_npa_aura_limit_modify(uint64_t aura_handle, uint16_t aura_limit)
385 struct npa_aq_enq_req *aura_req;
389 lf = idev_npa_obj_get();
391 return NPA_ERR_DEVICE_NOT_BOUNDED;
393 aura_req = mbox_alloc_msg_npa_aq_enq(lf->mbox);
394 if (aura_req == NULL)
396 aura_req->aura_id = roc_npa_aura_handle_to_aura(aura_handle);
397 aura_req->ctype = NPA_AQ_CTYPE_AURA;
398 aura_req->op = NPA_AQ_INSTOP_WRITE;
400 aura_req->aura.limit = aura_limit;
401 aura_req->aura_mask.limit = ~(aura_req->aura_mask.limit);
402 rc = mbox_process(lf->mbox);
408 npa_aura_pool_pair_free(struct npa_lf *lf, uint64_t aura_handle)
410 char name[PLT_MEMZONE_NAMESIZE];
411 int aura_id, pool_id, rc;
413 if (!lf || !aura_handle)
414 return NPA_ERR_PARAM;
416 aura_id = roc_npa_aura_handle_to_aura(aura_handle);
418 rc = npa_aura_pool_fini(lf->mbox, aura_id, aura_handle);
419 rc |= npa_stack_dma_free(lf, name, pool_id);
421 plt_bitmap_set(lf->npa_bmp, aura_id);
427 roc_npa_pool_destroy(uint64_t aura_handle)
429 struct npa_lf *lf = idev_npa_obj_get();
432 plt_npa_dbg("lf=%p aura_handle=0x%" PRIx64, lf, aura_handle);
433 rc = npa_aura_pool_pair_free(lf, aura_handle);
435 plt_err("Failed to destroy pool or aura rc=%d", rc);
437 /* Release the reference of npa */
443 roc_npa_pool_range_update_check(uint64_t aura_handle)
445 uint64_t aura_id = roc_npa_aura_handle_to_aura(aura_handle);
447 struct npa_aura_lim *lim;
448 __io struct npa_pool_s *pool;
449 struct npa_aq_enq_req *req;
450 struct npa_aq_enq_rsp *rsp;
453 lf = idev_npa_obj_get();
455 return NPA_ERR_PARAM;
459 req = mbox_alloc_msg_npa_aq_enq(lf->mbox);
463 req->aura_id = aura_id;
464 req->ctype = NPA_AQ_CTYPE_POOL;
465 req->op = NPA_AQ_INSTOP_READ;
467 rc = mbox_process_msg(lf->mbox, (void *)&rsp);
469 plt_err("Failed to get pool(0x%" PRIx64 ") context", aura_id);
474 if (lim[aura_id].ptr_start != pool->ptr_start ||
475 lim[aura_id].ptr_end != pool->ptr_end) {
476 plt_err("Range update failed on pool(0x%" PRIx64 ")", aura_id);
477 return NPA_ERR_PARAM;
484 npa_attach(struct mbox *mbox)
486 struct rsrc_attach_req *req;
488 req = mbox_alloc_msg_attach_resources(mbox);
494 return mbox_process(mbox);
498 npa_detach(struct mbox *mbox)
500 struct rsrc_detach_req *req;
502 req = mbox_alloc_msg_detach_resources(mbox);
508 return mbox_process(mbox);
512 npa_get_msix_offset(struct mbox *mbox, uint16_t *npa_msixoff)
514 struct msix_offset_rsp *msix_rsp;
517 /* Get NPA MSIX vector offsets */
518 mbox_alloc_msg_msix_offset(mbox);
519 rc = mbox_process_msg(mbox, (void *)&msix_rsp);
521 *npa_msixoff = msix_rsp->npa_msixoff;
527 npa_lf_alloc(struct npa_lf *lf)
529 struct mbox *mbox = lf->mbox;
530 struct npa_lf_alloc_req *req;
531 struct npa_lf_alloc_rsp *rsp;
534 req = mbox_alloc_msg_npa_lf_alloc(mbox);
537 req->aura_sz = lf->aura_sz;
538 req->nr_pools = lf->nr_pools;
540 rc = mbox_process_msg(mbox, (void *)&rsp);
542 return NPA_ERR_ALLOC;
544 lf->stack_pg_ptrs = rsp->stack_pg_ptrs;
545 lf->stack_pg_bytes = rsp->stack_pg_bytes;
546 lf->qints = rsp->qints;
552 npa_lf_free(struct mbox *mbox)
554 mbox_alloc_msg_npa_lf_free(mbox);
555 return mbox_process(mbox);
558 static inline uint32_t
559 aura_size_to_u32(uint8_t val)
561 if (val == NPA_AURA_SZ_0)
563 if (val >= NPA_AURA_SZ_MAX)
566 return 1 << (val + 6);
570 pool_count_aura_sz_get(uint32_t *nr_pools, uint8_t *aura_sz)
574 val = roc_idev_npa_maxpools_get();
575 if (val < aura_size_to_u32(NPA_AURA_SZ_128))
577 if (val > aura_size_to_u32(NPA_AURA_SZ_1M))
580 roc_idev_npa_maxpools_set(val);
582 *aura_sz = plt_log2_u32(val) - 6;
586 npa_dev_init(struct npa_lf *lf, uintptr_t base, struct mbox *mbox)
588 uint32_t i, bmp_sz, nr_pools;
593 if (!lf || !base || !mbox)
594 return NPA_ERR_PARAM;
596 if (base & ROC_AURA_ID_MASK)
597 return NPA_ERR_BASE_INVALID;
599 pool_count_aura_sz_get(&nr_pools, &aura_sz);
600 if (aura_sz == NPA_AURA_SZ_0 || aura_sz >= NPA_AURA_SZ_MAX)
601 return NPA_ERR_PARAM;
603 memset(lf, 0x0, sizeof(*lf));
605 lf->aura_sz = aura_sz;
606 lf->nr_pools = nr_pools;
609 rc = npa_lf_alloc(lf);
613 bmp_sz = plt_bitmap_get_memory_footprint(nr_pools);
615 /* Allocate memory for bitmap */
616 lf->npa_bmp_mem = plt_zmalloc(bmp_sz, ROC_ALIGN);
617 if (lf->npa_bmp_mem == NULL) {
622 /* Initialize pool resource bitmap array */
623 lf->npa_bmp = plt_bitmap_init(nr_pools, lf->npa_bmp_mem, bmp_sz);
624 if (lf->npa_bmp == NULL) {
629 /* Mark all pools available */
630 for (i = 0; i < nr_pools; i++)
631 plt_bitmap_set(lf->npa_bmp, i);
633 /* Allocate memory for qint context */
634 lf->npa_qint_mem = plt_zmalloc(sizeof(struct npa_qint) * nr_pools, 0);
635 if (lf->npa_qint_mem == NULL) {
640 /* Allocate memory for nap_aura_lim memory */
641 lf->aura_lim = plt_zmalloc(sizeof(struct npa_aura_lim) * nr_pools, 0);
642 if (lf->aura_lim == NULL) {
647 /* Init aura start & end limits */
648 for (i = 0; i < nr_pools; i++) {
649 lf->aura_lim[i].ptr_start = UINT64_MAX;
650 lf->aura_lim[i].ptr_end = 0x0ull;
656 plt_free(lf->npa_qint_mem);
658 plt_bitmap_free(lf->npa_bmp);
660 plt_free(lf->npa_bmp_mem);
662 npa_lf_free(lf->mbox);
668 npa_dev_fini(struct npa_lf *lf)
671 return NPA_ERR_PARAM;
673 plt_free(lf->aura_lim);
674 plt_free(lf->npa_qint_mem);
675 plt_bitmap_free(lf->npa_bmp);
676 plt_free(lf->npa_bmp_mem);
678 return npa_lf_free(lf->mbox);
682 npa_lf_init(struct dev *dev, struct plt_pci_device *pci_dev)
684 struct idev_cfg *idev;
685 uint16_t npa_msixoff;
689 idev = idev_get_cfg();
691 return NPA_ERR_ALLOC;
693 /* Not the first PCI device */
694 if (__atomic_fetch_add(&idev->npa_refcnt, 1, __ATOMIC_SEQ_CST) != 0)
697 rc = npa_attach(dev->mbox);
701 rc = npa_get_msix_offset(dev->mbox, &npa_msixoff);
706 rc = npa_dev_init(lf, dev->bar2 + (RVU_BLOCK_ADDR_NPA << 20),
711 lf->pf_func = dev->pf_func;
712 lf->npa_msixoff = npa_msixoff;
713 lf->intr_handle = pci_dev->intr_handle;
714 lf->pci_dev = pci_dev;
716 idev->npa_pf_func = dev->pf_func;
720 rc = npa_register_irqs(lf);
724 plt_npa_dbg("npa=%p max_pools=%d pf_func=0x%x msix=0x%x", lf,
725 roc_idev_npa_maxpools_get(), lf->pf_func, npa_msixoff);
730 npa_dev_fini(idev->npa);
732 npa_detach(dev->mbox);
734 __atomic_fetch_sub(&idev->npa_refcnt, 1, __ATOMIC_SEQ_CST);
741 struct idev_cfg *idev;
744 idev = idev_get_cfg();
746 return NPA_ERR_ALLOC;
748 /* Not the last PCI device */
749 if (__atomic_sub_fetch(&idev->npa_refcnt, 1, __ATOMIC_SEQ_CST) != 0)
752 npa_unregister_irqs(idev->npa);
753 rc |= npa_dev_fini(idev->npa);
754 rc |= npa_detach(idev->npa->mbox);
755 idev_set_defaults(idev);
761 roc_npa_dev_init(struct roc_npa *roc_npa)
763 struct plt_pci_device *pci_dev;
768 if (roc_npa == NULL || roc_npa->pci_dev == NULL)
769 return NPA_ERR_PARAM;
771 PLT_STATIC_ASSERT(sizeof(struct npa) <= ROC_NPA_MEM_SZ);
772 npa = roc_npa_to_npa_priv(roc_npa);
773 memset(npa, 0, sizeof(*npa));
774 pci_dev = roc_npa->pci_dev;
777 /* Initialize device */
778 rc = dev_init(dev, pci_dev);
780 plt_err("Failed to init roc device");
784 npa->pci_dev = pci_dev;
785 dev->drv_inited = true;
791 roc_npa_dev_fini(struct roc_npa *roc_npa)
793 struct npa *npa = roc_npa_to_npa_priv(roc_npa);
796 return NPA_ERR_PARAM;
798 npa->dev.drv_inited = false;
799 return dev_fini(&npa->dev, npa->pci_dev);