1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
5 #ifndef _ROC_PLATFORM_H_
6 #define _ROC_PLATFORM_H_
9 #include <rte_bitmap.h>
10 #include <rte_bus_pci.h>
11 #include <rte_byteorder.h>
12 #include <rte_common.h>
13 #include <rte_cycles.h>
14 #include <rte_interrupts.h>
17 #include <rte_malloc.h>
18 #include <rte_memzone.h>
20 #include <rte_spinlock.h>
21 #include <rte_string_fns.h>
25 #if defined(__ARM_FEATURE_SVE)
26 #define PLT_CPU_FEATURE_PREAMBLE ".cpu generic+crc+lse+sve\n"
28 #define PLT_CPU_FEATURE_PREAMBLE ".cpu generic+crc+lse\n"
31 #define PLT_ASSERT RTE_ASSERT
32 #define PLT_MEMZONE_NAMESIZE RTE_MEMZONE_NAMESIZE
33 #define PLT_STD_C11 RTE_STD_C11
34 #define PLT_PTR_ADD RTE_PTR_ADD
35 #define PLT_MAX_RXTX_INTR_VEC_ID RTE_MAX_RXTX_INTR_VEC_ID
36 #define PLT_INTR_VEC_RXTX_OFFSET RTE_INTR_VEC_RXTX_OFFSET
37 #define PLT_MIN RTE_MIN
38 #define PLT_MAX RTE_MAX
39 #define PLT_DIM RTE_DIM
40 #define PLT_SET_USED RTE_SET_USED
41 #define PLT_STATIC_ASSERT(s) _Static_assert(s, #s)
42 #define PLT_ALIGN RTE_ALIGN
43 #define PLT_ALIGN_MUL_CEIL RTE_ALIGN_MUL_CEIL
44 #define PLT_MODEL_MZ_NAME "roc_model_mz"
45 #define PLT_CACHE_LINE_SIZE RTE_CACHE_LINE_SIZE
46 #define BITMASK_ULL GENMASK_ULL
49 #define PLT_DIV_CEIL(x, y) \
51 __typeof(x) __x = x; \
52 __typeof(y) __y = y; \
53 (__x + __y - 1) / __y; \
56 #define __plt_cache_aligned __rte_cache_aligned
57 #define __plt_always_inline __rte_always_inline
58 #define __plt_packed __rte_packed
59 #define __roc_api __rte_internal
60 #define plt_iova_t rte_iova_t
62 #define plt_pci_device rte_pci_device
63 #define plt_pci_read_config rte_pci_read_config
64 #define plt_pci_find_ext_capability rte_pci_find_ext_capability
66 #define plt_log2_u32 rte_log2_u32
67 #define plt_cpu_to_be_16 rte_cpu_to_be_16
68 #define plt_be_to_cpu_16 rte_be_to_cpu_16
69 #define plt_cpu_to_be_32 rte_cpu_to_be_32
70 #define plt_be_to_cpu_32 rte_be_to_cpu_32
71 #define plt_cpu_to_be_64 rte_cpu_to_be_64
72 #define plt_be_to_cpu_64 rte_be_to_cpu_64
74 #define plt_align32prevpow2 rte_align32prevpow2
76 #define plt_bitmap rte_bitmap
77 #define plt_bitmap_init rte_bitmap_init
78 #define plt_bitmap_reset rte_bitmap_reset
79 #define plt_bitmap_free rte_bitmap_free
80 #define plt_bitmap_clear rte_bitmap_clear
81 #define plt_bitmap_set rte_bitmap_set
82 #define plt_bitmap_get rte_bitmap_get
83 #define plt_bitmap_scan_init __rte_bitmap_scan_init
84 #define plt_bitmap_scan rte_bitmap_scan
85 #define plt_bitmap_get_memory_footprint rte_bitmap_get_memory_footprint
87 #define plt_spinlock_t rte_spinlock_t
88 #define plt_spinlock_init rte_spinlock_init
89 #define plt_spinlock_lock rte_spinlock_lock
90 #define plt_spinlock_unlock rte_spinlock_unlock
92 #define plt_intr_callback_register rte_intr_callback_register
93 #define plt_intr_callback_unregister rte_intr_callback_unregister
94 #define plt_intr_disable rte_intr_disable
95 #define plt_thread_is_intr rte_thread_is_intr
96 #define plt_intr_callback_fn rte_intr_callback_fn
98 #define plt_alarm_set rte_eal_alarm_set
99 #define plt_alarm_cancel rte_eal_alarm_cancel
101 #define plt_intr_handle rte_intr_handle
103 #define plt_zmalloc(sz, align) rte_zmalloc("cnxk", sz, align)
104 #define plt_free rte_free
106 #define plt_read64(addr) rte_read64_relaxed((volatile void *)(addr))
107 #define plt_write64(val, addr) \
108 rte_write64_relaxed((val), (volatile void *)(addr))
110 #define plt_wmb() rte_wmb()
111 #define plt_rmb() rte_rmb()
112 #define plt_io_wmb() rte_io_wmb()
113 #define plt_io_rmb() rte_io_rmb()
115 #define plt_mmap mmap
116 #define PLT_PROT_READ PROT_READ
117 #define PLT_PROT_WRITE PROT_WRITE
118 #define PLT_MAP_SHARED MAP_SHARED
120 #define plt_memzone rte_memzone
121 #define plt_memzone_lookup rte_memzone_lookup
122 #define plt_memzone_reserve_cache_align(name, sz) \
123 rte_memzone_reserve_aligned(name, sz, 0, 0, RTE_CACHE_LINE_SIZE)
124 #define plt_memzone_free rte_memzone_free
126 #define plt_tsc_hz rte_get_tsc_hz
127 #define plt_delay_ms rte_delay_ms
128 #define plt_delay_us rte_delay_us
130 #define plt_lcore_id rte_lcore_id
132 #define plt_strlcpy rte_strlcpy
135 extern int cnxk_logtype_base;
136 extern int cnxk_logtype_mbox;
137 extern int cnxk_logtype_npa;
138 extern int cnxk_logtype_nix;
139 extern int cnxk_logtype_npc;
140 extern int cnxk_logtype_sso;
141 extern int cnxk_logtype_tim;
142 extern int cnxk_logtype_tm;
144 #define plt_err(fmt, args...) \
145 RTE_LOG(ERR, PMD, "%s():%u " fmt "\n", __func__, __LINE__, ##args)
146 #define plt_info(fmt, args...) RTE_LOG(INFO, PMD, fmt "\n", ##args)
147 #define plt_warn(fmt, args...) RTE_LOG(WARNING, PMD, fmt "\n", ##args)
148 #define plt_print(fmt, args...) RTE_LOG(INFO, PMD, fmt "\n", ##args)
151 * Log debug message if given subsystem logging is enabled.
153 #define plt_dbg(subsystem, fmt, args...) \
154 rte_log(RTE_LOG_DEBUG, cnxk_logtype_##subsystem, \
155 "[%s] %s():%u " fmt "\n", #subsystem, __func__, __LINE__, \
158 #define plt_base_dbg(fmt, ...) plt_dbg(base, fmt, ##__VA_ARGS__)
159 #define plt_mbox_dbg(fmt, ...) plt_dbg(mbox, fmt, ##__VA_ARGS__)
160 #define plt_npa_dbg(fmt, ...) plt_dbg(npa, fmt, ##__VA_ARGS__)
161 #define plt_nix_dbg(fmt, ...) plt_dbg(nix, fmt, ##__VA_ARGS__)
162 #define plt_npc_dbg(fmt, ...) plt_dbg(npc, fmt, ##__VA_ARGS__)
163 #define plt_sso_dbg(fmt, ...) plt_dbg(sso, fmt, ##__VA_ARGS__)
164 #define plt_tim_dbg(fmt, ...) plt_dbg(tim, fmt, ##__VA_ARGS__)
165 #define plt_tm_dbg(fmt, ...) plt_dbg(tm, fmt, ##__VA_ARGS__)
168 #define CNXK_PCI_ID(subsystem_dev, dev) \
170 RTE_CLASS_ANY_ID, PCI_VENDOR_ID_CAVIUM, (dev), RTE_PCI_ANY_ID, \
174 #define CNXK_PCI_ID(subsystem_dev, dev) \
176 .class_id = RTE_CLASS_ANY_ID, \
177 .vendor_id = PCI_VENDOR_ID_CAVIUM, .device_id = (dev), \
178 .subsystem_vendor_id = RTE_PCI_ANY_ID, \
179 .subsystem_device_id = (subsystem_dev), \
184 int roc_plt_init(void);
187 typedef int (*roc_plt_init_cb_t)(void);
188 int __roc_api roc_plt_init_cb_register(roc_plt_init_cb_t cb);
190 #endif /* _ROC_PLATFORM_H_ */