1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
9 sso_hwgrp_irq(void *param)
11 struct sso_rsrc *rsrc = param;
14 intr = plt_read64(rsrc->base + SSO_LF_GGRP_INT);
18 plt_err("GGRP %d GGRP_INT=0x%" PRIx64 "", rsrc->rsrc_id, intr);
21 plt_write64(intr, rsrc->base + SSO_LF_GGRP_INT);
25 sso_hwgrp_register_irq(struct plt_intr_handle *handle, uint16_t ggrp_msixoff,
26 struct sso_rsrc *rsrc)
30 vec = ggrp_msixoff + SSO_LF_INT_VEC_GRP;
32 /* Clear err interrupt */
33 plt_write64(~0ull, rsrc->base + SSO_LF_GGRP_INT_ENA_W1C);
34 /* Set used interrupt vectors */
35 rc = dev_irq_register(handle, sso_hwgrp_irq, (void *)rsrc, vec);
36 /* Enable hw interrupt */
37 plt_write64(~0ull, rsrc->base + SSO_LF_GGRP_INT_ENA_W1S);
43 sso_hws_irq(void *param)
45 struct sso_rsrc *rsrc = param;
48 intr = plt_read64(rsrc->base + SSOW_LF_GWS_INT);
52 plt_err("GWS %d GWS_INT=0x%" PRIx64 "", rsrc->rsrc_id, intr);
55 plt_write64(intr, rsrc->base + SSOW_LF_GWS_INT);
59 sso_hws_register_irq(struct plt_intr_handle *handle, uint16_t hws_msixoff,
60 struct sso_rsrc *rsrc)
64 vec = hws_msixoff + SSOW_LF_INT_VEC_IOP;
66 /* Clear err interrupt */
67 plt_write64(~0ull, rsrc->base + SSOW_LF_GWS_INT_ENA_W1C);
68 /* Set used interrupt vectors */
69 rc = dev_irq_register(handle, sso_hws_irq, (void *)rsrc, vec);
70 /* Enable hw interrupt */
71 plt_write64(~0ull, rsrc->base + SSOW_LF_GWS_INT_ENA_W1S);
77 sso_register_irqs_priv(struct roc_sso *roc_sso, struct plt_intr_handle *handle,
78 uint16_t nb_hws, uint16_t nb_hwgrp)
80 struct sso *sso = roc_sso_to_sso_priv(roc_sso);
81 struct dev *dev = &sso->dev;
82 int i, rc = SSO_ERR_PARAM;
84 for (i = 0; i < nb_hws; i++) {
85 if (sso->hws_msix_offset[i] == MSIX_VECTOR_INVALID) {
86 plt_err("Invalid SSO HWS MSIX offset[%d] vector 0x%x",
87 i, sso->hws_msix_offset[i]);
92 for (i = 0; i < nb_hwgrp; i++) {
93 if (sso->hwgrp_msix_offset[i] == MSIX_VECTOR_INVALID) {
94 plt_err("Invalid SSO HWGRP MSIX offset[%d] vector 0x%x",
95 i, sso->hwgrp_msix_offset[i]);
100 for (i = 0; i < nb_hws; i++) {
102 dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | i << 12);
104 sso->hws_rsrc[i].rsrc_id = i;
105 sso->hws_rsrc[i].base = base;
106 rc = sso_hws_register_irq(handle, sso->hws_msix_offset[i],
110 for (i = 0; i < nb_hwgrp; i++) {
112 dev->bar2 + (RVU_BLOCK_ADDR_SSO << 20 | i << 12);
114 sso->hwgrp_rsrc[i].rsrc_id = i;
115 sso->hwgrp_rsrc[i].base = base;
116 rc = sso_hwgrp_register_irq(handle, sso->hwgrp_msix_offset[i],
117 &sso->hwgrp_rsrc[i]);
124 sso_hwgrp_unregister_irq(struct plt_intr_handle *handle, uint16_t ggrp_msixoff,
125 struct sso_rsrc *rsrc)
129 vec = ggrp_msixoff + SSO_LF_INT_VEC_GRP;
131 /* Clear err interrupt */
132 plt_write64(~0ull, rsrc->base + SSO_LF_GGRP_INT_ENA_W1C);
133 dev_irq_unregister(handle, sso_hwgrp_irq, (void *)rsrc, vec);
137 sso_hws_unregister_irq(struct plt_intr_handle *handle, uint16_t gws_msixoff,
138 struct sso_rsrc *rsrc)
142 vec = gws_msixoff + SSOW_LF_INT_VEC_IOP;
144 /* Clear err interrupt */
145 plt_write64(~0ull, rsrc->base + SSOW_LF_GWS_INT_ENA_W1C);
146 dev_irq_unregister(handle, sso_hws_irq, (void *)rsrc, vec);
150 sso_unregister_irqs_priv(struct roc_sso *roc_sso,
151 struct plt_intr_handle *handle, uint16_t nb_hws,
154 struct sso *sso = roc_sso_to_sso_priv(roc_sso);
157 for (i = 0; i < nb_hwgrp; i++)
158 sso_hwgrp_unregister_irq(handle, sso->hwgrp_msix_offset[i],
159 &sso->hwgrp_rsrc[i]);
161 for (i = 0; i < nb_hws; i++)
162 sso_hws_unregister_irq(handle, sso->hws_msix_offset[i],