1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
9 tim_fill_msix(struct roc_tim *roc_tim, uint16_t nb_ring)
11 struct dev *dev = &roc_sso_to_sso_priv(roc_tim->roc_sso)->dev;
12 struct tim *tim = roc_tim_to_tim_priv(roc_tim);
13 struct msix_offset_rsp *rsp;
16 mbox_alloc_msg_msix_offset(dev->mbox);
17 rc = mbox_process_msg(dev->mbox, (void **)&rsp);
21 for (i = 0; i < nb_ring; i++)
22 tim->tim_msix_offsets[i] = rsp->timlf_msixoff[i];
31 case TIM_AF_NO_RINGS_LEFT:
32 plt_err("Unable to allocate new TIM ring.");
34 case TIM_AF_INVALID_NPA_PF_FUNC:
35 plt_err("Invalid NPA pf func.");
37 case TIM_AF_INVALID_SSO_PF_FUNC:
38 plt_err("Invalid SSO pf func.");
40 case TIM_AF_RING_STILL_RUNNING:
41 plt_err("Ring busy.");
43 case TIM_AF_LF_INVALID:
44 plt_err("Invalid Ring id.");
46 case TIM_AF_CSIZE_NOT_ALIGNED:
47 plt_err("Chunk size specified needs to be multiple of 16.");
49 case TIM_AF_CSIZE_TOO_SMALL:
50 plt_err("Chunk size too small.");
52 case TIM_AF_CSIZE_TOO_BIG:
53 plt_err("Chunk size too big.");
55 case TIM_AF_INTERVAL_TOO_SMALL:
56 plt_err("Bucket traversal interval too small.");
58 case TIM_AF_INVALID_BIG_ENDIAN_VALUE:
59 plt_err("Invalid Big endian value.");
61 case TIM_AF_INVALID_CLOCK_SOURCE:
62 plt_err("Invalid Clock source specified.");
64 case TIM_AF_GPIO_CLK_SRC_NOT_ENABLED:
65 plt_err("GPIO clock source not enabled.");
67 case TIM_AF_INVALID_BSIZE:
68 plt_err("Invalid bucket size.");
70 case TIM_AF_INVALID_ENABLE_PERIODIC:
71 plt_err("Invalid bucket size.");
73 case TIM_AF_INVALID_ENABLE_DONTFREE:
74 plt_err("Invalid Don't free value.");
76 case TIM_AF_ENA_DONTFRE_NSET_PERIODIC:
77 plt_err("Don't free bit not set when periodic is enabled.");
79 case TIM_AF_RING_ALREADY_DISABLED:
80 plt_err("Ring already stopped");
83 plt_err("Unknown Error.");
88 roc_tim_lf_enable(struct roc_tim *roc_tim, uint8_t ring_id, uint64_t *start_tsc,
91 struct dev *dev = &roc_sso_to_sso_priv(roc_tim->roc_sso)->dev;
92 struct tim_enable_rsp *rsp;
93 struct tim_ring_req *req;
96 req = mbox_alloc_msg_tim_enable_ring(dev->mbox);
101 rc = mbox_process_msg(dev->mbox, (void **)&rsp);
108 *cur_bkt = rsp->currentbucket;
110 *start_tsc = rsp->timestarted;
116 roc_tim_lf_disable(struct roc_tim *roc_tim, uint8_t ring_id)
118 struct dev *dev = &roc_sso_to_sso_priv(roc_tim->roc_sso)->dev;
119 struct tim_ring_req *req;
122 req = mbox_alloc_msg_tim_disable_ring(dev->mbox);
127 rc = mbox_process(dev->mbox);
137 roc_tim_lf_base_get(struct roc_tim *roc_tim, uint8_t ring_id)
139 struct dev *dev = &roc_sso_to_sso_priv(roc_tim->roc_sso)->dev;
141 return dev->bar2 + (RVU_BLOCK_ADDR_TIM << 20 | ring_id << 12);
145 roc_tim_lf_config(struct roc_tim *roc_tim, uint8_t ring_id,
146 enum roc_tim_clk_src clk_src, uint8_t ena_periodic,
147 uint8_t ena_dfb, uint32_t bucket_sz, uint32_t chunk_sz,
150 struct dev *dev = &roc_sso_to_sso_priv(roc_tim->roc_sso)->dev;
151 struct tim_config_req *req;
154 req = mbox_alloc_msg_tim_config_ring(dev->mbox);
158 req->bigendian = false;
159 req->bucketsize = bucket_sz;
160 req->chunksize = chunk_sz;
161 req->clocksource = clk_src;
162 req->enableperiodic = ena_periodic;
163 req->enabledontfreebuffer = ena_dfb;
164 req->interval = interval;
165 req->gpioedge = TIM_GPIO_LTOH_TRANS;
167 rc = mbox_process(dev->mbox);
177 roc_tim_lf_alloc(struct roc_tim *roc_tim, uint8_t ring_id, uint64_t *clk)
179 struct sso *sso = roc_sso_to_sso_priv(roc_tim->roc_sso);
180 struct tim *tim = roc_tim_to_tim_priv(roc_tim);
181 struct tim_ring_req *free_req;
182 struct tim_lf_alloc_req *req;
183 struct tim_lf_alloc_rsp *rsp;
184 struct dev *dev = &sso->dev;
187 req = mbox_alloc_msg_tim_lf_alloc(dev->mbox);
190 req->npa_pf_func = idev_npa_pffunc_get();
191 req->sso_pf_func = idev_sso_pffunc_get();
194 rc = mbox_process_msg(dev->mbox, (void **)&rsp);
201 *clk = rsp->tenns_clk;
203 rc = tim_register_irq_priv(roc_tim, &sso->pci_dev->intr_handle, ring_id,
204 tim->tim_msix_offsets[ring_id]);
206 plt_tim_dbg("Failed to register Ring[%d] IRQ", ring_id);
207 free_req = mbox_alloc_msg_tim_lf_free(dev->mbox);
208 if (free_req == NULL)
210 free_req->ring = ring_id;
211 mbox_process(dev->mbox);
218 roc_tim_lf_free(struct roc_tim *roc_tim, uint8_t ring_id)
220 struct sso *sso = roc_sso_to_sso_priv(roc_tim->roc_sso);
221 struct tim *tim = roc_tim_to_tim_priv(roc_tim);
222 struct dev *dev = &sso->dev;
223 struct tim_ring_req *req;
226 tim_unregister_irq_priv(roc_tim, &sso->pci_dev->intr_handle, ring_id,
227 tim->tim_msix_offsets[ring_id]);
229 req = mbox_alloc_msg_tim_lf_free(dev->mbox);
234 rc = mbox_process(dev->mbox);
244 roc_tim_init(struct roc_tim *roc_tim)
246 struct rsrc_attach_req *attach_req;
247 struct rsrc_detach_req *detach_req;
248 struct free_rsrcs_rsp *free_rsrc;
253 if (roc_tim == NULL || roc_tim->roc_sso == NULL)
254 return TIM_ERR_PARAM;
256 PLT_STATIC_ASSERT(sizeof(struct tim) <= TIM_MEM_SZ);
257 dev = &roc_sso_to_sso_priv(roc_tim->roc_sso)->dev;
258 nb_lfs = roc_tim->nb_lfs;
259 mbox_alloc_msg_free_rsrc_cnt(dev->mbox);
260 rc = mbox_process_msg(dev->mbox, (void *)&free_rsrc);
262 plt_err("Unable to get free rsrc count.");
266 if (nb_lfs && (free_rsrc->tim < nb_lfs)) {
267 plt_tim_dbg("Requested LFs : %d Available LFs : %d", nb_lfs,
272 attach_req = mbox_alloc_msg_attach_resources(dev->mbox);
273 if (attach_req == NULL)
275 attach_req->modify = true;
276 attach_req->timlfs = nb_lfs ? nb_lfs : free_rsrc->tim;
277 nb_lfs = attach_req->timlfs;
279 rc = mbox_process(dev->mbox);
281 plt_err("Unable to attach TIM LFs.");
285 rc = tim_fill_msix(roc_tim, nb_lfs);
287 plt_err("Unable to get TIM MSIX vectors");
289 detach_req = mbox_alloc_msg_detach_resources(dev->mbox);
290 if (detach_req == NULL)
292 detach_req->partial = true;
293 detach_req->timlfs = true;
294 mbox_process(dev->mbox);
303 roc_tim_fini(struct roc_tim *roc_tim)
305 struct dev *dev = &roc_sso_to_sso_priv(roc_tim->roc_sso)->dev;
306 struct rsrc_detach_req *detach_req;
308 detach_req = mbox_alloc_msg_detach_resources(dev->mbox);
309 PLT_ASSERT(detach_req);
310 detach_req->partial = true;
311 detach_req->timlfs = true;
313 mbox_process(dev->mbox);