1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Cavium, Inc
9 #include "cpt_common.h"
10 #include "cpt_hw_types.h"
11 #include "cpt_mcode_defines.h"
14 * This file defines functions that are interfaces to microcode spec.
18 static uint8_t zuc_d[32] = {
19 0x44, 0xD7, 0x26, 0xBC, 0x62, 0x6B, 0x13, 0x5E,
20 0x57, 0x89, 0x35, 0xE2, 0x71, 0x35, 0x09, 0xAF,
21 0x4D, 0x78, 0x2F, 0x13, 0x6B, 0xC4, 0x1A, 0xF1,
22 0x5E, 0x26, 0x3C, 0x4D, 0x78, 0x9A, 0x47, 0xAC
25 static __rte_always_inline void
26 gen_key_snow3g(const uint8_t *ck, uint32_t *keyx)
30 for (i = 0; i < 4; i++) {
32 keyx[3 - i] = (ck[base] << 24) | (ck[base + 1] << 16) |
33 (ck[base + 2] << 8) | (ck[base + 3]);
34 keyx[3 - i] = rte_cpu_to_be_32(keyx[3 - i]);
38 static __rte_always_inline void
39 cpt_fc_salt_update(void *ctx,
42 struct cpt_ctx *cpt_ctx = ctx;
43 memcpy(&cpt_ctx->fctx.enc.encr_iv, salt, 4);
46 static __rte_always_inline int
47 cpt_fc_ciph_validate_key_aes(uint16_t key_len)
59 static __rte_always_inline int
60 cpt_fc_ciph_set_type(cipher_type_t type, struct cpt_ctx *ctx, uint16_t key_len)
76 if (unlikely(cpt_fc_ciph_validate_key_aes(key_len) != 0))
81 key_len = key_len / 2;
82 if (unlikely(key_len == CPT_BYTE_24)) {
83 CPT_LOG_DP_ERR("Invalid AES key len for XTS");
86 if (unlikely(cpt_fc_ciph_validate_key_aes(key_len) != 0))
92 if (unlikely(key_len != 16))
94 /* No support for AEAD yet */
95 if (unlikely(ctx->hash_type))
101 if (unlikely(key_len != 16))
103 /* No support for AEAD yet */
104 if (unlikely(ctx->hash_type))
112 ctx->fc_type = fc_type;
116 static __rte_always_inline void
117 cpt_fc_ciph_set_key_passthrough(struct cpt_ctx *cpt_ctx, mc_fc_context_t *fctx)
119 cpt_ctx->enc_cipher = 0;
120 fctx->enc.enc_cipher = 0;
123 static __rte_always_inline void
124 cpt_fc_ciph_set_key_set_aes_key_type(mc_fc_context_t *fctx, uint16_t key_len)
126 mc_aes_type_t aes_key_type = 0;
129 aes_key_type = AES_128_BIT;
132 aes_key_type = AES_192_BIT;
135 aes_key_type = AES_256_BIT;
138 /* This should not happen */
139 CPT_LOG_DP_ERR("Invalid AES key len");
142 fctx->enc.aes_key = aes_key_type;
145 static __rte_always_inline void
146 cpt_fc_ciph_set_key_snow3g_uea2(struct cpt_ctx *cpt_ctx, const uint8_t *key,
151 gen_key_snow3g(key, keyx);
152 memcpy(cpt_ctx->zs_ctx.ci_key, keyx, key_len);
153 cpt_ctx->zsk_flags = 0;
156 static __rte_always_inline void
157 cpt_fc_ciph_set_key_zuc_eea3(struct cpt_ctx *cpt_ctx, const uint8_t *key,
161 memcpy(cpt_ctx->zs_ctx.ci_key, key, key_len);
162 memcpy(cpt_ctx->zs_ctx.zuc_const, zuc_d, 32);
163 cpt_ctx->zsk_flags = 0;
166 static __rte_always_inline void
167 cpt_fc_ciph_set_key_kasumi_f8_ecb(struct cpt_ctx *cpt_ctx, const uint8_t *key,
171 memcpy(cpt_ctx->k_ctx.ci_key, key, key_len);
172 cpt_ctx->zsk_flags = 0;
175 static __rte_always_inline void
176 cpt_fc_ciph_set_key_kasumi_f8_cbc(struct cpt_ctx *cpt_ctx, const uint8_t *key,
179 memcpy(cpt_ctx->k_ctx.ci_key, key, key_len);
180 cpt_ctx->zsk_flags = 0;
183 static __rte_always_inline int
184 cpt_fc_ciph_set_key(void *ctx, cipher_type_t type, const uint8_t *key,
185 uint16_t key_len, uint8_t *salt)
187 struct cpt_ctx *cpt_ctx = ctx;
188 mc_fc_context_t *fctx = &cpt_ctx->fctx;
191 ret = cpt_fc_ciph_set_type(type, cpt_ctx, key_len);
195 if (cpt_ctx->fc_type == FC_GEN) {
197 * We need to always say IV is from DPTR as user can
198 * sometimes iverride IV per operation.
200 fctx->enc.iv_source = CPT_FROM_DPTR;
202 if (cpt_ctx->auth_key_len > 64)
208 cpt_fc_ciph_set_key_passthrough(cpt_ctx, fctx);
211 /* CPT performs DES using 3DES with the 8B DES-key
212 * replicated 2 more times to match the 24B 3DES-key.
213 * Eg. If org. key is "0x0a 0x0b", then new key is
214 * "0x0a 0x0b 0x0a 0x0b 0x0a 0x0b"
217 /* Skipping the first 8B as it will be copied
218 * in the regular code flow
220 memcpy(fctx->enc.encr_key+key_len, key, key_len);
221 memcpy(fctx->enc.encr_key+2*key_len, key, key_len);
225 /* For DES3_ECB IV need to be from CTX. */
226 fctx->enc.iv_source = CPT_FROM_CTX;
232 cpt_fc_ciph_set_key_set_aes_key_type(fctx, key_len);
235 /* Even though iv source is from dptr,
236 * aes_gcm salt is taken from ctx
239 memcpy(fctx->enc.encr_iv, salt, 4);
240 /* Assuming it was just salt update
246 cpt_fc_ciph_set_key_set_aes_key_type(fctx, key_len);
249 key_len = key_len / 2;
250 cpt_fc_ciph_set_key_set_aes_key_type(fctx, key_len);
252 /* Copy key2 for XTS into ipad */
253 memset(fctx->hmac.ipad, 0, sizeof(fctx->hmac.ipad));
254 memcpy(fctx->hmac.ipad, &key[key_len], key_len);
257 cpt_fc_ciph_set_key_snow3g_uea2(cpt_ctx, key, key_len);
260 cpt_fc_ciph_set_key_zuc_eea3(cpt_ctx, key, key_len);
263 cpt_fc_ciph_set_key_kasumi_f8_ecb(cpt_ctx, key, key_len);
266 cpt_fc_ciph_set_key_kasumi_f8_cbc(cpt_ctx, key, key_len);
272 /* Only for FC_GEN case */
274 /* For GMAC auth, cipher must be NULL */
275 if (cpt_ctx->hash_type != GMAC_TYPE)
276 fctx->enc.enc_cipher = type;
278 memcpy(fctx->enc.encr_key, key, key_len);
281 cpt_ctx->enc_cipher = type;
286 static __rte_always_inline uint32_t
287 fill_sg_comp(sg_comp_t *list,
289 phys_addr_t dma_addr,
292 sg_comp_t *to = &list[i>>2];
294 to->u.s.len[i%4] = rte_cpu_to_be_16(size);
295 to->ptr[i%4] = rte_cpu_to_be_64(dma_addr);
300 static __rte_always_inline uint32_t
301 fill_sg_comp_from_buf(sg_comp_t *list,
305 sg_comp_t *to = &list[i>>2];
307 to->u.s.len[i%4] = rte_cpu_to_be_16(from->size);
308 to->ptr[i%4] = rte_cpu_to_be_64(from->dma_addr);
313 static __rte_always_inline uint32_t
314 fill_sg_comp_from_buf_min(sg_comp_t *list,
319 sg_comp_t *to = &list[i >> 2];
320 uint32_t size = *psize;
323 e_len = (size > from->size) ? from->size : size;
324 to->u.s.len[i % 4] = rte_cpu_to_be_16(e_len);
325 to->ptr[i % 4] = rte_cpu_to_be_64(from->dma_addr);
332 * This fills the MC expected SGIO list
333 * from IOV given by user.
335 static __rte_always_inline uint32_t
336 fill_sg_comp_from_iov(sg_comp_t *list,
338 iov_ptr_t *from, uint32_t from_offset,
339 uint32_t *psize, buf_ptr_t *extra_buf,
340 uint32_t extra_offset)
343 uint32_t extra_len = extra_buf ? extra_buf->size : 0;
344 uint32_t size = *psize;
348 for (j = 0; (j < from->buf_cnt) && size; j++) {
349 phys_addr_t e_dma_addr;
351 sg_comp_t *to = &list[i >> 2];
353 if (unlikely(from_offset)) {
354 if (from_offset >= bufs[j].size) {
355 from_offset -= bufs[j].size;
358 e_dma_addr = bufs[j].dma_addr + from_offset;
359 e_len = (size > (bufs[j].size - from_offset)) ?
360 (bufs[j].size - from_offset) : size;
363 e_dma_addr = bufs[j].dma_addr;
364 e_len = (size > bufs[j].size) ?
368 to->u.s.len[i % 4] = rte_cpu_to_be_16(e_len);
369 to->ptr[i % 4] = rte_cpu_to_be_64(e_dma_addr);
371 if (extra_len && (e_len >= extra_offset)) {
372 /* Break the data at given offset */
373 uint32_t next_len = e_len - extra_offset;
374 phys_addr_t next_dma = e_dma_addr + extra_offset;
379 e_len = extra_offset;
381 to->u.s.len[i % 4] = rte_cpu_to_be_16(e_len);
384 extra_len = RTE_MIN(extra_len, size);
385 /* Insert extra data ptr */
390 rte_cpu_to_be_16(extra_len);
392 rte_cpu_to_be_64(extra_buf->dma_addr);
396 next_len = RTE_MIN(next_len, size);
397 /* insert the rest of the data */
401 to->u.s.len[i % 4] = rte_cpu_to_be_16(next_len);
402 to->ptr[i % 4] = rte_cpu_to_be_64(next_dma);
411 extra_offset -= size;
419 static __rte_always_inline void
420 cpt_digest_gen_prep(uint32_t flags,
422 digest_params_t *params,
426 struct cpt_request_info *req;
428 uint16_t data_len, mac_len, key_len;
429 auth_type_t hash_type;
432 sg_comp_t *gather_comp;
433 sg_comp_t *scatter_comp;
435 uint32_t g_size_bytes, s_size_bytes;
436 uint64_t dptr_dma, rptr_dma;
437 vq_cmd_word0_t vq_cmd_w0;
438 vq_cmd_word3_t vq_cmd_w3;
439 void *c_vaddr, *m_vaddr;
440 uint64_t c_dma, m_dma;
441 opcode_info_t opcode;
443 ctx = params->ctx_buf.vaddr;
444 meta_p = ¶ms->meta_buf;
446 m_vaddr = meta_p->vaddr;
447 m_dma = meta_p->dma_addr;
450 * Save initial space that followed app data for completion code &
451 * alternate completion code to fall in same cache line as app data
453 m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
454 m_dma += COMPLETION_CODE_SIZE;
455 size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
457 c_vaddr = (uint8_t *)m_vaddr + size;
458 c_dma = m_dma + size;
459 size += sizeof(cpt_res_s_t);
461 m_vaddr = (uint8_t *)m_vaddr + size;
466 size = sizeof(struct cpt_request_info);
467 m_vaddr = (uint8_t *)m_vaddr + size;
470 hash_type = ctx->hash_type;
471 mac_len = ctx->mac_len;
472 key_len = ctx->auth_key_len;
473 data_len = AUTH_DLEN(d_lens);
477 vq_cmd_w0.s.param2 = ((uint16_t)hash_type << 8);
479 opcode.s.major = CPT_MAJOR_OP_HMAC | CPT_DMA_MODE;
480 vq_cmd_w0.s.param1 = key_len;
481 vq_cmd_w0.s.dlen = data_len + ROUNDUP8(key_len);
483 opcode.s.major = CPT_MAJOR_OP_HASH | CPT_DMA_MODE;
484 vq_cmd_w0.s.param1 = 0;
485 vq_cmd_w0.s.dlen = data_len;
490 /* Null auth only case enters the if */
491 if (unlikely(!hash_type && !ctx->enc_cipher)) {
492 opcode.s.major = CPT_MAJOR_OP_MISC;
493 /* Minor op is passthrough */
494 opcode.s.minor = 0x03;
495 /* Send out completion code only */
496 vq_cmd_w0.s.param2 = 0x1;
499 vq_cmd_w0.s.opcode = opcode.flags;
501 /* DPTR has SG list */
505 ((uint16_t *)in_buffer)[0] = 0;
506 ((uint16_t *)in_buffer)[1] = 0;
508 /* TODO Add error check if space will be sufficient */
509 gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
518 uint64_t k_dma = params->ctx_buf.dma_addr +
519 offsetof(struct cpt_ctx, auth_key);
521 i = fill_sg_comp(gather_comp, i, k_dma, ROUNDUP8(key_len));
527 i = fill_sg_comp_from_iov(gather_comp, i, params->src_iov,
529 if (unlikely(size)) {
530 CPT_LOG_DP_DEBUG("Insufficient dst IOV size, short"
536 * Looks like we need to support zero data
537 * gather ptr in case of hash & hmac
541 ((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
542 g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
549 scatter_comp = (sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
551 if (flags & VALID_MAC_BUF) {
552 if (unlikely(params->mac_buf.size < mac_len)) {
553 CPT_LOG_DP_ERR("Insufficient MAC size");
558 i = fill_sg_comp_from_buf_min(scatter_comp, i,
559 ¶ms->mac_buf, &size);
562 i = fill_sg_comp_from_iov(scatter_comp, i,
563 params->src_iov, data_len,
565 if (unlikely(size)) {
566 CPT_LOG_DP_ERR("Insufficient dst IOV size, short by"
572 ((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
573 s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
575 size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
577 /* This is DPTR len incase of SG mode */
578 vq_cmd_w0.s.dlen = size;
580 m_vaddr = (uint8_t *)m_vaddr + size;
583 /* cpt alternate completion address saved earlier */
584 req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
585 *req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
586 rptr_dma = c_dma - 8;
588 req->ist.ei1 = dptr_dma;
589 req->ist.ei2 = rptr_dma;
594 /* 16 byte aligned cpt res address */
595 req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
596 *req->completion_addr = COMPLETION_CODE_INIT;
597 req->comp_baddr = c_dma;
599 /* Fill microcode part of instruction */
600 req->ist.ei0 = vq_cmd_w0.u64;
601 req->ist.ei3 = vq_cmd_w3.u64;
609 static __rte_always_inline void
610 cpt_enc_hmac_prep(uint32_t flags,
613 fc_params_t *fc_params,
617 uint32_t iv_offset = 0;
618 int32_t inputlen, outputlen, enc_dlen, auth_dlen;
619 struct cpt_ctx *cpt_ctx;
620 uint32_t cipher_type, hash_type;
621 uint32_t mac_len, size;
623 struct cpt_request_info *req;
624 buf_ptr_t *meta_p, *aad_buf = NULL;
625 uint32_t encr_offset, auth_offset;
626 uint32_t encr_data_len, auth_data_len, aad_len = 0;
627 uint32_t passthrough_len = 0;
628 void *m_vaddr, *offset_vaddr;
629 uint64_t m_dma, offset_dma, ctx_dma;
630 vq_cmd_word0_t vq_cmd_w0;
631 vq_cmd_word3_t vq_cmd_w3;
634 opcode_info_t opcode;
636 meta_p = &fc_params->meta_buf;
637 m_vaddr = meta_p->vaddr;
638 m_dma = meta_p->dma_addr;
640 encr_offset = ENCR_OFFSET(d_offs);
641 auth_offset = AUTH_OFFSET(d_offs);
642 encr_data_len = ENCR_DLEN(d_lens);
643 auth_data_len = AUTH_DLEN(d_lens);
644 if (unlikely(flags & VALID_AAD_BUF)) {
646 * We dont support both aad
647 * and auth data separately
651 aad_len = fc_params->aad_buf.size;
652 aad_buf = &fc_params->aad_buf;
654 cpt_ctx = fc_params->ctx_buf.vaddr;
655 cipher_type = cpt_ctx->enc_cipher;
656 hash_type = cpt_ctx->hash_type;
657 mac_len = cpt_ctx->mac_len;
660 * Save initial space that followed app data for completion code &
661 * alternate completion code to fall in same cache line as app data
663 m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
664 m_dma += COMPLETION_CODE_SIZE;
665 size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
668 c_vaddr = (uint8_t *)m_vaddr + size;
669 c_dma = m_dma + size;
670 size += sizeof(cpt_res_s_t);
672 m_vaddr = (uint8_t *)m_vaddr + size;
675 /* start cpt request info struct at 8 byte boundary */
676 size = (uint8_t *)RTE_PTR_ALIGN(m_vaddr, 8) -
679 req = (struct cpt_request_info *)((uint8_t *)m_vaddr + size);
681 size += sizeof(struct cpt_request_info);
682 m_vaddr = (uint8_t *)m_vaddr + size;
685 if (hash_type == GMAC_TYPE)
688 if (unlikely(!(flags & VALID_IV_BUF))) {
690 iv_offset = ENCR_IV_OFFSET(d_offs);
693 if (unlikely(flags & VALID_AAD_BUF)) {
695 * When AAD is given, data above encr_offset is pass through
696 * Since AAD is given as separate pointer and not as offset,
697 * this is a special case as we need to fragment input data
698 * into passthrough + encr_data and then insert AAD in between.
700 if (hash_type != GMAC_TYPE) {
701 passthrough_len = encr_offset;
702 auth_offset = passthrough_len + iv_len;
703 encr_offset = passthrough_len + aad_len + iv_len;
704 auth_data_len = aad_len + encr_data_len;
706 passthrough_len = 16 + aad_len;
707 auth_offset = passthrough_len + iv_len;
708 auth_data_len = aad_len;
711 encr_offset += iv_len;
712 auth_offset += iv_len;
716 opcode.s.major = CPT_MAJOR_OP_FC;
719 auth_dlen = auth_offset + auth_data_len;
720 enc_dlen = encr_data_len + encr_offset;
721 if (unlikely(encr_data_len & 0xf)) {
722 if ((cipher_type == DES3_CBC) || (cipher_type == DES3_ECB))
723 enc_dlen = ROUNDUP8(encr_data_len) + encr_offset;
724 else if (likely((cipher_type == AES_CBC) ||
725 (cipher_type == AES_ECB)))
726 enc_dlen = ROUNDUP16(encr_data_len) + encr_offset;
729 if (unlikely(hash_type == GMAC_TYPE)) {
730 encr_offset = auth_dlen;
734 if (unlikely(auth_dlen > enc_dlen)) {
735 inputlen = auth_dlen;
736 outputlen = auth_dlen + mac_len;
739 outputlen = enc_dlen + mac_len;
744 vq_cmd_w0.s.param1 = encr_data_len;
745 vq_cmd_w0.s.param2 = auth_data_len;
747 * In 83XX since we have a limitation of
748 * IV & Offset control word not part of instruction
749 * and need to be part of Data Buffer, we check if
750 * head room is there and then only do the Direct mode processing
752 if (likely((flags & SINGLE_BUF_INPLACE) &&
753 (flags & SINGLE_BUF_HEADTAILROOM))) {
754 void *dm_vaddr = fc_params->bufs[0].vaddr;
755 uint64_t dm_dma_addr = fc_params->bufs[0].dma_addr;
757 * This flag indicates that there is 24 bytes head room and
758 * 8 bytes tail room available, so that we get to do
759 * DIRECT MODE with limitation
762 offset_vaddr = (uint8_t *)dm_vaddr - OFF_CTRL_LEN - iv_len;
763 offset_dma = dm_dma_addr - OFF_CTRL_LEN - iv_len;
766 req->ist.ei1 = offset_dma;
767 /* RPTR should just exclude offset control word */
768 req->ist.ei2 = dm_dma_addr - iv_len;
769 req->alternate_caddr = (uint64_t *)((uint8_t *)dm_vaddr
770 + outputlen - iv_len);
772 vq_cmd_w0.s.dlen = inputlen + OFF_CTRL_LEN;
774 vq_cmd_w0.s.opcode = opcode.flags;
776 if (likely(iv_len)) {
777 uint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr
779 uint64_t *src = fc_params->iv_buf;
784 *(uint64_t *)offset_vaddr =
785 rte_cpu_to_be_64(((uint64_t)encr_offset << 16) |
786 ((uint64_t)iv_offset << 8) |
787 ((uint64_t)auth_offset));
790 uint32_t i, g_size_bytes, s_size_bytes;
791 uint64_t dptr_dma, rptr_dma;
792 sg_comp_t *gather_comp;
793 sg_comp_t *scatter_comp;
796 /* This falls under strict SG mode */
797 offset_vaddr = m_vaddr;
799 size = OFF_CTRL_LEN + iv_len;
801 m_vaddr = (uint8_t *)m_vaddr + size;
804 opcode.s.major |= CPT_DMA_MODE;
806 vq_cmd_w0.s.opcode = opcode.flags;
808 if (likely(iv_len)) {
809 uint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr
811 uint64_t *src = fc_params->iv_buf;
816 *(uint64_t *)offset_vaddr =
817 rte_cpu_to_be_64(((uint64_t)encr_offset << 16) |
818 ((uint64_t)iv_offset << 8) |
819 ((uint64_t)auth_offset));
821 /* DPTR has SG list */
825 ((uint16_t *)in_buffer)[0] = 0;
826 ((uint16_t *)in_buffer)[1] = 0;
828 /* TODO Add error check if space will be sufficient */
829 gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
837 /* Offset control word that includes iv */
838 i = fill_sg_comp(gather_comp, i, offset_dma,
839 OFF_CTRL_LEN + iv_len);
842 size = inputlen - iv_len;
844 uint32_t aad_offset = aad_len ? passthrough_len : 0;
846 if (unlikely(flags & SINGLE_BUF_INPLACE)) {
847 i = fill_sg_comp_from_buf_min(gather_comp, i,
851 i = fill_sg_comp_from_iov(gather_comp, i,
854 aad_buf, aad_offset);
857 if (unlikely(size)) {
858 CPT_LOG_DP_ERR("Insufficient buffer space,"
859 " size %d needed", size);
863 ((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
864 g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
867 * Output Scatter list
871 (sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
874 if (likely(iv_len)) {
875 i = fill_sg_comp(scatter_comp, i,
876 offset_dma + OFF_CTRL_LEN,
880 /* output data or output data + digest*/
881 if (unlikely(flags & VALID_MAC_BUF)) {
882 size = outputlen - iv_len - mac_len;
884 uint32_t aad_offset =
885 aad_len ? passthrough_len : 0;
887 if (unlikely(flags & SINGLE_BUF_INPLACE)) {
888 i = fill_sg_comp_from_buf_min(
894 i = fill_sg_comp_from_iov(scatter_comp,
902 if (unlikely(size)) {
903 CPT_LOG_DP_ERR("Insufficient buffer"
904 " space, size %d needed",
911 i = fill_sg_comp_from_buf(scatter_comp, i,
912 &fc_params->mac_buf);
915 /* Output including mac */
916 size = outputlen - iv_len;
918 uint32_t aad_offset =
919 aad_len ? passthrough_len : 0;
921 if (unlikely(flags & SINGLE_BUF_INPLACE)) {
922 i = fill_sg_comp_from_buf_min(
928 i = fill_sg_comp_from_iov(scatter_comp,
936 if (unlikely(size)) {
937 CPT_LOG_DP_ERR("Insufficient buffer"
938 " space, size %d needed",
944 ((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
945 s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
947 size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
949 /* This is DPTR len incase of SG mode */
950 vq_cmd_w0.s.dlen = size;
952 m_vaddr = (uint8_t *)m_vaddr + size;
955 /* cpt alternate completion address saved earlier */
956 req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
957 *req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
958 rptr_dma = c_dma - 8;
960 req->ist.ei1 = dptr_dma;
961 req->ist.ei2 = rptr_dma;
964 ctx_dma = fc_params->ctx_buf.dma_addr +
965 offsetof(struct cpt_ctx, fctx);
969 vq_cmd_w3.s.cptr = ctx_dma;
971 /* 16 byte aligned cpt res address */
972 req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
973 *req->completion_addr = COMPLETION_CODE_INIT;
974 req->comp_baddr = c_dma;
976 /* Fill microcode part of instruction */
977 req->ist.ei0 = vq_cmd_w0.u64;
978 req->ist.ei3 = vq_cmd_w3.u64;
986 static __rte_always_inline void
987 cpt_dec_hmac_prep(uint32_t flags,
990 fc_params_t *fc_params,
994 uint32_t iv_offset = 0, size;
995 int32_t inputlen, outputlen, enc_dlen, auth_dlen;
996 struct cpt_ctx *cpt_ctx;
997 int32_t hash_type, mac_len;
999 struct cpt_request_info *req;
1000 buf_ptr_t *meta_p, *aad_buf = NULL;
1001 uint32_t encr_offset, auth_offset;
1002 uint32_t encr_data_len, auth_data_len, aad_len = 0;
1003 uint32_t passthrough_len = 0;
1004 void *m_vaddr, *offset_vaddr;
1005 uint64_t m_dma, offset_dma, ctx_dma;
1006 opcode_info_t opcode;
1007 vq_cmd_word0_t vq_cmd_w0;
1008 vq_cmd_word3_t vq_cmd_w3;
1012 meta_p = &fc_params->meta_buf;
1013 m_vaddr = meta_p->vaddr;
1014 m_dma = meta_p->dma_addr;
1016 encr_offset = ENCR_OFFSET(d_offs);
1017 auth_offset = AUTH_OFFSET(d_offs);
1018 encr_data_len = ENCR_DLEN(d_lens);
1019 auth_data_len = AUTH_DLEN(d_lens);
1021 if (unlikely(flags & VALID_AAD_BUF)) {
1023 * We dont support both aad
1024 * and auth data separately
1028 aad_len = fc_params->aad_buf.size;
1029 aad_buf = &fc_params->aad_buf;
1032 cpt_ctx = fc_params->ctx_buf.vaddr;
1033 hash_type = cpt_ctx->hash_type;
1034 mac_len = cpt_ctx->mac_len;
1036 if (hash_type == GMAC_TYPE)
1039 if (unlikely(!(flags & VALID_IV_BUF))) {
1041 iv_offset = ENCR_IV_OFFSET(d_offs);
1044 if (unlikely(flags & VALID_AAD_BUF)) {
1046 * When AAD is given, data above encr_offset is pass through
1047 * Since AAD is given as separate pointer and not as offset,
1048 * this is a special case as we need to fragment input data
1049 * into passthrough + encr_data and then insert AAD in between.
1051 if (hash_type != GMAC_TYPE) {
1052 passthrough_len = encr_offset;
1053 auth_offset = passthrough_len + iv_len;
1054 encr_offset = passthrough_len + aad_len + iv_len;
1055 auth_data_len = aad_len + encr_data_len;
1057 passthrough_len = 16 + aad_len;
1058 auth_offset = passthrough_len + iv_len;
1059 auth_data_len = aad_len;
1062 encr_offset += iv_len;
1063 auth_offset += iv_len;
1067 * Save initial space that followed app data for completion code &
1068 * alternate completion code to fall in same cache line as app data
1070 m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
1071 m_dma += COMPLETION_CODE_SIZE;
1072 size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
1074 c_vaddr = (uint8_t *)m_vaddr + size;
1075 c_dma = m_dma + size;
1076 size += sizeof(cpt_res_s_t);
1078 m_vaddr = (uint8_t *)m_vaddr + size;
1081 /* start cpt request info structure at 8 byte alignment */
1082 size = (uint8_t *)RTE_PTR_ALIGN(m_vaddr, 8) -
1085 req = (struct cpt_request_info *)((uint8_t *)m_vaddr + size);
1087 size += sizeof(struct cpt_request_info);
1088 m_vaddr = (uint8_t *)m_vaddr + size;
1092 opcode.s.major = CPT_MAJOR_OP_FC;
1095 enc_dlen = encr_offset + encr_data_len;
1096 auth_dlen = auth_offset + auth_data_len;
1098 if (auth_dlen > enc_dlen) {
1099 inputlen = auth_dlen + mac_len;
1100 outputlen = auth_dlen;
1102 inputlen = enc_dlen + mac_len;
1103 outputlen = enc_dlen;
1106 if (hash_type == GMAC_TYPE)
1107 encr_offset = inputlen;
1110 vq_cmd_w0.s.param1 = encr_data_len;
1111 vq_cmd_w0.s.param2 = auth_data_len;
1114 * In 83XX since we have a limitation of
1115 * IV & Offset control word not part of instruction
1116 * and need to be part of Data Buffer, we check if
1117 * head room is there and then only do the Direct mode processing
1119 if (likely((flags & SINGLE_BUF_INPLACE) &&
1120 (flags & SINGLE_BUF_HEADTAILROOM))) {
1121 void *dm_vaddr = fc_params->bufs[0].vaddr;
1122 uint64_t dm_dma_addr = fc_params->bufs[0].dma_addr;
1124 * This flag indicates that there is 24 bytes head room and
1125 * 8 bytes tail room available, so that we get to do
1126 * DIRECT MODE with limitation
1129 offset_vaddr = (uint8_t *)dm_vaddr - OFF_CTRL_LEN - iv_len;
1130 offset_dma = dm_dma_addr - OFF_CTRL_LEN - iv_len;
1131 req->ist.ei1 = offset_dma;
1133 /* RPTR should just exclude offset control word */
1134 req->ist.ei2 = dm_dma_addr - iv_len;
1136 req->alternate_caddr = (uint64_t *)((uint8_t *)dm_vaddr +
1137 outputlen - iv_len);
1138 /* since this is decryption,
1139 * don't touch the content of
1140 * alternate ccode space as it contains
1144 vq_cmd_w0.s.dlen = inputlen + OFF_CTRL_LEN;
1146 vq_cmd_w0.s.opcode = opcode.flags;
1148 if (likely(iv_len)) {
1149 uint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr +
1151 uint64_t *src = fc_params->iv_buf;
1156 *(uint64_t *)offset_vaddr =
1157 rte_cpu_to_be_64(((uint64_t)encr_offset << 16) |
1158 ((uint64_t)iv_offset << 8) |
1159 ((uint64_t)auth_offset));
1162 uint64_t dptr_dma, rptr_dma;
1163 uint32_t g_size_bytes, s_size_bytes;
1164 sg_comp_t *gather_comp;
1165 sg_comp_t *scatter_comp;
1169 /* This falls under strict SG mode */
1170 offset_vaddr = m_vaddr;
1172 size = OFF_CTRL_LEN + iv_len;
1174 m_vaddr = (uint8_t *)m_vaddr + size;
1177 opcode.s.major |= CPT_DMA_MODE;
1179 vq_cmd_w0.s.opcode = opcode.flags;
1181 if (likely(iv_len)) {
1182 uint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr +
1184 uint64_t *src = fc_params->iv_buf;
1189 *(uint64_t *)offset_vaddr =
1190 rte_cpu_to_be_64(((uint64_t)encr_offset << 16) |
1191 ((uint64_t)iv_offset << 8) |
1192 ((uint64_t)auth_offset));
1194 /* DPTR has SG list */
1195 in_buffer = m_vaddr;
1198 ((uint16_t *)in_buffer)[0] = 0;
1199 ((uint16_t *)in_buffer)[1] = 0;
1201 /* TODO Add error check if space will be sufficient */
1202 gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
1209 /* Offset control word that includes iv */
1210 i = fill_sg_comp(gather_comp, i, offset_dma,
1211 OFF_CTRL_LEN + iv_len);
1213 /* Add input data */
1214 if (flags & VALID_MAC_BUF) {
1215 size = inputlen - iv_len - mac_len;
1217 /* input data only */
1218 if (unlikely(flags & SINGLE_BUF_INPLACE)) {
1219 i = fill_sg_comp_from_buf_min(
1224 uint32_t aad_offset = aad_len ?
1225 passthrough_len : 0;
1227 i = fill_sg_comp_from_iov(gather_comp,
1234 if (unlikely(size)) {
1235 CPT_LOG_DP_ERR("Insufficient buffer"
1236 " space, size %d needed",
1244 i = fill_sg_comp_from_buf(gather_comp, i,
1245 &fc_params->mac_buf);
1248 /* input data + mac */
1249 size = inputlen - iv_len;
1251 if (unlikely(flags & SINGLE_BUF_INPLACE)) {
1252 i = fill_sg_comp_from_buf_min(
1257 uint32_t aad_offset = aad_len ?
1258 passthrough_len : 0;
1260 if (unlikely(!fc_params->src_iov)) {
1261 CPT_LOG_DP_ERR("Bad input args");
1265 i = fill_sg_comp_from_iov(
1273 if (unlikely(size)) {
1274 CPT_LOG_DP_ERR("Insufficient buffer"
1275 " space, size %d needed",
1281 ((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
1282 g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
1285 * Output Scatter List
1290 (sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
1294 i = fill_sg_comp(scatter_comp, i,
1295 offset_dma + OFF_CTRL_LEN,
1299 /* Add output data */
1300 size = outputlen - iv_len;
1302 if (unlikely(flags & SINGLE_BUF_INPLACE)) {
1303 /* handle single buffer here */
1304 i = fill_sg_comp_from_buf_min(scatter_comp, i,
1308 uint32_t aad_offset = aad_len ?
1309 passthrough_len : 0;
1311 if (unlikely(!fc_params->dst_iov)) {
1312 CPT_LOG_DP_ERR("Bad input args");
1316 i = fill_sg_comp_from_iov(scatter_comp, i,
1317 fc_params->dst_iov, 0,
1322 if (unlikely(size)) {
1323 CPT_LOG_DP_ERR("Insufficient buffer space,"
1324 " size %d needed", size);
1329 ((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
1330 s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
1332 size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
1334 /* This is DPTR len incase of SG mode */
1335 vq_cmd_w0.s.dlen = size;
1337 m_vaddr = (uint8_t *)m_vaddr + size;
1340 /* cpt alternate completion address saved earlier */
1341 req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
1342 *req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
1343 rptr_dma = c_dma - 8;
1344 size += COMPLETION_CODE_SIZE;
1346 req->ist.ei1 = dptr_dma;
1347 req->ist.ei2 = rptr_dma;
1350 ctx_dma = fc_params->ctx_buf.dma_addr +
1351 offsetof(struct cpt_ctx, fctx);
1354 vq_cmd_w3.s.grp = 0;
1355 vq_cmd_w3.s.cptr = ctx_dma;
1357 /* 16 byte aligned cpt res address */
1358 req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
1359 *req->completion_addr = COMPLETION_CODE_INIT;
1360 req->comp_baddr = c_dma;
1362 /* Fill microcode part of instruction */
1363 req->ist.ei0 = vq_cmd_w0.u64;
1364 req->ist.ei3 = vq_cmd_w3.u64;
1372 static __rte_always_inline void
1373 cpt_zuc_snow3g_enc_prep(uint32_t req_flags,
1376 fc_params_t *params,
1381 int32_t inputlen, outputlen;
1382 struct cpt_ctx *cpt_ctx;
1383 uint32_t mac_len = 0;
1385 struct cpt_request_info *req;
1387 uint32_t encr_offset = 0, auth_offset = 0;
1388 uint32_t encr_data_len = 0, auth_data_len = 0;
1389 int flags, iv_len = 16;
1390 void *m_vaddr, *c_vaddr;
1391 uint64_t m_dma, c_dma, offset_ctrl;
1392 uint64_t *offset_vaddr, offset_dma;
1393 uint32_t *iv_s, iv[4];
1394 vq_cmd_word0_t vq_cmd_w0;
1395 vq_cmd_word3_t vq_cmd_w3;
1396 opcode_info_t opcode;
1398 buf_p = ¶ms->meta_buf;
1399 m_vaddr = buf_p->vaddr;
1400 m_dma = buf_p->dma_addr;
1402 cpt_ctx = params->ctx_buf.vaddr;
1403 flags = cpt_ctx->zsk_flags;
1404 mac_len = cpt_ctx->mac_len;
1405 snow3g = cpt_ctx->snow3g;
1408 * Save initial space that followed app data for completion code &
1409 * alternate completion code to fall in same cache line as app data
1411 m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
1412 m_dma += COMPLETION_CODE_SIZE;
1413 size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
1416 c_vaddr = (uint8_t *)m_vaddr + size;
1417 c_dma = m_dma + size;
1418 size += sizeof(cpt_res_s_t);
1420 m_vaddr = (uint8_t *)m_vaddr + size;
1423 /* Reserve memory for cpt request info */
1426 size = sizeof(struct cpt_request_info);
1427 m_vaddr = (uint8_t *)m_vaddr + size;
1430 opcode.s.major = CPT_MAJOR_OP_ZUC_SNOW3G;
1432 /* indicates CPTR ctx, operation type, KEY & IV mode from DPTR */
1434 opcode.s.minor = ((1 << 7) | (snow3g << 5) | (0 << 4) |
1435 (0 << 3) | (flags & 0x7));
1439 * Microcode expects offsets in bytes
1440 * TODO: Rounding off
1442 auth_data_len = AUTH_DLEN(d_lens);
1445 auth_offset = AUTH_OFFSET(d_offs);
1446 auth_offset = auth_offset / 8;
1448 /* consider iv len */
1449 auth_offset += iv_len;
1451 inputlen = auth_offset + (RTE_ALIGN(auth_data_len, 8) / 8);
1452 outputlen = mac_len;
1454 offset_ctrl = rte_cpu_to_be_64((uint64_t)auth_offset);
1459 * Microcode expects offsets in bytes
1460 * TODO: Rounding off
1462 encr_data_len = ENCR_DLEN(d_lens);
1464 encr_offset = ENCR_OFFSET(d_offs);
1465 encr_offset = encr_offset / 8;
1466 /* consider iv len */
1467 encr_offset += iv_len;
1469 inputlen = encr_offset + (RTE_ALIGN(encr_data_len, 8) / 8);
1470 outputlen = inputlen;
1472 /* iv offset is 0 */
1473 offset_ctrl = rte_cpu_to_be_64((uint64_t)encr_offset << 16);
1477 iv_s = (flags == 0x1) ? params->auth_iv_buf :
1482 * DPDK seems to provide it in form of IV3 IV2 IV1 IV0
1483 * and BigEndian, MC needs it as IV0 IV1 IV2 IV3
1486 for (j = 0; j < 4; j++)
1487 iv[j] = iv_s[3 - j];
1489 /* ZUC doesn't need a swap */
1490 for (j = 0; j < 4; j++)
1495 * GP op header, lengths are expected in bits.
1498 vq_cmd_w0.s.param1 = encr_data_len;
1499 vq_cmd_w0.s.param2 = auth_data_len;
1502 * In 83XX since we have a limitation of
1503 * IV & Offset control word not part of instruction
1504 * and need to be part of Data Buffer, we check if
1505 * head room is there and then only do the Direct mode processing
1507 if (likely((req_flags & SINGLE_BUF_INPLACE) &&
1508 (req_flags & SINGLE_BUF_HEADTAILROOM))) {
1509 void *dm_vaddr = params->bufs[0].vaddr;
1510 uint64_t dm_dma_addr = params->bufs[0].dma_addr;
1512 * This flag indicates that there is 24 bytes head room and
1513 * 8 bytes tail room available, so that we get to do
1514 * DIRECT MODE with limitation
1517 offset_vaddr = (uint64_t *)((uint8_t *)dm_vaddr -
1518 OFF_CTRL_LEN - iv_len);
1519 offset_dma = dm_dma_addr - OFF_CTRL_LEN - iv_len;
1522 req->ist.ei1 = offset_dma;
1523 /* RPTR should just exclude offset control word */
1524 req->ist.ei2 = dm_dma_addr - iv_len;
1525 req->alternate_caddr = (uint64_t *)((uint8_t *)dm_vaddr
1526 + outputlen - iv_len);
1528 vq_cmd_w0.s.dlen = inputlen + OFF_CTRL_LEN;
1530 vq_cmd_w0.s.opcode = opcode.flags;
1532 if (likely(iv_len)) {
1533 uint32_t *iv_d = (uint32_t *)((uint8_t *)offset_vaddr
1535 memcpy(iv_d, iv, 16);
1538 *offset_vaddr = offset_ctrl;
1540 uint32_t i, g_size_bytes, s_size_bytes;
1541 uint64_t dptr_dma, rptr_dma;
1542 sg_comp_t *gather_comp;
1543 sg_comp_t *scatter_comp;
1547 /* save space for iv */
1548 offset_vaddr = m_vaddr;
1551 m_vaddr = (uint8_t *)m_vaddr + OFF_CTRL_LEN + iv_len;
1552 m_dma += OFF_CTRL_LEN + iv_len;
1554 opcode.s.major |= CPT_DMA_MODE;
1556 vq_cmd_w0.s.opcode = opcode.flags;
1558 /* DPTR has SG list */
1559 in_buffer = m_vaddr;
1562 ((uint16_t *)in_buffer)[0] = 0;
1563 ((uint16_t *)in_buffer)[1] = 0;
1565 /* TODO Add error check if space will be sufficient */
1566 gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
1573 /* Offset control word followed by iv */
1575 i = fill_sg_comp(gather_comp, i, offset_dma,
1576 OFF_CTRL_LEN + iv_len);
1578 /* iv offset is 0 */
1579 *offset_vaddr = offset_ctrl;
1581 iv_d = (uint32_t *)((uint8_t *)offset_vaddr + OFF_CTRL_LEN);
1582 memcpy(iv_d, iv, 16);
1585 size = inputlen - iv_len;
1587 i = fill_sg_comp_from_iov(gather_comp, i,
1590 if (unlikely(size)) {
1591 CPT_LOG_DP_ERR("Insufficient buffer space,"
1592 " size %d needed", size);
1596 ((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
1597 g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
1600 * Output Scatter List
1605 (sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
1608 /* IV in SLIST only for EEA3 & UEA2 */
1613 i = fill_sg_comp(scatter_comp, i,
1614 offset_dma + OFF_CTRL_LEN, iv_len);
1617 /* Add output data */
1618 if (req_flags & VALID_MAC_BUF) {
1619 size = outputlen - iv_len - mac_len;
1621 i = fill_sg_comp_from_iov(scatter_comp, i,
1625 if (unlikely(size)) {
1626 CPT_LOG_DP_ERR("Insufficient buffer space,"
1627 " size %d needed", size);
1634 i = fill_sg_comp_from_buf(scatter_comp, i,
1638 /* Output including mac */
1639 size = outputlen - iv_len;
1641 i = fill_sg_comp_from_iov(scatter_comp, i,
1645 if (unlikely(size)) {
1646 CPT_LOG_DP_ERR("Insufficient buffer space,"
1647 " size %d needed", size);
1652 ((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
1653 s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
1655 size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
1657 /* This is DPTR len incase of SG mode */
1658 vq_cmd_w0.s.dlen = size;
1660 m_vaddr = (uint8_t *)m_vaddr + size;
1663 /* cpt alternate completion address saved earlier */
1664 req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
1665 *req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
1666 rptr_dma = c_dma - 8;
1668 req->ist.ei1 = dptr_dma;
1669 req->ist.ei2 = rptr_dma;
1674 vq_cmd_w3.s.grp = 0;
1675 vq_cmd_w3.s.cptr = params->ctx_buf.dma_addr +
1676 offsetof(struct cpt_ctx, zs_ctx);
1678 /* 16 byte aligned cpt res address */
1679 req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
1680 *req->completion_addr = COMPLETION_CODE_INIT;
1681 req->comp_baddr = c_dma;
1683 /* Fill microcode part of instruction */
1684 req->ist.ei0 = vq_cmd_w0.u64;
1685 req->ist.ei3 = vq_cmd_w3.u64;
1693 static __rte_always_inline void
1694 cpt_zuc_snow3g_dec_prep(uint32_t req_flags,
1697 fc_params_t *params,
1702 int32_t inputlen = 0, outputlen;
1703 struct cpt_ctx *cpt_ctx;
1704 uint8_t snow3g, iv_len = 16;
1705 struct cpt_request_info *req;
1707 uint32_t encr_offset;
1708 uint32_t encr_data_len;
1710 void *m_vaddr, *c_vaddr;
1711 uint64_t m_dma, c_dma;
1712 uint64_t *offset_vaddr, offset_dma;
1713 uint32_t *iv_s, iv[4], j;
1714 vq_cmd_word0_t vq_cmd_w0;
1715 vq_cmd_word3_t vq_cmd_w3;
1716 opcode_info_t opcode;
1718 buf_p = ¶ms->meta_buf;
1719 m_vaddr = buf_p->vaddr;
1720 m_dma = buf_p->dma_addr;
1723 * Microcode expects offsets in bytes
1724 * TODO: Rounding off
1726 encr_offset = ENCR_OFFSET(d_offs) / 8;
1727 encr_data_len = ENCR_DLEN(d_lens);
1729 cpt_ctx = params->ctx_buf.vaddr;
1730 flags = cpt_ctx->zsk_flags;
1731 snow3g = cpt_ctx->snow3g;
1733 * Save initial space that followed app data for completion code &
1734 * alternate completion code to fall in same cache line as app data
1736 m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
1737 m_dma += COMPLETION_CODE_SIZE;
1738 size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
1741 c_vaddr = (uint8_t *)m_vaddr + size;
1742 c_dma = m_dma + size;
1743 size += sizeof(cpt_res_s_t);
1745 m_vaddr = (uint8_t *)m_vaddr + size;
1748 /* Reserve memory for cpt request info */
1751 size = sizeof(struct cpt_request_info);
1752 m_vaddr = (uint8_t *)m_vaddr + size;
1755 opcode.s.major = CPT_MAJOR_OP_ZUC_SNOW3G;
1757 /* indicates CPTR ctx, operation type, KEY & IV mode from DPTR */
1759 opcode.s.minor = ((1 << 7) | (snow3g << 5) | (0 << 4) |
1760 (0 << 3) | (flags & 0x7));
1762 /* consider iv len */
1763 encr_offset += iv_len;
1765 inputlen = encr_offset +
1766 (RTE_ALIGN(encr_data_len, 8) / 8);
1767 outputlen = inputlen;
1770 iv_s = params->iv_buf;
1773 * DPDK seems to provide it in form of IV3 IV2 IV1 IV0
1774 * and BigEndian, MC needs it as IV0 IV1 IV2 IV3
1777 for (j = 0; j < 4; j++)
1778 iv[j] = iv_s[3 - j];
1780 /* ZUC doesn't need a swap */
1781 for (j = 0; j < 4; j++)
1786 * GP op header, lengths are expected in bits.
1789 vq_cmd_w0.s.param1 = encr_data_len;
1792 * In 83XX since we have a limitation of
1793 * IV & Offset control word not part of instruction
1794 * and need to be part of Data Buffer, we check if
1795 * head room is there and then only do the Direct mode processing
1797 if (likely((req_flags & SINGLE_BUF_INPLACE) &&
1798 (req_flags & SINGLE_BUF_HEADTAILROOM))) {
1799 void *dm_vaddr = params->bufs[0].vaddr;
1800 uint64_t dm_dma_addr = params->bufs[0].dma_addr;
1802 * This flag indicates that there is 24 bytes head room and
1803 * 8 bytes tail room available, so that we get to do
1804 * DIRECT MODE with limitation
1807 offset_vaddr = (uint64_t *)((uint8_t *)dm_vaddr -
1808 OFF_CTRL_LEN - iv_len);
1809 offset_dma = dm_dma_addr - OFF_CTRL_LEN - iv_len;
1812 req->ist.ei1 = offset_dma;
1813 /* RPTR should just exclude offset control word */
1814 req->ist.ei2 = dm_dma_addr - iv_len;
1815 req->alternate_caddr = (uint64_t *)((uint8_t *)dm_vaddr
1816 + outputlen - iv_len);
1818 vq_cmd_w0.s.dlen = inputlen + OFF_CTRL_LEN;
1820 vq_cmd_w0.s.opcode = opcode.flags;
1822 if (likely(iv_len)) {
1823 uint32_t *iv_d = (uint32_t *)((uint8_t *)offset_vaddr
1825 memcpy(iv_d, iv, 16);
1828 /* iv offset is 0 */
1829 *offset_vaddr = rte_cpu_to_be_64((uint64_t)encr_offset << 16);
1831 uint32_t i, g_size_bytes, s_size_bytes;
1832 uint64_t dptr_dma, rptr_dma;
1833 sg_comp_t *gather_comp;
1834 sg_comp_t *scatter_comp;
1838 /* save space for offset and iv... */
1839 offset_vaddr = m_vaddr;
1842 m_vaddr = (uint8_t *)m_vaddr + OFF_CTRL_LEN + iv_len;
1843 m_dma += OFF_CTRL_LEN + iv_len;
1845 opcode.s.major |= CPT_DMA_MODE;
1847 vq_cmd_w0.s.opcode = opcode.flags;
1849 /* DPTR has SG list */
1850 in_buffer = m_vaddr;
1853 ((uint16_t *)in_buffer)[0] = 0;
1854 ((uint16_t *)in_buffer)[1] = 0;
1856 /* TODO Add error check if space will be sufficient */
1857 gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
1864 /* Offset control word */
1866 /* iv offset is 0 */
1867 *offset_vaddr = rte_cpu_to_be_64((uint64_t)encr_offset << 16);
1869 i = fill_sg_comp(gather_comp, i, offset_dma,
1870 OFF_CTRL_LEN + iv_len);
1872 iv_d = (uint32_t *)((uint8_t *)offset_vaddr + OFF_CTRL_LEN);
1873 memcpy(iv_d, iv, 16);
1875 /* Add input data */
1876 size = inputlen - iv_len;
1878 i = fill_sg_comp_from_iov(gather_comp, i,
1881 if (unlikely(size)) {
1882 CPT_LOG_DP_ERR("Insufficient buffer space,"
1883 " size %d needed", size);
1887 ((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
1888 g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
1891 * Output Scatter List
1896 (sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
1899 i = fill_sg_comp(scatter_comp, i,
1900 offset_dma + OFF_CTRL_LEN,
1903 /* Add output data */
1904 size = outputlen - iv_len;
1906 i = fill_sg_comp_from_iov(scatter_comp, i,
1910 if (unlikely(size)) {
1911 CPT_LOG_DP_ERR("Insufficient buffer space,"
1912 " size %d needed", size);
1916 ((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
1917 s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
1919 size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
1921 /* This is DPTR len incase of SG mode */
1922 vq_cmd_w0.s.dlen = size;
1924 m_vaddr = (uint8_t *)m_vaddr + size;
1927 /* cpt alternate completion address saved earlier */
1928 req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
1929 *req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
1930 rptr_dma = c_dma - 8;
1932 req->ist.ei1 = dptr_dma;
1933 req->ist.ei2 = rptr_dma;
1938 vq_cmd_w3.s.grp = 0;
1939 vq_cmd_w3.s.cptr = params->ctx_buf.dma_addr +
1940 offsetof(struct cpt_ctx, zs_ctx);
1942 /* 16 byte aligned cpt res address */
1943 req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
1944 *req->completion_addr = COMPLETION_CODE_INIT;
1945 req->comp_baddr = c_dma;
1947 /* Fill microcode part of instruction */
1948 req->ist.ei0 = vq_cmd_w0.u64;
1949 req->ist.ei3 = vq_cmd_w3.u64;
1957 static __rte_always_inline void
1958 cpt_kasumi_enc_prep(uint32_t req_flags,
1961 fc_params_t *params,
1966 int32_t inputlen = 0, outputlen = 0;
1967 struct cpt_ctx *cpt_ctx;
1968 uint32_t mac_len = 0;
1970 struct cpt_request_info *req;
1972 uint32_t encr_offset, auth_offset;
1973 uint32_t encr_data_len, auth_data_len;
1975 uint8_t *iv_s, *iv_d, iv_len = 8;
1977 void *m_vaddr, *c_vaddr;
1978 uint64_t m_dma, c_dma;
1979 uint64_t *offset_vaddr, offset_dma;
1980 vq_cmd_word0_t vq_cmd_w0;
1981 vq_cmd_word3_t vq_cmd_w3;
1982 opcode_info_t opcode;
1984 uint32_t g_size_bytes, s_size_bytes;
1985 uint64_t dptr_dma, rptr_dma;
1986 sg_comp_t *gather_comp;
1987 sg_comp_t *scatter_comp;
1989 buf_p = ¶ms->meta_buf;
1990 m_vaddr = buf_p->vaddr;
1991 m_dma = buf_p->dma_addr;
1993 encr_offset = ENCR_OFFSET(d_offs) / 8;
1994 auth_offset = AUTH_OFFSET(d_offs) / 8;
1995 encr_data_len = ENCR_DLEN(d_lens);
1996 auth_data_len = AUTH_DLEN(d_lens);
1998 cpt_ctx = params->ctx_buf.vaddr;
1999 flags = cpt_ctx->zsk_flags;
2000 mac_len = cpt_ctx->mac_len;
2003 iv_s = params->iv_buf;
2005 iv_s = params->auth_iv_buf;
2007 dir = iv_s[8] & 0x1;
2010 * Save initial space that followed app data for completion code &
2011 * alternate completion code to fall in same cache line as app data
2013 m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
2014 m_dma += COMPLETION_CODE_SIZE;
2015 size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
2018 c_vaddr = (uint8_t *)m_vaddr + size;
2019 c_dma = m_dma + size;
2020 size += sizeof(cpt_res_s_t);
2022 m_vaddr = (uint8_t *)m_vaddr + size;
2025 /* Reserve memory for cpt request info */
2028 size = sizeof(struct cpt_request_info);
2029 m_vaddr = (uint8_t *)m_vaddr + size;
2032 opcode.s.major = CPT_MAJOR_OP_KASUMI | CPT_DMA_MODE;
2034 /* indicates ECB/CBC, direction, ctx from cptr, iv from dptr */
2035 opcode.s.minor = ((1 << 6) | (cpt_ctx->k_ecb << 5) |
2036 (dir << 4) | (0 << 3) | (flags & 0x7));
2039 * GP op header, lengths are expected in bits.
2042 vq_cmd_w0.s.param1 = encr_data_len;
2043 vq_cmd_w0.s.param2 = auth_data_len;
2044 vq_cmd_w0.s.opcode = opcode.flags;
2046 /* consider iv len */
2048 encr_offset += iv_len;
2049 auth_offset += iv_len;
2052 /* save space for offset ctrl and iv */
2053 offset_vaddr = m_vaddr;
2056 m_vaddr = (uint8_t *)m_vaddr + OFF_CTRL_LEN + iv_len;
2057 m_dma += OFF_CTRL_LEN + iv_len;
2059 /* DPTR has SG list */
2060 in_buffer = m_vaddr;
2063 ((uint16_t *)in_buffer)[0] = 0;
2064 ((uint16_t *)in_buffer)[1] = 0;
2066 /* TODO Add error check if space will be sufficient */
2067 gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
2074 /* Offset control word followed by iv */
2077 inputlen = encr_offset + (RTE_ALIGN(encr_data_len, 8) / 8);
2078 outputlen = inputlen;
2079 /* iv offset is 0 */
2080 *offset_vaddr = rte_cpu_to_be_64((uint64_t)encr_offset << 16);
2082 inputlen = auth_offset + (RTE_ALIGN(auth_data_len, 8) / 8);
2083 outputlen = mac_len;
2084 /* iv offset is 0 */
2085 *offset_vaddr = rte_cpu_to_be_64((uint64_t)auth_offset);
2088 i = fill_sg_comp(gather_comp, i, offset_dma, OFF_CTRL_LEN + iv_len);
2091 iv_d = (uint8_t *)offset_vaddr + OFF_CTRL_LEN;
2092 memcpy(iv_d, iv_s, iv_len);
2095 size = inputlen - iv_len;
2097 i = fill_sg_comp_from_iov(gather_comp, i,
2101 if (unlikely(size)) {
2102 CPT_LOG_DP_ERR("Insufficient buffer space,"
2103 " size %d needed", size);
2107 ((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
2108 g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
2111 * Output Scatter List
2115 scatter_comp = (sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
2118 /* IV in SLIST only for F8 */
2124 i = fill_sg_comp(scatter_comp, i,
2125 offset_dma + OFF_CTRL_LEN,
2129 /* Add output data */
2130 if (req_flags & VALID_MAC_BUF) {
2131 size = outputlen - iv_len - mac_len;
2133 i = fill_sg_comp_from_iov(scatter_comp, i,
2137 if (unlikely(size)) {
2138 CPT_LOG_DP_ERR("Insufficient buffer space,"
2139 " size %d needed", size);
2146 i = fill_sg_comp_from_buf(scatter_comp, i,
2150 /* Output including mac */
2151 size = outputlen - iv_len;
2153 i = fill_sg_comp_from_iov(scatter_comp, i,
2157 if (unlikely(size)) {
2158 CPT_LOG_DP_ERR("Insufficient buffer space,"
2159 " size %d needed", size);
2164 ((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
2165 s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
2167 size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
2169 /* This is DPTR len incase of SG mode */
2170 vq_cmd_w0.s.dlen = size;
2172 m_vaddr = (uint8_t *)m_vaddr + size;
2175 /* cpt alternate completion address saved earlier */
2176 req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
2177 *req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
2178 rptr_dma = c_dma - 8;
2180 req->ist.ei1 = dptr_dma;
2181 req->ist.ei2 = rptr_dma;
2185 vq_cmd_w3.s.grp = 0;
2186 vq_cmd_w3.s.cptr = params->ctx_buf.dma_addr +
2187 offsetof(struct cpt_ctx, k_ctx);
2189 /* 16 byte aligned cpt res address */
2190 req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
2191 *req->completion_addr = COMPLETION_CODE_INIT;
2192 req->comp_baddr = c_dma;
2194 /* Fill microcode part of instruction */
2195 req->ist.ei0 = vq_cmd_w0.u64;
2196 req->ist.ei3 = vq_cmd_w3.u64;
2204 static __rte_always_inline void
2205 cpt_kasumi_dec_prep(uint64_t d_offs,
2207 fc_params_t *params,
2212 int32_t inputlen = 0, outputlen;
2213 struct cpt_ctx *cpt_ctx;
2214 uint8_t i = 0, iv_len = 8;
2215 struct cpt_request_info *req;
2217 uint32_t encr_offset;
2218 uint32_t encr_data_len;
2221 void *m_vaddr, *c_vaddr;
2222 uint64_t m_dma, c_dma;
2223 uint64_t *offset_vaddr, offset_dma;
2224 vq_cmd_word0_t vq_cmd_w0;
2225 vq_cmd_word3_t vq_cmd_w3;
2226 opcode_info_t opcode;
2228 uint32_t g_size_bytes, s_size_bytes;
2229 uint64_t dptr_dma, rptr_dma;
2230 sg_comp_t *gather_comp;
2231 sg_comp_t *scatter_comp;
2233 buf_p = ¶ms->meta_buf;
2234 m_vaddr = buf_p->vaddr;
2235 m_dma = buf_p->dma_addr;
2237 encr_offset = ENCR_OFFSET(d_offs) / 8;
2238 encr_data_len = ENCR_DLEN(d_lens);
2240 cpt_ctx = params->ctx_buf.vaddr;
2241 flags = cpt_ctx->zsk_flags;
2243 * Save initial space that followed app data for completion code &
2244 * alternate completion code to fall in same cache line as app data
2246 m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
2247 m_dma += COMPLETION_CODE_SIZE;
2248 size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
2251 c_vaddr = (uint8_t *)m_vaddr + size;
2252 c_dma = m_dma + size;
2253 size += sizeof(cpt_res_s_t);
2255 m_vaddr = (uint8_t *)m_vaddr + size;
2258 /* Reserve memory for cpt request info */
2261 size = sizeof(struct cpt_request_info);
2262 m_vaddr = (uint8_t *)m_vaddr + size;
2265 opcode.s.major = CPT_MAJOR_OP_KASUMI | CPT_DMA_MODE;
2267 /* indicates ECB/CBC, direction, ctx from cptr, iv from dptr */
2268 opcode.s.minor = ((1 << 6) | (cpt_ctx->k_ecb << 5) |
2269 (dir << 4) | (0 << 3) | (flags & 0x7));
2272 * GP op header, lengths are expected in bits.
2275 vq_cmd_w0.s.param1 = encr_data_len;
2276 vq_cmd_w0.s.opcode = opcode.flags;
2278 /* consider iv len */
2279 encr_offset += iv_len;
2281 inputlen = iv_len + (RTE_ALIGN(encr_data_len, 8) / 8);
2282 outputlen = inputlen;
2284 /* save space for offset ctrl & iv */
2285 offset_vaddr = m_vaddr;
2288 m_vaddr = (uint8_t *)m_vaddr + OFF_CTRL_LEN + iv_len;
2289 m_dma += OFF_CTRL_LEN + iv_len;
2291 /* DPTR has SG list */
2292 in_buffer = m_vaddr;
2295 ((uint16_t *)in_buffer)[0] = 0;
2296 ((uint16_t *)in_buffer)[1] = 0;
2298 /* TODO Add error check if space will be sufficient */
2299 gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
2306 /* Offset control word followed by iv */
2307 *offset_vaddr = rte_cpu_to_be_64((uint64_t)encr_offset << 16);
2309 i = fill_sg_comp(gather_comp, i, offset_dma, OFF_CTRL_LEN + iv_len);
2312 memcpy((uint8_t *)offset_vaddr + OFF_CTRL_LEN,
2313 params->iv_buf, iv_len);
2315 /* Add input data */
2316 size = inputlen - iv_len;
2318 i = fill_sg_comp_from_iov(gather_comp, i,
2321 if (unlikely(size)) {
2322 CPT_LOG_DP_ERR("Insufficient buffer space,"
2323 " size %d needed", size);
2327 ((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
2328 g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
2331 * Output Scatter List
2335 scatter_comp = (sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
2338 i = fill_sg_comp(scatter_comp, i,
2339 offset_dma + OFF_CTRL_LEN,
2342 /* Add output data */
2343 size = outputlen - iv_len;
2345 i = fill_sg_comp_from_iov(scatter_comp, i,
2348 if (unlikely(size)) {
2349 CPT_LOG_DP_ERR("Insufficient buffer space,"
2350 " size %d needed", size);
2354 ((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
2355 s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
2357 size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
2359 /* This is DPTR len incase of SG mode */
2360 vq_cmd_w0.s.dlen = size;
2362 m_vaddr = (uint8_t *)m_vaddr + size;
2365 /* cpt alternate completion address saved earlier */
2366 req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
2367 *req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
2368 rptr_dma = c_dma - 8;
2370 req->ist.ei1 = dptr_dma;
2371 req->ist.ei2 = rptr_dma;
2375 vq_cmd_w3.s.grp = 0;
2376 vq_cmd_w3.s.cptr = params->ctx_buf.dma_addr +
2377 offsetof(struct cpt_ctx, k_ctx);
2379 /* 16 byte aligned cpt res address */
2380 req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
2381 *req->completion_addr = COMPLETION_CODE_INIT;
2382 req->comp_baddr = c_dma;
2384 /* Fill microcode part of instruction */
2385 req->ist.ei0 = vq_cmd_w0.u64;
2386 req->ist.ei3 = vq_cmd_w3.u64;
2394 static __rte_always_inline void *
2395 cpt_fc_dec_hmac_prep(uint32_t flags,
2398 fc_params_t *fc_params,
2401 struct cpt_ctx *ctx = fc_params->ctx_buf.vaddr;
2403 void *prep_req = NULL;
2405 fc_type = ctx->fc_type;
2407 if (likely(fc_type == FC_GEN)) {
2408 cpt_dec_hmac_prep(flags, d_offs, d_lens, fc_params, op,
2410 } else if (fc_type == ZUC_SNOW3G) {
2411 cpt_zuc_snow3g_dec_prep(flags, d_offs, d_lens, fc_params, op,
2413 } else if (fc_type == KASUMI) {
2414 cpt_kasumi_dec_prep(d_offs, d_lens, fc_params, op, &prep_req);
2418 * For AUTH_ONLY case,
2419 * MC only supports digest generation and verification
2420 * should be done in software by memcmp()
2426 static __rte_always_inline void *__rte_hot
2427 cpt_fc_enc_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens,
2428 fc_params_t *fc_params, void *op)
2430 struct cpt_ctx *ctx = fc_params->ctx_buf.vaddr;
2432 void *prep_req = NULL;
2434 fc_type = ctx->fc_type;
2436 /* Common api for rest of the ops */
2437 if (likely(fc_type == FC_GEN)) {
2438 cpt_enc_hmac_prep(flags, d_offs, d_lens, fc_params, op,
2440 } else if (fc_type == ZUC_SNOW3G) {
2441 cpt_zuc_snow3g_enc_prep(flags, d_offs, d_lens, fc_params, op,
2443 } else if (fc_type == KASUMI) {
2444 cpt_kasumi_enc_prep(flags, d_offs, d_lens, fc_params, op,
2446 } else if (fc_type == HASH_HMAC) {
2447 cpt_digest_gen_prep(flags, d_lens, fc_params, op, &prep_req);
2453 static __rte_always_inline int
2454 cpt_fc_auth_set_key(void *ctx, auth_type_t type, const uint8_t *key,
2455 uint16_t key_len, uint16_t mac_len)
2457 struct cpt_ctx *cpt_ctx = ctx;
2458 mc_fc_context_t *fctx = &cpt_ctx->fctx;
2460 if ((type >= ZUC_EIA3) && (type <= KASUMI_F9_ECB)) {
2465 /* No support for AEAD yet */
2466 if (cpt_ctx->enc_cipher)
2468 /* For ZUC/SNOW3G/Kasumi */
2471 cpt_ctx->snow3g = 1;
2472 gen_key_snow3g(key, keyx);
2473 memcpy(cpt_ctx->zs_ctx.ci_key, keyx, key_len);
2474 cpt_ctx->fc_type = ZUC_SNOW3G;
2475 cpt_ctx->zsk_flags = 0x1;
2478 cpt_ctx->snow3g = 0;
2479 memcpy(cpt_ctx->zs_ctx.ci_key, key, key_len);
2480 memcpy(cpt_ctx->zs_ctx.zuc_const, zuc_d, 32);
2481 cpt_ctx->fc_type = ZUC_SNOW3G;
2482 cpt_ctx->zsk_flags = 0x1;
2485 /* Kasumi ECB mode */
2487 memcpy(cpt_ctx->k_ctx.ci_key, key, key_len);
2488 cpt_ctx->fc_type = KASUMI;
2489 cpt_ctx->zsk_flags = 0x1;
2492 memcpy(cpt_ctx->k_ctx.ci_key, key, key_len);
2493 cpt_ctx->fc_type = KASUMI;
2494 cpt_ctx->zsk_flags = 0x1;
2499 cpt_ctx->mac_len = 4;
2500 cpt_ctx->hash_type = type;
2504 if (!(cpt_ctx->fc_type == FC_GEN && !type)) {
2505 if (!cpt_ctx->fc_type || !cpt_ctx->enc_cipher)
2506 cpt_ctx->fc_type = HASH_HMAC;
2509 if (cpt_ctx->fc_type == FC_GEN && key_len > 64)
2512 /* For GMAC auth, cipher must be NULL */
2513 if (type == GMAC_TYPE)
2514 fctx->enc.enc_cipher = 0;
2516 fctx->enc.hash_type = cpt_ctx->hash_type = type;
2517 fctx->enc.mac_len = cpt_ctx->mac_len = mac_len;
2521 memset(cpt_ctx->auth_key, 0, sizeof(cpt_ctx->auth_key));
2522 memcpy(cpt_ctx->auth_key, key, key_len);
2523 cpt_ctx->auth_key_len = key_len;
2524 memset(fctx->hmac.ipad, 0, sizeof(fctx->hmac.ipad));
2525 memset(fctx->hmac.opad, 0, sizeof(fctx->hmac.opad));
2528 memcpy(fctx->hmac.opad, key, key_len);
2529 fctx->enc.auth_input_type = 1;
2534 static __rte_always_inline int
2535 fill_sess_aead(struct rte_crypto_sym_xform *xform,
2536 struct cpt_sess_misc *sess)
2538 struct rte_crypto_aead_xform *aead_form;
2539 cipher_type_t enc_type = 0; /* NULL Cipher type */
2540 auth_type_t auth_type = 0; /* NULL Auth type */
2541 uint32_t cipher_key_len = 0;
2542 uint8_t aes_gcm = 0;
2543 aead_form = &xform->aead;
2544 void *ctx = SESS_PRIV(sess);
2546 if (aead_form->op == RTE_CRYPTO_AEAD_OP_ENCRYPT &&
2547 aead_form->algo == RTE_CRYPTO_AEAD_AES_GCM) {
2548 sess->cpt_op |= CPT_OP_CIPHER_ENCRYPT;
2549 sess->cpt_op |= CPT_OP_AUTH_GENERATE;
2550 } else if (aead_form->op == RTE_CRYPTO_AEAD_OP_DECRYPT &&
2551 aead_form->algo == RTE_CRYPTO_AEAD_AES_GCM) {
2552 sess->cpt_op |= CPT_OP_CIPHER_DECRYPT;
2553 sess->cpt_op |= CPT_OP_AUTH_VERIFY;
2555 CPT_LOG_DP_ERR("Unknown cipher operation\n");
2558 switch (aead_form->algo) {
2559 case RTE_CRYPTO_AEAD_AES_GCM:
2561 cipher_key_len = 16;
2564 case RTE_CRYPTO_AEAD_AES_CCM:
2565 CPT_LOG_DP_ERR("Crypto: Unsupported cipher algo %u",
2569 CPT_LOG_DP_ERR("Crypto: Undefined cipher algo %u specified",
2573 if (aead_form->key.length < cipher_key_len) {
2574 CPT_LOG_DP_ERR("Invalid cipher params keylen %lu",
2575 (unsigned int long)aead_form->key.length);
2579 sess->aes_gcm = aes_gcm;
2580 sess->mac_len = aead_form->digest_length;
2581 sess->iv_offset = aead_form->iv.offset;
2582 sess->iv_length = aead_form->iv.length;
2583 sess->aad_length = aead_form->aad_length;
2585 if (unlikely(cpt_fc_ciph_set_key(ctx, enc_type, aead_form->key.data,
2586 aead_form->key.length, NULL)))
2589 if (unlikely(cpt_fc_auth_set_key(ctx, auth_type, NULL, 0,
2590 aead_form->digest_length)))
2596 static __rte_always_inline int
2597 fill_sess_cipher(struct rte_crypto_sym_xform *xform,
2598 struct cpt_sess_misc *sess)
2600 struct rte_crypto_cipher_xform *c_form;
2601 cipher_type_t enc_type = 0; /* NULL Cipher type */
2602 uint32_t cipher_key_len = 0;
2603 uint8_t zsk_flag = 0, aes_ctr = 0, is_null = 0;
2605 c_form = &xform->cipher;
2607 if (c_form->op == RTE_CRYPTO_CIPHER_OP_ENCRYPT)
2608 sess->cpt_op |= CPT_OP_CIPHER_ENCRYPT;
2609 else if (c_form->op == RTE_CRYPTO_CIPHER_OP_DECRYPT)
2610 sess->cpt_op |= CPT_OP_CIPHER_DECRYPT;
2612 CPT_LOG_DP_ERR("Unknown cipher operation\n");
2616 switch (c_form->algo) {
2617 case RTE_CRYPTO_CIPHER_AES_CBC:
2619 cipher_key_len = 16;
2621 case RTE_CRYPTO_CIPHER_3DES_CBC:
2622 enc_type = DES3_CBC;
2623 cipher_key_len = 24;
2625 case RTE_CRYPTO_CIPHER_DES_CBC:
2626 /* DES is implemented using 3DES in hardware */
2627 enc_type = DES3_CBC;
2630 case RTE_CRYPTO_CIPHER_AES_CTR:
2632 cipher_key_len = 16;
2635 case RTE_CRYPTO_CIPHER_NULL:
2639 case RTE_CRYPTO_CIPHER_KASUMI_F8:
2640 enc_type = KASUMI_F8_ECB;
2641 cipher_key_len = 16;
2644 case RTE_CRYPTO_CIPHER_SNOW3G_UEA2:
2645 enc_type = SNOW3G_UEA2;
2646 cipher_key_len = 16;
2649 case RTE_CRYPTO_CIPHER_ZUC_EEA3:
2650 enc_type = ZUC_EEA3;
2651 cipher_key_len = 16;
2654 case RTE_CRYPTO_CIPHER_AES_XTS:
2656 cipher_key_len = 16;
2658 case RTE_CRYPTO_CIPHER_3DES_ECB:
2659 enc_type = DES3_ECB;
2660 cipher_key_len = 24;
2662 case RTE_CRYPTO_CIPHER_AES_ECB:
2664 cipher_key_len = 16;
2666 case RTE_CRYPTO_CIPHER_3DES_CTR:
2667 case RTE_CRYPTO_CIPHER_AES_F8:
2668 case RTE_CRYPTO_CIPHER_ARC4:
2669 CPT_LOG_DP_ERR("Crypto: Unsupported cipher algo %u",
2673 CPT_LOG_DP_ERR("Crypto: Undefined cipher algo %u specified",
2678 if (c_form->key.length < cipher_key_len) {
2679 CPT_LOG_DP_ERR("Invalid cipher params keylen %lu",
2680 (unsigned long) c_form->key.length);
2684 sess->zsk_flag = zsk_flag;
2686 sess->aes_ctr = aes_ctr;
2687 sess->iv_offset = c_form->iv.offset;
2688 sess->iv_length = c_form->iv.length;
2689 sess->is_null = is_null;
2691 if (unlikely(cpt_fc_ciph_set_key(SESS_PRIV(sess), enc_type,
2692 c_form->key.data, c_form->key.length, NULL)))
2698 static __rte_always_inline int
2699 fill_sess_auth(struct rte_crypto_sym_xform *xform,
2700 struct cpt_sess_misc *sess)
2702 struct rte_crypto_auth_xform *a_form;
2703 auth_type_t auth_type = 0; /* NULL Auth type */
2704 uint8_t zsk_flag = 0, aes_gcm = 0, is_null = 0;
2706 a_form = &xform->auth;
2708 if (a_form->op == RTE_CRYPTO_AUTH_OP_VERIFY)
2709 sess->cpt_op |= CPT_OP_AUTH_VERIFY;
2710 else if (a_form->op == RTE_CRYPTO_AUTH_OP_GENERATE)
2711 sess->cpt_op |= CPT_OP_AUTH_GENERATE;
2713 CPT_LOG_DP_ERR("Unknown auth operation");
2717 switch (a_form->algo) {
2718 case RTE_CRYPTO_AUTH_SHA1_HMAC:
2720 case RTE_CRYPTO_AUTH_SHA1:
2721 auth_type = SHA1_TYPE;
2723 case RTE_CRYPTO_AUTH_SHA256_HMAC:
2724 case RTE_CRYPTO_AUTH_SHA256:
2725 auth_type = SHA2_SHA256;
2727 case RTE_CRYPTO_AUTH_SHA512_HMAC:
2728 case RTE_CRYPTO_AUTH_SHA512:
2729 auth_type = SHA2_SHA512;
2731 case RTE_CRYPTO_AUTH_AES_GMAC:
2732 auth_type = GMAC_TYPE;
2735 case RTE_CRYPTO_AUTH_SHA224_HMAC:
2736 case RTE_CRYPTO_AUTH_SHA224:
2737 auth_type = SHA2_SHA224;
2739 case RTE_CRYPTO_AUTH_SHA384_HMAC:
2740 case RTE_CRYPTO_AUTH_SHA384:
2741 auth_type = SHA2_SHA384;
2743 case RTE_CRYPTO_AUTH_MD5_HMAC:
2744 case RTE_CRYPTO_AUTH_MD5:
2745 auth_type = MD5_TYPE;
2747 case RTE_CRYPTO_AUTH_KASUMI_F9:
2748 auth_type = KASUMI_F9_ECB;
2750 * Indicate that direction needs to be taken out
2755 case RTE_CRYPTO_AUTH_SNOW3G_UIA2:
2756 auth_type = SNOW3G_UIA2;
2759 case RTE_CRYPTO_AUTH_ZUC_EIA3:
2760 auth_type = ZUC_EIA3;
2763 case RTE_CRYPTO_AUTH_NULL:
2767 case RTE_CRYPTO_AUTH_AES_XCBC_MAC:
2768 case RTE_CRYPTO_AUTH_AES_CMAC:
2769 case RTE_CRYPTO_AUTH_AES_CBC_MAC:
2770 CPT_LOG_DP_ERR("Crypto: Unsupported hash algo %u",
2774 CPT_LOG_DP_ERR("Crypto: Undefined Hash algo %u specified",
2779 sess->zsk_flag = zsk_flag;
2780 sess->aes_gcm = aes_gcm;
2781 sess->mac_len = a_form->digest_length;
2782 sess->is_null = is_null;
2784 sess->auth_iv_offset = a_form->iv.offset;
2785 sess->auth_iv_length = a_form->iv.length;
2787 if (unlikely(cpt_fc_auth_set_key(SESS_PRIV(sess), auth_type,
2788 a_form->key.data, a_form->key.length,
2789 a_form->digest_length)))
2795 static __rte_always_inline int
2796 fill_sess_gmac(struct rte_crypto_sym_xform *xform,
2797 struct cpt_sess_misc *sess)
2799 struct rte_crypto_auth_xform *a_form;
2800 cipher_type_t enc_type = 0; /* NULL Cipher type */
2801 auth_type_t auth_type = 0; /* NULL Auth type */
2802 void *ctx = SESS_PRIV(sess);
2804 a_form = &xform->auth;
2806 if (a_form->op == RTE_CRYPTO_AUTH_OP_GENERATE)
2807 sess->cpt_op |= CPT_OP_ENCODE;
2808 else if (a_form->op == RTE_CRYPTO_AUTH_OP_VERIFY)
2809 sess->cpt_op |= CPT_OP_DECODE;
2811 CPT_LOG_DP_ERR("Unknown auth operation");
2815 switch (a_form->algo) {
2816 case RTE_CRYPTO_AUTH_AES_GMAC:
2818 auth_type = GMAC_TYPE;
2821 CPT_LOG_DP_ERR("Crypto: Undefined cipher algo %u specified",
2829 sess->iv_offset = a_form->iv.offset;
2830 sess->iv_length = a_form->iv.length;
2831 sess->mac_len = a_form->digest_length;
2833 if (unlikely(cpt_fc_ciph_set_key(ctx, enc_type, a_form->key.data,
2834 a_form->key.length, NULL)))
2837 if (unlikely(cpt_fc_auth_set_key(ctx, auth_type, NULL, 0,
2838 a_form->digest_length)))
2844 static __rte_always_inline void *
2845 alloc_op_meta(struct rte_mbuf *m_src,
2848 struct rte_mempool *cpt_meta_pool)
2852 #ifndef CPT_ALWAYS_USE_SEPARATE_BUF
2853 if (likely(m_src && (m_src->nb_segs == 1))) {
2857 /* Check if tailroom is sufficient to hold meta data */
2858 tailroom = rte_pktmbuf_tailroom(m_src);
2859 if (likely(tailroom > len + 8)) {
2860 mdata = (uint8_t *)m_src->buf_addr + m_src->buf_len;
2861 mphys = m_src->buf_physaddr + m_src->buf_len;
2865 buf->dma_addr = mphys;
2867 /* Indicate that this is a mbuf allocated mdata */
2868 mdata = (uint8_t *)((uint64_t)mdata | 1ull);
2873 RTE_SET_USED(m_src);
2876 if (unlikely(rte_mempool_get(cpt_meta_pool, (void **)&mdata) < 0))
2880 buf->dma_addr = rte_mempool_virt2iova(mdata);
2887 * cpt_free_metabuf - free metabuf to mempool.
2888 * @param instance: pointer to instance.
2889 * @param objp: pointer to the metabuf.
2891 static __rte_always_inline void
2892 free_op_meta(void *mdata, struct rte_mempool *cpt_meta_pool)
2894 bool nofree = ((uintptr_t)mdata & 1ull);
2898 rte_mempool_put(cpt_meta_pool, mdata);
2901 static __rte_always_inline uint32_t
2902 prepare_iov_from_pkt(struct rte_mbuf *pkt,
2903 iov_ptr_t *iovec, uint32_t start_offset)
2906 void *seg_data = NULL;
2907 phys_addr_t seg_phys;
2908 int32_t seg_size = 0;
2915 if (!start_offset) {
2916 seg_data = rte_pktmbuf_mtod(pkt, void *);
2917 seg_phys = rte_pktmbuf_mtophys(pkt);
2918 seg_size = pkt->data_len;
2920 while (start_offset >= pkt->data_len) {
2921 start_offset -= pkt->data_len;
2925 seg_data = rte_pktmbuf_mtod_offset(pkt, void *, start_offset);
2926 seg_phys = rte_pktmbuf_mtophys_offset(pkt, start_offset);
2927 seg_size = pkt->data_len - start_offset;
2933 iovec->bufs[index].vaddr = seg_data;
2934 iovec->bufs[index].dma_addr = seg_phys;
2935 iovec->bufs[index].size = seg_size;
2939 while (unlikely(pkt != NULL)) {
2940 seg_data = rte_pktmbuf_mtod(pkt, void *);
2941 seg_phys = rte_pktmbuf_mtophys(pkt);
2942 seg_size = pkt->data_len;
2946 iovec->bufs[index].vaddr = seg_data;
2947 iovec->bufs[index].dma_addr = seg_phys;
2948 iovec->bufs[index].size = seg_size;
2955 iovec->buf_cnt = index;
2959 static __rte_always_inline uint32_t
2960 prepare_iov_from_pkt_inplace(struct rte_mbuf *pkt,
2965 void *seg_data = NULL;
2966 phys_addr_t seg_phys;
2967 uint32_t seg_size = 0;
2970 seg_data = rte_pktmbuf_mtod(pkt, void *);
2971 seg_phys = rte_pktmbuf_mtophys(pkt);
2972 seg_size = pkt->data_len;
2975 if (likely(!pkt->next)) {
2976 uint32_t headroom, tailroom;
2978 *flags |= SINGLE_BUF_INPLACE;
2979 headroom = rte_pktmbuf_headroom(pkt);
2980 tailroom = rte_pktmbuf_tailroom(pkt);
2981 if (likely((headroom >= 24) &&
2983 /* In 83XX this is prerequivisit for Direct mode */
2984 *flags |= SINGLE_BUF_HEADTAILROOM;
2986 param->bufs[0].vaddr = seg_data;
2987 param->bufs[0].dma_addr = seg_phys;
2988 param->bufs[0].size = seg_size;
2991 iovec = param->src_iov;
2992 iovec->bufs[index].vaddr = seg_data;
2993 iovec->bufs[index].dma_addr = seg_phys;
2994 iovec->bufs[index].size = seg_size;
2998 while (unlikely(pkt != NULL)) {
2999 seg_data = rte_pktmbuf_mtod(pkt, void *);
3000 seg_phys = rte_pktmbuf_mtophys(pkt);
3001 seg_size = pkt->data_len;
3006 iovec->bufs[index].vaddr = seg_data;
3007 iovec->bufs[index].dma_addr = seg_phys;
3008 iovec->bufs[index].size = seg_size;
3015 iovec->buf_cnt = index;
3019 static __rte_always_inline int
3020 fill_fc_params(struct rte_crypto_op *cop,
3021 struct cpt_sess_misc *sess_misc,
3022 struct cpt_qp_meta_info *m_info,
3027 struct rte_crypto_sym_op *sym_op = cop->sym;
3030 uint32_t mc_hash_off;
3032 uint64_t d_offs, d_lens;
3033 struct rte_mbuf *m_src, *m_dst;
3034 uint8_t cpt_op = sess_misc->cpt_op;
3035 #ifdef CPT_ALWAYS_USE_SG_MODE
3036 uint8_t inplace = 0;
3038 uint8_t inplace = 1;
3040 fc_params_t fc_params;
3041 char src[SRC_IOV_SIZE];
3042 char dst[SRC_IOV_SIZE];
3046 if (likely(sess_misc->iv_length)) {
3047 flags |= VALID_IV_BUF;
3048 fc_params.iv_buf = rte_crypto_op_ctod_offset(cop,
3049 uint8_t *, sess_misc->iv_offset);
3050 if (sess_misc->aes_ctr &&
3051 unlikely(sess_misc->iv_length != 16)) {
3052 memcpy((uint8_t *)iv_buf,
3053 rte_crypto_op_ctod_offset(cop,
3054 uint8_t *, sess_misc->iv_offset), 12);
3055 iv_buf[3] = rte_cpu_to_be_32(0x1);
3056 fc_params.iv_buf = iv_buf;
3060 if (sess_misc->zsk_flag) {
3061 fc_params.auth_iv_buf = rte_crypto_op_ctod_offset(cop,
3063 sess_misc->auth_iv_offset);
3064 if (sess_misc->zsk_flag != ZS_EA)
3067 m_src = sym_op->m_src;
3068 m_dst = sym_op->m_dst;
3070 if (sess_misc->aes_gcm) {
3075 d_offs = sym_op->aead.data.offset;
3076 d_lens = sym_op->aead.data.length;
3077 mc_hash_off = sym_op->aead.data.offset +
3078 sym_op->aead.data.length;
3080 aad_data = sym_op->aead.aad.data;
3081 aad_len = sess_misc->aad_length;
3082 if (likely((aad_data + aad_len) ==
3083 rte_pktmbuf_mtod_offset(m_src,
3085 sym_op->aead.data.offset))) {
3086 d_offs = (d_offs - aad_len) | (d_offs << 16);
3087 d_lens = (d_lens + aad_len) | (d_lens << 32);
3089 fc_params.aad_buf.vaddr = sym_op->aead.aad.data;
3090 fc_params.aad_buf.dma_addr = sym_op->aead.aad.phys_addr;
3091 fc_params.aad_buf.size = aad_len;
3092 flags |= VALID_AAD_BUF;
3094 d_offs = d_offs << 16;
3095 d_lens = d_lens << 32;
3098 salt = fc_params.iv_buf;
3099 if (unlikely(*(uint32_t *)salt != sess_misc->salt)) {
3100 cpt_fc_salt_update(SESS_PRIV(sess_misc), salt);
3101 sess_misc->salt = *(uint32_t *)salt;
3103 fc_params.iv_buf = salt + 4;
3104 if (likely(sess_misc->mac_len)) {
3105 struct rte_mbuf *m = (cpt_op & CPT_OP_ENCODE) ? m_dst :
3111 /* hmac immediately following data is best case */
3112 if (unlikely(rte_pktmbuf_mtod(m, uint8_t *) +
3114 (uint8_t *)sym_op->aead.digest.data)) {
3115 flags |= VALID_MAC_BUF;
3116 fc_params.mac_buf.size = sess_misc->mac_len;
3117 fc_params.mac_buf.vaddr =
3118 sym_op->aead.digest.data;
3119 fc_params.mac_buf.dma_addr =
3120 sym_op->aead.digest.phys_addr;
3125 d_offs = sym_op->cipher.data.offset;
3126 d_lens = sym_op->cipher.data.length;
3127 mc_hash_off = sym_op->cipher.data.offset +
3128 sym_op->cipher.data.length;
3129 d_offs = (d_offs << 16) | sym_op->auth.data.offset;
3130 d_lens = (d_lens << 32) | sym_op->auth.data.length;
3132 if (mc_hash_off < (sym_op->auth.data.offset +
3133 sym_op->auth.data.length)){
3134 mc_hash_off = (sym_op->auth.data.offset +
3135 sym_op->auth.data.length);
3137 /* for gmac, salt should be updated like in gcm */
3138 if (unlikely(sess_misc->is_gmac)) {
3140 salt = fc_params.iv_buf;
3141 if (unlikely(*(uint32_t *)salt != sess_misc->salt)) {
3142 cpt_fc_salt_update(SESS_PRIV(sess_misc), salt);
3143 sess_misc->salt = *(uint32_t *)salt;
3145 fc_params.iv_buf = salt + 4;
3147 if (likely(sess_misc->mac_len)) {
3150 m = (cpt_op & CPT_OP_ENCODE) ? m_dst : m_src;
3154 /* hmac immediately following data is best case */
3155 if (unlikely(rte_pktmbuf_mtod(m, uint8_t *) +
3157 (uint8_t *)sym_op->auth.digest.data)) {
3158 flags |= VALID_MAC_BUF;
3159 fc_params.mac_buf.size =
3161 fc_params.mac_buf.vaddr =
3162 sym_op->auth.digest.data;
3163 fc_params.mac_buf.dma_addr =
3164 sym_op->auth.digest.phys_addr;
3169 fc_params.ctx_buf.vaddr = SESS_PRIV(sess_misc);
3170 fc_params.ctx_buf.dma_addr = sess_misc->ctx_dma_addr;
3172 if (unlikely(sess_misc->is_null || sess_misc->cpt_op == CPT_OP_DECODE))
3175 if (likely(!m_dst && inplace)) {
3176 /* Case of single buffer without AAD buf or
3177 * separate mac buf in place and
3180 fc_params.dst_iov = fc_params.src_iov = (void *)src;
3182 if (unlikely(prepare_iov_from_pkt_inplace(m_src,
3185 CPT_LOG_DP_ERR("Prepare inplace src iov failed");
3191 /* Out of place processing */
3192 fc_params.src_iov = (void *)src;
3193 fc_params.dst_iov = (void *)dst;
3195 /* Store SG I/O in the api for reuse */
3196 if (prepare_iov_from_pkt(m_src, fc_params.src_iov, 0)) {
3197 CPT_LOG_DP_ERR("Prepare src iov failed");
3202 if (unlikely(m_dst != NULL)) {
3205 /* Try to make room as much as src has */
3206 pkt_len = rte_pktmbuf_pkt_len(m_dst);
3208 if (unlikely(pkt_len < rte_pktmbuf_pkt_len(m_src))) {
3209 pkt_len = rte_pktmbuf_pkt_len(m_src) - pkt_len;
3210 if (!rte_pktmbuf_append(m_dst, pkt_len)) {
3211 CPT_LOG_DP_ERR("Not enough space in "
3220 if (prepare_iov_from_pkt(m_dst, fc_params.dst_iov, 0)) {
3221 CPT_LOG_DP_ERR("Prepare dst iov failed for "
3227 fc_params.dst_iov = (void *)src;
3231 if (likely(flags & SINGLE_BUF_HEADTAILROOM))
3232 mdata = alloc_op_meta(m_src, &fc_params.meta_buf,
3233 m_info->lb_mlen, m_info->pool);
3235 mdata = alloc_op_meta(NULL, &fc_params.meta_buf,
3236 m_info->sg_mlen, m_info->pool);
3238 if (unlikely(mdata == NULL)) {
3239 CPT_LOG_DP_ERR("Error allocating meta buffer for request");
3244 op = (uintptr_t *)((uintptr_t)mdata & (uintptr_t)~1ull);
3245 op[0] = (uintptr_t)mdata;
3246 op[1] = (uintptr_t)cop;
3247 op[2] = op[3] = 0; /* Used to indicate auth verify */
3248 space += 4 * sizeof(uint64_t);
3250 fc_params.meta_buf.vaddr = (uint8_t *)op + space;
3251 fc_params.meta_buf.dma_addr += space;
3252 fc_params.meta_buf.size -= space;
3254 /* Finally prepare the instruction */
3255 if (cpt_op & CPT_OP_ENCODE)
3256 *prep_req = cpt_fc_enc_hmac_prep(flags, d_offs, d_lens,
3259 *prep_req = cpt_fc_dec_hmac_prep(flags, d_offs, d_lens,
3262 if (unlikely(*prep_req == NULL)) {
3263 CPT_LOG_DP_ERR("Preparing request failed due to bad input arg");
3265 goto free_mdata_and_exit;
3272 free_mdata_and_exit:
3273 free_op_meta(mdata, m_info->pool);
3278 static __rte_always_inline void
3279 compl_auth_verify(struct rte_crypto_op *op,
3284 struct rte_crypto_sym_op *sym_op = op->sym;
3286 if (sym_op->auth.digest.data)
3287 mac = sym_op->auth.digest.data;
3289 mac = rte_pktmbuf_mtod_offset(sym_op->m_src,
3291 sym_op->auth.data.length +
3292 sym_op->auth.data.offset);
3294 op->status = RTE_CRYPTO_OP_STATUS_ERROR;
3298 if (memcmp(mac, gen_mac, mac_len))
3299 op->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
3301 op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
3304 static __rte_always_inline void
3305 find_kasumif9_direction_and_length(uint8_t *src,
3306 uint32_t counter_num_bytes,
3307 uint32_t *addr_length_in_bits,
3308 uint8_t *addr_direction)
3313 while (!found && counter_num_bytes > 0) {
3314 counter_num_bytes--;
3315 if (src[counter_num_bytes] == 0x00)
3317 pos = rte_bsf32(src[counter_num_bytes]);
3319 if (likely(counter_num_bytes > 0)) {
3320 last_byte = src[counter_num_bytes - 1];
3321 *addr_direction = last_byte & 0x1;
3322 *addr_length_in_bits = counter_num_bytes * 8
3326 last_byte = src[counter_num_bytes];
3327 *addr_direction = (last_byte >> (pos + 1)) & 0x1;
3328 *addr_length_in_bits = counter_num_bytes * 8
3336 * This handles all auth only except AES_GMAC
3338 static __rte_always_inline int
3339 fill_digest_params(struct rte_crypto_op *cop,
3340 struct cpt_sess_misc *sess,
3341 struct cpt_qp_meta_info *m_info,
3346 struct rte_crypto_sym_op *sym_op = cop->sym;
3350 uint32_t auth_range_off;
3352 uint64_t d_offs = 0, d_lens;
3353 struct rte_mbuf *m_src, *m_dst;
3354 uint16_t auth_op = sess->cpt_op & CPT_OP_AUTH_MASK;
3355 uint16_t mac_len = sess->mac_len;
3357 char src[SRC_IOV_SIZE];
3361 memset(¶ms, 0, sizeof(fc_params_t));
3363 m_src = sym_op->m_src;
3365 /* For just digest lets force mempool alloc */
3366 mdata = alloc_op_meta(NULL, ¶ms.meta_buf, m_info->sg_mlen,
3368 if (mdata == NULL) {
3373 mphys = params.meta_buf.dma_addr;
3376 op[0] = (uintptr_t)mdata;
3377 op[1] = (uintptr_t)cop;
3378 op[2] = op[3] = 0; /* Used to indicate auth verify */
3379 space += 4 * sizeof(uint64_t);
3381 auth_range_off = sym_op->auth.data.offset;
3383 flags = VALID_MAC_BUF;
3384 params.src_iov = (void *)src;
3385 if (unlikely(sess->zsk_flag)) {
3387 * Since for Zuc, Kasumi, Snow3g offsets are in bits
3388 * we will send pass through even for auth only case,
3391 d_offs = auth_range_off;
3393 params.auth_iv_buf = rte_crypto_op_ctod_offset(cop,
3394 uint8_t *, sess->auth_iv_offset);
3395 if (sess->zsk_flag == K_F9) {
3396 uint32_t length_in_bits, num_bytes;
3397 uint8_t *src, direction = 0;
3399 memcpy(iv_buf, rte_pktmbuf_mtod(cop->sym->m_src,
3402 * This is kasumi f9, take direction from
3405 length_in_bits = cop->sym->auth.data.length;
3406 num_bytes = (length_in_bits >> 3);
3407 src = rte_pktmbuf_mtod(cop->sym->m_src, uint8_t *);
3408 find_kasumif9_direction_and_length(src,
3412 length_in_bits -= 64;
3413 cop->sym->auth.data.offset += 64;
3414 d_offs = cop->sym->auth.data.offset;
3415 auth_range_off = d_offs / 8;
3416 cop->sym->auth.data.length = length_in_bits;
3418 /* Store it at end of auth iv */
3419 iv_buf[8] = direction;
3420 params.auth_iv_buf = iv_buf;
3424 d_lens = sym_op->auth.data.length;
3426 params.ctx_buf.vaddr = SESS_PRIV(sess);
3427 params.ctx_buf.dma_addr = sess->ctx_dma_addr;
3429 if (auth_op == CPT_OP_AUTH_GENERATE) {
3430 if (sym_op->auth.digest.data) {
3432 * Digest to be generated
3433 * in separate buffer
3435 params.mac_buf.size =
3437 params.mac_buf.vaddr =
3438 sym_op->auth.digest.data;
3439 params.mac_buf.dma_addr =
3440 sym_op->auth.digest.phys_addr;
3442 uint32_t off = sym_op->auth.data.offset +
3443 sym_op->auth.data.length;
3444 int32_t dlen, space;
3446 m_dst = sym_op->m_dst ?
3447 sym_op->m_dst : sym_op->m_src;
3448 dlen = rte_pktmbuf_pkt_len(m_dst);
3450 space = off + mac_len - dlen;
3452 if (!rte_pktmbuf_append(m_dst, space)) {
3453 CPT_LOG_DP_ERR("Failed to extend "
3454 "mbuf by %uB", space);
3456 goto free_mdata_and_exit;
3459 params.mac_buf.vaddr =
3460 rte_pktmbuf_mtod_offset(m_dst, void *, off);
3461 params.mac_buf.dma_addr =
3462 rte_pktmbuf_mtophys_offset(m_dst, off);
3463 params.mac_buf.size = mac_len;
3466 /* Need space for storing generated mac */
3467 params.mac_buf.vaddr = (uint8_t *)mdata + space;
3468 params.mac_buf.dma_addr = mphys + space;
3469 params.mac_buf.size = mac_len;
3470 space += RTE_ALIGN_CEIL(mac_len, 8);
3471 op[2] = (uintptr_t)params.mac_buf.vaddr;
3475 params.meta_buf.vaddr = (uint8_t *)mdata + space;
3476 params.meta_buf.dma_addr = mphys + space;
3477 params.meta_buf.size -= space;
3479 /* Out of place processing */
3480 params.src_iov = (void *)src;
3482 /*Store SG I/O in the api for reuse */
3483 if (prepare_iov_from_pkt(m_src, params.src_iov, auth_range_off)) {
3484 CPT_LOG_DP_ERR("Prepare src iov failed");
3486 goto free_mdata_and_exit;
3489 *prep_req = cpt_fc_enc_hmac_prep(flags, d_offs, d_lens, ¶ms, op);
3490 if (unlikely(*prep_req == NULL)) {
3492 goto free_mdata_and_exit;
3499 free_mdata_and_exit:
3500 free_op_meta(mdata, m_info->pool);
3505 #endif /*_CPT_UCODE_H_ */