drivers/common/cpt/cpt_ucode.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Cavium, Inc
   3  */
   4
   5 #ifndef _CPT_UCODE_H_
   6 #define _CPT_UCODE_H_
   7 #include <stdbool.h>
   8
   9 #include "cpt_common.h"
  10 #include "cpt_hw_types.h"
  11 #include "cpt_mcode_defines.h"
  12
  13 /*
  14  * This file defines functions that are interfaces to microcode spec.
  15  *
  16  */
  17
  18 static uint8_t zuc_d[32] = {
  19         0x44, 0xD7, 0x26, 0xBC, 0x62, 0x6B, 0x13, 0x5E,
  20         0x57, 0x89, 0x35, 0xE2, 0x71, 0x35, 0x09, 0xAF,
  21         0x4D, 0x78, 0x2F, 0x13, 0x6B, 0xC4, 0x1A, 0xF1,
  22         0x5E, 0x26, 0x3C, 0x4D, 0x78, 0x9A, 0x47, 0xAC
  23 };
  24
  25 static __rte_always_inline void
  26 gen_key_snow3g(const uint8_t *ck, uint32_t *keyx)
  27 {
  28         int i, base;
  29
  30         for (i = 0; i < 4; i++) {
  31                 base = 4 * i;
  32                 keyx[3 - i] = (ck[base] << 24) | (ck[base + 1] << 16) |
  33                         (ck[base + 2] << 8) | (ck[base + 3]);
  34                 keyx[3 - i] = rte_cpu_to_be_32(keyx[3 - i]);
  35         }
  36 }
  37
  38 static __rte_always_inline int
  39 cpt_mac_len_verify(struct rte_crypto_auth_xform *auth)
  40 {
  41         uint16_t mac_len = auth->digest_length;
  42         int ret;
  43
  44         switch (auth->algo) {
  45         case RTE_CRYPTO_AUTH_MD5:
  46         case RTE_CRYPTO_AUTH_MD5_HMAC:
  47                 ret = (mac_len == 16) ? 0 : -1;
  48                 break;
  49         case RTE_CRYPTO_AUTH_SHA1:
  50         case RTE_CRYPTO_AUTH_SHA1_HMAC:
  51                 ret = (mac_len == 20) ? 0 : -1;
  52                 break;
  53         case RTE_CRYPTO_AUTH_SHA224:
  54         case RTE_CRYPTO_AUTH_SHA224_HMAC:
  55                 ret = (mac_len == 28) ? 0 : -1;
  56                 break;
  57         case RTE_CRYPTO_AUTH_SHA256:
  58         case RTE_CRYPTO_AUTH_SHA256_HMAC:
  59                 ret = (mac_len == 32) ? 0 : -1;
  60                 break;
  61         case RTE_CRYPTO_AUTH_SHA384:
  62         case RTE_CRYPTO_AUTH_SHA384_HMAC:
  63                 ret = (mac_len == 48) ? 0 : -1;
  64                 break;
  65         case RTE_CRYPTO_AUTH_SHA512:
  66         case RTE_CRYPTO_AUTH_SHA512_HMAC:
  67                 ret = (mac_len == 64) ? 0 : -1;
  68                 break;
  69         case RTE_CRYPTO_AUTH_NULL:
  70                 ret = 0;
  71                 break;
  72         default:
  73                 ret = -1;
  74         }
  75
  76         return ret;
  77 }
  78
  79 static __rte_always_inline void
  80 cpt_fc_salt_update(struct cpt_ctx *cpt_ctx,
  81                    uint8_t *salt)
  82 {
  83         mc_fc_context_t *fctx = &cpt_ctx->mc_ctx.fctx;
  84         memcpy(fctx->enc.encr_iv, salt, 4);
  85 }
  86
  87 static __rte_always_inline int
  88 cpt_fc_ciph_validate_key_aes(uint16_t key_len)
  89 {
  90         switch (key_len) {
  91         case 16:
  92         case 24:
  93         case 32:
  94                 return 0;
  95         default:
  96                 return -1;
  97         }
  98 }
  99
 100 static __rte_always_inline int
 101 cpt_fc_ciph_set_type(cipher_type_t type, struct cpt_ctx *ctx, uint16_t key_len)
 102 {
 103         int fc_type = 0;
 104         switch (type) {
 105         case PASSTHROUGH:
 106                 fc_type = FC_GEN;
 107                 break;
 108         case DES3_CBC:
 109         case DES3_ECB:
 110                 fc_type = FC_GEN;
 111                 break;
 112         case AES_CBC:
 113         case AES_ECB:
 114         case AES_CFB:
 115         case AES_CTR:
 116         case AES_GCM:
 117                 if (unlikely(cpt_fc_ciph_validate_key_aes(key_len) != 0))
 118                         return -1;
 119                 fc_type = FC_GEN;
 120                 break;
 121         case CHACHA20:
 122                 fc_type = FC_GEN;
 123                 break;
 124         case AES_XTS:
 125                 key_len = key_len / 2;
 126                 if (unlikely(key_len == 24)) {
 127                         CPT_LOG_DP_ERR("Invalid AES key len for XTS");
 128                         return -1;
 129                 }
 130                 if (unlikely(cpt_fc_ciph_validate_key_aes(key_len) != 0))
 131                         return -1;
 132                 fc_type = FC_GEN;
 133                 break;
 134         case ZUC_EEA3:
 135         case SNOW3G_UEA2:
 136                 if (unlikely(key_len != 16))
 137                         return -1;
 138                 /* No support for AEAD yet */
 139                 if (unlikely(ctx->hash_type))
 140                         return -1;
 141                 fc_type = ZUC_SNOW3G;
 142                 break;
 143         case KASUMI_F8_CBC:
 144         case KASUMI_F8_ECB:
 145                 if (unlikely(key_len != 16))
 146                         return -1;
 147                 /* No support for AEAD yet */
 148                 if (unlikely(ctx->hash_type))
 149                         return -1;
 150                 fc_type = KASUMI;
 151                 break;
 152         default:
 153                 return -1;
 154         }
 155
 156         ctx->fc_type = fc_type;
 157         return 0;
 158 }
 159
 160 static __rte_always_inline void
 161 cpt_fc_ciph_set_key_passthrough(struct cpt_ctx *cpt_ctx, mc_fc_context_t *fctx)
 162 {
 163         cpt_ctx->enc_cipher = 0;
 164         fctx->enc.enc_cipher = 0;
 165 }
 166
 167 static __rte_always_inline void
 168 cpt_fc_ciph_set_key_set_aes_key_type(mc_fc_context_t *fctx, uint16_t key_len)
 169 {
 170         mc_aes_type_t aes_key_type = 0;
 171         switch (key_len) {
 172         case 16:
 173                 aes_key_type = AES_128_BIT;
 174                 break;
 175         case 24:
 176                 aes_key_type = AES_192_BIT;
 177                 break;
 178         case 32:
 179                 aes_key_type = AES_256_BIT;
 180                 break;
 181         default:
 182                 /* This should not happen */
 183                 CPT_LOG_DP_ERR("Invalid AES key len");
 184                 return;
 185         }
 186         fctx->enc.aes_key = aes_key_type;
 187 }
 188
 189 static __rte_always_inline void
 190 cpt_fc_ciph_set_key_snow3g_uea2(struct cpt_ctx *cpt_ctx, const uint8_t *key,
 191                 uint16_t key_len)
 192 {
 193         mc_zuc_snow3g_ctx_t *zs_ctx = &cpt_ctx->mc_ctx.zs_ctx;
 194         uint32_t keyx[4];
 195
 196         cpt_ctx->snow3g = 1;
 197         gen_key_snow3g(key, keyx);
 198         memcpy(zs_ctx->ci_key, keyx, key_len);
 199         cpt_ctx->zsk_flags = 0;
 200 }
 201
 202 static __rte_always_inline void
 203 cpt_fc_ciph_set_key_zuc_eea3(struct cpt_ctx *cpt_ctx, const uint8_t *key,
 204                 uint16_t key_len)
 205 {
 206         mc_zuc_snow3g_ctx_t *zs_ctx = &cpt_ctx->mc_ctx.zs_ctx;
 207
 208         cpt_ctx->snow3g = 0;
 209         memcpy(zs_ctx->ci_key, key, key_len);
 210         memcpy(zs_ctx->zuc_const, zuc_d, 32);
 211         cpt_ctx->zsk_flags = 0;
 212 }
 213
 214 static __rte_always_inline void
 215 cpt_fc_ciph_set_key_kasumi_f8_ecb(struct cpt_ctx *cpt_ctx, const uint8_t *key,
 216                 uint16_t key_len)
 217 {
 218         mc_kasumi_ctx_t *k_ctx = &cpt_ctx->mc_ctx.k_ctx;
 219
 220         cpt_ctx->k_ecb = 1;
 221         memcpy(k_ctx->ci_key, key, key_len);
 222         cpt_ctx->zsk_flags = 0;
 223 }
 224
 225 static __rte_always_inline void
 226 cpt_fc_ciph_set_key_kasumi_f8_cbc(struct cpt_ctx *cpt_ctx, const uint8_t *key,
 227                 uint16_t key_len)
 228 {
 229         mc_kasumi_ctx_t *k_ctx = &cpt_ctx->mc_ctx.k_ctx;
 230
 231         memcpy(k_ctx->ci_key, key, key_len);
 232         cpt_ctx->zsk_flags = 0;
 233 }
 234
 235 static __rte_always_inline int
 236 cpt_fc_ciph_set_key(struct cpt_ctx *cpt_ctx, cipher_type_t type,
 237                     const uint8_t *key, uint16_t key_len, uint8_t *salt)
 238 {
 239         mc_fc_context_t *fctx = &cpt_ctx->mc_ctx.fctx;
 240         int ret;
 241
 242         ret = cpt_fc_ciph_set_type(type, cpt_ctx, key_len);
 243         if (unlikely(ret))
 244                 return -1;
 245
 246         if (cpt_ctx->fc_type == FC_GEN) {
 247                 /*
 248                  * We need to always say IV is from DPTR as user can
 249                  * sometimes iverride IV per operation.
 250                  */
 251                 fctx->enc.iv_source = CPT_FROM_DPTR;
 252
 253                 if (cpt_ctx->auth_key_len > 64)
 254                         return -1;
 255         }
 256
 257         switch (type) {
 258         case PASSTHROUGH:
 259                 cpt_fc_ciph_set_key_passthrough(cpt_ctx, fctx);
 260                 goto success;
 261         case DES3_CBC:
 262                 /* CPT performs DES using 3DES with the 8B DES-key
 263                  * replicated 2 more times to match the 24B 3DES-key.
 264                  * Eg. If org. key is "0x0a 0x0b", then new key is
 265                  * "0x0a 0x0b 0x0a 0x0b 0x0a 0x0b"
 266                  */
 267                 if (key_len == 8) {
 268                         /* Skipping the first 8B as it will be copied
 269                          * in the regular code flow
 270                          */
 271                         memcpy(fctx->enc.encr_key+key_len, key, key_len);
 272                         memcpy(fctx->enc.encr_key+2*key_len, key, key_len);
 273                 }
 274                 break;
 275         case DES3_ECB:
 276                 /* For DES3_ECB IV need to be from CTX. */
 277                 fctx->enc.iv_source = CPT_FROM_CTX;
 278                 break;
 279         case AES_CBC:
 280         case AES_ECB:
 281         case AES_CFB:
 282         case AES_CTR:
 283         case CHACHA20:
 284                 cpt_fc_ciph_set_key_set_aes_key_type(fctx, key_len);
 285                 break;
 286         case AES_GCM:
 287                 /* Even though iv source is from dptr,
 288                  * aes_gcm salt is taken from ctx
 289                  */
 290                 if (salt) {
 291                         memcpy(fctx->enc.encr_iv, salt, 4);
 292                         /* Assuming it was just salt update
 293                          * and nothing else
 294                          */
 295                         if (!key)
 296                                 goto success;
 297                 }
 298                 cpt_fc_ciph_set_key_set_aes_key_type(fctx, key_len);
 299                 break;
 300         case AES_XTS:
 301                 key_len = key_len / 2;
 302                 cpt_fc_ciph_set_key_set_aes_key_type(fctx, key_len);
 303
 304                 /* Copy key2 for XTS into ipad */
 305                 memset(fctx->hmac.ipad, 0, sizeof(fctx->hmac.ipad));
 306                 memcpy(fctx->hmac.ipad, &key[key_len], key_len);
 307                 break;
 308         case SNOW3G_UEA2:
 309                 cpt_fc_ciph_set_key_snow3g_uea2(cpt_ctx, key, key_len);
 310                 goto success;
 311         case ZUC_EEA3:
 312                 cpt_fc_ciph_set_key_zuc_eea3(cpt_ctx, key, key_len);
 313                 goto success;
 314         case KASUMI_F8_ECB:
 315                 cpt_fc_ciph_set_key_kasumi_f8_ecb(cpt_ctx, key, key_len);
 316                 goto success;
 317         case KASUMI_F8_CBC:
 318                 cpt_fc_ciph_set_key_kasumi_f8_cbc(cpt_ctx, key, key_len);
 319                 goto success;
 320         default:
 321                 return -1;
 322         }
 323
 324         /* Only for FC_GEN case */
 325
 326         /* For GMAC auth, cipher must be NULL */
 327         if (cpt_ctx->hash_type != GMAC_TYPE)
 328                 fctx->enc.enc_cipher = type;
 329
 330         memcpy(fctx->enc.encr_key, key, key_len);
 331
 332 success:
 333         cpt_ctx->enc_cipher = type;
 334
 335         return 0;
 336 }
 337
 338 static __rte_always_inline uint32_t
 339 fill_sg_comp(sg_comp_t *list,
 340              uint32_t i,
 341              phys_addr_t dma_addr,
 342              uint32_t size)
 343 {
 344         sg_comp_t *to = &list[i>>2];
 345
 346         to->u.s.len[i%4] = rte_cpu_to_be_16(size);
 347         to->ptr[i%4] = rte_cpu_to_be_64(dma_addr);
 348         i++;
 349         return i;
 350 }
 351
 352 static __rte_always_inline uint32_t
 353 fill_sg_comp_from_buf(sg_comp_t *list,
 354                       uint32_t i,
 355                       buf_ptr_t *from)
 356 {
 357         sg_comp_t *to = &list[i>>2];
 358
 359         to->u.s.len[i%4] = rte_cpu_to_be_16(from->size);
 360         to->ptr[i%4] = rte_cpu_to_be_64(from->dma_addr);
 361         i++;
 362         return i;
 363 }
 364
 365 static __rte_always_inline uint32_t
 366 fill_sg_comp_from_buf_min(sg_comp_t *list,
 367                           uint32_t i,
 368                           buf_ptr_t *from,
 369                           uint32_t *psize)
 370 {
 371         sg_comp_t *to = &list[i >> 2];
 372         uint32_t size = *psize;
 373         uint32_t e_len;
 374
 375         e_len = (size > from->size) ? from->size : size;
 376         to->u.s.len[i % 4] = rte_cpu_to_be_16(e_len);
 377         to->ptr[i % 4] = rte_cpu_to_be_64(from->dma_addr);
 378         *psize -= e_len;
 379         i++;
 380         return i;
 381 }
 382
 383 /*
 384  * This fills the MC expected SGIO list
 385  * from IOV given by user.
 386  */
 387 static __rte_always_inline uint32_t
 388 fill_sg_comp_from_iov(sg_comp_t *list,
 389                       uint32_t i,
 390                       iov_ptr_t *from, uint32_t from_offset,
 391                       uint32_t *psize, buf_ptr_t *extra_buf,
 392                       uint32_t extra_offset)
 393 {
 394         int32_t j;
 395         uint32_t extra_len = extra_buf ? extra_buf->size : 0;
 396         uint32_t size = *psize;
 397         buf_ptr_t *bufs;
 398
 399         bufs = from->bufs;
 400         for (j = 0; (j < from->buf_cnt) && size; j++) {
 401                 phys_addr_t e_dma_addr;
 402                 uint32_t e_len;
 403                 sg_comp_t *to = &list[i >> 2];
 404
 405                 if (unlikely(from_offset)) {
 406                         if (from_offset >= bufs[j].size) {
 407                                 from_offset -= bufs[j].size;
 408                                 continue;
 409                         }
 410                         e_dma_addr = bufs[j].dma_addr + from_offset;
 411                         e_len = (size > (bufs[j].size - from_offset)) ?
 412                                 (bufs[j].size - from_offset) : size;
 413                         from_offset = 0;
 414                 } else {
 415                         e_dma_addr = bufs[j].dma_addr;
 416                         e_len = (size > bufs[j].size) ?
 417                                 bufs[j].size : size;
 418                 }
 419
 420                 to->u.s.len[i % 4] = rte_cpu_to_be_16(e_len);
 421                 to->ptr[i % 4] = rte_cpu_to_be_64(e_dma_addr);
 422
 423                 if (extra_len && (e_len >= extra_offset)) {
 424                         /* Break the data at given offset */
 425                         uint32_t next_len = e_len - extra_offset;
 426                         phys_addr_t next_dma = e_dma_addr + extra_offset;
 427
 428                         if (!extra_offset) {
 429                                 i--;
 430                         } else {
 431                                 e_len = extra_offset;
 432                                 size -= e_len;
 433                                 to->u.s.len[i % 4] = rte_cpu_to_be_16(e_len);
 434                         }
 435
 436                         extra_len = RTE_MIN(extra_len, size);
 437                         /* Insert extra data ptr */
 438                         if (extra_len) {
 439                                 i++;
 440                                 to = &list[i >> 2];
 441                                 to->u.s.len[i % 4] =
 442                                         rte_cpu_to_be_16(extra_len);
 443                                 to->ptr[i % 4] =
 444                                         rte_cpu_to_be_64(extra_buf->dma_addr);
 445                                 size -= extra_len;
 446                         }
 447
 448                         next_len = RTE_MIN(next_len, size);
 449                         /* insert the rest of the data */
 450                         if (next_len) {
 451                                 i++;
 452                                 to = &list[i >> 2];
 453                                 to->u.s.len[i % 4] = rte_cpu_to_be_16(next_len);
 454                                 to->ptr[i % 4] = rte_cpu_to_be_64(next_dma);
 455                                 size -= next_len;
 456                         }
 457                         extra_len = 0;
 458
 459                 } else {
 460                         size -= e_len;
 461                 }
 462                 if (extra_offset)
 463                         extra_offset -= size;
 464                 i++;
 465         }
 466
 467         *psize = size;
 468         return (uint32_t)i;
 469 }
 470
 471 static __rte_always_inline void
 472 cpt_digest_gen_prep(uint32_t flags,
 473                     uint64_t d_lens,
 474                     digest_params_t *params,
 475                     void *op,
 476                     void **prep_req)
 477 {
 478         struct cpt_request_info *req;
 479         uint32_t size, i;
 480         uint16_t data_len, mac_len, key_len;
 481         auth_type_t hash_type;
 482         buf_ptr_t *meta_p;
 483         struct cpt_ctx *ctx;
 484         sg_comp_t *gather_comp;
 485         sg_comp_t *scatter_comp;
 486         uint8_t *in_buffer;
 487         uint32_t g_size_bytes, s_size_bytes;
 488         uint64_t dptr_dma, rptr_dma;
 489         vq_cmd_word0_t vq_cmd_w0;
 490         void *c_vaddr, *m_vaddr;
 491         uint64_t c_dma, m_dma;
 492         opcode_info_t opcode;
 493
 494         ctx = params->ctx_buf.vaddr;
 495         meta_p = &params->meta_buf;
 496
 497         m_vaddr = meta_p->vaddr;
 498         m_dma = meta_p->dma_addr;
 499
 500         /*
 501          * Save initial space that followed app data for completion code &
 502          * alternate completion code to fall in same cache line as app data
 503          */
 504         m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
 505         m_dma += COMPLETION_CODE_SIZE;
 506         size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
 507                 (uint8_t *)m_vaddr;
 508         c_vaddr = (uint8_t *)m_vaddr + size;
 509         c_dma = m_dma + size;
 510         size += sizeof(cpt_res_s_t);
 511
 512         m_vaddr = (uint8_t *)m_vaddr + size;
 513         m_dma += size;
 514
 515         req = m_vaddr;
 516
 517         size = sizeof(struct cpt_request_info);
 518         m_vaddr = (uint8_t *)m_vaddr + size;
 519         m_dma += size;
 520
 521         hash_type = ctx->hash_type;
 522         mac_len = ctx->mac_len;
 523         key_len = ctx->auth_key_len;
 524         data_len = AUTH_DLEN(d_lens);
 525
 526         /*GP op header */
 527         vq_cmd_w0.u64 = 0;
 528         vq_cmd_w0.s.param2 = ((uint16_t)hash_type << 8);
 529         if (ctx->hmac) {
 530                 opcode.s.major = CPT_MAJOR_OP_HMAC | CPT_DMA_MODE;
 531                 vq_cmd_w0.s.param1 = key_len;
 532                 vq_cmd_w0.s.dlen = data_len + ROUNDUP8(key_len);
 533         } else {
 534                 opcode.s.major = CPT_MAJOR_OP_HASH | CPT_DMA_MODE;
 535                 vq_cmd_w0.s.param1 = 0;
 536                 vq_cmd_w0.s.dlen = data_len;
 537         }
 538
 539         opcode.s.minor = 0;
 540
 541         /* Null auth only case enters the if */
 542         if (unlikely(!hash_type && !ctx->enc_cipher)) {
 543                 opcode.s.major = CPT_MAJOR_OP_MISC;
 544                 /* Minor op is passthrough */
 545                 opcode.s.minor = 0x03;
 546                 /* Send out completion code only */
 547                 vq_cmd_w0.s.param2 = 0x1;
 548         }
 549
 550         vq_cmd_w0.s.opcode = opcode.flags;
 551
 552         /* DPTR has SG list */
 553         in_buffer = m_vaddr;
 554         dptr_dma = m_dma;
 555
 556         ((uint16_t *)in_buffer)[0] = 0;
 557         ((uint16_t *)in_buffer)[1] = 0;
 558
 559         /* TODO Add error check if space will be sufficient */
 560         gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
 561
 562         /*
 563          * Input gather list
 564          */
 565
 566         i = 0;
 567
 568         if (ctx->hmac) {
 569                 uint64_t k_dma = params->ctx_buf.dma_addr +
 570                         offsetof(struct cpt_ctx, auth_key);
 571                 /* Key */
 572                 i = fill_sg_comp(gather_comp, i, k_dma, ROUNDUP8(key_len));
 573         }
 574
 575         /* input data */
 576         size = data_len;
 577         if (size) {
 578                 i = fill_sg_comp_from_iov(gather_comp, i, params->src_iov,
 579                                           0, &size, NULL, 0);
 580                 if (unlikely(size)) {
 581                         CPT_LOG_DP_DEBUG("Insufficient dst IOV size, short"
 582                                          " by %dB", size);
 583                         return;
 584                 }
 585         } else {
 586                 /*
 587                  * Looks like we need to support zero data
 588                  * gather ptr in case of hash & hmac
 589                  */
 590                 i++;
 591         }
 592         ((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
 593         g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
 594
 595         /*
 596          * Output Gather list
 597          */
 598
 599         i = 0;
 600         scatter_comp = (sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
 601
 602         if (flags & VALID_MAC_BUF) {
 603                 if (unlikely(params->mac_buf.size < mac_len)) {
 604                         CPT_LOG_DP_ERR("Insufficient MAC size");
 605                         return;
 606                 }
 607
 608                 size = mac_len;
 609                 i = fill_sg_comp_from_buf_min(scatter_comp, i,
 610                                               &params->mac_buf, &size);
 611         } else {
 612                 size = mac_len;
 613                 i = fill_sg_comp_from_iov(scatter_comp, i,
 614                                           params->src_iov, data_len,
 615                                           &size, NULL, 0);
 616                 if (unlikely(size)) {
 617                         CPT_LOG_DP_ERR("Insufficient dst IOV size, short by"
 618                                        " %dB", size);
 619                         return;
 620                 }
 621         }
 622
 623         ((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
 624         s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
 625
 626         size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
 627
 628         /* This is DPTR len incase of SG mode */
 629         vq_cmd_w0.s.dlen = size;
 630
 631         m_vaddr = (uint8_t *)m_vaddr + size;
 632         m_dma += size;
 633
 634         /* cpt alternate completion address saved earlier */
 635         req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
 636         *req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
 637         rptr_dma = c_dma - 8;
 638
 639         req->ist.ei1 = dptr_dma;
 640         req->ist.ei2 = rptr_dma;
 641
 642         /* 16 byte aligned cpt res address */
 643         req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
 644         *req->completion_addr = COMPLETION_CODE_INIT;
 645         req->comp_baddr  = c_dma;
 646
 647         /* Fill microcode part of instruction */
 648         req->ist.ei0 = vq_cmd_w0.u64;
 649
 650         req->op = op;
 651
 652         *prep_req = req;
 653         return;
 654 }
 655
 656 static __rte_always_inline void
 657 cpt_enc_hmac_prep(uint32_t flags,
 658                   uint64_t d_offs,
 659                   uint64_t d_lens,
 660                   fc_params_t *fc_params,
 661                   void *op,
 662                   void **prep_req)
 663 {
 664         uint32_t iv_offset = 0;
 665         int32_t inputlen, outputlen, enc_dlen, auth_dlen;
 666         struct cpt_ctx *cpt_ctx;
 667         uint32_t cipher_type, hash_type;
 668         uint32_t mac_len, size;
 669         uint8_t iv_len = 16;
 670         struct cpt_request_info *req;
 671         buf_ptr_t *meta_p, *aad_buf = NULL;
 672         uint32_t encr_offset, auth_offset;
 673         uint32_t encr_data_len, auth_data_len, aad_len = 0;
 674         uint32_t passthrough_len = 0;
 675         void *m_vaddr, *offset_vaddr;
 676         uint64_t m_dma, offset_dma;
 677         vq_cmd_word0_t vq_cmd_w0;
 678         void *c_vaddr;
 679         uint64_t c_dma;
 680         opcode_info_t opcode;
 681
 682         meta_p = &fc_params->meta_buf;
 683         m_vaddr = meta_p->vaddr;
 684         m_dma = meta_p->dma_addr;
 685
 686         encr_offset = ENCR_OFFSET(d_offs);
 687         auth_offset = AUTH_OFFSET(d_offs);
 688         encr_data_len = ENCR_DLEN(d_lens);
 689         auth_data_len = AUTH_DLEN(d_lens);
 690         if (unlikely(flags & VALID_AAD_BUF)) {
 691                 /*
 692                  * We dont support both aad
 693                  * and auth data separately
 694                  */
 695                 auth_data_len = 0;
 696                 auth_offset = 0;
 697                 aad_len = fc_params->aad_buf.size;
 698                 aad_buf = &fc_params->aad_buf;
 699         }
 700         cpt_ctx = fc_params->ctx_buf.vaddr;
 701         cipher_type = cpt_ctx->enc_cipher;
 702         hash_type = cpt_ctx->hash_type;
 703         mac_len = cpt_ctx->mac_len;
 704
 705         /*
 706          * Save initial space that followed app data for completion code &
 707          * alternate completion code to fall in same cache line as app data
 708          */
 709         m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
 710         m_dma += COMPLETION_CODE_SIZE;
 711         size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
 712                 (uint8_t *)m_vaddr;
 713
 714         c_vaddr = (uint8_t *)m_vaddr + size;
 715         c_dma = m_dma + size;
 716         size += sizeof(cpt_res_s_t);
 717
 718         m_vaddr = (uint8_t *)m_vaddr + size;
 719         m_dma += size;
 720
 721         /* start cpt request info struct at 8 byte boundary */
 722         size = (uint8_t *)RTE_PTR_ALIGN(m_vaddr, 8) -
 723                 (uint8_t *)m_vaddr;
 724
 725         req = (struct cpt_request_info *)((uint8_t *)m_vaddr + size);
 726
 727         size += sizeof(struct cpt_request_info);
 728         m_vaddr = (uint8_t *)m_vaddr + size;
 729         m_dma += size;
 730
 731         if (unlikely(!(flags & VALID_IV_BUF))) {
 732                 iv_len = 0;
 733                 iv_offset = ENCR_IV_OFFSET(d_offs);
 734         }
 735
 736         if (unlikely(flags & VALID_AAD_BUF)) {
 737                 /*
 738                  * When AAD is given, data above encr_offset is pass through
 739                  * Since AAD is given as separate pointer and not as offset,
 740                  * this is a special case as we need to fragment input data
 741                  * into passthrough + encr_data and then insert AAD in between.
 742                  */
 743                 if (hash_type != GMAC_TYPE) {
 744                         passthrough_len = encr_offset;
 745                         auth_offset = passthrough_len + iv_len;
 746                         encr_offset = passthrough_len + aad_len + iv_len;
 747                         auth_data_len = aad_len + encr_data_len;
 748                 } else {
 749                         passthrough_len = 16 + aad_len;
 750                         auth_offset = passthrough_len + iv_len;
 751                         auth_data_len = aad_len;
 752                 }
 753         } else {
 754                 encr_offset += iv_len;
 755                 auth_offset += iv_len;
 756         }
 757
 758         /* Encryption */
 759         opcode.s.major = CPT_MAJOR_OP_FC;
 760         opcode.s.minor = 0;
 761
 762         if (hash_type == GMAC_TYPE) {
 763                 encr_offset = 0;
 764                 encr_data_len = 0;
 765         }
 766
 767         auth_dlen = auth_offset + auth_data_len;
 768         enc_dlen = encr_data_len + encr_offset;
 769         if (unlikely(encr_data_len & 0xf)) {
 770                 if ((cipher_type == DES3_CBC) || (cipher_type == DES3_ECB))
 771                         enc_dlen = ROUNDUP8(encr_data_len) + encr_offset;
 772                 else if (likely((cipher_type == AES_CBC) ||
 773                                 (cipher_type == AES_ECB)))
 774                         enc_dlen = ROUNDUP16(encr_data_len) + encr_offset;
 775         }
 776
 777         if (unlikely(auth_dlen > enc_dlen)) {
 778                 inputlen = auth_dlen;
 779                 outputlen = auth_dlen + mac_len;
 780         } else {
 781                 inputlen = enc_dlen;
 782                 outputlen = enc_dlen + mac_len;
 783         }
 784
 785         /* GP op header */
 786         vq_cmd_w0.u64 = 0;
 787         vq_cmd_w0.s.param1 = encr_data_len;
 788         vq_cmd_w0.s.param2 = auth_data_len;
 789         /*
 790          * In 83XX since we have a limitation of
 791          * IV & Offset control word not part of instruction
 792          * and need to be part of Data Buffer, we check if
 793          * head room is there and then only do the Direct mode processing
 794          */
 795         if (likely((flags & SINGLE_BUF_INPLACE) &&
 796                    (flags & SINGLE_BUF_HEADTAILROOM))) {
 797                 void *dm_vaddr = fc_params->bufs[0].vaddr;
 798                 uint64_t dm_dma_addr = fc_params->bufs[0].dma_addr;
 799                 /*
 800                  * This flag indicates that there is 24 bytes head room and
 801                  * 8 bytes tail room available, so that we get to do
 802                  * DIRECT MODE with limitation
 803                  */
 804
 805                 offset_vaddr = (uint8_t *)dm_vaddr - OFF_CTRL_LEN - iv_len;
 806                 offset_dma = dm_dma_addr - OFF_CTRL_LEN - iv_len;
 807
 808                 /* DPTR */
 809                 req->ist.ei1 = offset_dma;
 810                 /* RPTR should just exclude offset control word */
 811                 req->ist.ei2 = dm_dma_addr - iv_len;
 812                 req->alternate_caddr = (uint64_t *)((uint8_t *)dm_vaddr
 813                                                     + outputlen - iv_len);
 814
 815                 vq_cmd_w0.s.dlen = inputlen + OFF_CTRL_LEN;
 816
 817                 vq_cmd_w0.s.opcode = opcode.flags;
 818
 819                 if (likely(iv_len)) {
 820                         uint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr
 821                                                       + OFF_CTRL_LEN);
 822                         uint64_t *src = fc_params->iv_buf;
 823                         dest[0] = src[0];
 824                         dest[1] = src[1];
 825                 }
 826
 827                 *(uint64_t *)offset_vaddr =
 828                         rte_cpu_to_be_64(((uint64_t)encr_offset << 16) |
 829                                 ((uint64_t)iv_offset << 8) |
 830                                 ((uint64_t)auth_offset));
 831
 832         } else {
 833                 uint32_t i, g_size_bytes, s_size_bytes;
 834                 uint64_t dptr_dma, rptr_dma;
 835                 sg_comp_t *gather_comp;
 836                 sg_comp_t *scatter_comp;
 837                 uint8_t *in_buffer;
 838
 839                 /* This falls under strict SG mode */
 840                 offset_vaddr = m_vaddr;
 841                 offset_dma = m_dma;
 842                 size = OFF_CTRL_LEN + iv_len;
 843
 844                 m_vaddr = (uint8_t *)m_vaddr + size;
 845                 m_dma += size;
 846
 847                 opcode.s.major |= CPT_DMA_MODE;
 848
 849                 vq_cmd_w0.s.opcode = opcode.flags;
 850
 851                 if (likely(iv_len)) {
 852                         uint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr
 853                                                       + OFF_CTRL_LEN);
 854                         uint64_t *src = fc_params->iv_buf;
 855                         dest[0] = src[0];
 856                         dest[1] = src[1];
 857                 }
 858
 859                 *(uint64_t *)offset_vaddr =
 860                         rte_cpu_to_be_64(((uint64_t)encr_offset << 16) |
 861                                 ((uint64_t)iv_offset << 8) |
 862                                 ((uint64_t)auth_offset));
 863
 864                 /* DPTR has SG list */
 865                 in_buffer = m_vaddr;
 866                 dptr_dma = m_dma;
 867
 868                 ((uint16_t *)in_buffer)[0] = 0;
 869                 ((uint16_t *)in_buffer)[1] = 0;
 870
 871                 /* TODO Add error check if space will be sufficient */
 872                 gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
 873
 874                 /*
 875                  * Input Gather List
 876                  */
 877
 878                 i = 0;
 879
 880                 /* Offset control word that includes iv */
 881                 i = fill_sg_comp(gather_comp, i, offset_dma,
 882                                  OFF_CTRL_LEN + iv_len);
 883
 884                 /* Add input data */
 885                 size = inputlen - iv_len;
 886                 if (likely(size)) {
 887                         uint32_t aad_offset = aad_len ? passthrough_len : 0;
 888
 889                         if (unlikely(flags & SINGLE_BUF_INPLACE)) {
 890                                 i = fill_sg_comp_from_buf_min(gather_comp, i,
 891                                                               fc_params->bufs,
 892                                                               &size);
 893                         } else {
 894                                 i = fill_sg_comp_from_iov(gather_comp, i,
 895                                                           fc_params->src_iov,
 896                                                           0, &size,
 897                                                           aad_buf, aad_offset);
 898                         }
 899
 900                         if (unlikely(size)) {
 901                                 CPT_LOG_DP_ERR("Insufficient buffer space,"
 902                                                " size %d needed", size);
 903                                 return;
 904                         }
 905                 }
 906                 ((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
 907                 g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
 908
 909                 /*
 910                  * Output Scatter list
 911                  */
 912                 i = 0;
 913                 scatter_comp =
 914                         (sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
 915
 916                 /* Add IV */
 917                 if (likely(iv_len)) {
 918                         i = fill_sg_comp(scatter_comp, i,
 919                                          offset_dma + OFF_CTRL_LEN,
 920                                          iv_len);
 921                 }
 922
 923                 /* output data or output data + digest*/
 924                 if (unlikely(flags & VALID_MAC_BUF)) {
 925                         size = outputlen - iv_len - mac_len;
 926                         if (size) {
 927                                 uint32_t aad_offset =
 928                                         aad_len ? passthrough_len : 0;
 929
 930                                 if (unlikely(flags & SINGLE_BUF_INPLACE)) {
 931                                         i = fill_sg_comp_from_buf_min(
 932                                                         scatter_comp,
 933                                                         i,
 934                                                         fc_params->bufs,
 935                                                         &size);
 936                                 } else {
 937                                         i = fill_sg_comp_from_iov(scatter_comp,
 938                                                         i,
 939                                                         fc_params->dst_iov,
 940                                                         0,
 941                                                         &size,
 942                                                         aad_buf,
 943                                                         aad_offset);
 944                                 }
 945                                 if (unlikely(size)) {
 946                                         CPT_LOG_DP_ERR("Insufficient buffer"
 947                                                        " space, size %d needed",
 948                                                        size);
 949                                         return;
 950                                 }
 951                         }
 952                         /* mac_data */
 953                         if (mac_len) {
 954                                 i = fill_sg_comp_from_buf(scatter_comp, i,
 955                                                           &fc_params->mac_buf);
 956                         }
 957                 } else {
 958                         /* Output including mac */
 959                         size = outputlen - iv_len;
 960                         if (likely(size)) {
 961                                 uint32_t aad_offset =
 962                                         aad_len ? passthrough_len : 0;
 963
 964                                 if (unlikely(flags & SINGLE_BUF_INPLACE)) {
 965                                         i = fill_sg_comp_from_buf_min(
 966                                                         scatter_comp,
 967                                                         i,
 968                                                         fc_params->bufs,
 969                                                         &size);
 970                                 } else {
 971                                         i = fill_sg_comp_from_iov(scatter_comp,
 972                                                         i,
 973                                                         fc_params->dst_iov,
 974                                                         0,
 975                                                         &size,
 976                                                         aad_buf,
 977                                                         aad_offset);
 978                                 }
 979                                 if (unlikely(size)) {
 980                                         CPT_LOG_DP_ERR("Insufficient buffer"
 981                                                        " space, size %d needed",
 982                                                        size);
 983                                         return;
 984                                 }
 985                         }
 986                 }
 987                 ((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
 988                 s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
 989
 990                 size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
 991
 992                 /* This is DPTR len incase of SG mode */
 993                 vq_cmd_w0.s.dlen = size;
 994
 995                 m_vaddr = (uint8_t *)m_vaddr + size;
 996                 m_dma += size;
 997
 998                 /* cpt alternate completion address saved earlier */
 999                 req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
1000                 *req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
1001                 rptr_dma = c_dma - 8;
1002
1003                 req->ist.ei1 = dptr_dma;
1004                 req->ist.ei2 = rptr_dma;
1005         }
1006
1007         /* 16 byte aligned cpt res address */
1008         req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
1009         *req->completion_addr = COMPLETION_CODE_INIT;
1010         req->comp_baddr  = c_dma;
1011
1012         /* Fill microcode part of instruction */
1013         req->ist.ei0 = vq_cmd_w0.u64;
1014
1015         req->op  = op;
1016
1017         *prep_req = req;
1018         return;
1019 }
1020
1021 static __rte_always_inline void
1022 cpt_dec_hmac_prep(uint32_t flags,
1023                   uint64_t d_offs,
1024                   uint64_t d_lens,
1025                   fc_params_t *fc_params,
1026                   void *op,
1027                   void **prep_req)
1028 {
1029         uint32_t iv_offset = 0, size;
1030         int32_t inputlen, outputlen, enc_dlen, auth_dlen;
1031         struct cpt_ctx *cpt_ctx;
1032         int32_t hash_type, mac_len;
1033         uint8_t iv_len = 16;
1034         struct cpt_request_info *req;
1035         buf_ptr_t *meta_p, *aad_buf = NULL;
1036         uint32_t encr_offset, auth_offset;
1037         uint32_t encr_data_len, auth_data_len, aad_len = 0;
1038         uint32_t passthrough_len = 0;
1039         void *m_vaddr, *offset_vaddr;
1040         uint64_t m_dma, offset_dma;
1041         opcode_info_t opcode;
1042         vq_cmd_word0_t vq_cmd_w0;
1043         void *c_vaddr;
1044         uint64_t c_dma;
1045
1046         meta_p = &fc_params->meta_buf;
1047         m_vaddr = meta_p->vaddr;
1048         m_dma = meta_p->dma_addr;
1049
1050         encr_offset = ENCR_OFFSET(d_offs);
1051         auth_offset = AUTH_OFFSET(d_offs);
1052         encr_data_len = ENCR_DLEN(d_lens);
1053         auth_data_len = AUTH_DLEN(d_lens);
1054
1055         if (unlikely(flags & VALID_AAD_BUF)) {
1056                 /*
1057                  * We dont support both aad
1058                  * and auth data separately
1059                  */
1060                 auth_data_len = 0;
1061                 auth_offset = 0;
1062                 aad_len = fc_params->aad_buf.size;
1063                 aad_buf = &fc_params->aad_buf;
1064         }
1065
1066         cpt_ctx = fc_params->ctx_buf.vaddr;
1067         hash_type = cpt_ctx->hash_type;
1068         mac_len = cpt_ctx->mac_len;
1069
1070         if (unlikely(!(flags & VALID_IV_BUF))) {
1071                 iv_len = 0;
1072                 iv_offset = ENCR_IV_OFFSET(d_offs);
1073         }
1074
1075         if (unlikely(flags & VALID_AAD_BUF)) {
1076                 /*
1077                  * When AAD is given, data above encr_offset is pass through
1078                  * Since AAD is given as separate pointer and not as offset,
1079                  * this is a special case as we need to fragment input data
1080                  * into passthrough + encr_data and then insert AAD in between.
1081                  */
1082                 if (hash_type != GMAC_TYPE) {
1083                         passthrough_len = encr_offset;
1084                         auth_offset = passthrough_len + iv_len;
1085                         encr_offset = passthrough_len + aad_len + iv_len;
1086                         auth_data_len = aad_len + encr_data_len;
1087                 } else {
1088                         passthrough_len = 16 + aad_len;
1089                         auth_offset = passthrough_len + iv_len;
1090                         auth_data_len = aad_len;
1091                 }
1092         } else {
1093                 encr_offset += iv_len;
1094                 auth_offset += iv_len;
1095         }
1096
1097         /*
1098          * Save initial space that followed app data for completion code &
1099          * alternate completion code to fall in same cache line as app data
1100          */
1101         m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
1102         m_dma += COMPLETION_CODE_SIZE;
1103         size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
1104                (uint8_t *)m_vaddr;
1105         c_vaddr = (uint8_t *)m_vaddr + size;
1106         c_dma = m_dma + size;
1107         size += sizeof(cpt_res_s_t);
1108
1109         m_vaddr = (uint8_t *)m_vaddr + size;
1110         m_dma += size;
1111
1112         /* start cpt request info structure at 8 byte alignment */
1113         size = (uint8_t *)RTE_PTR_ALIGN(m_vaddr, 8) -
1114                 (uint8_t *)m_vaddr;
1115
1116         req = (struct cpt_request_info *)((uint8_t *)m_vaddr + size);
1117
1118         size += sizeof(struct cpt_request_info);
1119         m_vaddr = (uint8_t *)m_vaddr + size;
1120         m_dma += size;
1121
1122         /* Decryption */
1123         opcode.s.major = CPT_MAJOR_OP_FC;
1124         opcode.s.minor = 1;
1125
1126         if (hash_type == GMAC_TYPE) {
1127                 encr_offset = 0;
1128                 encr_data_len = 0;
1129         }
1130
1131         enc_dlen = encr_offset + encr_data_len;
1132         auth_dlen = auth_offset + auth_data_len;
1133
1134         if (auth_dlen > enc_dlen) {
1135                 inputlen = auth_dlen + mac_len;
1136                 outputlen = auth_dlen;
1137         } else {
1138                 inputlen = enc_dlen + mac_len;
1139                 outputlen = enc_dlen;
1140         }
1141
1142         vq_cmd_w0.u64 = 0;
1143         vq_cmd_w0.s.param1 = encr_data_len;
1144         vq_cmd_w0.s.param2 = auth_data_len;
1145
1146         /*
1147          * In 83XX since we have a limitation of
1148          * IV & Offset control word not part of instruction
1149          * and need to be part of Data Buffer, we check if
1150          * head room is there and then only do the Direct mode processing
1151          */
1152         if (likely((flags & SINGLE_BUF_INPLACE) &&
1153                    (flags & SINGLE_BUF_HEADTAILROOM))) {
1154                 void *dm_vaddr = fc_params->bufs[0].vaddr;
1155                 uint64_t dm_dma_addr = fc_params->bufs[0].dma_addr;
1156                 /*
1157                  * This flag indicates that there is 24 bytes head room and
1158                  * 8 bytes tail room available, so that we get to do
1159                  * DIRECT MODE with limitation
1160                  */
1161
1162                 offset_vaddr = (uint8_t *)dm_vaddr - OFF_CTRL_LEN - iv_len;
1163                 offset_dma = dm_dma_addr - OFF_CTRL_LEN - iv_len;
1164                 req->ist.ei1 = offset_dma;
1165
1166                 /* RPTR should just exclude offset control word */
1167                 req->ist.ei2 = dm_dma_addr - iv_len;
1168
1169                 req->alternate_caddr = (uint64_t *)((uint8_t *)dm_vaddr +
1170                                         outputlen - iv_len);
1171                 /* since this is decryption,
1172                  * don't touch the content of
1173                  * alternate ccode space as it contains
1174                  * hmac.
1175                  */
1176
1177                 vq_cmd_w0.s.dlen = inputlen + OFF_CTRL_LEN;
1178
1179                 vq_cmd_w0.s.opcode = opcode.flags;
1180
1181                 if (likely(iv_len)) {
1182                         uint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr +
1183                                                       OFF_CTRL_LEN);
1184                         uint64_t *src = fc_params->iv_buf;
1185                         dest[0] = src[0];
1186                         dest[1] = src[1];
1187                 }
1188
1189                 *(uint64_t *)offset_vaddr =
1190                         rte_cpu_to_be_64(((uint64_t)encr_offset << 16) |
1191                                 ((uint64_t)iv_offset << 8) |
1192                                 ((uint64_t)auth_offset));
1193
1194         } else {
1195                 uint64_t dptr_dma, rptr_dma;
1196                 uint32_t g_size_bytes, s_size_bytes;
1197                 sg_comp_t *gather_comp;
1198                 sg_comp_t *scatter_comp;
1199                 uint8_t *in_buffer;
1200                 uint8_t i = 0;
1201
1202                 /* This falls under strict SG mode */
1203                 offset_vaddr = m_vaddr;
1204                 offset_dma = m_dma;
1205                 size = OFF_CTRL_LEN + iv_len;
1206
1207                 m_vaddr = (uint8_t *)m_vaddr + size;
1208                 m_dma += size;
1209
1210                 opcode.s.major |= CPT_DMA_MODE;
1211
1212                 vq_cmd_w0.s.opcode = opcode.flags;
1213
1214                 if (likely(iv_len)) {
1215                         uint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr +
1216                                                       OFF_CTRL_LEN);
1217                         uint64_t *src = fc_params->iv_buf;
1218                         dest[0] = src[0];
1219                         dest[1] = src[1];
1220                 }
1221
1222                 *(uint64_t *)offset_vaddr =
1223                         rte_cpu_to_be_64(((uint64_t)encr_offset << 16) |
1224                                 ((uint64_t)iv_offset << 8) |
1225                                 ((uint64_t)auth_offset));
1226
1227                 /* DPTR has SG list */
1228                 in_buffer = m_vaddr;
1229                 dptr_dma = m_dma;
1230
1231                 ((uint16_t *)in_buffer)[0] = 0;
1232                 ((uint16_t *)in_buffer)[1] = 0;
1233
1234                 /* TODO Add error check if space will be sufficient */
1235                 gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
1236
1237                 /*
1238                  * Input Gather List
1239                  */
1240                 i = 0;
1241
1242                 /* Offset control word that includes iv */
1243                 i = fill_sg_comp(gather_comp, i, offset_dma,
1244                                  OFF_CTRL_LEN + iv_len);
1245
1246                 /* Add input data */
1247                 if (flags & VALID_MAC_BUF) {
1248                         size = inputlen - iv_len - mac_len;
1249                         if (size) {
1250                                 /* input data only */
1251                                 if (unlikely(flags & SINGLE_BUF_INPLACE)) {
1252                                         i = fill_sg_comp_from_buf_min(
1253                                                         gather_comp, i,
1254                                                         fc_params->bufs,
1255                                                         &size);
1256                                 } else {
1257                                         uint32_t aad_offset = aad_len ?
1258                                                 passthrough_len : 0;
1259
1260                                         i = fill_sg_comp_from_iov(gather_comp,
1261                                                         i,
1262                                                         fc_params->src_iov,
1263                                                         0, &size,
1264                                                         aad_buf,
1265                                                         aad_offset);
1266                                 }
1267                                 if (unlikely(size)) {
1268                                         CPT_LOG_DP_ERR("Insufficient buffer"
1269                                                        " space, size %d needed",
1270                                                        size);
1271                                         return;
1272                                 }
1273                         }
1274
1275                         /* mac data */
1276                         if (mac_len) {
1277                                 i = fill_sg_comp_from_buf(gather_comp, i,
1278                                                           &fc_params->mac_buf);
1279                         }
1280                 } else {
1281                         /* input data + mac */
1282                         size = inputlen - iv_len;
1283                         if (size) {
1284                                 if (unlikely(flags & SINGLE_BUF_INPLACE)) {
1285                                         i = fill_sg_comp_from_buf_min(
1286                                                         gather_comp, i,
1287                                                         fc_params->bufs,
1288                                                         &size);
1289                                 } else {
1290                                         uint32_t aad_offset = aad_len ?
1291                                                 passthrough_len : 0;
1292
1293                                         if (unlikely(!fc_params->src_iov)) {
1294                                                 CPT_LOG_DP_ERR("Bad input args");
1295                                                 return;
1296                                         }
1297
1298                                         i = fill_sg_comp_from_iov(
1299                                                         gather_comp, i,
1300                                                         fc_params->src_iov,
1301                                                         0, &size,
1302                                                         aad_buf,
1303                                                         aad_offset);
1304                                 }
1305
1306                                 if (unlikely(size)) {
1307                                         CPT_LOG_DP_ERR("Insufficient buffer"
1308                                                        " space, size %d needed",
1309                                                        size);
1310                                         return;
1311                                 }
1312                         }
1313                 }
1314                 ((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
1315                 g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
1316
1317                 /*
1318                  * Output Scatter List
1319                  */
1320
1321                 i = 0;
1322                 scatter_comp =
1323                         (sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
1324
1325                 /* Add iv */
1326                 if (iv_len) {
1327                         i = fill_sg_comp(scatter_comp, i,
1328                                          offset_dma + OFF_CTRL_LEN,
1329                                          iv_len);
1330                 }
1331
1332                 /* Add output data */
1333                 size = outputlen - iv_len;
1334                 if (size) {
1335                         if (unlikely(flags & SINGLE_BUF_INPLACE)) {
1336                                 /* handle single buffer here */
1337                                 i = fill_sg_comp_from_buf_min(scatter_comp, i,
1338                                                               fc_params->bufs,
1339                                                               &size);
1340                         } else {
1341                                 uint32_t aad_offset = aad_len ?
1342                                         passthrough_len : 0;
1343
1344                                 if (unlikely(!fc_params->dst_iov)) {
1345                                         CPT_LOG_DP_ERR("Bad input args");
1346                                         return;
1347                                 }
1348
1349                                 i = fill_sg_comp_from_iov(scatter_comp, i,
1350                                                           fc_params->dst_iov, 0,
1351                                                           &size, aad_buf,
1352                                                           aad_offset);
1353                         }
1354
1355                         if (unlikely(size)) {
1356                                 CPT_LOG_DP_ERR("Insufficient buffer space,"
1357                                                " size %d needed", size);
1358                                 return;
1359                         }
1360                 }
1361
1362                 ((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
1363                 s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
1364
1365                 size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
1366
1367                 /* This is DPTR len incase of SG mode */
1368                 vq_cmd_w0.s.dlen = size;
1369
1370                 m_vaddr = (uint8_t *)m_vaddr + size;
1371                 m_dma += size;
1372
1373                 /* cpt alternate completion address saved earlier */
1374                 req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
1375                 *req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
1376                 rptr_dma = c_dma - 8;
1377                 size += COMPLETION_CODE_SIZE;
1378
1379                 req->ist.ei1 = dptr_dma;
1380                 req->ist.ei2 = rptr_dma;
1381         }
1382
1383         /* 16 byte aligned cpt res address */
1384         req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
1385         *req->completion_addr = COMPLETION_CODE_INIT;
1386         req->comp_baddr  = c_dma;
1387
1388         /* Fill microcode part of instruction */
1389         req->ist.ei0 = vq_cmd_w0.u64;
1390
1391         req->op = op;
1392
1393         *prep_req = req;
1394         return;
1395 }
1396
1397 static __rte_always_inline void
1398 cpt_zuc_snow3g_enc_prep(uint32_t req_flags,
1399                         uint64_t d_offs,
1400                         uint64_t d_lens,
1401                         fc_params_t *params,
1402                         void *op,
1403                         void **prep_req)
1404 {
1405         uint32_t size;
1406         int32_t inputlen, outputlen;
1407         struct cpt_ctx *cpt_ctx;
1408         uint32_t mac_len = 0;
1409         uint8_t snow3g, j;
1410         struct cpt_request_info *req;
1411         buf_ptr_t *buf_p;
1412         uint32_t encr_offset = 0, auth_offset = 0;
1413         uint32_t encr_data_len = 0, auth_data_len = 0;
1414         int flags, iv_len = 16;
1415         void *m_vaddr, *c_vaddr;
1416         uint64_t m_dma, c_dma, offset_ctrl;
1417         uint64_t *offset_vaddr, offset_dma;
1418         uint32_t *iv_s, iv[4];
1419         vq_cmd_word0_t vq_cmd_w0;
1420         opcode_info_t opcode;
1421
1422         buf_p = &params->meta_buf;
1423         m_vaddr = buf_p->vaddr;
1424         m_dma = buf_p->dma_addr;
1425
1426         cpt_ctx = params->ctx_buf.vaddr;
1427         flags = cpt_ctx->zsk_flags;
1428         mac_len = cpt_ctx->mac_len;
1429         snow3g = cpt_ctx->snow3g;
1430
1431         /*
1432          * Save initial space that followed app data for completion code &
1433          * alternate completion code to fall in same cache line as app data
1434          */
1435         m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
1436         m_dma += COMPLETION_CODE_SIZE;
1437         size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
1438                 (uint8_t *)m_vaddr;
1439
1440         c_vaddr = (uint8_t *)m_vaddr + size;
1441         c_dma = m_dma + size;
1442         size += sizeof(cpt_res_s_t);
1443
1444         m_vaddr = (uint8_t *)m_vaddr + size;
1445         m_dma += size;
1446
1447         /* Reserve memory for cpt request info */
1448         req = m_vaddr;
1449
1450         size = sizeof(struct cpt_request_info);
1451         m_vaddr = (uint8_t *)m_vaddr + size;
1452         m_dma += size;
1453
1454         opcode.s.major = CPT_MAJOR_OP_ZUC_SNOW3G;
1455
1456         /* indicates CPTR ctx, operation type, KEY & IV mode from DPTR */
1457
1458         opcode.s.minor = ((1 << 7) | (snow3g << 5) | (0 << 4) |
1459                           (0 << 3) | (flags & 0x7));
1460
1461         if (flags == 0x1) {
1462                 /*
1463                  * Microcode expects offsets in bytes
1464                  * TODO: Rounding off
1465                  */
1466                 auth_data_len = AUTH_DLEN(d_lens);
1467
1468                 /* EIA3 or UIA2 */
1469                 auth_offset = AUTH_OFFSET(d_offs);
1470                 auth_offset = auth_offset / 8;
1471
1472                 /* consider iv len */
1473                 auth_offset += iv_len;
1474
1475                 inputlen = auth_offset + (RTE_ALIGN(auth_data_len, 8) / 8);
1476                 outputlen = mac_len;
1477
1478                 offset_ctrl = rte_cpu_to_be_64((uint64_t)auth_offset);
1479
1480         } else {
1481                 /* EEA3 or UEA2 */
1482                 /*
1483                  * Microcode expects offsets in bytes
1484                  * TODO: Rounding off
1485                  */
1486                 encr_data_len = ENCR_DLEN(d_lens);
1487
1488                 encr_offset = ENCR_OFFSET(d_offs);
1489                 encr_offset = encr_offset / 8;
1490                 /* consider iv len */
1491                 encr_offset += iv_len;
1492
1493                 inputlen = encr_offset + (RTE_ALIGN(encr_data_len, 8) / 8);
1494                 outputlen = inputlen;
1495
1496                 /* iv offset is 0 */
1497                 offset_ctrl = rte_cpu_to_be_64((uint64_t)encr_offset << 16);
1498         }
1499
1500         /* IV */
1501         iv_s = (flags == 0x1) ? params->auth_iv_buf :
1502                 params->iv_buf;
1503
1504         if (snow3g) {
1505                 /*
1506                  * DPDK seems to provide it in form of IV3 IV2 IV1 IV0
1507                  * and BigEndian, MC needs it as IV0 IV1 IV2 IV3
1508                  */
1509
1510                 for (j = 0; j < 4; j++)
1511                         iv[j] = iv_s[3 - j];
1512         } else {
1513                 /* ZUC doesn't need a swap */
1514                 for (j = 0; j < 4; j++)
1515                         iv[j] = iv_s[j];
1516         }
1517
1518         /*
1519          * GP op header, lengths are expected in bits.
1520          */
1521         vq_cmd_w0.u64 = 0;
1522         vq_cmd_w0.s.param1 = encr_data_len;
1523         vq_cmd_w0.s.param2 = auth_data_len;
1524
1525         /*
1526          * In 83XX since we have a limitation of
1527          * IV & Offset control word not part of instruction
1528          * and need to be part of Data Buffer, we check if
1529          * head room is there and then only do the Direct mode processing
1530          */
1531         if (likely((req_flags & SINGLE_BUF_INPLACE) &&
1532                    (req_flags & SINGLE_BUF_HEADTAILROOM))) {
1533                 void *dm_vaddr = params->bufs[0].vaddr;
1534                 uint64_t dm_dma_addr = params->bufs[0].dma_addr;
1535                 /*
1536                  * This flag indicates that there is 24 bytes head room and
1537                  * 8 bytes tail room available, so that we get to do
1538                  * DIRECT MODE with limitation
1539                  */
1540
1541                 offset_vaddr = (uint64_t *)((uint8_t *)dm_vaddr -
1542                                             OFF_CTRL_LEN - iv_len);
1543                 offset_dma = dm_dma_addr - OFF_CTRL_LEN - iv_len;
1544
1545                 /* DPTR */
1546                 req->ist.ei1 = offset_dma;
1547                 /* RPTR should just exclude offset control word */
1548                 req->ist.ei2 = dm_dma_addr - iv_len;
1549                 req->alternate_caddr = (uint64_t *)((uint8_t *)dm_vaddr
1550                                                     + outputlen - iv_len);
1551
1552                 vq_cmd_w0.s.dlen = inputlen + OFF_CTRL_LEN;
1553
1554                 vq_cmd_w0.s.opcode = opcode.flags;
1555
1556                 if (likely(iv_len)) {
1557                         uint32_t *iv_d = (uint32_t *)((uint8_t *)offset_vaddr
1558                                                       + OFF_CTRL_LEN);
1559                         memcpy(iv_d, iv, 16);
1560                 }
1561
1562                 *offset_vaddr = offset_ctrl;
1563         } else {
1564                 uint32_t i, g_size_bytes, s_size_bytes;
1565                 uint64_t dptr_dma, rptr_dma;
1566                 sg_comp_t *gather_comp;
1567                 sg_comp_t *scatter_comp;
1568                 uint8_t *in_buffer;
1569                 uint32_t *iv_d;
1570
1571                 /* save space for iv */
1572                 offset_vaddr = m_vaddr;
1573                 offset_dma = m_dma;
1574
1575                 m_vaddr = (uint8_t *)m_vaddr + OFF_CTRL_LEN + iv_len;
1576                 m_dma += OFF_CTRL_LEN + iv_len;
1577
1578                 opcode.s.major |= CPT_DMA_MODE;
1579
1580                 vq_cmd_w0.s.opcode = opcode.flags;
1581
1582                 /* DPTR has SG list */
1583                 in_buffer = m_vaddr;
1584                 dptr_dma = m_dma;
1585
1586                 ((uint16_t *)in_buffer)[0] = 0;
1587                 ((uint16_t *)in_buffer)[1] = 0;
1588
1589                 /* TODO Add error check if space will be sufficient */
1590                 gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
1591
1592                 /*
1593                  * Input Gather List
1594                  */
1595                 i = 0;
1596
1597                 /* Offset control word followed by iv */
1598
1599                 i = fill_sg_comp(gather_comp, i, offset_dma,
1600                                  OFF_CTRL_LEN + iv_len);
1601
1602                 /* iv offset is 0 */
1603                 *offset_vaddr = offset_ctrl;
1604
1605                 iv_d = (uint32_t *)((uint8_t *)offset_vaddr + OFF_CTRL_LEN);
1606                 memcpy(iv_d, iv, 16);
1607
1608                 /* input data */
1609                 size = inputlen - iv_len;
1610                 if (size) {
1611                         i = fill_sg_comp_from_iov(gather_comp, i,
1612                                                   params->src_iov,
1613                                                   0, &size, NULL, 0);
1614                         if (unlikely(size)) {
1615                                 CPT_LOG_DP_ERR("Insufficient buffer space,"
1616                                                " size %d needed", size);
1617                                 return;
1618                         }
1619                 }
1620                 ((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
1621                 g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
1622
1623                 /*
1624                  * Output Scatter List
1625                  */
1626
1627                 i = 0;
1628                 scatter_comp =
1629                         (sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
1630
1631                 if (flags == 0x1) {
1632                         /* IV in SLIST only for EEA3 & UEA2 */
1633                         iv_len = 0;
1634                 }
1635
1636                 if (iv_len) {
1637                         i = fill_sg_comp(scatter_comp, i,
1638                                          offset_dma + OFF_CTRL_LEN, iv_len);
1639                 }
1640
1641                 /* Add output data */
1642                 if (req_flags & VALID_MAC_BUF) {
1643                         size = outputlen - iv_len - mac_len;
1644                         if (size) {
1645                                 i = fill_sg_comp_from_iov(scatter_comp, i,
1646                                                           params->dst_iov, 0,
1647                                                           &size, NULL, 0);
1648
1649                                 if (unlikely(size)) {
1650                                         CPT_LOG_DP_ERR("Insufficient buffer space,"
1651                                                        " size %d needed", size);
1652                                         return;
1653                                 }
1654                         }
1655
1656                         /* mac data */
1657                         if (mac_len) {
1658                                 i = fill_sg_comp_from_buf(scatter_comp, i,
1659                                                           &params->mac_buf);
1660                         }
1661                 } else {
1662                         /* Output including mac */
1663                         size = outputlen - iv_len;
1664                         if (size) {
1665                                 i = fill_sg_comp_from_iov(scatter_comp, i,
1666                                                           params->dst_iov, 0,
1667                                                           &size, NULL, 0);
1668
1669                                 if (unlikely(size)) {
1670                                         CPT_LOG_DP_ERR("Insufficient buffer space,"
1671                                                        " size %d needed", size);
1672                                         return;
1673                                 }
1674                         }
1675                 }
1676                 ((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
1677                 s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
1678
1679                 size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
1680
1681                 /* This is DPTR len incase of SG mode */
1682                 vq_cmd_w0.s.dlen = size;
1683
1684                 m_vaddr = (uint8_t *)m_vaddr + size;
1685                 m_dma += size;
1686
1687                 /* cpt alternate completion address saved earlier */
1688                 req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
1689                 *req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
1690                 rptr_dma = c_dma - 8;
1691
1692                 req->ist.ei1 = dptr_dma;
1693                 req->ist.ei2 = rptr_dma;
1694         }
1695
1696         /* 16 byte aligned cpt res address */
1697         req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
1698         *req->completion_addr = COMPLETION_CODE_INIT;
1699         req->comp_baddr  = c_dma;
1700
1701         /* Fill microcode part of instruction */
1702         req->ist.ei0 = vq_cmd_w0.u64;
1703
1704         req->op = op;
1705
1706         *prep_req = req;
1707         return;
1708 }
1709
1710 static __rte_always_inline void
1711 cpt_zuc_snow3g_dec_prep(uint32_t req_flags,
1712                         uint64_t d_offs,
1713                         uint64_t d_lens,
1714                         fc_params_t *params,
1715                         void *op,
1716                         void **prep_req)
1717 {
1718         uint32_t size;
1719         int32_t inputlen = 0, outputlen;
1720         struct cpt_ctx *cpt_ctx;
1721         uint8_t snow3g, iv_len = 16;
1722         struct cpt_request_info *req;
1723         buf_ptr_t *buf_p;
1724         uint32_t encr_offset;
1725         uint32_t encr_data_len;
1726         int flags;
1727         void *m_vaddr, *c_vaddr;
1728         uint64_t m_dma, c_dma;
1729         uint64_t *offset_vaddr, offset_dma;
1730         uint32_t *iv_s, iv[4], j;
1731         vq_cmd_word0_t vq_cmd_w0;
1732         opcode_info_t opcode;
1733
1734         buf_p = &params->meta_buf;
1735         m_vaddr = buf_p->vaddr;
1736         m_dma = buf_p->dma_addr;
1737
1738         /*
1739          * Microcode expects offsets in bytes
1740          * TODO: Rounding off
1741          */
1742         encr_offset = ENCR_OFFSET(d_offs) / 8;
1743         encr_data_len = ENCR_DLEN(d_lens);
1744
1745         cpt_ctx = params->ctx_buf.vaddr;
1746         flags = cpt_ctx->zsk_flags;
1747         snow3g = cpt_ctx->snow3g;
1748         /*
1749          * Save initial space that followed app data for completion code &
1750          * alternate completion code to fall in same cache line as app data
1751          */
1752         m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
1753         m_dma += COMPLETION_CODE_SIZE;
1754         size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
1755                 (uint8_t *)m_vaddr;
1756
1757         c_vaddr = (uint8_t *)m_vaddr + size;
1758         c_dma = m_dma + size;
1759         size += sizeof(cpt_res_s_t);
1760
1761         m_vaddr = (uint8_t *)m_vaddr + size;
1762         m_dma += size;
1763
1764         /* Reserve memory for cpt request info */
1765         req = m_vaddr;
1766
1767         size = sizeof(struct cpt_request_info);
1768         m_vaddr = (uint8_t *)m_vaddr + size;
1769         m_dma += size;
1770
1771         opcode.s.major = CPT_MAJOR_OP_ZUC_SNOW3G;
1772
1773         /* indicates CPTR ctx, operation type, KEY & IV mode from DPTR */
1774
1775         opcode.s.minor = ((1 << 7) | (snow3g << 5) | (0 << 4) |
1776                           (0 << 3) | (flags & 0x7));
1777
1778         /* consider iv len */
1779         encr_offset += iv_len;
1780
1781         inputlen = encr_offset +
1782                 (RTE_ALIGN(encr_data_len, 8) / 8);
1783         outputlen = inputlen;
1784
1785         /* IV */
1786         iv_s = params->iv_buf;
1787         if (snow3g) {
1788                 /*
1789                  * DPDK seems to provide it in form of IV3 IV2 IV1 IV0
1790                  * and BigEndian, MC needs it as IV0 IV1 IV2 IV3
1791                  */
1792
1793                 for (j = 0; j < 4; j++)
1794                         iv[j] = iv_s[3 - j];
1795         } else {
1796                 /* ZUC doesn't need a swap */
1797                 for (j = 0; j < 4; j++)
1798                         iv[j] = iv_s[j];
1799         }
1800
1801         /*
1802          * GP op header, lengths are expected in bits.
1803          */
1804         vq_cmd_w0.u64 = 0;
1805         vq_cmd_w0.s.param1 = encr_data_len;
1806
1807         /*
1808          * In 83XX since we have a limitation of
1809          * IV & Offset control word not part of instruction
1810          * and need to be part of Data Buffer, we check if
1811          * head room is there and then only do the Direct mode processing
1812          */
1813         if (likely((req_flags & SINGLE_BUF_INPLACE) &&
1814                    (req_flags & SINGLE_BUF_HEADTAILROOM))) {
1815                 void *dm_vaddr = params->bufs[0].vaddr;
1816                 uint64_t dm_dma_addr = params->bufs[0].dma_addr;
1817                 /*
1818                  * This flag indicates that there is 24 bytes head room and
1819                  * 8 bytes tail room available, so that we get to do
1820                  * DIRECT MODE with limitation
1821                  */
1822
1823                 offset_vaddr = (uint64_t *)((uint8_t *)dm_vaddr -
1824                                             OFF_CTRL_LEN - iv_len);
1825                 offset_dma = dm_dma_addr - OFF_CTRL_LEN - iv_len;
1826
1827                 /* DPTR */
1828                 req->ist.ei1 = offset_dma;
1829                 /* RPTR should just exclude offset control word */
1830                 req->ist.ei2 = dm_dma_addr - iv_len;
1831                 req->alternate_caddr = (uint64_t *)((uint8_t *)dm_vaddr
1832                                                     + outputlen - iv_len);
1833
1834                 vq_cmd_w0.s.dlen = inputlen + OFF_CTRL_LEN;
1835
1836                 vq_cmd_w0.s.opcode = opcode.flags;
1837
1838                 if (likely(iv_len)) {
1839                         uint32_t *iv_d = (uint32_t *)((uint8_t *)offset_vaddr
1840                                                       + OFF_CTRL_LEN);
1841                         memcpy(iv_d, iv, 16);
1842                 }
1843
1844                 /* iv offset is 0 */
1845                 *offset_vaddr = rte_cpu_to_be_64((uint64_t)encr_offset << 16);
1846         } else {
1847                 uint32_t i, g_size_bytes, s_size_bytes;
1848                 uint64_t dptr_dma, rptr_dma;
1849                 sg_comp_t *gather_comp;
1850                 sg_comp_t *scatter_comp;
1851                 uint8_t *in_buffer;
1852                 uint32_t *iv_d;
1853
1854                 /* save space for offset and iv... */
1855                 offset_vaddr = m_vaddr;
1856                 offset_dma = m_dma;
1857
1858                 m_vaddr = (uint8_t *)m_vaddr + OFF_CTRL_LEN + iv_len;
1859                 m_dma += OFF_CTRL_LEN + iv_len;
1860
1861                 opcode.s.major |= CPT_DMA_MODE;
1862
1863                 vq_cmd_w0.s.opcode = opcode.flags;
1864
1865                 /* DPTR has SG list */
1866                 in_buffer = m_vaddr;
1867                 dptr_dma = m_dma;
1868
1869                 ((uint16_t *)in_buffer)[0] = 0;
1870                 ((uint16_t *)in_buffer)[1] = 0;
1871
1872                 /* TODO Add error check if space will be sufficient */
1873                 gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
1874
1875                 /*
1876                  * Input Gather List
1877                  */
1878                 i = 0;
1879
1880                 /* Offset control word */
1881
1882                 /* iv offset is 0 */
1883                 *offset_vaddr = rte_cpu_to_be_64((uint64_t)encr_offset << 16);
1884
1885                 i = fill_sg_comp(gather_comp, i, offset_dma,
1886                                  OFF_CTRL_LEN + iv_len);
1887
1888                 iv_d = (uint32_t *)((uint8_t *)offset_vaddr + OFF_CTRL_LEN);
1889                 memcpy(iv_d, iv, 16);
1890
1891                 /* Add input data */
1892                 size = inputlen - iv_len;
1893                 if (size) {
1894                         i = fill_sg_comp_from_iov(gather_comp, i,
1895                                                   params->src_iov,
1896                                                   0, &size, NULL, 0);
1897                         if (unlikely(size)) {
1898                                 CPT_LOG_DP_ERR("Insufficient buffer space,"
1899                                                " size %d needed", size);
1900                                 return;
1901                         }
1902                 }
1903                 ((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
1904                 g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
1905
1906                 /*
1907                  * Output Scatter List
1908                  */
1909
1910                 i = 0;
1911                 scatter_comp =
1912                         (sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
1913
1914                 /* IV */
1915                 i = fill_sg_comp(scatter_comp, i,
1916                                  offset_dma + OFF_CTRL_LEN,
1917                                  iv_len);
1918
1919                 /* Add output data */
1920                 size = outputlen - iv_len;
1921                 if (size) {
1922                         i = fill_sg_comp_from_iov(scatter_comp, i,
1923                                                   params->dst_iov, 0,
1924                                                   &size, NULL, 0);
1925
1926                         if (unlikely(size)) {
1927                                 CPT_LOG_DP_ERR("Insufficient buffer space,"
1928                                                " size %d needed", size);
1929                                 return;
1930                         }
1931                 }
1932                 ((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
1933                 s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
1934
1935                 size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
1936
1937                 /* This is DPTR len incase of SG mode */
1938                 vq_cmd_w0.s.dlen = size;
1939
1940                 m_vaddr = (uint8_t *)m_vaddr + size;
1941                 m_dma += size;
1942
1943                 /* cpt alternate completion address saved earlier */
1944                 req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
1945                 *req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
1946                 rptr_dma = c_dma - 8;
1947
1948                 req->ist.ei1 = dptr_dma;
1949                 req->ist.ei2 = rptr_dma;
1950         }
1951
1952         /* 16 byte aligned cpt res address */
1953         req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
1954         *req->completion_addr = COMPLETION_CODE_INIT;
1955         req->comp_baddr  = c_dma;
1956
1957         /* Fill microcode part of instruction */
1958         req->ist.ei0 = vq_cmd_w0.u64;
1959
1960         req->op = op;
1961
1962         *prep_req = req;
1963         return;
1964 }
1965
1966 static __rte_always_inline void
1967 cpt_kasumi_enc_prep(uint32_t req_flags,
1968                     uint64_t d_offs,
1969                     uint64_t d_lens,
1970                     fc_params_t *params,
1971                     void *op,
1972                     void **prep_req)
1973 {
1974         uint32_t size;
1975         int32_t inputlen = 0, outputlen = 0;
1976         struct cpt_ctx *cpt_ctx;
1977         uint32_t mac_len = 0;
1978         uint8_t i = 0;
1979         struct cpt_request_info *req;
1980         buf_ptr_t *buf_p;
1981         uint32_t encr_offset, auth_offset;
1982         uint32_t encr_data_len, auth_data_len;
1983         int flags;
1984         uint8_t *iv_s, *iv_d, iv_len = 8;
1985         uint8_t dir = 0;
1986         void *m_vaddr, *c_vaddr;
1987         uint64_t m_dma, c_dma;
1988         uint64_t *offset_vaddr, offset_dma;
1989         vq_cmd_word0_t vq_cmd_w0;
1990         opcode_info_t opcode;
1991         uint8_t *in_buffer;
1992         uint32_t g_size_bytes, s_size_bytes;
1993         uint64_t dptr_dma, rptr_dma;
1994         sg_comp_t *gather_comp;
1995         sg_comp_t *scatter_comp;
1996
1997         buf_p = &params->meta_buf;
1998         m_vaddr = buf_p->vaddr;
1999         m_dma = buf_p->dma_addr;
2000
2001         encr_offset = ENCR_OFFSET(d_offs) / 8;
2002         auth_offset = AUTH_OFFSET(d_offs) / 8;
2003         encr_data_len = ENCR_DLEN(d_lens);
2004         auth_data_len = AUTH_DLEN(d_lens);
2005
2006         cpt_ctx = params->ctx_buf.vaddr;
2007         flags = cpt_ctx->zsk_flags;
2008         mac_len = cpt_ctx->mac_len;
2009
2010         if (flags == 0x0)
2011                 iv_s = params->iv_buf;
2012         else
2013                 iv_s = params->auth_iv_buf;
2014
2015         dir = iv_s[8] & 0x1;
2016
2017         /*
2018          * Save initial space that followed app data for completion code &
2019          * alternate completion code to fall in same cache line as app data
2020          */
2021         m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
2022         m_dma += COMPLETION_CODE_SIZE;
2023         size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
2024                 (uint8_t *)m_vaddr;
2025
2026         c_vaddr = (uint8_t *)m_vaddr + size;
2027         c_dma = m_dma + size;
2028         size += sizeof(cpt_res_s_t);
2029
2030         m_vaddr = (uint8_t *)m_vaddr + size;
2031         m_dma += size;
2032
2033         /* Reserve memory for cpt request info */
2034         req = m_vaddr;
2035
2036         size = sizeof(struct cpt_request_info);
2037         m_vaddr = (uint8_t *)m_vaddr + size;
2038         m_dma += size;
2039
2040         opcode.s.major = CPT_MAJOR_OP_KASUMI | CPT_DMA_MODE;
2041
2042         /* indicates ECB/CBC, direction, ctx from cptr, iv from dptr */
2043         opcode.s.minor = ((1 << 6) | (cpt_ctx->k_ecb << 5) |
2044                           (dir << 4) | (0 << 3) | (flags & 0x7));
2045
2046         /*
2047          * GP op header, lengths are expected in bits.
2048          */
2049         vq_cmd_w0.u64 = 0;
2050         vq_cmd_w0.s.param1 = encr_data_len;
2051         vq_cmd_w0.s.param2 = auth_data_len;
2052         vq_cmd_w0.s.opcode = opcode.flags;
2053
2054         /* consider iv len */
2055         if (flags == 0x0) {
2056                 encr_offset += iv_len;
2057                 auth_offset += iv_len;
2058         }
2059
2060         /* save space for offset ctrl and iv */
2061         offset_vaddr = m_vaddr;
2062         offset_dma = m_dma;
2063
2064         m_vaddr = (uint8_t *)m_vaddr + OFF_CTRL_LEN + iv_len;
2065         m_dma += OFF_CTRL_LEN + iv_len;
2066
2067         /* DPTR has SG list */
2068         in_buffer = m_vaddr;
2069         dptr_dma = m_dma;
2070
2071         ((uint16_t *)in_buffer)[0] = 0;
2072         ((uint16_t *)in_buffer)[1] = 0;
2073
2074         /* TODO Add error check if space will be sufficient */
2075         gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
2076
2077         /*
2078          * Input Gather List
2079          */
2080         i = 0;
2081
2082         /* Offset control word followed by iv */
2083
2084         if (flags == 0x0) {
2085                 inputlen = encr_offset + (RTE_ALIGN(encr_data_len, 8) / 8);
2086                 outputlen = inputlen;
2087                 /* iv offset is 0 */
2088                 *offset_vaddr = rte_cpu_to_be_64((uint64_t)encr_offset << 16);
2089         } else {
2090                 inputlen = auth_offset + (RTE_ALIGN(auth_data_len, 8) / 8);
2091                 outputlen = mac_len;
2092                 /* iv offset is 0 */
2093                 *offset_vaddr = rte_cpu_to_be_64((uint64_t)auth_offset);
2094         }
2095
2096         i = fill_sg_comp(gather_comp, i, offset_dma, OFF_CTRL_LEN + iv_len);
2097
2098         /* IV */
2099         iv_d = (uint8_t *)offset_vaddr + OFF_CTRL_LEN;
2100         memcpy(iv_d, iv_s, iv_len);
2101
2102         /* input data */
2103         size = inputlen - iv_len;
2104         if (size) {
2105                 i = fill_sg_comp_from_iov(gather_comp, i,
2106                                           params->src_iov, 0,
2107                                           &size, NULL, 0);
2108
2109                 if (unlikely(size)) {
2110                         CPT_LOG_DP_ERR("Insufficient buffer space,"
2111                                        " size %d needed", size);
2112                         return;
2113                 }
2114         }
2115         ((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
2116         g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
2117
2118         /*
2119          * Output Scatter List
2120          */
2121
2122         i = 0;
2123         scatter_comp = (sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
2124
2125         if (flags == 0x1) {
2126                 /* IV in SLIST only for F8 */
2127                 iv_len = 0;
2128         }
2129
2130         /* IV */
2131         if (iv_len) {
2132                 i = fill_sg_comp(scatter_comp, i,
2133                                  offset_dma + OFF_CTRL_LEN,
2134                                  iv_len);
2135         }
2136
2137         /* Add output data */
2138         if (req_flags & VALID_MAC_BUF) {
2139                 size = outputlen - iv_len - mac_len;
2140                 if (size) {
2141                         i = fill_sg_comp_from_iov(scatter_comp, i,
2142                                                   params->dst_iov, 0,
2143                                                   &size, NULL, 0);
2144
2145                         if (unlikely(size)) {
2146                                 CPT_LOG_DP_ERR("Insufficient buffer space,"
2147                                                " size %d needed", size);
2148                                 return;
2149                         }
2150                 }
2151
2152                 /* mac data */
2153                 if (mac_len) {
2154                         i = fill_sg_comp_from_buf(scatter_comp, i,
2155                                                   &params->mac_buf);
2156                 }
2157         } else {
2158                 /* Output including mac */
2159                 size = outputlen - iv_len;
2160                 if (size) {
2161                         i = fill_sg_comp_from_iov(scatter_comp, i,
2162                                                   params->dst_iov, 0,
2163                                                   &size, NULL, 0);
2164
2165                         if (unlikely(size)) {
2166                                 CPT_LOG_DP_ERR("Insufficient buffer space,"
2167                                                " size %d needed", size);
2168                                 return;
2169                         }
2170                 }
2171         }
2172         ((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
2173         s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
2174
2175         size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
2176
2177         /* This is DPTR len incase of SG mode */
2178         vq_cmd_w0.s.dlen = size;
2179
2180         m_vaddr = (uint8_t *)m_vaddr + size;
2181         m_dma += size;
2182
2183         /* cpt alternate completion address saved earlier */
2184         req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
2185         *req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
2186         rptr_dma = c_dma - 8;
2187
2188         req->ist.ei1 = dptr_dma;
2189         req->ist.ei2 = rptr_dma;
2190
2191         /* 16 byte aligned cpt res address */
2192         req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
2193         *req->completion_addr = COMPLETION_CODE_INIT;
2194         req->comp_baddr  = c_dma;
2195
2196         /* Fill microcode part of instruction */
2197         req->ist.ei0 = vq_cmd_w0.u64;
2198
2199         req->op = op;
2200
2201         *prep_req = req;
2202         return;
2203 }
2204
2205 static __rte_always_inline void
2206 cpt_kasumi_dec_prep(uint64_t d_offs,
2207                     uint64_t d_lens,
2208                     fc_params_t *params,
2209                     void *op,
2210                     void **prep_req)
2211 {
2212         uint32_t size;
2213         int32_t inputlen = 0, outputlen;
2214         struct cpt_ctx *cpt_ctx;
2215         uint8_t i = 0, iv_len = 8;
2216         struct cpt_request_info *req;
2217         buf_ptr_t *buf_p;
2218         uint32_t encr_offset;
2219         uint32_t encr_data_len;
2220         int flags;
2221         uint8_t dir = 0;
2222         void *m_vaddr, *c_vaddr;
2223         uint64_t m_dma, c_dma;
2224         uint64_t *offset_vaddr, offset_dma;
2225         vq_cmd_word0_t vq_cmd_w0;
2226         opcode_info_t opcode;
2227         uint8_t *in_buffer;
2228         uint32_t g_size_bytes, s_size_bytes;
2229         uint64_t dptr_dma, rptr_dma;
2230         sg_comp_t *gather_comp;
2231         sg_comp_t *scatter_comp;
2232
2233         buf_p = &params->meta_buf;
2234         m_vaddr = buf_p->vaddr;
2235         m_dma = buf_p->dma_addr;
2236
2237         encr_offset = ENCR_OFFSET(d_offs) / 8;
2238         encr_data_len = ENCR_DLEN(d_lens);
2239
2240         cpt_ctx = params->ctx_buf.vaddr;
2241         flags = cpt_ctx->zsk_flags;
2242         /*
2243          * Save initial space that followed app data for completion code &
2244          * alternate completion code to fall in same cache line as app data
2245          */
2246         m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
2247         m_dma += COMPLETION_CODE_SIZE;
2248         size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
2249                 (uint8_t *)m_vaddr;
2250
2251         c_vaddr = (uint8_t *)m_vaddr + size;
2252         c_dma = m_dma + size;
2253         size += sizeof(cpt_res_s_t);
2254
2255         m_vaddr = (uint8_t *)m_vaddr + size;
2256         m_dma += size;
2257
2258         /* Reserve memory for cpt request info */
2259         req = m_vaddr;
2260
2261         size = sizeof(struct cpt_request_info);
2262         m_vaddr = (uint8_t *)m_vaddr + size;
2263         m_dma += size;
2264
2265         opcode.s.major = CPT_MAJOR_OP_KASUMI | CPT_DMA_MODE;
2266
2267         /* indicates ECB/CBC, direction, ctx from cptr, iv from dptr */
2268         opcode.s.minor = ((1 << 6) | (cpt_ctx->k_ecb << 5) |
2269                           (dir << 4) | (0 << 3) | (flags & 0x7));
2270
2271         /*
2272          * GP op header, lengths are expected in bits.
2273          */
2274         vq_cmd_w0.u64 = 0;
2275         vq_cmd_w0.s.param1 = encr_data_len;
2276         vq_cmd_w0.s.opcode = opcode.flags;
2277
2278         /* consider iv len */
2279         encr_offset += iv_len;
2280
2281         inputlen = iv_len + (RTE_ALIGN(encr_data_len, 8) / 8);
2282         outputlen = inputlen;
2283
2284         /* save space for offset ctrl & iv */
2285         offset_vaddr = m_vaddr;
2286         offset_dma = m_dma;
2287
2288         m_vaddr = (uint8_t *)m_vaddr + OFF_CTRL_LEN + iv_len;
2289         m_dma += OFF_CTRL_LEN + iv_len;
2290
2291         /* DPTR has SG list */
2292         in_buffer = m_vaddr;
2293         dptr_dma = m_dma;
2294
2295         ((uint16_t *)in_buffer)[0] = 0;
2296         ((uint16_t *)in_buffer)[1] = 0;
2297
2298         /* TODO Add error check if space will be sufficient */
2299         gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
2300
2301         /*
2302          * Input Gather List
2303          */
2304         i = 0;
2305
2306         /* Offset control word followed by iv */
2307         *offset_vaddr = rte_cpu_to_be_64((uint64_t)encr_offset << 16);
2308
2309         i = fill_sg_comp(gather_comp, i, offset_dma, OFF_CTRL_LEN + iv_len);
2310
2311         /* IV */
2312         memcpy((uint8_t *)offset_vaddr + OFF_CTRL_LEN,
2313                params->iv_buf, iv_len);
2314
2315         /* Add input data */
2316         size = inputlen - iv_len;
2317         if (size) {
2318                 i = fill_sg_comp_from_iov(gather_comp, i,
2319                                           params->src_iov,
2320                                           0, &size, NULL, 0);
2321                 if (unlikely(size)) {
2322                         CPT_LOG_DP_ERR("Insufficient buffer space,"
2323                                        " size %d needed", size);
2324                         return;
2325                 }
2326         }
2327         ((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
2328         g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
2329
2330         /*
2331          * Output Scatter List
2332          */
2333
2334         i = 0;
2335         scatter_comp = (sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
2336
2337         /* IV */
2338         i = fill_sg_comp(scatter_comp, i,
2339                          offset_dma + OFF_CTRL_LEN,
2340                          iv_len);
2341
2342         /* Add output data */
2343         size = outputlen - iv_len;
2344         if (size) {
2345                 i = fill_sg_comp_from_iov(scatter_comp, i,
2346                                           params->dst_iov, 0,
2347                                           &size, NULL, 0);
2348                 if (unlikely(size)) {
2349                         CPT_LOG_DP_ERR("Insufficient buffer space,"
2350                                        " size %d needed", size);
2351                         return;
2352                 }
2353         }
2354         ((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
2355         s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
2356
2357         size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
2358
2359         /* This is DPTR len incase of SG mode */
2360         vq_cmd_w0.s.dlen = size;
2361
2362         m_vaddr = (uint8_t *)m_vaddr + size;
2363         m_dma += size;
2364
2365         /* cpt alternate completion address saved earlier */
2366         req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
2367         *req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
2368         rptr_dma = c_dma - 8;
2369
2370         req->ist.ei1 = dptr_dma;
2371         req->ist.ei2 = rptr_dma;
2372
2373         /* 16 byte aligned cpt res address */
2374         req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
2375         *req->completion_addr = COMPLETION_CODE_INIT;
2376         req->comp_baddr  = c_dma;
2377
2378         /* Fill microcode part of instruction */
2379         req->ist.ei0 = vq_cmd_w0.u64;
2380
2381         req->op = op;
2382
2383         *prep_req = req;
2384         return;
2385 }
2386
2387 static __rte_always_inline void *
2388 cpt_fc_dec_hmac_prep(uint32_t flags,
2389                      uint64_t d_offs,
2390                      uint64_t d_lens,
2391                      fc_params_t *fc_params,
2392                      void *op)
2393 {
2394         struct cpt_ctx *ctx = fc_params->ctx_buf.vaddr;
2395         uint8_t fc_type;
2396         void *prep_req = NULL;
2397
2398         fc_type = ctx->fc_type;
2399
2400         if (likely(fc_type == FC_GEN)) {
2401                 cpt_dec_hmac_prep(flags, d_offs, d_lens, fc_params, op,
2402                                   &prep_req);
2403         } else if (fc_type == ZUC_SNOW3G) {
2404                 cpt_zuc_snow3g_dec_prep(flags, d_offs, d_lens, fc_params, op,
2405                                         &prep_req);
2406         } else if (fc_type == KASUMI) {
2407                 cpt_kasumi_dec_prep(d_offs, d_lens, fc_params, op, &prep_req);
2408         }
2409
2410         /*
2411          * For AUTH_ONLY case,
2412          * MC only supports digest generation and verification
2413          * should be done in software by memcmp()
2414          */
2415
2416         return prep_req;
2417 }
2418
2419 static __rte_always_inline void *__rte_hot
2420 cpt_fc_enc_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens,
2421                      fc_params_t *fc_params, void *op)
2422 {
2423         struct cpt_ctx *ctx = fc_params->ctx_buf.vaddr;
2424         uint8_t fc_type;
2425         void *prep_req = NULL;
2426
2427         fc_type = ctx->fc_type;
2428
2429         /* Common api for rest of the ops */
2430         if (likely(fc_type == FC_GEN)) {
2431                 cpt_enc_hmac_prep(flags, d_offs, d_lens, fc_params, op,
2432                                   &prep_req);
2433         } else if (fc_type == ZUC_SNOW3G) {
2434                 cpt_zuc_snow3g_enc_prep(flags, d_offs, d_lens, fc_params, op,
2435                                         &prep_req);
2436         } else if (fc_type == KASUMI) {
2437                 cpt_kasumi_enc_prep(flags, d_offs, d_lens, fc_params, op,
2438                                     &prep_req);
2439         } else if (fc_type == HASH_HMAC) {
2440                 cpt_digest_gen_prep(flags, d_lens, fc_params, op, &prep_req);
2441         }
2442
2443         return prep_req;
2444 }
2445
2446 static __rte_always_inline int
2447 cpt_fc_auth_set_key(struct cpt_ctx *cpt_ctx, auth_type_t type,
2448                     const uint8_t *key, uint16_t key_len, uint16_t mac_len)
2449 {
2450         mc_fc_context_t *fctx = &cpt_ctx->mc_ctx.fctx;
2451         mc_zuc_snow3g_ctx_t *zs_ctx = &cpt_ctx->mc_ctx.zs_ctx;
2452         mc_kasumi_ctx_t *k_ctx = &cpt_ctx->mc_ctx.k_ctx;
2453
2454         if ((type >= ZUC_EIA3) && (type <= KASUMI_F9_ECB)) {
2455                 uint32_t keyx[4];
2456
2457                 if (key_len != 16)
2458                         return -1;
2459                 /* No support for AEAD yet */
2460                 if (cpt_ctx->enc_cipher)
2461                         return -1;
2462                 /* For ZUC/SNOW3G/Kasumi */
2463                 switch (type) {
2464                 case SNOW3G_UIA2:
2465                         cpt_ctx->snow3g = 1;
2466                         gen_key_snow3g(key, keyx);
2467                         memcpy(zs_ctx->ci_key, keyx, key_len);
2468                         cpt_ctx->fc_type = ZUC_SNOW3G;
2469                         cpt_ctx->zsk_flags = 0x1;
2470                         break;
2471                 case ZUC_EIA3:
2472                         cpt_ctx->snow3g = 0;
2473                         memcpy(zs_ctx->ci_key, key, key_len);
2474                         memcpy(zs_ctx->zuc_const, zuc_d, 32);
2475                         cpt_ctx->fc_type = ZUC_SNOW3G;
2476                         cpt_ctx->zsk_flags = 0x1;
2477                         break;
2478                 case KASUMI_F9_ECB:
2479                         /* Kasumi ECB mode */
2480                         cpt_ctx->k_ecb = 1;
2481                         memcpy(k_ctx->ci_key, key, key_len);
2482                         cpt_ctx->fc_type = KASUMI;
2483                         cpt_ctx->zsk_flags = 0x1;
2484                         break;
2485                 case KASUMI_F9_CBC:
2486                         memcpy(k_ctx->ci_key, key, key_len);
2487                         cpt_ctx->fc_type = KASUMI;
2488                         cpt_ctx->zsk_flags = 0x1;
2489                         break;
2490                 default:
2491                         return -1;
2492                 }
2493                 cpt_ctx->mac_len = 4;
2494                 cpt_ctx->hash_type = type;
2495                 return 0;
2496         }
2497
2498         if (!(cpt_ctx->fc_type == FC_GEN && !type)) {
2499                 if (!cpt_ctx->fc_type || !cpt_ctx->enc_cipher)
2500                         cpt_ctx->fc_type = HASH_HMAC;
2501         }
2502
2503         if (cpt_ctx->fc_type == FC_GEN && key_len > 64)
2504                 return -1;
2505
2506         /* For GMAC auth, cipher must be NULL */
2507         if (type == GMAC_TYPE)
2508                 fctx->enc.enc_cipher = 0;
2509
2510         fctx->enc.hash_type = cpt_ctx->hash_type = type;
2511         fctx->enc.mac_len = cpt_ctx->mac_len = mac_len;
2512
2513         if (key_len) {
2514                 cpt_ctx->hmac = 1;
2515                 memset(cpt_ctx->auth_key, 0, sizeof(cpt_ctx->auth_key));
2516                 memcpy(cpt_ctx->auth_key, key, key_len);
2517                 cpt_ctx->auth_key_len = key_len;
2518                 memset(fctx->hmac.ipad, 0, sizeof(fctx->hmac.ipad));
2519                 memset(fctx->hmac.opad, 0, sizeof(fctx->hmac.opad));
2520
2521                 if (key_len <= 64)
2522                         memcpy(fctx->hmac.opad, key, key_len);
2523                 fctx->enc.auth_input_type = 1;
2524         }
2525         return 0;
2526 }
2527
2528 static __rte_always_inline int
2529 fill_sess_aead(struct rte_crypto_sym_xform *xform,
2530                  struct cpt_sess_misc *sess)
2531 {
2532         struct rte_crypto_aead_xform *aead_form;
2533         cipher_type_t enc_type = 0; /* NULL Cipher type */
2534         auth_type_t auth_type = 0; /* NULL Auth type */
2535         uint32_t cipher_key_len = 0;
2536         uint8_t aes_gcm = 0;
2537         aead_form = &xform->aead;
2538         void *ctx = SESS_PRIV(sess);
2539
2540         if (aead_form->op == RTE_CRYPTO_AEAD_OP_ENCRYPT) {
2541                 sess->cpt_op |= CPT_OP_CIPHER_ENCRYPT;
2542                 sess->cpt_op |= CPT_OP_AUTH_GENERATE;
2543         } else if (aead_form->op == RTE_CRYPTO_AEAD_OP_DECRYPT) {
2544                 sess->cpt_op |= CPT_OP_CIPHER_DECRYPT;
2545                 sess->cpt_op |= CPT_OP_AUTH_VERIFY;
2546         } else {
2547                 CPT_LOG_DP_ERR("Unknown aead operation\n");
2548                 return -1;
2549         }
2550         switch (aead_form->algo) {
2551         case RTE_CRYPTO_AEAD_AES_GCM:
2552                 enc_type = AES_GCM;
2553                 cipher_key_len = 16;
2554                 aes_gcm = 1;
2555                 break;
2556         case RTE_CRYPTO_AEAD_AES_CCM:
2557                 CPT_LOG_DP_ERR("Crypto: Unsupported cipher algo %u",
2558                                aead_form->algo);
2559                 return -1;
2560         case RTE_CRYPTO_AEAD_CHACHA20_POLY1305:
2561                 enc_type = CHACHA20;
2562                 auth_type = POLY1305;
2563                 cipher_key_len = 32;
2564                 sess->chacha_poly = 1;
2565                 break;
2566         default:
2567                 CPT_LOG_DP_ERR("Crypto: Undefined cipher algo %u specified",
2568                                aead_form->algo);
2569                 return -1;
2570         }
2571         if (aead_form->key.length < cipher_key_len) {
2572                 CPT_LOG_DP_ERR("Invalid cipher params keylen %lu",
2573                                (unsigned int long)aead_form->key.length);
2574                 return -1;
2575         }
2576         sess->zsk_flag = 0;
2577         sess->aes_gcm = aes_gcm;
2578         sess->mac_len = aead_form->digest_length;
2579         sess->iv_offset = aead_form->iv.offset;
2580         sess->iv_length = aead_form->iv.length;
2581         sess->aad_length = aead_form->aad_length;
2582
2583         if (unlikely(cpt_fc_ciph_set_key(ctx, enc_type, aead_form->key.data,
2584                         aead_form->key.length, NULL)))
2585                 return -1;
2586
2587         if (unlikely(cpt_fc_auth_set_key(ctx, auth_type, NULL, 0,
2588                         aead_form->digest_length)))
2589                 return -1;
2590
2591         return 0;
2592 }
2593
2594 static __rte_always_inline int
2595 fill_sess_cipher(struct rte_crypto_sym_xform *xform,
2596                  struct cpt_sess_misc *sess)
2597 {
2598         struct rte_crypto_cipher_xform *c_form;
2599         cipher_type_t enc_type = 0; /* NULL Cipher type */
2600         uint32_t cipher_key_len = 0;
2601         uint8_t zsk_flag = 0, aes_ctr = 0, is_null = 0;
2602
2603         c_form = &xform->cipher;
2604
2605         if (c_form->op == RTE_CRYPTO_CIPHER_OP_ENCRYPT)
2606                 sess->cpt_op |= CPT_OP_CIPHER_ENCRYPT;
2607         else if (c_form->op == RTE_CRYPTO_CIPHER_OP_DECRYPT)
2608                 sess->cpt_op |= CPT_OP_CIPHER_DECRYPT;
2609         else {
2610                 CPT_LOG_DP_ERR("Unknown cipher operation\n");
2611                 return -1;
2612         }
2613
2614         switch (c_form->algo) {
2615         case RTE_CRYPTO_CIPHER_AES_CBC:
2616                 enc_type = AES_CBC;
2617                 cipher_key_len = 16;
2618                 break;
2619         case RTE_CRYPTO_CIPHER_3DES_CBC:
2620                 enc_type = DES3_CBC;
2621                 cipher_key_len = 24;
2622                 break;
2623         case RTE_CRYPTO_CIPHER_DES_CBC:
2624                 /* DES is implemented using 3DES in hardware */
2625                 enc_type = DES3_CBC;
2626                 cipher_key_len = 8;
2627                 break;
2628         case RTE_CRYPTO_CIPHER_AES_CTR:
2629                 enc_type = AES_CTR;
2630                 cipher_key_len = 16;
2631                 aes_ctr = 1;
2632                 break;
2633         case RTE_CRYPTO_CIPHER_NULL:
2634                 enc_type = 0;
2635                 is_null = 1;
2636                 break;
2637         case RTE_CRYPTO_CIPHER_KASUMI_F8:
2638                 enc_type = KASUMI_F8_ECB;
2639                 cipher_key_len = 16;
2640                 zsk_flag = K_F8;
2641                 break;
2642         case RTE_CRYPTO_CIPHER_SNOW3G_UEA2:
2643                 enc_type = SNOW3G_UEA2;
2644                 cipher_key_len = 16;
2645                 zsk_flag = ZS_EA;
2646                 break;
2647         case RTE_CRYPTO_CIPHER_ZUC_EEA3:
2648                 enc_type = ZUC_EEA3;
2649                 cipher_key_len = 16;
2650                 zsk_flag = ZS_EA;
2651                 break;
2652         case RTE_CRYPTO_CIPHER_AES_XTS:
2653                 enc_type = AES_XTS;
2654                 cipher_key_len = 16;
2655                 break;
2656         case RTE_CRYPTO_CIPHER_3DES_ECB:
2657                 enc_type = DES3_ECB;
2658                 cipher_key_len = 24;
2659                 break;
2660         case RTE_CRYPTO_CIPHER_AES_ECB:
2661                 enc_type = AES_ECB;
2662                 cipher_key_len = 16;
2663                 break;
2664         case RTE_CRYPTO_CIPHER_3DES_CTR:
2665         case RTE_CRYPTO_CIPHER_AES_F8:
2666         case RTE_CRYPTO_CIPHER_ARC4:
2667                 CPT_LOG_DP_ERR("Crypto: Unsupported cipher algo %u",
2668                                c_form->algo);
2669                 return -1;
2670         default:
2671                 CPT_LOG_DP_ERR("Crypto: Undefined cipher algo %u specified",
2672                                c_form->algo);
2673                 return -1;
2674         }
2675
2676         if (c_form->key.length < cipher_key_len) {
2677                 CPT_LOG_DP_ERR("Invalid cipher params keylen %lu",
2678                                (unsigned long) c_form->key.length);
2679                 return -1;
2680         }
2681
2682         sess->zsk_flag = zsk_flag;
2683         sess->aes_gcm = 0;
2684         sess->aes_ctr = aes_ctr;
2685         sess->iv_offset = c_form->iv.offset;
2686         sess->iv_length = c_form->iv.length;
2687         sess->is_null = is_null;
2688
2689         if (unlikely(cpt_fc_ciph_set_key(SESS_PRIV(sess), enc_type,
2690                         c_form->key.data, c_form->key.length, NULL)))
2691                 return -1;
2692
2693         return 0;
2694 }
2695
2696 static __rte_always_inline int
2697 fill_sess_auth(struct rte_crypto_sym_xform *xform,
2698                struct cpt_sess_misc *sess)
2699 {
2700         struct rte_crypto_auth_xform *a_form;
2701         auth_type_t auth_type = 0; /* NULL Auth type */
2702         uint8_t zsk_flag = 0, aes_gcm = 0, is_null = 0;
2703
2704         a_form = &xform->auth;
2705
2706         if (a_form->op == RTE_CRYPTO_AUTH_OP_VERIFY)
2707                 sess->cpt_op |= CPT_OP_AUTH_VERIFY;
2708         else if (a_form->op == RTE_CRYPTO_AUTH_OP_GENERATE)
2709                 sess->cpt_op |= CPT_OP_AUTH_GENERATE;
2710         else {
2711                 CPT_LOG_DP_ERR("Unknown auth operation");
2712                 return -1;
2713         }
2714
2715         switch (a_form->algo) {
2716         case RTE_CRYPTO_AUTH_SHA1_HMAC:
2717                 /* Fall through */
2718         case RTE_CRYPTO_AUTH_SHA1:
2719                 auth_type = SHA1_TYPE;
2720                 break;
2721         case RTE_CRYPTO_AUTH_SHA256_HMAC:
2722         case RTE_CRYPTO_AUTH_SHA256:
2723                 auth_type = SHA2_SHA256;
2724                 break;
2725         case RTE_CRYPTO_AUTH_SHA512_HMAC:
2726         case RTE_CRYPTO_AUTH_SHA512:
2727                 auth_type = SHA2_SHA512;
2728                 break;
2729         case RTE_CRYPTO_AUTH_AES_GMAC:
2730                 auth_type = GMAC_TYPE;
2731                 aes_gcm = 1;
2732                 break;
2733         case RTE_CRYPTO_AUTH_SHA224_HMAC:
2734         case RTE_CRYPTO_AUTH_SHA224:
2735                 auth_type = SHA2_SHA224;
2736                 break;
2737         case RTE_CRYPTO_AUTH_SHA384_HMAC:
2738         case RTE_CRYPTO_AUTH_SHA384:
2739                 auth_type = SHA2_SHA384;
2740                 break;
2741         case RTE_CRYPTO_AUTH_MD5_HMAC:
2742         case RTE_CRYPTO_AUTH_MD5:
2743                 auth_type = MD5_TYPE;
2744                 break;
2745         case RTE_CRYPTO_AUTH_KASUMI_F9:
2746                 auth_type = KASUMI_F9_ECB;
2747                 /*
2748                  * Indicate that direction needs to be taken out
2749                  * from end of src
2750                  */
2751                 zsk_flag = K_F9;
2752                 break;
2753         case RTE_CRYPTO_AUTH_SNOW3G_UIA2:
2754                 auth_type = SNOW3G_UIA2;
2755                 zsk_flag = ZS_IA;
2756                 break;
2757         case RTE_CRYPTO_AUTH_ZUC_EIA3:
2758                 auth_type = ZUC_EIA3;
2759                 zsk_flag = ZS_IA;
2760                 break;
2761         case RTE_CRYPTO_AUTH_NULL:
2762                 auth_type = 0;
2763                 is_null = 1;
2764                 break;
2765         case RTE_CRYPTO_AUTH_AES_XCBC_MAC:
2766         case RTE_CRYPTO_AUTH_AES_CMAC:
2767         case RTE_CRYPTO_AUTH_AES_CBC_MAC:
2768                 CPT_LOG_DP_ERR("Crypto: Unsupported hash algo %u",
2769                                a_form->algo);
2770                 return -1;
2771         default:
2772                 CPT_LOG_DP_ERR("Crypto: Undefined Hash algo %u specified",
2773                                a_form->algo);
2774                 return -1;
2775         }
2776
2777         sess->zsk_flag = zsk_flag;
2778         sess->aes_gcm = aes_gcm;
2779         sess->mac_len = a_form->digest_length;
2780         sess->is_null = is_null;
2781         if (zsk_flag) {
2782                 sess->auth_iv_offset = a_form->iv.offset;
2783                 sess->auth_iv_length = a_form->iv.length;
2784         }
2785         if (unlikely(cpt_fc_auth_set_key(SESS_PRIV(sess), auth_type,
2786                         a_form->key.data, a_form->key.length,
2787                         a_form->digest_length)))
2788                 return -1;
2789
2790         return 0;
2791 }
2792
2793 static __rte_always_inline int
2794 fill_sess_gmac(struct rte_crypto_sym_xform *xform,
2795                  struct cpt_sess_misc *sess)
2796 {
2797         struct rte_crypto_auth_xform *a_form;
2798         cipher_type_t enc_type = 0; /* NULL Cipher type */
2799         auth_type_t auth_type = 0; /* NULL Auth type */
2800         void *ctx = SESS_PRIV(sess);
2801
2802         a_form = &xform->auth;
2803
2804         if (a_form->op == RTE_CRYPTO_AUTH_OP_GENERATE)
2805                 sess->cpt_op |= CPT_OP_ENCODE;
2806         else if (a_form->op == RTE_CRYPTO_AUTH_OP_VERIFY)
2807                 sess->cpt_op |= CPT_OP_DECODE;
2808         else {
2809                 CPT_LOG_DP_ERR("Unknown auth operation");
2810                 return -1;
2811         }
2812
2813         switch (a_form->algo) {
2814         case RTE_CRYPTO_AUTH_AES_GMAC:
2815                 enc_type = AES_GCM;
2816                 auth_type = GMAC_TYPE;
2817                 break;
2818         default:
2819                 CPT_LOG_DP_ERR("Crypto: Undefined cipher algo %u specified",
2820                                a_form->algo);
2821                 return -1;
2822         }
2823
2824         sess->zsk_flag = 0;
2825         sess->aes_gcm = 0;
2826         sess->is_gmac = 1;
2827         sess->iv_offset = a_form->iv.offset;
2828         sess->iv_length = a_form->iv.length;
2829         sess->mac_len = a_form->digest_length;
2830
2831         if (unlikely(cpt_fc_ciph_set_key(ctx, enc_type, a_form->key.data,
2832                         a_form->key.length, NULL)))
2833                 return -1;
2834
2835         if (unlikely(cpt_fc_auth_set_key(ctx, auth_type, NULL, 0,
2836                         a_form->digest_length)))
2837                 return -1;
2838
2839         return 0;
2840 }
2841
2842 static __rte_always_inline void *
2843 alloc_op_meta(struct rte_mbuf *m_src,
2844               buf_ptr_t *buf,
2845               int32_t len,
2846               struct rte_mempool *cpt_meta_pool)
2847 {
2848         uint8_t *mdata;
2849
2850 #ifndef CPT_ALWAYS_USE_SEPARATE_BUF
2851         if (likely(m_src && (m_src->nb_segs == 1))) {
2852                 int32_t tailroom;
2853                 phys_addr_t mphys;
2854
2855                 /* Check if tailroom is sufficient to hold meta data */
2856                 tailroom = rte_pktmbuf_tailroom(m_src);
2857                 if (likely(tailroom > len + 8)) {
2858                         mdata = (uint8_t *)m_src->buf_addr + m_src->buf_len;
2859                         mphys = m_src->buf_iova + m_src->buf_len;
2860                         mdata -= len;
2861                         mphys -= len;
2862                         buf->vaddr = mdata;
2863                         buf->dma_addr = mphys;
2864                         buf->size = len;
2865                         /* Indicate that this is a mbuf allocated mdata */
2866                         mdata = (uint8_t *)((uint64_t)mdata | 1ull);
2867                         return mdata;
2868                 }
2869         }
2870 #else
2871         RTE_SET_USED(m_src);
2872 #endif
2873
2874         if (unlikely(rte_mempool_get(cpt_meta_pool, (void **)&mdata) < 0))
2875                 return NULL;
2876
2877         buf->vaddr = mdata;
2878         buf->dma_addr = rte_mempool_virt2iova(mdata);
2879         buf->size = len;
2880
2881         return mdata;
2882 }
2883
2884 /**
2885  * cpt_free_metabuf - free metabuf to mempool.
2886  * @param instance: pointer to instance.
2887  * @param objp: pointer to the metabuf.
2888  */
2889 static __rte_always_inline void
2890 free_op_meta(void *mdata, struct rte_mempool *cpt_meta_pool)
2891 {
2892         bool nofree = ((uintptr_t)mdata & 1ull);
2893
2894         if (likely(nofree))
2895                 return;
2896         rte_mempool_put(cpt_meta_pool, mdata);
2897 }
2898
2899 static __rte_always_inline uint32_t
2900 prepare_iov_from_pkt(struct rte_mbuf *pkt,
2901                      iov_ptr_t *iovec, uint32_t start_offset)
2902 {
2903         uint16_t index = 0;
2904         void *seg_data = NULL;
2905         phys_addr_t seg_phys;
2906         int32_t seg_size = 0;
2907
2908         if (!pkt) {
2909                 iovec->buf_cnt = 0;
2910                 return 0;
2911         }
2912
2913         if (!start_offset) {
2914                 seg_data = rte_pktmbuf_mtod(pkt, void *);
2915                 seg_phys = rte_pktmbuf_iova(pkt);
2916                 seg_size = pkt->data_len;
2917         } else {
2918                 while (start_offset >= pkt->data_len) {
2919                         start_offset -= pkt->data_len;
2920                         pkt = pkt->next;
2921                 }
2922
2923                 seg_data = rte_pktmbuf_mtod_offset(pkt, void *, start_offset);
2924                 seg_phys = rte_pktmbuf_iova_offset(pkt, start_offset);
2925                 seg_size = pkt->data_len - start_offset;
2926                 if (!seg_size)
2927                         return 1;
2928         }
2929
2930         /* first seg */
2931         iovec->bufs[index].vaddr = seg_data;
2932         iovec->bufs[index].dma_addr = seg_phys;
2933         iovec->bufs[index].size = seg_size;
2934         index++;
2935         pkt = pkt->next;
2936
2937         while (unlikely(pkt != NULL)) {
2938                 seg_data = rte_pktmbuf_mtod(pkt, void *);
2939                 seg_phys = rte_pktmbuf_iova(pkt);
2940                 seg_size = pkt->data_len;
2941                 if (!seg_size)
2942                         break;
2943
2944                 iovec->bufs[index].vaddr = seg_data;
2945                 iovec->bufs[index].dma_addr = seg_phys;
2946                 iovec->bufs[index].size = seg_size;
2947
2948                 index++;
2949
2950                 pkt = pkt->next;
2951         }
2952
2953         iovec->buf_cnt = index;
2954         return 0;
2955 }
2956
2957 static __rte_always_inline uint32_t
2958 prepare_iov_from_pkt_inplace(struct rte_mbuf *pkt,
2959                              fc_params_t *param,
2960                              uint32_t *flags)
2961 {
2962         uint16_t index = 0;
2963         void *seg_data = NULL;
2964         phys_addr_t seg_phys;
2965         uint32_t seg_size = 0;
2966         iov_ptr_t *iovec;
2967
2968         seg_data = rte_pktmbuf_mtod(pkt, void *);
2969         seg_phys = rte_pktmbuf_iova(pkt);
2970         seg_size = pkt->data_len;
2971
2972         /* first seg */
2973         if (likely(!pkt->next)) {
2974                 uint32_t headroom, tailroom;
2975
2976                 *flags |= SINGLE_BUF_INPLACE;
2977                 headroom = rte_pktmbuf_headroom(pkt);
2978                 tailroom = rte_pktmbuf_tailroom(pkt);
2979                 if (likely((headroom >= 24) &&
2980                     (tailroom >= 8))) {
2981                         /* In 83XX this is prerequivisit for Direct mode */
2982                         *flags |= SINGLE_BUF_HEADTAILROOM;
2983                 }
2984                 param->bufs[0].vaddr = seg_data;
2985                 param->bufs[0].dma_addr = seg_phys;
2986                 param->bufs[0].size = seg_size;
2987                 return 0;
2988         }
2989         iovec = param->src_iov;
2990         iovec->bufs[index].vaddr = seg_data;
2991         iovec->bufs[index].dma_addr = seg_phys;
2992         iovec->bufs[index].size = seg_size;
2993         index++;
2994         pkt = pkt->next;
2995
2996         while (unlikely(pkt != NULL)) {
2997                 seg_data = rte_pktmbuf_mtod(pkt, void *);
2998                 seg_phys = rte_pktmbuf_iova(pkt);
2999                 seg_size = pkt->data_len;
3000
3001                 if (!seg_size)
3002                         break;
3003
3004                 iovec->bufs[index].vaddr = seg_data;
3005                 iovec->bufs[index].dma_addr = seg_phys;
3006                 iovec->bufs[index].size = seg_size;
3007
3008                 index++;
3009
3010                 pkt = pkt->next;
3011         }
3012
3013         iovec->buf_cnt = index;
3014         return 0;
3015 }
3016
3017 static __rte_always_inline int
3018 fill_fc_params(struct rte_crypto_op *cop,
3019                struct cpt_sess_misc *sess_misc,
3020                struct cpt_qp_meta_info *m_info,
3021                void **mdata_ptr,
3022                void **prep_req)
3023 {
3024         uint32_t space = 0;
3025         struct rte_crypto_sym_op *sym_op = cop->sym;
3026         void *mdata = NULL;
3027         uintptr_t *op;
3028         uint32_t mc_hash_off;
3029         uint32_t flags = 0;
3030         uint64_t d_offs, d_lens;
3031         struct rte_mbuf *m_src, *m_dst;
3032         uint8_t cpt_op = sess_misc->cpt_op;
3033 #ifdef CPT_ALWAYS_USE_SG_MODE
3034         uint8_t inplace = 0;
3035 #else
3036         uint8_t inplace = 1;
3037 #endif
3038         fc_params_t fc_params;
3039         char src[SRC_IOV_SIZE];
3040         char dst[SRC_IOV_SIZE];
3041         uint32_t iv_buf[4];
3042         int ret;
3043
3044         if (likely(sess_misc->iv_length)) {
3045                 flags |= VALID_IV_BUF;
3046                 fc_params.iv_buf = rte_crypto_op_ctod_offset(cop,
3047                                    uint8_t *, sess_misc->iv_offset);
3048                 if (sess_misc->aes_ctr &&
3049                     unlikely(sess_misc->iv_length != 16)) {
3050                         memcpy((uint8_t *)iv_buf,
3051                                 rte_crypto_op_ctod_offset(cop,
3052                                 uint8_t *, sess_misc->iv_offset), 12);
3053                         iv_buf[3] = rte_cpu_to_be_32(0x1);
3054                         fc_params.iv_buf = iv_buf;
3055                 }
3056         }
3057
3058         if (sess_misc->zsk_flag) {
3059                 fc_params.auth_iv_buf = rte_crypto_op_ctod_offset(cop,
3060                                         uint8_t *,
3061                                         sess_misc->auth_iv_offset);
3062                 if (sess_misc->zsk_flag != ZS_EA)
3063                         inplace = 0;
3064         }
3065         m_src = sym_op->m_src;
3066         m_dst = sym_op->m_dst;
3067
3068         if (sess_misc->aes_gcm || sess_misc->chacha_poly) {
3069                 uint8_t *salt;
3070                 uint8_t *aad_data;
3071                 uint16_t aad_len;
3072
3073                 d_offs = sym_op->aead.data.offset;
3074                 d_lens = sym_op->aead.data.length;
3075                 mc_hash_off = sym_op->aead.data.offset +
3076                               sym_op->aead.data.length;
3077
3078                 aad_data = sym_op->aead.aad.data;
3079                 aad_len = sess_misc->aad_length;
3080                 if (likely((aad_data + aad_len) ==
3081                            rte_pktmbuf_mtod_offset(m_src,
3082                                 uint8_t *,
3083                                 sym_op->aead.data.offset))) {
3084                         d_offs = (d_offs - aad_len) | (d_offs << 16);
3085                         d_lens = (d_lens + aad_len) | (d_lens << 32);
3086                 } else {
3087                         fc_params.aad_buf.vaddr = sym_op->aead.aad.data;
3088                         fc_params.aad_buf.dma_addr = sym_op->aead.aad.phys_addr;
3089                         fc_params.aad_buf.size = aad_len;
3090                         flags |= VALID_AAD_BUF;
3091                         inplace = 0;
3092                         d_offs = d_offs << 16;
3093                         d_lens = d_lens << 32;
3094                 }
3095
3096                 salt = fc_params.iv_buf;
3097                 if (unlikely(*(uint32_t *)salt != sess_misc->salt)) {
3098                         cpt_fc_salt_update(SESS_PRIV(sess_misc), salt);
3099                         sess_misc->salt = *(uint32_t *)salt;
3100                 }
3101                 fc_params.iv_buf = salt + 4;
3102                 if (likely(sess_misc->mac_len)) {
3103                         struct rte_mbuf *m = (cpt_op & CPT_OP_ENCODE) ? m_dst :
3104                                              m_src;
3105
3106                         if (!m)
3107                                 m = m_src;
3108
3109                         /* hmac immediately following data is best case */
3110                         if (unlikely(rte_pktmbuf_mtod(m, uint8_t *) +
3111                             mc_hash_off !=
3112                             (uint8_t *)sym_op->aead.digest.data)) {
3113                                 flags |= VALID_MAC_BUF;
3114                                 fc_params.mac_buf.size = sess_misc->mac_len;
3115                                 fc_params.mac_buf.vaddr =
3116                                   sym_op->aead.digest.data;
3117                                 fc_params.mac_buf.dma_addr =
3118                                  sym_op->aead.digest.phys_addr;
3119                                 inplace = 0;
3120                         }
3121                 }
3122         } else {
3123                 d_offs = sym_op->cipher.data.offset;
3124                 d_lens = sym_op->cipher.data.length;
3125                 mc_hash_off = sym_op->cipher.data.offset +
3126                               sym_op->cipher.data.length;
3127                 d_offs = (d_offs << 16) | sym_op->auth.data.offset;
3128                 d_lens = (d_lens << 32) | sym_op->auth.data.length;
3129
3130                 if (mc_hash_off < (sym_op->auth.data.offset +
3131                                    sym_op->auth.data.length)){
3132                         mc_hash_off = (sym_op->auth.data.offset +
3133                                        sym_op->auth.data.length);
3134                 }
3135                 /* for gmac, salt should be updated like in gcm */
3136                 if (unlikely(sess_misc->is_gmac)) {
3137                         uint8_t *salt;
3138                         salt = fc_params.iv_buf;
3139                         if (unlikely(*(uint32_t *)salt != sess_misc->salt)) {
3140                                 cpt_fc_salt_update(SESS_PRIV(sess_misc), salt);
3141                                 sess_misc->salt = *(uint32_t *)salt;
3142                         }
3143                         fc_params.iv_buf = salt + 4;
3144                 }
3145                 if (likely(sess_misc->mac_len)) {
3146                         struct rte_mbuf *m;
3147
3148                         m = (cpt_op & CPT_OP_ENCODE) ? m_dst : m_src;
3149                         if (!m)
3150                                 m = m_src;
3151
3152                         /* hmac immediately following data is best case */
3153                         if (unlikely(rte_pktmbuf_mtod(m, uint8_t *) +
3154                             mc_hash_off !=
3155                              (uint8_t *)sym_op->auth.digest.data)) {
3156                                 flags |= VALID_MAC_BUF;
3157                                 fc_params.mac_buf.size =
3158                                         sess_misc->mac_len;
3159                                 fc_params.mac_buf.vaddr =
3160                                         sym_op->auth.digest.data;
3161                                 fc_params.mac_buf.dma_addr =
3162                                 sym_op->auth.digest.phys_addr;
3163                                 inplace = 0;
3164                         }
3165                 }
3166         }
3167         fc_params.ctx_buf.vaddr = SESS_PRIV(sess_misc);
3168         fc_params.ctx_buf.dma_addr = sess_misc->ctx_dma_addr;
3169
3170         if (unlikely(sess_misc->is_null || sess_misc->cpt_op == CPT_OP_DECODE))
3171                 inplace = 0;
3172
3173         if (likely(!m_dst && inplace)) {
3174                 /* Case of single buffer without AAD buf or
3175                  * separate mac buf in place and
3176                  * not air crypto
3177                  */
3178                 fc_params.dst_iov = fc_params.src_iov = (void *)src;
3179
3180                 if (unlikely(prepare_iov_from_pkt_inplace(m_src,
3181                                                           &fc_params,
3182                                                           &flags))) {
3183                         CPT_LOG_DP_ERR("Prepare inplace src iov failed");
3184                         ret = -EINVAL;
3185                         goto err_exit;
3186                 }
3187
3188         } else {
3189                 /* Out of place processing */
3190                 fc_params.src_iov = (void *)src;
3191                 fc_params.dst_iov = (void *)dst;
3192
3193                 /* Store SG I/O in the api for reuse */
3194                 if (prepare_iov_from_pkt(m_src, fc_params.src_iov, 0)) {
3195                         CPT_LOG_DP_ERR("Prepare src iov failed");
3196                         ret = -EINVAL;
3197                         goto err_exit;
3198                 }
3199
3200                 if (unlikely(m_dst != NULL)) {
3201                         uint32_t pkt_len;
3202
3203                         /* Try to make room as much as src has */
3204                         pkt_len = rte_pktmbuf_pkt_len(m_dst);
3205
3206                         if (unlikely(pkt_len < rte_pktmbuf_pkt_len(m_src))) {
3207                                 pkt_len = rte_pktmbuf_pkt_len(m_src) - pkt_len;
3208                                 if (!rte_pktmbuf_append(m_dst, pkt_len)) {
3209                                         CPT_LOG_DP_ERR("Not enough space in "
3210                                                        "m_dst %p, need %u"
3211                                                        " more",
3212                                                        m_dst, pkt_len);
3213                                         ret = -EINVAL;
3214                                         goto err_exit;
3215                                 }
3216                         }
3217
3218                         if (prepare_iov_from_pkt(m_dst, fc_params.dst_iov, 0)) {
3219                                 CPT_LOG_DP_ERR("Prepare dst iov failed for "
3220                                                "m_dst %p", m_dst);
3221                                 ret = -EINVAL;
3222                                 goto err_exit;
3223                         }
3224                 } else {
3225                         fc_params.dst_iov = (void *)src;
3226                 }
3227         }
3228
3229         if (likely(flags & SINGLE_BUF_HEADTAILROOM))
3230                 mdata = alloc_op_meta(m_src, &fc_params.meta_buf,
3231                                       m_info->lb_mlen, m_info->pool);
3232         else
3233                 mdata = alloc_op_meta(NULL, &fc_params.meta_buf,
3234                                       m_info->sg_mlen, m_info->pool);
3235
3236         if (unlikely(mdata == NULL)) {
3237                 CPT_LOG_DP_ERR("Error allocating meta buffer for request");
3238                 ret = -ENOMEM;
3239                 goto err_exit;
3240         }
3241
3242         op = (uintptr_t *)((uintptr_t)mdata & (uintptr_t)~1ull);
3243         op[0] = (uintptr_t)mdata;
3244         op[1] = (uintptr_t)cop;
3245         op[2] = op[3] = 0; /* Used to indicate auth verify */
3246         space += 4 * sizeof(uint64_t);
3247
3248         fc_params.meta_buf.vaddr = (uint8_t *)op + space;
3249         fc_params.meta_buf.dma_addr += space;
3250         fc_params.meta_buf.size -= space;
3251
3252         /* Finally prepare the instruction */
3253         if (cpt_op & CPT_OP_ENCODE)
3254                 *prep_req = cpt_fc_enc_hmac_prep(flags, d_offs, d_lens,
3255                                                  &fc_params, op);
3256         else
3257                 *prep_req = cpt_fc_dec_hmac_prep(flags, d_offs, d_lens,
3258                                                  &fc_params, op);
3259
3260         if (unlikely(*prep_req == NULL)) {
3261                 CPT_LOG_DP_ERR("Preparing request failed due to bad input arg");
3262                 ret = -EINVAL;
3263                 goto free_mdata_and_exit;
3264         }
3265
3266         *mdata_ptr = mdata;
3267
3268         return 0;
3269
3270 free_mdata_and_exit:
3271         free_op_meta(mdata, m_info->pool);
3272 err_exit:
3273         return ret;
3274 }
3275
3276 static __rte_always_inline void
3277 compl_auth_verify(struct rte_crypto_op *op,
3278                       uint8_t *gen_mac,
3279                       uint64_t mac_len)
3280 {
3281         uint8_t *mac;
3282         struct rte_crypto_sym_op *sym_op = op->sym;
3283
3284         if (sym_op->auth.digest.data)
3285                 mac = sym_op->auth.digest.data;
3286         else
3287                 mac = rte_pktmbuf_mtod_offset(sym_op->m_src,
3288                                               uint8_t *,
3289                                               sym_op->auth.data.length +
3290                                               sym_op->auth.data.offset);
3291         if (!mac) {
3292                 op->status = RTE_CRYPTO_OP_STATUS_ERROR;
3293                 return;
3294         }
3295
3296         if (memcmp(mac, gen_mac, mac_len))
3297                 op->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
3298         else
3299                 op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
3300 }
3301
3302 static __rte_always_inline void
3303 find_kasumif9_direction_and_length(uint8_t *src,
3304                                    uint32_t counter_num_bytes,
3305                                    uint32_t *addr_length_in_bits,
3306                                    uint8_t *addr_direction)
3307 {
3308         uint8_t found = 0;
3309         uint32_t pos;
3310         uint8_t last_byte;
3311         while (!found && counter_num_bytes > 0) {
3312                 counter_num_bytes--;
3313                 if (src[counter_num_bytes] == 0x00)
3314                         continue;
3315                 pos = rte_bsf32(src[counter_num_bytes]);
3316                 if (pos == 7) {
3317                         if (likely(counter_num_bytes > 0)) {
3318                                 last_byte = src[counter_num_bytes - 1];
3319                                 *addr_direction  =  last_byte & 0x1;
3320                                 *addr_length_in_bits = counter_num_bytes * 8
3321                                                         - 1;
3322                         }
3323                 } else {
3324                         last_byte = src[counter_num_bytes];
3325                         *addr_direction = (last_byte >> (pos + 1)) & 0x1;
3326                         *addr_length_in_bits = counter_num_bytes * 8
3327                                                 + (8 - (pos + 2));
3328                 }
3329                 found = 1;
3330         }
3331 }
3332
3333 /*
3334  * This handles all auth only except AES_GMAC
3335  */
3336 static __rte_always_inline int
3337 fill_digest_params(struct rte_crypto_op *cop,
3338                    struct cpt_sess_misc *sess,
3339                    struct cpt_qp_meta_info *m_info,
3340                    void **mdata_ptr,
3341                    void **prep_req)
3342 {
3343         uint32_t space = 0;
3344         struct rte_crypto_sym_op *sym_op = cop->sym;
3345         void *mdata;
3346         phys_addr_t mphys;
3347         uint64_t *op;
3348         uint32_t auth_range_off;
3349         uint32_t flags = 0;
3350         uint64_t d_offs = 0, d_lens;
3351         struct rte_mbuf *m_src, *m_dst;
3352         uint16_t auth_op = sess->cpt_op & CPT_OP_AUTH_MASK;
3353         uint16_t mac_len = sess->mac_len;
3354         fc_params_t params;
3355         char src[SRC_IOV_SIZE];
3356         uint8_t iv_buf[16];
3357         int ret;
3358
3359         memset(&params, 0, sizeof(fc_params_t));
3360
3361         m_src = sym_op->m_src;
3362
3363         /* For just digest lets force mempool alloc */
3364         mdata = alloc_op_meta(NULL, &params.meta_buf, m_info->sg_mlen,
3365                               m_info->pool);
3366         if (mdata == NULL) {
3367                 ret = -ENOMEM;
3368                 goto err_exit;
3369         }
3370
3371         mphys = params.meta_buf.dma_addr;
3372
3373         op = mdata;
3374         op[0] = (uintptr_t)mdata;
3375         op[1] = (uintptr_t)cop;
3376         op[2] = op[3] = 0; /* Used to indicate auth verify */
3377         space += 4 * sizeof(uint64_t);
3378
3379         auth_range_off = sym_op->auth.data.offset;
3380
3381         flags = VALID_MAC_BUF;
3382         params.src_iov = (void *)src;
3383         if (unlikely(sess->zsk_flag)) {
3384                 /*
3385                  * Since for Zuc, Kasumi, Snow3g offsets are in bits
3386                  * we will send pass through even for auth only case,
3387                  * let MC handle it
3388                  */
3389                 d_offs = auth_range_off;
3390                 auth_range_off = 0;
3391                 params.auth_iv_buf = rte_crypto_op_ctod_offset(cop,
3392                                         uint8_t *, sess->auth_iv_offset);
3393                 if (sess->zsk_flag == K_F9) {
3394                         uint32_t length_in_bits, num_bytes;
3395                         uint8_t *src, direction = 0;
3396
3397                         memcpy(iv_buf, rte_pktmbuf_mtod(cop->sym->m_src,
3398                                                         uint8_t *), 8);
3399                         /*
3400                          * This is kasumi f9, take direction from
3401                          * source buffer
3402                          */
3403                         length_in_bits = cop->sym->auth.data.length;
3404                         num_bytes = (length_in_bits >> 3);
3405                         src = rte_pktmbuf_mtod(cop->sym->m_src, uint8_t *);
3406                         find_kasumif9_direction_and_length(src,
3407                                                 num_bytes,
3408                                                 &length_in_bits,
3409                                                 &direction);
3410                         length_in_bits -= 64;
3411                         cop->sym->auth.data.offset += 64;
3412                         d_offs = cop->sym->auth.data.offset;
3413                         auth_range_off = d_offs / 8;
3414                         cop->sym->auth.data.length = length_in_bits;
3415
3416                         /* Store it at end of auth iv */
3417                         iv_buf[8] = direction;
3418                         params.auth_iv_buf = iv_buf;
3419                 }
3420         }
3421
3422         d_lens = sym_op->auth.data.length;
3423
3424         params.ctx_buf.vaddr = SESS_PRIV(sess);
3425         params.ctx_buf.dma_addr = sess->ctx_dma_addr;
3426
3427         if (auth_op == CPT_OP_AUTH_GENERATE) {
3428                 if (sym_op->auth.digest.data) {
3429                         /*
3430                          * Digest to be generated
3431                          * in separate buffer
3432                          */
3433                         params.mac_buf.size =
3434                                 sess->mac_len;
3435                         params.mac_buf.vaddr =
3436                                 sym_op->auth.digest.data;
3437                         params.mac_buf.dma_addr =
3438                                 sym_op->auth.digest.phys_addr;
3439                 } else {
3440                         uint32_t off = sym_op->auth.data.offset +
3441                                 sym_op->auth.data.length;
3442                         int32_t dlen, space;
3443
3444                         m_dst = sym_op->m_dst ?
3445                                 sym_op->m_dst : sym_op->m_src;
3446                         dlen = rte_pktmbuf_pkt_len(m_dst);
3447
3448                         space = off + mac_len - dlen;
3449                         if (space > 0)
3450                                 if (!rte_pktmbuf_append(m_dst, space)) {
3451                                         CPT_LOG_DP_ERR("Failed to extend "
3452                                                        "mbuf by %uB", space);
3453                                         ret = -EINVAL;
3454                                         goto free_mdata_and_exit;
3455                                 }
3456
3457                         params.mac_buf.vaddr =
3458                                 rte_pktmbuf_mtod_offset(m_dst, void *, off);
3459                         params.mac_buf.dma_addr =
3460                                 rte_pktmbuf_iova_offset(m_dst, off);
3461                         params.mac_buf.size = mac_len;
3462                 }
3463         } else {
3464                 /* Need space for storing generated mac */
3465                 params.mac_buf.vaddr = (uint8_t *)mdata + space;
3466                 params.mac_buf.dma_addr = mphys + space;
3467                 params.mac_buf.size = mac_len;
3468                 space += RTE_ALIGN_CEIL(mac_len, 8);
3469                 op[2] = (uintptr_t)params.mac_buf.vaddr;
3470                 op[3] = mac_len;
3471         }
3472
3473         params.meta_buf.vaddr = (uint8_t *)mdata + space;
3474         params.meta_buf.dma_addr = mphys + space;
3475         params.meta_buf.size -= space;
3476
3477         /* Out of place processing */
3478         params.src_iov = (void *)src;
3479
3480         /*Store SG I/O in the api for reuse */
3481         if (prepare_iov_from_pkt(m_src, params.src_iov, auth_range_off)) {
3482                 CPT_LOG_DP_ERR("Prepare src iov failed");
3483                 ret = -EINVAL;
3484                 goto free_mdata_and_exit;
3485         }
3486
3487         *prep_req = cpt_fc_enc_hmac_prep(flags, d_offs, d_lens, &params, op);
3488         if (unlikely(*prep_req == NULL)) {
3489                 ret = -EINVAL;
3490                 goto free_mdata_and_exit;
3491         }
3492
3493         *mdata_ptr = mdata;
3494
3495         return 0;
3496
3497 free_mdata_and_exit:
3498         free_op_meta(mdata, m_info->pool);
3499 err_exit:
3500         return ret;
3501 }
3502
3503 #endif /*_CPT_UCODE_H_ */