1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Cavium, Inc
9 #include "cpt_common.h"
10 #include "cpt_hw_types.h"
11 #include "cpt_mcode_defines.h"
14 * This file defines functions that are interfaces to microcode spec.
18 static uint8_t zuc_d[32] = {
19 0x44, 0xD7, 0x26, 0xBC, 0x62, 0x6B, 0x13, 0x5E,
20 0x57, 0x89, 0x35, 0xE2, 0x71, 0x35, 0x09, 0xAF,
21 0x4D, 0x78, 0x2F, 0x13, 0x6B, 0xC4, 0x1A, 0xF1,
22 0x5E, 0x26, 0x3C, 0x4D, 0x78, 0x9A, 0x47, 0xAC
25 static __rte_always_inline void
26 gen_key_snow3g(const uint8_t *ck, uint32_t *keyx)
30 for (i = 0; i < 4; i++) {
32 keyx[3 - i] = (ck[base] << 24) | (ck[base + 1] << 16) |
33 (ck[base + 2] << 8) | (ck[base + 3]);
34 keyx[3 - i] = rte_cpu_to_be_32(keyx[3 - i]);
38 static __rte_always_inline int
39 cpt_mac_len_verify(struct rte_crypto_auth_xform *auth)
41 uint16_t mac_len = auth->digest_length;
45 case RTE_CRYPTO_AUTH_MD5:
46 case RTE_CRYPTO_AUTH_MD5_HMAC:
47 ret = (mac_len == 16) ? 0 : -1;
49 case RTE_CRYPTO_AUTH_SHA1:
50 case RTE_CRYPTO_AUTH_SHA1_HMAC:
51 ret = (mac_len == 20) ? 0 : -1;
53 case RTE_CRYPTO_AUTH_SHA224:
54 case RTE_CRYPTO_AUTH_SHA224_HMAC:
55 ret = (mac_len == 28) ? 0 : -1;
57 case RTE_CRYPTO_AUTH_SHA256:
58 case RTE_CRYPTO_AUTH_SHA256_HMAC:
59 ret = (mac_len == 32) ? 0 : -1;
61 case RTE_CRYPTO_AUTH_SHA384:
62 case RTE_CRYPTO_AUTH_SHA384_HMAC:
63 ret = (mac_len == 48) ? 0 : -1;
65 case RTE_CRYPTO_AUTH_SHA512:
66 case RTE_CRYPTO_AUTH_SHA512_HMAC:
67 ret = (mac_len == 64) ? 0 : -1;
69 case RTE_CRYPTO_AUTH_NULL:
79 static __rte_always_inline void
80 cpt_fc_salt_update(struct cpt_ctx *cpt_ctx,
83 mc_fc_context_t *fctx = &cpt_ctx->mc_ctx.fctx;
84 memcpy(fctx->enc.encr_iv, salt, 4);
87 static __rte_always_inline int
88 cpt_fc_ciph_validate_key_aes(uint16_t key_len)
100 static __rte_always_inline int
101 cpt_fc_ciph_set_type(cipher_type_t type, struct cpt_ctx *ctx, uint16_t key_len)
117 if (unlikely(cpt_fc_ciph_validate_key_aes(key_len) != 0))
125 key_len = key_len / 2;
126 if (unlikely(key_len == 24)) {
127 CPT_LOG_DP_ERR("Invalid AES key len for XTS");
130 if (unlikely(cpt_fc_ciph_validate_key_aes(key_len) != 0))
136 if (unlikely(key_len != 16))
138 /* No support for AEAD yet */
139 if (unlikely(ctx->hash_type))
141 fc_type = ZUC_SNOW3G;
145 if (unlikely(key_len != 16))
147 /* No support for AEAD yet */
148 if (unlikely(ctx->hash_type))
156 ctx->fc_type = fc_type;
160 static __rte_always_inline void
161 cpt_fc_ciph_set_key_passthrough(struct cpt_ctx *cpt_ctx, mc_fc_context_t *fctx)
163 cpt_ctx->enc_cipher = 0;
164 fctx->enc.enc_cipher = 0;
167 static __rte_always_inline void
168 cpt_fc_ciph_set_key_set_aes_key_type(mc_fc_context_t *fctx, uint16_t key_len)
170 mc_aes_type_t aes_key_type = 0;
173 aes_key_type = AES_128_BIT;
176 aes_key_type = AES_192_BIT;
179 aes_key_type = AES_256_BIT;
182 /* This should not happen */
183 CPT_LOG_DP_ERR("Invalid AES key len");
186 fctx->enc.aes_key = aes_key_type;
189 static __rte_always_inline void
190 cpt_fc_ciph_set_key_snow3g_uea2(struct cpt_ctx *cpt_ctx, const uint8_t *key,
193 mc_zuc_snow3g_ctx_t *zs_ctx = &cpt_ctx->mc_ctx.zs_ctx;
197 gen_key_snow3g(key, keyx);
198 memcpy(zs_ctx->ci_key, keyx, key_len);
199 cpt_ctx->zsk_flags = 0;
202 static __rte_always_inline void
203 cpt_fc_ciph_set_key_zuc_eea3(struct cpt_ctx *cpt_ctx, const uint8_t *key,
206 mc_zuc_snow3g_ctx_t *zs_ctx = &cpt_ctx->mc_ctx.zs_ctx;
209 memcpy(zs_ctx->ci_key, key, key_len);
210 memcpy(zs_ctx->zuc_const, zuc_d, 32);
211 cpt_ctx->zsk_flags = 0;
214 static __rte_always_inline void
215 cpt_fc_ciph_set_key_kasumi_f8_ecb(struct cpt_ctx *cpt_ctx, const uint8_t *key,
218 mc_kasumi_ctx_t *k_ctx = &cpt_ctx->mc_ctx.k_ctx;
221 memcpy(k_ctx->ci_key, key, key_len);
222 cpt_ctx->zsk_flags = 0;
225 static __rte_always_inline void
226 cpt_fc_ciph_set_key_kasumi_f8_cbc(struct cpt_ctx *cpt_ctx, const uint8_t *key,
229 mc_kasumi_ctx_t *k_ctx = &cpt_ctx->mc_ctx.k_ctx;
231 memcpy(k_ctx->ci_key, key, key_len);
232 cpt_ctx->zsk_flags = 0;
235 static __rte_always_inline int
236 cpt_fc_ciph_set_key(struct cpt_ctx *cpt_ctx, cipher_type_t type,
237 const uint8_t *key, uint16_t key_len, uint8_t *salt)
239 mc_fc_context_t *fctx = &cpt_ctx->mc_ctx.fctx;
242 ret = cpt_fc_ciph_set_type(type, cpt_ctx, key_len);
246 if (cpt_ctx->fc_type == FC_GEN) {
248 * We need to always say IV is from DPTR as user can
249 * sometimes iverride IV per operation.
251 fctx->enc.iv_source = CPT_FROM_DPTR;
253 if (cpt_ctx->auth_key_len > 64)
259 cpt_fc_ciph_set_key_passthrough(cpt_ctx, fctx);
262 /* CPT performs DES using 3DES with the 8B DES-key
263 * replicated 2 more times to match the 24B 3DES-key.
264 * Eg. If org. key is "0x0a 0x0b", then new key is
265 * "0x0a 0x0b 0x0a 0x0b 0x0a 0x0b"
268 /* Skipping the first 8B as it will be copied
269 * in the regular code flow
271 memcpy(fctx->enc.encr_key+key_len, key, key_len);
272 memcpy(fctx->enc.encr_key+2*key_len, key, key_len);
276 /* For DES3_ECB IV need to be from CTX. */
277 fctx->enc.iv_source = CPT_FROM_CTX;
284 cpt_fc_ciph_set_key_set_aes_key_type(fctx, key_len);
287 /* Even though iv source is from dptr,
288 * aes_gcm salt is taken from ctx
291 memcpy(fctx->enc.encr_iv, salt, 4);
292 /* Assuming it was just salt update
298 cpt_fc_ciph_set_key_set_aes_key_type(fctx, key_len);
301 key_len = key_len / 2;
302 cpt_fc_ciph_set_key_set_aes_key_type(fctx, key_len);
304 /* Copy key2 for XTS into ipad */
305 memset(fctx->hmac.ipad, 0, sizeof(fctx->hmac.ipad));
306 memcpy(fctx->hmac.ipad, &key[key_len], key_len);
309 cpt_fc_ciph_set_key_snow3g_uea2(cpt_ctx, key, key_len);
312 cpt_fc_ciph_set_key_zuc_eea3(cpt_ctx, key, key_len);
315 cpt_fc_ciph_set_key_kasumi_f8_ecb(cpt_ctx, key, key_len);
318 cpt_fc_ciph_set_key_kasumi_f8_cbc(cpt_ctx, key, key_len);
324 /* Only for FC_GEN case */
326 /* For GMAC auth, cipher must be NULL */
327 if (cpt_ctx->hash_type != GMAC_TYPE)
328 fctx->enc.enc_cipher = type;
330 memcpy(fctx->enc.encr_key, key, key_len);
333 cpt_ctx->enc_cipher = type;
338 static __rte_always_inline uint32_t
339 fill_sg_comp(sg_comp_t *list,
341 phys_addr_t dma_addr,
344 sg_comp_t *to = &list[i>>2];
346 to->u.s.len[i%4] = rte_cpu_to_be_16(size);
347 to->ptr[i%4] = rte_cpu_to_be_64(dma_addr);
352 static __rte_always_inline uint32_t
353 fill_sg_comp_from_buf(sg_comp_t *list,
357 sg_comp_t *to = &list[i>>2];
359 to->u.s.len[i%4] = rte_cpu_to_be_16(from->size);
360 to->ptr[i%4] = rte_cpu_to_be_64(from->dma_addr);
365 static __rte_always_inline uint32_t
366 fill_sg_comp_from_buf_min(sg_comp_t *list,
371 sg_comp_t *to = &list[i >> 2];
372 uint32_t size = *psize;
375 e_len = (size > from->size) ? from->size : size;
376 to->u.s.len[i % 4] = rte_cpu_to_be_16(e_len);
377 to->ptr[i % 4] = rte_cpu_to_be_64(from->dma_addr);
384 * This fills the MC expected SGIO list
385 * from IOV given by user.
387 static __rte_always_inline uint32_t
388 fill_sg_comp_from_iov(sg_comp_t *list,
390 iov_ptr_t *from, uint32_t from_offset,
391 uint32_t *psize, buf_ptr_t *extra_buf,
392 uint32_t extra_offset)
395 uint32_t extra_len = extra_buf ? extra_buf->size : 0;
396 uint32_t size = *psize;
400 for (j = 0; (j < from->buf_cnt) && size; j++) {
401 phys_addr_t e_dma_addr;
403 sg_comp_t *to = &list[i >> 2];
405 if (unlikely(from_offset)) {
406 if (from_offset >= bufs[j].size) {
407 from_offset -= bufs[j].size;
410 e_dma_addr = bufs[j].dma_addr + from_offset;
411 e_len = (size > (bufs[j].size - from_offset)) ?
412 (bufs[j].size - from_offset) : size;
415 e_dma_addr = bufs[j].dma_addr;
416 e_len = (size > bufs[j].size) ?
420 to->u.s.len[i % 4] = rte_cpu_to_be_16(e_len);
421 to->ptr[i % 4] = rte_cpu_to_be_64(e_dma_addr);
423 if (extra_len && (e_len >= extra_offset)) {
424 /* Break the data at given offset */
425 uint32_t next_len = e_len - extra_offset;
426 phys_addr_t next_dma = e_dma_addr + extra_offset;
431 e_len = extra_offset;
433 to->u.s.len[i % 4] = rte_cpu_to_be_16(e_len);
436 extra_len = RTE_MIN(extra_len, size);
437 /* Insert extra data ptr */
442 rte_cpu_to_be_16(extra_len);
444 rte_cpu_to_be_64(extra_buf->dma_addr);
448 next_len = RTE_MIN(next_len, size);
449 /* insert the rest of the data */
453 to->u.s.len[i % 4] = rte_cpu_to_be_16(next_len);
454 to->ptr[i % 4] = rte_cpu_to_be_64(next_dma);
463 extra_offset -= size;
471 static __rte_always_inline void
472 cpt_digest_gen_prep(uint32_t flags,
474 digest_params_t *params,
478 struct cpt_request_info *req;
480 uint16_t data_len, mac_len, key_len;
481 auth_type_t hash_type;
484 sg_comp_t *gather_comp;
485 sg_comp_t *scatter_comp;
487 uint32_t g_size_bytes, s_size_bytes;
488 uint64_t dptr_dma, rptr_dma;
489 vq_cmd_word0_t vq_cmd_w0;
490 void *c_vaddr, *m_vaddr;
491 uint64_t c_dma, m_dma;
493 ctx = params->ctx_buf.vaddr;
494 meta_p = ¶ms->meta_buf;
496 m_vaddr = meta_p->vaddr;
497 m_dma = meta_p->dma_addr;
500 * Save initial space that followed app data for completion code &
501 * alternate completion code to fall in same cache line as app data
503 m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
504 m_dma += COMPLETION_CODE_SIZE;
505 size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
507 c_vaddr = (uint8_t *)m_vaddr + size;
508 c_dma = m_dma + size;
509 size += sizeof(cpt_res_s_t);
511 m_vaddr = (uint8_t *)m_vaddr + size;
516 size = sizeof(struct cpt_request_info);
517 m_vaddr = (uint8_t *)m_vaddr + size;
520 hash_type = ctx->hash_type;
521 mac_len = ctx->mac_len;
522 key_len = ctx->auth_key_len;
523 data_len = AUTH_DLEN(d_lens);
526 vq_cmd_w0.s.opcode.minor = 0;
527 vq_cmd_w0.s.param2 = ((uint16_t)hash_type << 8);
529 vq_cmd_w0.s.opcode.major = CPT_MAJOR_OP_HMAC | CPT_DMA_MODE;
530 vq_cmd_w0.s.param1 = key_len;
531 vq_cmd_w0.s.dlen = data_len + RTE_ALIGN_CEIL(key_len, 8);
533 vq_cmd_w0.s.opcode.major = CPT_MAJOR_OP_HASH | CPT_DMA_MODE;
534 vq_cmd_w0.s.param1 = 0;
535 vq_cmd_w0.s.dlen = data_len;
538 /* Null auth only case enters the if */
539 if (unlikely(!hash_type && !ctx->enc_cipher)) {
540 vq_cmd_w0.s.opcode.major = CPT_MAJOR_OP_MISC;
541 /* Minor op is passthrough */
542 vq_cmd_w0.s.opcode.minor = 0x03;
543 /* Send out completion code only */
544 vq_cmd_w0.s.param2 = 0x1;
547 /* DPTR has SG list */
551 ((uint16_t *)in_buffer)[0] = 0;
552 ((uint16_t *)in_buffer)[1] = 0;
554 /* TODO Add error check if space will be sufficient */
555 gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
564 uint64_t k_dma = params->ctx_buf.dma_addr +
565 offsetof(struct cpt_ctx, auth_key);
567 i = fill_sg_comp(gather_comp, i, k_dma,
568 RTE_ALIGN_CEIL(key_len, 8));
574 i = fill_sg_comp_from_iov(gather_comp, i, params->src_iov,
576 if (unlikely(size)) {
577 CPT_LOG_DP_DEBUG("Insufficient dst IOV size, short"
583 * Looks like we need to support zero data
584 * gather ptr in case of hash & hmac
588 ((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
589 g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
596 scatter_comp = (sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
598 if (flags & VALID_MAC_BUF) {
599 if (unlikely(params->mac_buf.size < mac_len)) {
600 CPT_LOG_DP_ERR("Insufficient MAC size");
605 i = fill_sg_comp_from_buf_min(scatter_comp, i,
606 ¶ms->mac_buf, &size);
609 i = fill_sg_comp_from_iov(scatter_comp, i,
610 params->src_iov, data_len,
612 if (unlikely(size)) {
613 CPT_LOG_DP_ERR("Insufficient dst IOV size, short by"
619 ((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
620 s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
622 size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
624 /* This is DPTR len incase of SG mode */
625 vq_cmd_w0.s.dlen = size;
627 m_vaddr = (uint8_t *)m_vaddr + size;
630 /* cpt alternate completion address saved earlier */
631 req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
632 *req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
633 rptr_dma = c_dma - 8;
635 req->ist.ei1 = dptr_dma;
636 req->ist.ei2 = rptr_dma;
638 /* 16 byte aligned cpt res address */
639 req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
640 *req->completion_addr = COMPLETION_CODE_INIT;
641 req->comp_baddr = c_dma;
643 /* Fill microcode part of instruction */
644 req->ist.ei0 = vq_cmd_w0.u64;
652 static __rte_always_inline void
653 cpt_enc_hmac_prep(uint32_t flags,
656 fc_params_t *fc_params,
660 uint32_t iv_offset = 0;
661 int32_t inputlen, outputlen, enc_dlen, auth_dlen;
662 struct cpt_ctx *cpt_ctx;
663 uint32_t cipher_type, hash_type;
664 uint32_t mac_len, size;
666 struct cpt_request_info *req;
667 buf_ptr_t *meta_p, *aad_buf = NULL;
668 uint32_t encr_offset, auth_offset;
669 uint32_t encr_data_len, auth_data_len, aad_len = 0;
670 uint32_t passthrough_len = 0;
671 void *m_vaddr, *offset_vaddr;
672 uint64_t m_dma, offset_dma;
673 vq_cmd_word0_t vq_cmd_w0;
677 meta_p = &fc_params->meta_buf;
678 m_vaddr = meta_p->vaddr;
679 m_dma = meta_p->dma_addr;
681 encr_offset = ENCR_OFFSET(d_offs);
682 auth_offset = AUTH_OFFSET(d_offs);
683 encr_data_len = ENCR_DLEN(d_lens);
684 auth_data_len = AUTH_DLEN(d_lens);
685 if (unlikely(flags & VALID_AAD_BUF)) {
687 * We dont support both aad
688 * and auth data separately
692 aad_len = fc_params->aad_buf.size;
693 aad_buf = &fc_params->aad_buf;
695 cpt_ctx = fc_params->ctx_buf.vaddr;
696 cipher_type = cpt_ctx->enc_cipher;
697 hash_type = cpt_ctx->hash_type;
698 mac_len = cpt_ctx->mac_len;
701 * Save initial space that followed app data for completion code &
702 * alternate completion code to fall in same cache line as app data
704 m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
705 m_dma += COMPLETION_CODE_SIZE;
706 size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
709 c_vaddr = (uint8_t *)m_vaddr + size;
710 c_dma = m_dma + size;
711 size += sizeof(cpt_res_s_t);
713 m_vaddr = (uint8_t *)m_vaddr + size;
716 /* start cpt request info struct at 8 byte boundary */
717 size = (uint8_t *)RTE_PTR_ALIGN(m_vaddr, 8) -
720 req = (struct cpt_request_info *)((uint8_t *)m_vaddr + size);
722 size += sizeof(struct cpt_request_info);
723 m_vaddr = (uint8_t *)m_vaddr + size;
726 if (unlikely(!(flags & VALID_IV_BUF))) {
728 iv_offset = ENCR_IV_OFFSET(d_offs);
731 if (unlikely(flags & VALID_AAD_BUF)) {
733 * When AAD is given, data above encr_offset is pass through
734 * Since AAD is given as separate pointer and not as offset,
735 * this is a special case as we need to fragment input data
736 * into passthrough + encr_data and then insert AAD in between.
738 if (hash_type != GMAC_TYPE) {
739 passthrough_len = encr_offset;
740 auth_offset = passthrough_len + iv_len;
741 encr_offset = passthrough_len + aad_len + iv_len;
742 auth_data_len = aad_len + encr_data_len;
744 passthrough_len = 16 + aad_len;
745 auth_offset = passthrough_len + iv_len;
746 auth_data_len = aad_len;
749 encr_offset += iv_len;
750 auth_offset += iv_len;
754 vq_cmd_w0.s.opcode.major = CPT_MAJOR_OP_FC;
755 vq_cmd_w0.s.opcode.minor = CPT_FC_MINOR_OP_ENCRYPT;
756 vq_cmd_w0.s.opcode.minor |= (cpt_ctx->auth_enc <<
757 CPT_HMAC_FIRST_BIT_POS);
759 if (hash_type == GMAC_TYPE) {
764 auth_dlen = auth_offset + auth_data_len;
765 enc_dlen = encr_data_len + encr_offset;
766 if (unlikely(encr_data_len & 0xf)) {
767 if ((cipher_type == DES3_CBC) || (cipher_type == DES3_ECB))
768 enc_dlen = RTE_ALIGN_CEIL(encr_data_len, 8) +
770 else if (likely((cipher_type == AES_CBC) ||
771 (cipher_type == AES_ECB)))
772 enc_dlen = RTE_ALIGN_CEIL(encr_data_len, 8) +
776 if (unlikely(auth_dlen > enc_dlen)) {
777 inputlen = auth_dlen;
778 outputlen = auth_dlen + mac_len;
781 outputlen = enc_dlen + mac_len;
784 if (cpt_ctx->auth_enc != 0)
785 outputlen = enc_dlen;
788 vq_cmd_w0.s.param1 = encr_data_len;
789 vq_cmd_w0.s.param2 = auth_data_len;
791 * In 83XX since we have a limitation of
792 * IV & Offset control word not part of instruction
793 * and need to be part of Data Buffer, we check if
794 * head room is there and then only do the Direct mode processing
796 if (likely((flags & SINGLE_BUF_INPLACE) &&
797 (flags & SINGLE_BUF_HEADTAILROOM))) {
798 void *dm_vaddr = fc_params->bufs[0].vaddr;
799 uint64_t dm_dma_addr = fc_params->bufs[0].dma_addr;
801 * This flag indicates that there is 24 bytes head room and
802 * 8 bytes tail room available, so that we get to do
803 * DIRECT MODE with limitation
806 offset_vaddr = (uint8_t *)dm_vaddr - OFF_CTRL_LEN - iv_len;
807 offset_dma = dm_dma_addr - OFF_CTRL_LEN - iv_len;
810 req->ist.ei1 = offset_dma;
811 /* RPTR should just exclude offset control word */
812 req->ist.ei2 = dm_dma_addr - iv_len;
813 req->alternate_caddr = (uint64_t *)((uint8_t *)dm_vaddr
814 + outputlen - iv_len);
816 vq_cmd_w0.s.dlen = inputlen + OFF_CTRL_LEN;
818 if (likely(iv_len)) {
819 uint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr
821 uint64_t *src = fc_params->iv_buf;
826 *(uint64_t *)offset_vaddr =
827 rte_cpu_to_be_64(((uint64_t)encr_offset << 16) |
828 ((uint64_t)iv_offset << 8) |
829 ((uint64_t)auth_offset));
832 uint32_t i, g_size_bytes, s_size_bytes;
833 uint64_t dptr_dma, rptr_dma;
834 sg_comp_t *gather_comp;
835 sg_comp_t *scatter_comp;
838 /* This falls under strict SG mode */
839 offset_vaddr = m_vaddr;
841 size = OFF_CTRL_LEN + iv_len;
843 m_vaddr = (uint8_t *)m_vaddr + size;
846 vq_cmd_w0.s.opcode.major |= CPT_DMA_MODE;
848 if (likely(iv_len)) {
849 uint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr
851 uint64_t *src = fc_params->iv_buf;
856 *(uint64_t *)offset_vaddr =
857 rte_cpu_to_be_64(((uint64_t)encr_offset << 16) |
858 ((uint64_t)iv_offset << 8) |
859 ((uint64_t)auth_offset));
861 /* DPTR has SG list */
865 ((uint16_t *)in_buffer)[0] = 0;
866 ((uint16_t *)in_buffer)[1] = 0;
868 /* TODO Add error check if space will be sufficient */
869 gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
877 /* Offset control word that includes iv */
878 i = fill_sg_comp(gather_comp, i, offset_dma,
879 OFF_CTRL_LEN + iv_len);
882 size = inputlen - iv_len;
884 uint32_t aad_offset = aad_len ? passthrough_len : 0;
886 if (unlikely(flags & SINGLE_BUF_INPLACE)) {
887 i = fill_sg_comp_from_buf_min(gather_comp, i,
891 i = fill_sg_comp_from_iov(gather_comp, i,
894 aad_buf, aad_offset);
897 if (unlikely(size)) {
898 CPT_LOG_DP_ERR("Insufficient buffer space,"
899 " size %d needed", size);
903 ((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
904 g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
907 * Output Scatter list
911 (sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
914 if (likely(iv_len)) {
915 i = fill_sg_comp(scatter_comp, i,
916 offset_dma + OFF_CTRL_LEN,
920 /* output data or output data + digest*/
921 if (unlikely(flags & VALID_MAC_BUF)) {
922 size = outputlen - iv_len - mac_len;
924 uint32_t aad_offset =
925 aad_len ? passthrough_len : 0;
927 if (unlikely(flags & SINGLE_BUF_INPLACE)) {
928 i = fill_sg_comp_from_buf_min(
934 i = fill_sg_comp_from_iov(scatter_comp,
942 if (unlikely(size)) {
943 CPT_LOG_DP_ERR("Insufficient buffer"
944 " space, size %d needed",
951 i = fill_sg_comp_from_buf(scatter_comp, i,
952 &fc_params->mac_buf);
955 /* Output including mac */
956 size = outputlen - iv_len;
958 uint32_t aad_offset =
959 aad_len ? passthrough_len : 0;
961 if (unlikely(flags & SINGLE_BUF_INPLACE)) {
962 i = fill_sg_comp_from_buf_min(
968 i = fill_sg_comp_from_iov(scatter_comp,
976 if (unlikely(size)) {
977 CPT_LOG_DP_ERR("Insufficient buffer"
978 " space, size %d needed",
984 ((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
985 s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
987 size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
989 /* This is DPTR len incase of SG mode */
990 vq_cmd_w0.s.dlen = size;
992 m_vaddr = (uint8_t *)m_vaddr + size;
995 /* cpt alternate completion address saved earlier */
996 req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
997 *req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
998 rptr_dma = c_dma - 8;
1000 req->ist.ei1 = dptr_dma;
1001 req->ist.ei2 = rptr_dma;
1004 /* 16 byte aligned cpt res address */
1005 req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
1006 *req->completion_addr = COMPLETION_CODE_INIT;
1007 req->comp_baddr = c_dma;
1009 /* Fill microcode part of instruction */
1010 req->ist.ei0 = vq_cmd_w0.u64;
1018 static __rte_always_inline void
1019 cpt_dec_hmac_prep(uint32_t flags,
1022 fc_params_t *fc_params,
1026 uint32_t iv_offset = 0, size;
1027 int32_t inputlen, outputlen, enc_dlen, auth_dlen;
1028 struct cpt_ctx *cpt_ctx;
1029 int32_t hash_type, mac_len;
1030 uint8_t iv_len = 16;
1031 struct cpt_request_info *req;
1032 buf_ptr_t *meta_p, *aad_buf = NULL;
1033 uint32_t encr_offset, auth_offset;
1034 uint32_t encr_data_len, auth_data_len, aad_len = 0;
1035 uint32_t passthrough_len = 0;
1036 void *m_vaddr, *offset_vaddr;
1037 uint64_t m_dma, offset_dma;
1038 vq_cmd_word0_t vq_cmd_w0;
1042 meta_p = &fc_params->meta_buf;
1043 m_vaddr = meta_p->vaddr;
1044 m_dma = meta_p->dma_addr;
1046 encr_offset = ENCR_OFFSET(d_offs);
1047 auth_offset = AUTH_OFFSET(d_offs);
1048 encr_data_len = ENCR_DLEN(d_lens);
1049 auth_data_len = AUTH_DLEN(d_lens);
1051 if (unlikely(flags & VALID_AAD_BUF)) {
1053 * We dont support both aad
1054 * and auth data separately
1058 aad_len = fc_params->aad_buf.size;
1059 aad_buf = &fc_params->aad_buf;
1062 cpt_ctx = fc_params->ctx_buf.vaddr;
1063 hash_type = cpt_ctx->hash_type;
1064 mac_len = cpt_ctx->mac_len;
1066 if (unlikely(!(flags & VALID_IV_BUF))) {
1068 iv_offset = ENCR_IV_OFFSET(d_offs);
1071 if (unlikely(flags & VALID_AAD_BUF)) {
1073 * When AAD is given, data above encr_offset is pass through
1074 * Since AAD is given as separate pointer and not as offset,
1075 * this is a special case as we need to fragment input data
1076 * into passthrough + encr_data and then insert AAD in between.
1078 if (hash_type != GMAC_TYPE) {
1079 passthrough_len = encr_offset;
1080 auth_offset = passthrough_len + iv_len;
1081 encr_offset = passthrough_len + aad_len + iv_len;
1082 auth_data_len = aad_len + encr_data_len;
1084 passthrough_len = 16 + aad_len;
1085 auth_offset = passthrough_len + iv_len;
1086 auth_data_len = aad_len;
1089 encr_offset += iv_len;
1090 auth_offset += iv_len;
1094 * Save initial space that followed app data for completion code &
1095 * alternate completion code to fall in same cache line as app data
1097 m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
1098 m_dma += COMPLETION_CODE_SIZE;
1099 size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
1101 c_vaddr = (uint8_t *)m_vaddr + size;
1102 c_dma = m_dma + size;
1103 size += sizeof(cpt_res_s_t);
1105 m_vaddr = (uint8_t *)m_vaddr + size;
1108 /* start cpt request info structure at 8 byte alignment */
1109 size = (uint8_t *)RTE_PTR_ALIGN(m_vaddr, 8) -
1112 req = (struct cpt_request_info *)((uint8_t *)m_vaddr + size);
1114 size += sizeof(struct cpt_request_info);
1115 m_vaddr = (uint8_t *)m_vaddr + size;
1119 vq_cmd_w0.s.opcode.major = CPT_MAJOR_OP_FC;
1120 vq_cmd_w0.s.opcode.minor = CPT_FC_MINOR_OP_DECRYPT;
1121 vq_cmd_w0.s.opcode.minor |= (cpt_ctx->dec_auth <<
1122 CPT_HMAC_FIRST_BIT_POS);
1124 if (hash_type == GMAC_TYPE) {
1129 enc_dlen = encr_offset + encr_data_len;
1130 auth_dlen = auth_offset + auth_data_len;
1132 if (auth_dlen > enc_dlen) {
1133 inputlen = auth_dlen + mac_len;
1134 outputlen = auth_dlen;
1136 inputlen = enc_dlen + mac_len;
1137 outputlen = enc_dlen;
1140 if (cpt_ctx->dec_auth != 0)
1141 outputlen = inputlen = enc_dlen;
1143 vq_cmd_w0.s.param1 = encr_data_len;
1144 vq_cmd_w0.s.param2 = auth_data_len;
1147 * In 83XX since we have a limitation of
1148 * IV & Offset control word not part of instruction
1149 * and need to be part of Data Buffer, we check if
1150 * head room is there and then only do the Direct mode processing
1152 if (likely((flags & SINGLE_BUF_INPLACE) &&
1153 (flags & SINGLE_BUF_HEADTAILROOM))) {
1154 void *dm_vaddr = fc_params->bufs[0].vaddr;
1155 uint64_t dm_dma_addr = fc_params->bufs[0].dma_addr;
1157 * This flag indicates that there is 24 bytes head room and
1158 * 8 bytes tail room available, so that we get to do
1159 * DIRECT MODE with limitation
1162 offset_vaddr = (uint8_t *)dm_vaddr - OFF_CTRL_LEN - iv_len;
1163 offset_dma = dm_dma_addr - OFF_CTRL_LEN - iv_len;
1164 req->ist.ei1 = offset_dma;
1166 /* RPTR should just exclude offset control word */
1167 req->ist.ei2 = dm_dma_addr - iv_len;
1169 req->alternate_caddr = (uint64_t *)((uint8_t *)dm_vaddr +
1170 outputlen - iv_len);
1171 /* since this is decryption,
1172 * don't touch the content of
1173 * alternate ccode space as it contains
1177 vq_cmd_w0.s.dlen = inputlen + OFF_CTRL_LEN;
1179 if (likely(iv_len)) {
1180 uint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr +
1182 uint64_t *src = fc_params->iv_buf;
1187 *(uint64_t *)offset_vaddr =
1188 rte_cpu_to_be_64(((uint64_t)encr_offset << 16) |
1189 ((uint64_t)iv_offset << 8) |
1190 ((uint64_t)auth_offset));
1193 uint64_t dptr_dma, rptr_dma;
1194 uint32_t g_size_bytes, s_size_bytes;
1195 sg_comp_t *gather_comp;
1196 sg_comp_t *scatter_comp;
1200 /* This falls under strict SG mode */
1201 offset_vaddr = m_vaddr;
1203 size = OFF_CTRL_LEN + iv_len;
1205 m_vaddr = (uint8_t *)m_vaddr + size;
1208 vq_cmd_w0.s.opcode.major |= CPT_DMA_MODE;
1210 if (likely(iv_len)) {
1211 uint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr +
1213 uint64_t *src = fc_params->iv_buf;
1218 *(uint64_t *)offset_vaddr =
1219 rte_cpu_to_be_64(((uint64_t)encr_offset << 16) |
1220 ((uint64_t)iv_offset << 8) |
1221 ((uint64_t)auth_offset));
1223 /* DPTR has SG list */
1224 in_buffer = m_vaddr;
1227 ((uint16_t *)in_buffer)[0] = 0;
1228 ((uint16_t *)in_buffer)[1] = 0;
1230 /* TODO Add error check if space will be sufficient */
1231 gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
1238 /* Offset control word that includes iv */
1239 i = fill_sg_comp(gather_comp, i, offset_dma,
1240 OFF_CTRL_LEN + iv_len);
1242 /* Add input data */
1243 if (flags & VALID_MAC_BUF) {
1244 size = inputlen - iv_len - mac_len;
1246 /* input data only */
1247 if (unlikely(flags & SINGLE_BUF_INPLACE)) {
1248 i = fill_sg_comp_from_buf_min(
1253 uint32_t aad_offset = aad_len ?
1254 passthrough_len : 0;
1256 i = fill_sg_comp_from_iov(gather_comp,
1263 if (unlikely(size)) {
1264 CPT_LOG_DP_ERR("Insufficient buffer"
1265 " space, size %d needed",
1273 i = fill_sg_comp_from_buf(gather_comp, i,
1274 &fc_params->mac_buf);
1277 /* input data + mac */
1278 size = inputlen - iv_len;
1280 if (unlikely(flags & SINGLE_BUF_INPLACE)) {
1281 i = fill_sg_comp_from_buf_min(
1286 uint32_t aad_offset = aad_len ?
1287 passthrough_len : 0;
1289 if (unlikely(!fc_params->src_iov)) {
1290 CPT_LOG_DP_ERR("Bad input args");
1294 i = fill_sg_comp_from_iov(
1302 if (unlikely(size)) {
1303 CPT_LOG_DP_ERR("Insufficient buffer"
1304 " space, size %d needed",
1310 ((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
1311 g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
1314 * Output Scatter List
1319 (sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
1323 i = fill_sg_comp(scatter_comp, i,
1324 offset_dma + OFF_CTRL_LEN,
1328 /* Add output data */
1329 size = outputlen - iv_len;
1331 if (unlikely(flags & SINGLE_BUF_INPLACE)) {
1332 /* handle single buffer here */
1333 i = fill_sg_comp_from_buf_min(scatter_comp, i,
1337 uint32_t aad_offset = aad_len ?
1338 passthrough_len : 0;
1340 if (unlikely(!fc_params->dst_iov)) {
1341 CPT_LOG_DP_ERR("Bad input args");
1345 i = fill_sg_comp_from_iov(scatter_comp, i,
1346 fc_params->dst_iov, 0,
1351 if (unlikely(size)) {
1352 CPT_LOG_DP_ERR("Insufficient buffer space,"
1353 " size %d needed", size);
1358 ((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
1359 s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
1361 size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
1363 /* This is DPTR len incase of SG mode */
1364 vq_cmd_w0.s.dlen = size;
1366 m_vaddr = (uint8_t *)m_vaddr + size;
1369 /* cpt alternate completion address saved earlier */
1370 req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
1371 *req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
1372 rptr_dma = c_dma - 8;
1373 size += COMPLETION_CODE_SIZE;
1375 req->ist.ei1 = dptr_dma;
1376 req->ist.ei2 = rptr_dma;
1379 /* 16 byte aligned cpt res address */
1380 req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
1381 *req->completion_addr = COMPLETION_CODE_INIT;
1382 req->comp_baddr = c_dma;
1384 /* Fill microcode part of instruction */
1385 req->ist.ei0 = vq_cmd_w0.u64;
1393 static __rte_always_inline void
1394 cpt_zuc_snow3g_enc_prep(uint32_t req_flags,
1397 fc_params_t *params,
1402 int32_t inputlen, outputlen;
1403 struct cpt_ctx *cpt_ctx;
1404 uint32_t mac_len = 0;
1406 struct cpt_request_info *req;
1408 uint32_t encr_offset = 0, auth_offset = 0;
1409 uint32_t encr_data_len = 0, auth_data_len = 0;
1410 int flags, iv_len = 16;
1411 void *m_vaddr, *c_vaddr;
1412 uint64_t m_dma, c_dma, offset_ctrl;
1413 uint64_t *offset_vaddr, offset_dma;
1414 uint32_t *iv_s, iv[4];
1415 vq_cmd_word0_t vq_cmd_w0;
1417 buf_p = ¶ms->meta_buf;
1418 m_vaddr = buf_p->vaddr;
1419 m_dma = buf_p->dma_addr;
1421 cpt_ctx = params->ctx_buf.vaddr;
1422 flags = cpt_ctx->zsk_flags;
1423 mac_len = cpt_ctx->mac_len;
1424 snow3g = cpt_ctx->snow3g;
1427 * Save initial space that followed app data for completion code &
1428 * alternate completion code to fall in same cache line as app data
1430 m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
1431 m_dma += COMPLETION_CODE_SIZE;
1432 size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
1435 c_vaddr = (uint8_t *)m_vaddr + size;
1436 c_dma = m_dma + size;
1437 size += sizeof(cpt_res_s_t);
1439 m_vaddr = (uint8_t *)m_vaddr + size;
1442 /* Reserve memory for cpt request info */
1445 size = sizeof(struct cpt_request_info);
1446 m_vaddr = (uint8_t *)m_vaddr + size;
1449 vq_cmd_w0.s.opcode.major = CPT_MAJOR_OP_ZUC_SNOW3G;
1451 /* indicates CPTR ctx, operation type, KEY & IV mode from DPTR */
1453 vq_cmd_w0.s.opcode.minor = ((1 << 7) | (snow3g << 5) | (0 << 4) |
1454 (0 << 3) | (flags & 0x7));
1458 * Microcode expects offsets in bytes
1459 * TODO: Rounding off
1461 auth_data_len = AUTH_DLEN(d_lens);
1464 auth_offset = AUTH_OFFSET(d_offs);
1465 auth_offset = auth_offset / 8;
1467 /* consider iv len */
1468 auth_offset += iv_len;
1470 inputlen = auth_offset + (RTE_ALIGN(auth_data_len, 8) / 8);
1471 outputlen = mac_len;
1473 offset_ctrl = rte_cpu_to_be_64((uint64_t)auth_offset);
1478 * Microcode expects offsets in bytes
1479 * TODO: Rounding off
1481 encr_data_len = ENCR_DLEN(d_lens);
1483 encr_offset = ENCR_OFFSET(d_offs);
1484 encr_offset = encr_offset / 8;
1485 /* consider iv len */
1486 encr_offset += iv_len;
1488 inputlen = encr_offset + (RTE_ALIGN(encr_data_len, 8) / 8);
1489 outputlen = inputlen;
1491 /* iv offset is 0 */
1492 offset_ctrl = rte_cpu_to_be_64((uint64_t)encr_offset << 16);
1496 iv_s = (flags == 0x1) ? params->auth_iv_buf :
1501 * DPDK seems to provide it in form of IV3 IV2 IV1 IV0
1502 * and BigEndian, MC needs it as IV0 IV1 IV2 IV3
1505 for (j = 0; j < 4; j++)
1506 iv[j] = iv_s[3 - j];
1508 /* ZUC doesn't need a swap */
1509 for (j = 0; j < 4; j++)
1514 * GP op header, lengths are expected in bits.
1516 vq_cmd_w0.s.param1 = encr_data_len;
1517 vq_cmd_w0.s.param2 = auth_data_len;
1520 * In 83XX since we have a limitation of
1521 * IV & Offset control word not part of instruction
1522 * and need to be part of Data Buffer, we check if
1523 * head room is there and then only do the Direct mode processing
1525 if (likely((req_flags & SINGLE_BUF_INPLACE) &&
1526 (req_flags & SINGLE_BUF_HEADTAILROOM))) {
1527 void *dm_vaddr = params->bufs[0].vaddr;
1528 uint64_t dm_dma_addr = params->bufs[0].dma_addr;
1530 * This flag indicates that there is 24 bytes head room and
1531 * 8 bytes tail room available, so that we get to do
1532 * DIRECT MODE with limitation
1535 offset_vaddr = (uint64_t *)((uint8_t *)dm_vaddr -
1536 OFF_CTRL_LEN - iv_len);
1537 offset_dma = dm_dma_addr - OFF_CTRL_LEN - iv_len;
1540 req->ist.ei1 = offset_dma;
1541 /* RPTR should just exclude offset control word */
1542 req->ist.ei2 = dm_dma_addr - iv_len;
1543 req->alternate_caddr = (uint64_t *)((uint8_t *)dm_vaddr
1544 + outputlen - iv_len);
1546 vq_cmd_w0.s.dlen = inputlen + OFF_CTRL_LEN;
1548 if (likely(iv_len)) {
1549 uint32_t *iv_d = (uint32_t *)((uint8_t *)offset_vaddr
1551 memcpy(iv_d, iv, 16);
1554 *offset_vaddr = offset_ctrl;
1556 uint32_t i, g_size_bytes, s_size_bytes;
1557 uint64_t dptr_dma, rptr_dma;
1558 sg_comp_t *gather_comp;
1559 sg_comp_t *scatter_comp;
1563 /* save space for iv */
1564 offset_vaddr = m_vaddr;
1567 m_vaddr = (uint8_t *)m_vaddr + OFF_CTRL_LEN + iv_len;
1568 m_dma += OFF_CTRL_LEN + iv_len;
1570 vq_cmd_w0.s.opcode.major |= CPT_DMA_MODE;
1572 /* DPTR has SG list */
1573 in_buffer = m_vaddr;
1576 ((uint16_t *)in_buffer)[0] = 0;
1577 ((uint16_t *)in_buffer)[1] = 0;
1579 /* TODO Add error check if space will be sufficient */
1580 gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
1587 /* Offset control word followed by iv */
1589 i = fill_sg_comp(gather_comp, i, offset_dma,
1590 OFF_CTRL_LEN + iv_len);
1592 /* iv offset is 0 */
1593 *offset_vaddr = offset_ctrl;
1595 iv_d = (uint32_t *)((uint8_t *)offset_vaddr + OFF_CTRL_LEN);
1596 memcpy(iv_d, iv, 16);
1599 size = inputlen - iv_len;
1601 i = fill_sg_comp_from_iov(gather_comp, i,
1604 if (unlikely(size)) {
1605 CPT_LOG_DP_ERR("Insufficient buffer space,"
1606 " size %d needed", size);
1610 ((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
1611 g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
1614 * Output Scatter List
1619 (sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
1622 /* IV in SLIST only for EEA3 & UEA2 */
1627 i = fill_sg_comp(scatter_comp, i,
1628 offset_dma + OFF_CTRL_LEN, iv_len);
1631 /* Add output data */
1632 if (req_flags & VALID_MAC_BUF) {
1633 size = outputlen - iv_len - mac_len;
1635 i = fill_sg_comp_from_iov(scatter_comp, i,
1639 if (unlikely(size)) {
1640 CPT_LOG_DP_ERR("Insufficient buffer space,"
1641 " size %d needed", size);
1648 i = fill_sg_comp_from_buf(scatter_comp, i,
1652 /* Output including mac */
1653 size = outputlen - iv_len;
1655 i = fill_sg_comp_from_iov(scatter_comp, i,
1659 if (unlikely(size)) {
1660 CPT_LOG_DP_ERR("Insufficient buffer space,"
1661 " size %d needed", size);
1666 ((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
1667 s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
1669 size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
1671 /* This is DPTR len incase of SG mode */
1672 vq_cmd_w0.s.dlen = size;
1674 m_vaddr = (uint8_t *)m_vaddr + size;
1677 /* cpt alternate completion address saved earlier */
1678 req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
1679 *req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
1680 rptr_dma = c_dma - 8;
1682 req->ist.ei1 = dptr_dma;
1683 req->ist.ei2 = rptr_dma;
1686 /* 16 byte aligned cpt res address */
1687 req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
1688 *req->completion_addr = COMPLETION_CODE_INIT;
1689 req->comp_baddr = c_dma;
1691 /* Fill microcode part of instruction */
1692 req->ist.ei0 = vq_cmd_w0.u64;
1700 static __rte_always_inline void
1701 cpt_zuc_snow3g_dec_prep(uint32_t req_flags,
1704 fc_params_t *params,
1709 int32_t inputlen = 0, outputlen;
1710 struct cpt_ctx *cpt_ctx;
1711 uint8_t snow3g, iv_len = 16;
1712 struct cpt_request_info *req;
1714 uint32_t encr_offset;
1715 uint32_t encr_data_len;
1717 void *m_vaddr, *c_vaddr;
1718 uint64_t m_dma, c_dma;
1719 uint64_t *offset_vaddr, offset_dma;
1720 uint32_t *iv_s, iv[4], j;
1721 vq_cmd_word0_t vq_cmd_w0;
1723 buf_p = ¶ms->meta_buf;
1724 m_vaddr = buf_p->vaddr;
1725 m_dma = buf_p->dma_addr;
1728 * Microcode expects offsets in bytes
1729 * TODO: Rounding off
1731 encr_offset = ENCR_OFFSET(d_offs) / 8;
1732 encr_data_len = ENCR_DLEN(d_lens);
1734 cpt_ctx = params->ctx_buf.vaddr;
1735 flags = cpt_ctx->zsk_flags;
1736 snow3g = cpt_ctx->snow3g;
1738 * Save initial space that followed app data for completion code &
1739 * alternate completion code to fall in same cache line as app data
1741 m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
1742 m_dma += COMPLETION_CODE_SIZE;
1743 size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
1746 c_vaddr = (uint8_t *)m_vaddr + size;
1747 c_dma = m_dma + size;
1748 size += sizeof(cpt_res_s_t);
1750 m_vaddr = (uint8_t *)m_vaddr + size;
1753 /* Reserve memory for cpt request info */
1756 size = sizeof(struct cpt_request_info);
1757 m_vaddr = (uint8_t *)m_vaddr + size;
1761 vq_cmd_w0.s.opcode.major = CPT_MAJOR_OP_ZUC_SNOW3G;
1763 /* indicates CPTR ctx, operation type, KEY & IV mode from DPTR */
1765 vq_cmd_w0.s.opcode.minor = ((1 << 7) | (snow3g << 5) | (0 << 4) |
1766 (0 << 3) | (flags & 0x7));
1768 /* consider iv len */
1769 encr_offset += iv_len;
1771 inputlen = encr_offset +
1772 (RTE_ALIGN(encr_data_len, 8) / 8);
1773 outputlen = inputlen;
1776 iv_s = params->iv_buf;
1779 * DPDK seems to provide it in form of IV3 IV2 IV1 IV0
1780 * and BigEndian, MC needs it as IV0 IV1 IV2 IV3
1783 for (j = 0; j < 4; j++)
1784 iv[j] = iv_s[3 - j];
1786 /* ZUC doesn't need a swap */
1787 for (j = 0; j < 4; j++)
1792 * GP op header, lengths are expected in bits.
1794 vq_cmd_w0.s.param1 = encr_data_len;
1797 * In 83XX since we have a limitation of
1798 * IV & Offset control word not part of instruction
1799 * and need to be part of Data Buffer, we check if
1800 * head room is there and then only do the Direct mode processing
1802 if (likely((req_flags & SINGLE_BUF_INPLACE) &&
1803 (req_flags & SINGLE_BUF_HEADTAILROOM))) {
1804 void *dm_vaddr = params->bufs[0].vaddr;
1805 uint64_t dm_dma_addr = params->bufs[0].dma_addr;
1807 * This flag indicates that there is 24 bytes head room and
1808 * 8 bytes tail room available, so that we get to do
1809 * DIRECT MODE with limitation
1812 offset_vaddr = (uint64_t *)((uint8_t *)dm_vaddr -
1813 OFF_CTRL_LEN - iv_len);
1814 offset_dma = dm_dma_addr - OFF_CTRL_LEN - iv_len;
1817 req->ist.ei1 = offset_dma;
1818 /* RPTR should just exclude offset control word */
1819 req->ist.ei2 = dm_dma_addr - iv_len;
1820 req->alternate_caddr = (uint64_t *)((uint8_t *)dm_vaddr
1821 + outputlen - iv_len);
1823 vq_cmd_w0.s.dlen = inputlen + OFF_CTRL_LEN;
1825 if (likely(iv_len)) {
1826 uint32_t *iv_d = (uint32_t *)((uint8_t *)offset_vaddr
1828 memcpy(iv_d, iv, 16);
1831 /* iv offset is 0 */
1832 *offset_vaddr = rte_cpu_to_be_64((uint64_t)encr_offset << 16);
1834 uint32_t i, g_size_bytes, s_size_bytes;
1835 uint64_t dptr_dma, rptr_dma;
1836 sg_comp_t *gather_comp;
1837 sg_comp_t *scatter_comp;
1841 /* save space for offset and iv... */
1842 offset_vaddr = m_vaddr;
1845 m_vaddr = (uint8_t *)m_vaddr + OFF_CTRL_LEN + iv_len;
1846 m_dma += OFF_CTRL_LEN + iv_len;
1848 vq_cmd_w0.s.opcode.major |= CPT_DMA_MODE;
1850 /* DPTR has SG list */
1851 in_buffer = m_vaddr;
1854 ((uint16_t *)in_buffer)[0] = 0;
1855 ((uint16_t *)in_buffer)[1] = 0;
1857 /* TODO Add error check if space will be sufficient */
1858 gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
1865 /* Offset control word */
1867 /* iv offset is 0 */
1868 *offset_vaddr = rte_cpu_to_be_64((uint64_t)encr_offset << 16);
1870 i = fill_sg_comp(gather_comp, i, offset_dma,
1871 OFF_CTRL_LEN + iv_len);
1873 iv_d = (uint32_t *)((uint8_t *)offset_vaddr + OFF_CTRL_LEN);
1874 memcpy(iv_d, iv, 16);
1876 /* Add input data */
1877 size = inputlen - iv_len;
1879 i = fill_sg_comp_from_iov(gather_comp, i,
1882 if (unlikely(size)) {
1883 CPT_LOG_DP_ERR("Insufficient buffer space,"
1884 " size %d needed", size);
1888 ((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
1889 g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
1892 * Output Scatter List
1897 (sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
1900 i = fill_sg_comp(scatter_comp, i,
1901 offset_dma + OFF_CTRL_LEN,
1904 /* Add output data */
1905 size = outputlen - iv_len;
1907 i = fill_sg_comp_from_iov(scatter_comp, i,
1911 if (unlikely(size)) {
1912 CPT_LOG_DP_ERR("Insufficient buffer space,"
1913 " size %d needed", size);
1917 ((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
1918 s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
1920 size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
1922 /* This is DPTR len incase of SG mode */
1923 vq_cmd_w0.s.dlen = size;
1925 m_vaddr = (uint8_t *)m_vaddr + size;
1928 /* cpt alternate completion address saved earlier */
1929 req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
1930 *req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
1931 rptr_dma = c_dma - 8;
1933 req->ist.ei1 = dptr_dma;
1934 req->ist.ei2 = rptr_dma;
1937 /* 16 byte aligned cpt res address */
1938 req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
1939 *req->completion_addr = COMPLETION_CODE_INIT;
1940 req->comp_baddr = c_dma;
1942 /* Fill microcode part of instruction */
1943 req->ist.ei0 = vq_cmd_w0.u64;
1951 static __rte_always_inline void
1952 cpt_kasumi_enc_prep(uint32_t req_flags,
1955 fc_params_t *params,
1960 int32_t inputlen = 0, outputlen = 0;
1961 struct cpt_ctx *cpt_ctx;
1962 uint32_t mac_len = 0;
1964 struct cpt_request_info *req;
1966 uint32_t encr_offset, auth_offset;
1967 uint32_t encr_data_len, auth_data_len;
1969 uint8_t *iv_s, *iv_d, iv_len = 8;
1971 void *m_vaddr, *c_vaddr;
1972 uint64_t m_dma, c_dma;
1973 uint64_t *offset_vaddr, offset_dma;
1974 vq_cmd_word0_t vq_cmd_w0;
1976 uint32_t g_size_bytes, s_size_bytes;
1977 uint64_t dptr_dma, rptr_dma;
1978 sg_comp_t *gather_comp;
1979 sg_comp_t *scatter_comp;
1981 buf_p = ¶ms->meta_buf;
1982 m_vaddr = buf_p->vaddr;
1983 m_dma = buf_p->dma_addr;
1985 encr_offset = ENCR_OFFSET(d_offs) / 8;
1986 auth_offset = AUTH_OFFSET(d_offs) / 8;
1987 encr_data_len = ENCR_DLEN(d_lens);
1988 auth_data_len = AUTH_DLEN(d_lens);
1990 cpt_ctx = params->ctx_buf.vaddr;
1991 flags = cpt_ctx->zsk_flags;
1992 mac_len = cpt_ctx->mac_len;
1995 iv_s = params->iv_buf;
1997 iv_s = params->auth_iv_buf;
1999 dir = iv_s[8] & 0x1;
2002 * Save initial space that followed app data for completion code &
2003 * alternate completion code to fall in same cache line as app data
2005 m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
2006 m_dma += COMPLETION_CODE_SIZE;
2007 size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
2010 c_vaddr = (uint8_t *)m_vaddr + size;
2011 c_dma = m_dma + size;
2012 size += sizeof(cpt_res_s_t);
2014 m_vaddr = (uint8_t *)m_vaddr + size;
2017 /* Reserve memory for cpt request info */
2020 size = sizeof(struct cpt_request_info);
2021 m_vaddr = (uint8_t *)m_vaddr + size;
2024 vq_cmd_w0.s.opcode.major = CPT_MAJOR_OP_KASUMI | CPT_DMA_MODE;
2026 /* indicates ECB/CBC, direction, ctx from cptr, iv from dptr */
2027 vq_cmd_w0.s.opcode.minor = ((1 << 6) | (cpt_ctx->k_ecb << 5) |
2028 (dir << 4) | (0 << 3) | (flags & 0x7));
2031 * GP op header, lengths are expected in bits.
2033 vq_cmd_w0.s.param1 = encr_data_len;
2034 vq_cmd_w0.s.param2 = auth_data_len;
2036 /* consider iv len */
2038 encr_offset += iv_len;
2039 auth_offset += iv_len;
2042 /* save space for offset ctrl and iv */
2043 offset_vaddr = m_vaddr;
2046 m_vaddr = (uint8_t *)m_vaddr + OFF_CTRL_LEN + iv_len;
2047 m_dma += OFF_CTRL_LEN + iv_len;
2049 /* DPTR has SG list */
2050 in_buffer = m_vaddr;
2053 ((uint16_t *)in_buffer)[0] = 0;
2054 ((uint16_t *)in_buffer)[1] = 0;
2056 /* TODO Add error check if space will be sufficient */
2057 gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
2064 /* Offset control word followed by iv */
2067 inputlen = encr_offset + (RTE_ALIGN(encr_data_len, 8) / 8);
2068 outputlen = inputlen;
2069 /* iv offset is 0 */
2070 *offset_vaddr = rte_cpu_to_be_64((uint64_t)encr_offset << 16);
2072 inputlen = auth_offset + (RTE_ALIGN(auth_data_len, 8) / 8);
2073 outputlen = mac_len;
2074 /* iv offset is 0 */
2075 *offset_vaddr = rte_cpu_to_be_64((uint64_t)auth_offset);
2078 i = fill_sg_comp(gather_comp, i, offset_dma, OFF_CTRL_LEN + iv_len);
2081 iv_d = (uint8_t *)offset_vaddr + OFF_CTRL_LEN;
2082 memcpy(iv_d, iv_s, iv_len);
2085 size = inputlen - iv_len;
2087 i = fill_sg_comp_from_iov(gather_comp, i,
2091 if (unlikely(size)) {
2092 CPT_LOG_DP_ERR("Insufficient buffer space,"
2093 " size %d needed", size);
2097 ((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
2098 g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
2101 * Output Scatter List
2105 scatter_comp = (sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
2108 /* IV in SLIST only for F8 */
2114 i = fill_sg_comp(scatter_comp, i,
2115 offset_dma + OFF_CTRL_LEN,
2119 /* Add output data */
2120 if (req_flags & VALID_MAC_BUF) {
2121 size = outputlen - iv_len - mac_len;
2123 i = fill_sg_comp_from_iov(scatter_comp, i,
2127 if (unlikely(size)) {
2128 CPT_LOG_DP_ERR("Insufficient buffer space,"
2129 " size %d needed", size);
2136 i = fill_sg_comp_from_buf(scatter_comp, i,
2140 /* Output including mac */
2141 size = outputlen - iv_len;
2143 i = fill_sg_comp_from_iov(scatter_comp, i,
2147 if (unlikely(size)) {
2148 CPT_LOG_DP_ERR("Insufficient buffer space,"
2149 " size %d needed", size);
2154 ((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
2155 s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
2157 size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
2159 /* This is DPTR len incase of SG mode */
2160 vq_cmd_w0.s.dlen = size;
2162 m_vaddr = (uint8_t *)m_vaddr + size;
2165 /* cpt alternate completion address saved earlier */
2166 req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
2167 *req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
2168 rptr_dma = c_dma - 8;
2170 req->ist.ei1 = dptr_dma;
2171 req->ist.ei2 = rptr_dma;
2173 /* 16 byte aligned cpt res address */
2174 req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
2175 *req->completion_addr = COMPLETION_CODE_INIT;
2176 req->comp_baddr = c_dma;
2178 /* Fill microcode part of instruction */
2179 req->ist.ei0 = vq_cmd_w0.u64;
2187 static __rte_always_inline void
2188 cpt_kasumi_dec_prep(uint64_t d_offs,
2190 fc_params_t *params,
2195 int32_t inputlen = 0, outputlen;
2196 struct cpt_ctx *cpt_ctx;
2197 uint8_t i = 0, iv_len = 8;
2198 struct cpt_request_info *req;
2200 uint32_t encr_offset;
2201 uint32_t encr_data_len;
2204 void *m_vaddr, *c_vaddr;
2205 uint64_t m_dma, c_dma;
2206 uint64_t *offset_vaddr, offset_dma;
2207 vq_cmd_word0_t vq_cmd_w0;
2209 uint32_t g_size_bytes, s_size_bytes;
2210 uint64_t dptr_dma, rptr_dma;
2211 sg_comp_t *gather_comp;
2212 sg_comp_t *scatter_comp;
2214 buf_p = ¶ms->meta_buf;
2215 m_vaddr = buf_p->vaddr;
2216 m_dma = buf_p->dma_addr;
2218 encr_offset = ENCR_OFFSET(d_offs) / 8;
2219 encr_data_len = ENCR_DLEN(d_lens);
2221 cpt_ctx = params->ctx_buf.vaddr;
2222 flags = cpt_ctx->zsk_flags;
2224 * Save initial space that followed app data for completion code &
2225 * alternate completion code to fall in same cache line as app data
2227 m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
2228 m_dma += COMPLETION_CODE_SIZE;
2229 size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
2232 c_vaddr = (uint8_t *)m_vaddr + size;
2233 c_dma = m_dma + size;
2234 size += sizeof(cpt_res_s_t);
2236 m_vaddr = (uint8_t *)m_vaddr + size;
2239 /* Reserve memory for cpt request info */
2242 size = sizeof(struct cpt_request_info);
2243 m_vaddr = (uint8_t *)m_vaddr + size;
2247 vq_cmd_w0.s.opcode.major = CPT_MAJOR_OP_KASUMI | CPT_DMA_MODE;
2249 /* indicates ECB/CBC, direction, ctx from cptr, iv from dptr */
2250 vq_cmd_w0.s.opcode.minor = ((1 << 6) | (cpt_ctx->k_ecb << 5) |
2251 (dir << 4) | (0 << 3) | (flags & 0x7));
2254 * GP op header, lengths are expected in bits.
2256 vq_cmd_w0.s.param1 = encr_data_len;
2258 /* consider iv len */
2259 encr_offset += iv_len;
2261 inputlen = iv_len + (RTE_ALIGN(encr_data_len, 8) / 8);
2262 outputlen = inputlen;
2264 /* save space for offset ctrl & iv */
2265 offset_vaddr = m_vaddr;
2268 m_vaddr = (uint8_t *)m_vaddr + OFF_CTRL_LEN + iv_len;
2269 m_dma += OFF_CTRL_LEN + iv_len;
2271 /* DPTR has SG list */
2272 in_buffer = m_vaddr;
2275 ((uint16_t *)in_buffer)[0] = 0;
2276 ((uint16_t *)in_buffer)[1] = 0;
2278 /* TODO Add error check if space will be sufficient */
2279 gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
2286 /* Offset control word followed by iv */
2287 *offset_vaddr = rte_cpu_to_be_64((uint64_t)encr_offset << 16);
2289 i = fill_sg_comp(gather_comp, i, offset_dma, OFF_CTRL_LEN + iv_len);
2292 memcpy((uint8_t *)offset_vaddr + OFF_CTRL_LEN,
2293 params->iv_buf, iv_len);
2295 /* Add input data */
2296 size = inputlen - iv_len;
2298 i = fill_sg_comp_from_iov(gather_comp, i,
2301 if (unlikely(size)) {
2302 CPT_LOG_DP_ERR("Insufficient buffer space,"
2303 " size %d needed", size);
2307 ((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
2308 g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
2311 * Output Scatter List
2315 scatter_comp = (sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
2318 i = fill_sg_comp(scatter_comp, i,
2319 offset_dma + OFF_CTRL_LEN,
2322 /* Add output data */
2323 size = outputlen - iv_len;
2325 i = fill_sg_comp_from_iov(scatter_comp, i,
2328 if (unlikely(size)) {
2329 CPT_LOG_DP_ERR("Insufficient buffer space,"
2330 " size %d needed", size);
2334 ((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
2335 s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
2337 size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
2339 /* This is DPTR len incase of SG mode */
2340 vq_cmd_w0.s.dlen = size;
2342 m_vaddr = (uint8_t *)m_vaddr + size;
2345 /* cpt alternate completion address saved earlier */
2346 req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
2347 *req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
2348 rptr_dma = c_dma - 8;
2350 req->ist.ei1 = dptr_dma;
2351 req->ist.ei2 = rptr_dma;
2353 /* 16 byte aligned cpt res address */
2354 req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
2355 *req->completion_addr = COMPLETION_CODE_INIT;
2356 req->comp_baddr = c_dma;
2358 /* Fill microcode part of instruction */
2359 req->ist.ei0 = vq_cmd_w0.u64;
2367 static __rte_always_inline void *
2368 cpt_fc_dec_hmac_prep(uint32_t flags,
2371 fc_params_t *fc_params,
2374 struct cpt_ctx *ctx = fc_params->ctx_buf.vaddr;
2376 void *prep_req = NULL;
2378 fc_type = ctx->fc_type;
2380 if (likely(fc_type == FC_GEN)) {
2381 cpt_dec_hmac_prep(flags, d_offs, d_lens, fc_params, op,
2383 } else if (fc_type == ZUC_SNOW3G) {
2384 cpt_zuc_snow3g_dec_prep(flags, d_offs, d_lens, fc_params, op,
2386 } else if (fc_type == KASUMI) {
2387 cpt_kasumi_dec_prep(d_offs, d_lens, fc_params, op, &prep_req);
2391 * For AUTH_ONLY case,
2392 * MC only supports digest generation and verification
2393 * should be done in software by memcmp()
2399 static __rte_always_inline void *__rte_hot
2400 cpt_fc_enc_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens,
2401 fc_params_t *fc_params, void *op)
2403 struct cpt_ctx *ctx = fc_params->ctx_buf.vaddr;
2405 void *prep_req = NULL;
2407 fc_type = ctx->fc_type;
2409 /* Common api for rest of the ops */
2410 if (likely(fc_type == FC_GEN)) {
2411 cpt_enc_hmac_prep(flags, d_offs, d_lens, fc_params, op,
2413 } else if (fc_type == ZUC_SNOW3G) {
2414 cpt_zuc_snow3g_enc_prep(flags, d_offs, d_lens, fc_params, op,
2416 } else if (fc_type == KASUMI) {
2417 cpt_kasumi_enc_prep(flags, d_offs, d_lens, fc_params, op,
2419 } else if (fc_type == HASH_HMAC) {
2420 cpt_digest_gen_prep(flags, d_lens, fc_params, op, &prep_req);
2426 static __rte_always_inline int
2427 cpt_fc_auth_set_key(struct cpt_ctx *cpt_ctx, auth_type_t type,
2428 const uint8_t *key, uint16_t key_len, uint16_t mac_len)
2430 mc_fc_context_t *fctx = &cpt_ctx->mc_ctx.fctx;
2431 mc_zuc_snow3g_ctx_t *zs_ctx = &cpt_ctx->mc_ctx.zs_ctx;
2432 mc_kasumi_ctx_t *k_ctx = &cpt_ctx->mc_ctx.k_ctx;
2434 if ((type >= ZUC_EIA3) && (type <= KASUMI_F9_ECB)) {
2439 /* No support for AEAD yet */
2440 if (cpt_ctx->enc_cipher)
2442 /* For ZUC/SNOW3G/Kasumi */
2445 cpt_ctx->snow3g = 1;
2446 gen_key_snow3g(key, keyx);
2447 memcpy(zs_ctx->ci_key, keyx, key_len);
2448 cpt_ctx->fc_type = ZUC_SNOW3G;
2449 cpt_ctx->zsk_flags = 0x1;
2452 cpt_ctx->snow3g = 0;
2453 memcpy(zs_ctx->ci_key, key, key_len);
2454 memcpy(zs_ctx->zuc_const, zuc_d, 32);
2455 cpt_ctx->fc_type = ZUC_SNOW3G;
2456 cpt_ctx->zsk_flags = 0x1;
2459 /* Kasumi ECB mode */
2461 memcpy(k_ctx->ci_key, key, key_len);
2462 cpt_ctx->fc_type = KASUMI;
2463 cpt_ctx->zsk_flags = 0x1;
2466 memcpy(k_ctx->ci_key, key, key_len);
2467 cpt_ctx->fc_type = KASUMI;
2468 cpt_ctx->zsk_flags = 0x1;
2473 cpt_ctx->mac_len = 4;
2474 cpt_ctx->hash_type = type;
2478 if (!(cpt_ctx->fc_type == FC_GEN && !type)) {
2479 if (!cpt_ctx->fc_type || !cpt_ctx->enc_cipher)
2480 cpt_ctx->fc_type = HASH_HMAC;
2483 if (cpt_ctx->fc_type == FC_GEN && key_len > 64)
2486 /* For GMAC auth, cipher must be NULL */
2487 if (type == GMAC_TYPE)
2488 fctx->enc.enc_cipher = 0;
2490 fctx->enc.hash_type = cpt_ctx->hash_type = type;
2491 fctx->enc.mac_len = cpt_ctx->mac_len = mac_len;
2495 memset(cpt_ctx->auth_key, 0, sizeof(cpt_ctx->auth_key));
2496 memcpy(cpt_ctx->auth_key, key, key_len);
2497 cpt_ctx->auth_key_len = key_len;
2498 memset(fctx->hmac.ipad, 0, sizeof(fctx->hmac.ipad));
2499 memset(fctx->hmac.opad, 0, sizeof(fctx->hmac.opad));
2502 memcpy(fctx->hmac.opad, key, key_len);
2503 fctx->enc.auth_input_type = 1;
2508 static __rte_always_inline int
2509 fill_sess_aead(struct rte_crypto_sym_xform *xform,
2510 struct cpt_sess_misc *sess)
2512 struct rte_crypto_aead_xform *aead_form;
2513 cipher_type_t enc_type = 0; /* NULL Cipher type */
2514 auth_type_t auth_type = 0; /* NULL Auth type */
2515 uint32_t cipher_key_len = 0;
2516 uint8_t aes_gcm = 0;
2517 aead_form = &xform->aead;
2518 void *ctx = SESS_PRIV(sess);
2520 if (aead_form->op == RTE_CRYPTO_AEAD_OP_ENCRYPT) {
2521 sess->cpt_op |= CPT_OP_CIPHER_ENCRYPT;
2522 sess->cpt_op |= CPT_OP_AUTH_GENERATE;
2523 } else if (aead_form->op == RTE_CRYPTO_AEAD_OP_DECRYPT) {
2524 sess->cpt_op |= CPT_OP_CIPHER_DECRYPT;
2525 sess->cpt_op |= CPT_OP_AUTH_VERIFY;
2527 CPT_LOG_DP_ERR("Unknown aead operation\n");
2530 switch (aead_form->algo) {
2531 case RTE_CRYPTO_AEAD_AES_GCM:
2533 cipher_key_len = 16;
2536 case RTE_CRYPTO_AEAD_AES_CCM:
2537 CPT_LOG_DP_ERR("Crypto: Unsupported cipher algo %u",
2540 case RTE_CRYPTO_AEAD_CHACHA20_POLY1305:
2541 enc_type = CHACHA20;
2542 auth_type = POLY1305;
2543 cipher_key_len = 32;
2544 sess->chacha_poly = 1;
2547 CPT_LOG_DP_ERR("Crypto: Undefined cipher algo %u specified",
2551 if (aead_form->key.length < cipher_key_len) {
2552 CPT_LOG_DP_ERR("Invalid cipher params keylen %lu",
2553 (unsigned int long)aead_form->key.length);
2557 sess->aes_gcm = aes_gcm;
2558 sess->mac_len = aead_form->digest_length;
2559 sess->iv_offset = aead_form->iv.offset;
2560 sess->iv_length = aead_form->iv.length;
2561 sess->aad_length = aead_form->aad_length;
2563 if (unlikely(cpt_fc_ciph_set_key(ctx, enc_type, aead_form->key.data,
2564 aead_form->key.length, NULL)))
2567 if (unlikely(cpt_fc_auth_set_key(ctx, auth_type, NULL, 0,
2568 aead_form->digest_length)))
2574 static __rte_always_inline int
2575 fill_sess_cipher(struct rte_crypto_sym_xform *xform,
2576 struct cpt_sess_misc *sess)
2578 struct rte_crypto_cipher_xform *c_form;
2579 struct cpt_ctx *ctx = SESS_PRIV(sess);
2580 cipher_type_t enc_type = 0; /* NULL Cipher type */
2581 uint32_t cipher_key_len = 0;
2582 uint8_t zsk_flag = 0, aes_ctr = 0, is_null = 0;
2584 c_form = &xform->cipher;
2586 if (c_form->op == RTE_CRYPTO_CIPHER_OP_ENCRYPT)
2587 sess->cpt_op |= CPT_OP_CIPHER_ENCRYPT;
2588 else if (c_form->op == RTE_CRYPTO_CIPHER_OP_DECRYPT) {
2589 sess->cpt_op |= CPT_OP_CIPHER_DECRYPT;
2590 if (xform->next != NULL &&
2591 xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH) {
2592 /* Perform decryption followed by auth verify */
2596 CPT_LOG_DP_ERR("Unknown cipher operation\n");
2600 switch (c_form->algo) {
2601 case RTE_CRYPTO_CIPHER_AES_CBC:
2603 cipher_key_len = 16;
2605 case RTE_CRYPTO_CIPHER_3DES_CBC:
2606 enc_type = DES3_CBC;
2607 cipher_key_len = 24;
2609 case RTE_CRYPTO_CIPHER_DES_CBC:
2610 /* DES is implemented using 3DES in hardware */
2611 enc_type = DES3_CBC;
2614 case RTE_CRYPTO_CIPHER_AES_CTR:
2616 cipher_key_len = 16;
2619 case RTE_CRYPTO_CIPHER_NULL:
2623 case RTE_CRYPTO_CIPHER_KASUMI_F8:
2624 enc_type = KASUMI_F8_ECB;
2625 cipher_key_len = 16;
2628 case RTE_CRYPTO_CIPHER_SNOW3G_UEA2:
2629 enc_type = SNOW3G_UEA2;
2630 cipher_key_len = 16;
2633 case RTE_CRYPTO_CIPHER_ZUC_EEA3:
2634 enc_type = ZUC_EEA3;
2635 cipher_key_len = 16;
2638 case RTE_CRYPTO_CIPHER_AES_XTS:
2640 cipher_key_len = 16;
2642 case RTE_CRYPTO_CIPHER_3DES_ECB:
2643 enc_type = DES3_ECB;
2644 cipher_key_len = 24;
2646 case RTE_CRYPTO_CIPHER_AES_ECB:
2648 cipher_key_len = 16;
2650 case RTE_CRYPTO_CIPHER_3DES_CTR:
2651 case RTE_CRYPTO_CIPHER_AES_F8:
2652 case RTE_CRYPTO_CIPHER_ARC4:
2653 CPT_LOG_DP_ERR("Crypto: Unsupported cipher algo %u",
2657 CPT_LOG_DP_ERR("Crypto: Undefined cipher algo %u specified",
2662 if (c_form->key.length < cipher_key_len) {
2663 CPT_LOG_DP_ERR("Invalid cipher params keylen %lu",
2664 (unsigned long) c_form->key.length);
2668 sess->zsk_flag = zsk_flag;
2670 sess->aes_ctr = aes_ctr;
2671 sess->iv_offset = c_form->iv.offset;
2672 sess->iv_length = c_form->iv.length;
2673 sess->is_null = is_null;
2675 if (unlikely(cpt_fc_ciph_set_key(SESS_PRIV(sess), enc_type,
2676 c_form->key.data, c_form->key.length, NULL)))
2682 static __rte_always_inline int
2683 fill_sess_auth(struct rte_crypto_sym_xform *xform,
2684 struct cpt_sess_misc *sess)
2686 struct cpt_ctx *ctx = SESS_PRIV(sess);
2687 struct rte_crypto_auth_xform *a_form;
2688 auth_type_t auth_type = 0; /* NULL Auth type */
2689 uint8_t zsk_flag = 0, aes_gcm = 0, is_null = 0;
2691 if (xform->next != NULL &&
2692 xform->next->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
2693 xform->next->cipher.op == RTE_CRYPTO_CIPHER_OP_ENCRYPT) {
2694 /* Perform auth followed by encryption */
2698 a_form = &xform->auth;
2700 if (a_form->op == RTE_CRYPTO_AUTH_OP_VERIFY)
2701 sess->cpt_op |= CPT_OP_AUTH_VERIFY;
2702 else if (a_form->op == RTE_CRYPTO_AUTH_OP_GENERATE)
2703 sess->cpt_op |= CPT_OP_AUTH_GENERATE;
2705 CPT_LOG_DP_ERR("Unknown auth operation");
2709 switch (a_form->algo) {
2710 case RTE_CRYPTO_AUTH_SHA1_HMAC:
2712 case RTE_CRYPTO_AUTH_SHA1:
2713 auth_type = SHA1_TYPE;
2715 case RTE_CRYPTO_AUTH_SHA256_HMAC:
2716 case RTE_CRYPTO_AUTH_SHA256:
2717 auth_type = SHA2_SHA256;
2719 case RTE_CRYPTO_AUTH_SHA512_HMAC:
2720 case RTE_CRYPTO_AUTH_SHA512:
2721 auth_type = SHA2_SHA512;
2723 case RTE_CRYPTO_AUTH_AES_GMAC:
2724 auth_type = GMAC_TYPE;
2727 case RTE_CRYPTO_AUTH_SHA224_HMAC:
2728 case RTE_CRYPTO_AUTH_SHA224:
2729 auth_type = SHA2_SHA224;
2731 case RTE_CRYPTO_AUTH_SHA384_HMAC:
2732 case RTE_CRYPTO_AUTH_SHA384:
2733 auth_type = SHA2_SHA384;
2735 case RTE_CRYPTO_AUTH_MD5_HMAC:
2736 case RTE_CRYPTO_AUTH_MD5:
2737 auth_type = MD5_TYPE;
2739 case RTE_CRYPTO_AUTH_KASUMI_F9:
2740 auth_type = KASUMI_F9_ECB;
2742 * Indicate that direction needs to be taken out
2747 case RTE_CRYPTO_AUTH_SNOW3G_UIA2:
2748 auth_type = SNOW3G_UIA2;
2751 case RTE_CRYPTO_AUTH_ZUC_EIA3:
2752 auth_type = ZUC_EIA3;
2755 case RTE_CRYPTO_AUTH_NULL:
2759 case RTE_CRYPTO_AUTH_AES_XCBC_MAC:
2760 case RTE_CRYPTO_AUTH_AES_CMAC:
2761 case RTE_CRYPTO_AUTH_AES_CBC_MAC:
2762 CPT_LOG_DP_ERR("Crypto: Unsupported hash algo %u",
2766 CPT_LOG_DP_ERR("Crypto: Undefined Hash algo %u specified",
2771 sess->zsk_flag = zsk_flag;
2772 sess->aes_gcm = aes_gcm;
2773 sess->mac_len = a_form->digest_length;
2774 sess->is_null = is_null;
2776 sess->auth_iv_offset = a_form->iv.offset;
2777 sess->auth_iv_length = a_form->iv.length;
2779 if (unlikely(cpt_fc_auth_set_key(SESS_PRIV(sess), auth_type,
2780 a_form->key.data, a_form->key.length,
2781 a_form->digest_length)))
2787 static __rte_always_inline int
2788 fill_sess_gmac(struct rte_crypto_sym_xform *xform,
2789 struct cpt_sess_misc *sess)
2791 struct rte_crypto_auth_xform *a_form;
2792 cipher_type_t enc_type = 0; /* NULL Cipher type */
2793 auth_type_t auth_type = 0; /* NULL Auth type */
2794 void *ctx = SESS_PRIV(sess);
2796 a_form = &xform->auth;
2798 if (a_form->op == RTE_CRYPTO_AUTH_OP_GENERATE)
2799 sess->cpt_op |= CPT_OP_ENCODE;
2800 else if (a_form->op == RTE_CRYPTO_AUTH_OP_VERIFY)
2801 sess->cpt_op |= CPT_OP_DECODE;
2803 CPT_LOG_DP_ERR("Unknown auth operation");
2807 switch (a_form->algo) {
2808 case RTE_CRYPTO_AUTH_AES_GMAC:
2810 auth_type = GMAC_TYPE;
2813 CPT_LOG_DP_ERR("Crypto: Undefined cipher algo %u specified",
2821 sess->iv_offset = a_form->iv.offset;
2822 sess->iv_length = a_form->iv.length;
2823 sess->mac_len = a_form->digest_length;
2825 if (unlikely(cpt_fc_ciph_set_key(ctx, enc_type, a_form->key.data,
2826 a_form->key.length, NULL)))
2829 if (unlikely(cpt_fc_auth_set_key(ctx, auth_type, NULL, 0,
2830 a_form->digest_length)))
2836 static __rte_always_inline void *
2837 alloc_op_meta(struct rte_mbuf *m_src,
2840 struct rte_mempool *cpt_meta_pool)
2844 #ifndef CPT_ALWAYS_USE_SEPARATE_BUF
2845 if (likely(m_src && (m_src->nb_segs == 1))) {
2849 /* Check if tailroom is sufficient to hold meta data */
2850 tailroom = rte_pktmbuf_tailroom(m_src);
2851 if (likely(tailroom > len + 8)) {
2852 mdata = (uint8_t *)m_src->buf_addr + m_src->buf_len;
2853 mphys = m_src->buf_iova + m_src->buf_len;
2857 buf->dma_addr = mphys;
2859 /* Indicate that this is a mbuf allocated mdata */
2860 mdata = (uint8_t *)((uint64_t)mdata | 1ull);
2865 RTE_SET_USED(m_src);
2868 if (unlikely(rte_mempool_get(cpt_meta_pool, (void **)&mdata) < 0))
2872 buf->dma_addr = rte_mempool_virt2iova(mdata);
2879 * cpt_free_metabuf - free metabuf to mempool.
2880 * @param instance: pointer to instance.
2881 * @param objp: pointer to the metabuf.
2883 static __rte_always_inline void
2884 free_op_meta(void *mdata, struct rte_mempool *cpt_meta_pool)
2886 bool nofree = ((uintptr_t)mdata & 1ull);
2890 rte_mempool_put(cpt_meta_pool, mdata);
2893 static __rte_always_inline uint32_t
2894 prepare_iov_from_pkt(struct rte_mbuf *pkt,
2895 iov_ptr_t *iovec, uint32_t start_offset)
2898 void *seg_data = NULL;
2899 phys_addr_t seg_phys;
2900 int32_t seg_size = 0;
2907 if (!start_offset) {
2908 seg_data = rte_pktmbuf_mtod(pkt, void *);
2909 seg_phys = rte_pktmbuf_iova(pkt);
2910 seg_size = pkt->data_len;
2912 while (start_offset >= pkt->data_len) {
2913 start_offset -= pkt->data_len;
2917 seg_data = rte_pktmbuf_mtod_offset(pkt, void *, start_offset);
2918 seg_phys = rte_pktmbuf_iova_offset(pkt, start_offset);
2919 seg_size = pkt->data_len - start_offset;
2925 iovec->bufs[index].vaddr = seg_data;
2926 iovec->bufs[index].dma_addr = seg_phys;
2927 iovec->bufs[index].size = seg_size;
2931 while (unlikely(pkt != NULL)) {
2932 seg_data = rte_pktmbuf_mtod(pkt, void *);
2933 seg_phys = rte_pktmbuf_iova(pkt);
2934 seg_size = pkt->data_len;
2938 iovec->bufs[index].vaddr = seg_data;
2939 iovec->bufs[index].dma_addr = seg_phys;
2940 iovec->bufs[index].size = seg_size;
2947 iovec->buf_cnt = index;
2951 static __rte_always_inline uint32_t
2952 prepare_iov_from_pkt_inplace(struct rte_mbuf *pkt,
2957 void *seg_data = NULL;
2958 phys_addr_t seg_phys;
2959 uint32_t seg_size = 0;
2962 seg_data = rte_pktmbuf_mtod(pkt, void *);
2963 seg_phys = rte_pktmbuf_iova(pkt);
2964 seg_size = pkt->data_len;
2967 if (likely(!pkt->next)) {
2968 uint32_t headroom, tailroom;
2970 *flags |= SINGLE_BUF_INPLACE;
2971 headroom = rte_pktmbuf_headroom(pkt);
2972 tailroom = rte_pktmbuf_tailroom(pkt);
2973 if (likely((headroom >= 24) &&
2975 /* In 83XX this is prerequivisit for Direct mode */
2976 *flags |= SINGLE_BUF_HEADTAILROOM;
2978 param->bufs[0].vaddr = seg_data;
2979 param->bufs[0].dma_addr = seg_phys;
2980 param->bufs[0].size = seg_size;
2983 iovec = param->src_iov;
2984 iovec->bufs[index].vaddr = seg_data;
2985 iovec->bufs[index].dma_addr = seg_phys;
2986 iovec->bufs[index].size = seg_size;
2990 while (unlikely(pkt != NULL)) {
2991 seg_data = rte_pktmbuf_mtod(pkt, void *);
2992 seg_phys = rte_pktmbuf_iova(pkt);
2993 seg_size = pkt->data_len;
2998 iovec->bufs[index].vaddr = seg_data;
2999 iovec->bufs[index].dma_addr = seg_phys;
3000 iovec->bufs[index].size = seg_size;
3007 iovec->buf_cnt = index;
3011 static __rte_always_inline int
3012 fill_fc_params(struct rte_crypto_op *cop,
3013 struct cpt_sess_misc *sess_misc,
3014 struct cpt_qp_meta_info *m_info,
3019 struct rte_crypto_sym_op *sym_op = cop->sym;
3020 struct cpt_ctx *ctx = SESS_PRIV(sess_misc);
3023 uint32_t mc_hash_off;
3025 uint64_t d_offs, d_lens;
3026 struct rte_mbuf *m_src, *m_dst;
3027 uint8_t cpt_op = sess_misc->cpt_op;
3028 #ifdef CPT_ALWAYS_USE_SG_MODE
3029 uint8_t inplace = 0;
3031 uint8_t inplace = 1;
3033 fc_params_t fc_params;
3034 char src[SRC_IOV_SIZE];
3035 char dst[SRC_IOV_SIZE];
3039 if (likely(sess_misc->iv_length)) {
3040 flags |= VALID_IV_BUF;
3041 fc_params.iv_buf = rte_crypto_op_ctod_offset(cop,
3042 uint8_t *, sess_misc->iv_offset);
3043 if (sess_misc->aes_ctr &&
3044 unlikely(sess_misc->iv_length != 16)) {
3045 memcpy((uint8_t *)iv_buf,
3046 rte_crypto_op_ctod_offset(cop,
3047 uint8_t *, sess_misc->iv_offset), 12);
3048 iv_buf[3] = rte_cpu_to_be_32(0x1);
3049 fc_params.iv_buf = iv_buf;
3053 if (sess_misc->zsk_flag) {
3054 fc_params.auth_iv_buf = rte_crypto_op_ctod_offset(cop,
3056 sess_misc->auth_iv_offset);
3057 if (sess_misc->zsk_flag != ZS_EA)
3060 m_src = sym_op->m_src;
3061 m_dst = sym_op->m_dst;
3063 if (sess_misc->aes_gcm || sess_misc->chacha_poly) {
3068 d_offs = sym_op->aead.data.offset;
3069 d_lens = sym_op->aead.data.length;
3070 mc_hash_off = sym_op->aead.data.offset +
3071 sym_op->aead.data.length;
3073 aad_data = sym_op->aead.aad.data;
3074 aad_len = sess_misc->aad_length;
3075 if (likely((aad_data + aad_len) ==
3076 rte_pktmbuf_mtod_offset(m_src,
3078 sym_op->aead.data.offset))) {
3079 d_offs = (d_offs - aad_len) | (d_offs << 16);
3080 d_lens = (d_lens + aad_len) | (d_lens << 32);
3082 fc_params.aad_buf.vaddr = sym_op->aead.aad.data;
3083 fc_params.aad_buf.dma_addr = sym_op->aead.aad.phys_addr;
3084 fc_params.aad_buf.size = aad_len;
3085 flags |= VALID_AAD_BUF;
3087 d_offs = d_offs << 16;
3088 d_lens = d_lens << 32;
3091 salt = fc_params.iv_buf;
3092 if (unlikely(*(uint32_t *)salt != sess_misc->salt)) {
3093 cpt_fc_salt_update(SESS_PRIV(sess_misc), salt);
3094 sess_misc->salt = *(uint32_t *)salt;
3096 fc_params.iv_buf = salt + 4;
3097 if (likely(sess_misc->mac_len)) {
3098 struct rte_mbuf *m = (cpt_op & CPT_OP_ENCODE) ? m_dst :
3104 /* hmac immediately following data is best case */
3105 if (unlikely(rte_pktmbuf_mtod(m, uint8_t *) +
3107 (uint8_t *)sym_op->aead.digest.data)) {
3108 flags |= VALID_MAC_BUF;
3109 fc_params.mac_buf.size = sess_misc->mac_len;
3110 fc_params.mac_buf.vaddr =
3111 sym_op->aead.digest.data;
3112 fc_params.mac_buf.dma_addr =
3113 sym_op->aead.digest.phys_addr;
3118 d_offs = sym_op->cipher.data.offset;
3119 d_lens = sym_op->cipher.data.length;
3120 mc_hash_off = sym_op->cipher.data.offset +
3121 sym_op->cipher.data.length;
3122 d_offs = (d_offs << 16) | sym_op->auth.data.offset;
3123 d_lens = (d_lens << 32) | sym_op->auth.data.length;
3125 if (mc_hash_off < (sym_op->auth.data.offset +
3126 sym_op->auth.data.length)){
3127 mc_hash_off = (sym_op->auth.data.offset +
3128 sym_op->auth.data.length);
3130 /* for gmac, salt should be updated like in gcm */
3131 if (unlikely(sess_misc->is_gmac)) {
3133 salt = fc_params.iv_buf;
3134 if (unlikely(*(uint32_t *)salt != sess_misc->salt)) {
3135 cpt_fc_salt_update(SESS_PRIV(sess_misc), salt);
3136 sess_misc->salt = *(uint32_t *)salt;
3138 fc_params.iv_buf = salt + 4;
3140 if (likely(sess_misc->mac_len)) {
3143 m = (cpt_op & CPT_OP_ENCODE) ? m_dst : m_src;
3147 /* hmac immediately following data is best case */
3148 if (!ctx->dec_auth && !ctx->auth_enc &&
3149 (unlikely(rte_pktmbuf_mtod(m, uint8_t *) +
3151 (uint8_t *)sym_op->auth.digest.data))) {
3152 flags |= VALID_MAC_BUF;
3153 fc_params.mac_buf.size =
3155 fc_params.mac_buf.vaddr =
3156 sym_op->auth.digest.data;
3157 fc_params.mac_buf.dma_addr =
3158 sym_op->auth.digest.phys_addr;
3163 fc_params.ctx_buf.vaddr = SESS_PRIV(sess_misc);
3164 fc_params.ctx_buf.dma_addr = sess_misc->ctx_dma_addr;
3166 if (!ctx->dec_auth &&
3167 unlikely(sess_misc->is_null ||
3168 sess_misc->cpt_op == CPT_OP_DECODE))
3171 if (likely(!m_dst && inplace)) {
3172 /* Case of single buffer without AAD buf or
3173 * separate mac buf in place and
3176 fc_params.dst_iov = fc_params.src_iov = (void *)src;
3178 if (unlikely(prepare_iov_from_pkt_inplace(m_src,
3181 CPT_LOG_DP_ERR("Prepare inplace src iov failed");
3187 /* Out of place processing */
3188 fc_params.src_iov = (void *)src;
3189 fc_params.dst_iov = (void *)dst;
3191 /* Store SG I/O in the api for reuse */
3192 if (prepare_iov_from_pkt(m_src, fc_params.src_iov, 0)) {
3193 CPT_LOG_DP_ERR("Prepare src iov failed");
3198 if (unlikely(m_dst != NULL)) {
3201 /* Try to make room as much as src has */
3202 pkt_len = rte_pktmbuf_pkt_len(m_dst);
3204 if (unlikely(pkt_len < rte_pktmbuf_pkt_len(m_src))) {
3205 pkt_len = rte_pktmbuf_pkt_len(m_src) - pkt_len;
3206 if (!rte_pktmbuf_append(m_dst, pkt_len)) {
3207 CPT_LOG_DP_ERR("Not enough space in "
3216 if (prepare_iov_from_pkt(m_dst, fc_params.dst_iov, 0)) {
3217 CPT_LOG_DP_ERR("Prepare dst iov failed for "
3223 fc_params.dst_iov = (void *)src;
3227 if (likely(flags & SINGLE_BUF_HEADTAILROOM))
3228 mdata = alloc_op_meta(m_src, &fc_params.meta_buf,
3229 m_info->lb_mlen, m_info->pool);
3231 mdata = alloc_op_meta(NULL, &fc_params.meta_buf,
3232 m_info->sg_mlen, m_info->pool);
3234 if (unlikely(mdata == NULL)) {
3235 CPT_LOG_DP_ERR("Error allocating meta buffer for request");
3240 op = (uintptr_t *)((uintptr_t)mdata & (uintptr_t)~1ull);
3241 op[0] = (uintptr_t)mdata;
3242 op[1] = (uintptr_t)cop;
3243 op[2] = op[3] = 0; /* Used to indicate auth verify */
3244 space += 4 * sizeof(uint64_t);
3246 fc_params.meta_buf.vaddr = (uint8_t *)op + space;
3247 fc_params.meta_buf.dma_addr += space;
3248 fc_params.meta_buf.size -= space;
3250 /* Finally prepare the instruction */
3251 if (cpt_op & CPT_OP_ENCODE)
3252 *prep_req = cpt_fc_enc_hmac_prep(flags, d_offs, d_lens,
3255 *prep_req = cpt_fc_dec_hmac_prep(flags, d_offs, d_lens,
3258 if (unlikely(*prep_req == NULL)) {
3259 CPT_LOG_DP_ERR("Preparing request failed due to bad input arg");
3261 goto free_mdata_and_exit;
3268 free_mdata_and_exit:
3269 free_op_meta(mdata, m_info->pool);
3274 static __rte_always_inline void
3275 compl_auth_verify(struct rte_crypto_op *op,
3280 struct rte_crypto_sym_op *sym_op = op->sym;
3282 if (sym_op->auth.digest.data)
3283 mac = sym_op->auth.digest.data;
3285 mac = rte_pktmbuf_mtod_offset(sym_op->m_src,
3287 sym_op->auth.data.length +
3288 sym_op->auth.data.offset);
3290 op->status = RTE_CRYPTO_OP_STATUS_ERROR;
3294 if (memcmp(mac, gen_mac, mac_len))
3295 op->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
3297 op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
3300 static __rte_always_inline void
3301 find_kasumif9_direction_and_length(uint8_t *src,
3302 uint32_t counter_num_bytes,
3303 uint32_t *addr_length_in_bits,
3304 uint8_t *addr_direction)
3309 while (!found && counter_num_bytes > 0) {
3310 counter_num_bytes--;
3311 if (src[counter_num_bytes] == 0x00)
3313 pos = rte_bsf32(src[counter_num_bytes]);
3315 if (likely(counter_num_bytes > 0)) {
3316 last_byte = src[counter_num_bytes - 1];
3317 *addr_direction = last_byte & 0x1;
3318 *addr_length_in_bits = counter_num_bytes * 8
3322 last_byte = src[counter_num_bytes];
3323 *addr_direction = (last_byte >> (pos + 1)) & 0x1;
3324 *addr_length_in_bits = counter_num_bytes * 8
3332 * This handles all auth only except AES_GMAC
3334 static __rte_always_inline int
3335 fill_digest_params(struct rte_crypto_op *cop,
3336 struct cpt_sess_misc *sess,
3337 struct cpt_qp_meta_info *m_info,
3342 struct rte_crypto_sym_op *sym_op = cop->sym;
3346 uint32_t auth_range_off;
3348 uint64_t d_offs = 0, d_lens;
3349 struct rte_mbuf *m_src, *m_dst;
3350 uint16_t auth_op = sess->cpt_op & CPT_OP_AUTH_MASK;
3351 uint16_t mac_len = sess->mac_len;
3353 char src[SRC_IOV_SIZE];
3357 memset(¶ms, 0, sizeof(fc_params_t));
3359 m_src = sym_op->m_src;
3361 /* For just digest lets force mempool alloc */
3362 mdata = alloc_op_meta(NULL, ¶ms.meta_buf, m_info->sg_mlen,
3364 if (mdata == NULL) {
3369 mphys = params.meta_buf.dma_addr;
3372 op[0] = (uintptr_t)mdata;
3373 op[1] = (uintptr_t)cop;
3374 op[2] = op[3] = 0; /* Used to indicate auth verify */
3375 space += 4 * sizeof(uint64_t);
3377 auth_range_off = sym_op->auth.data.offset;
3379 flags = VALID_MAC_BUF;
3380 params.src_iov = (void *)src;
3381 if (unlikely(sess->zsk_flag)) {
3383 * Since for Zuc, Kasumi, Snow3g offsets are in bits
3384 * we will send pass through even for auth only case,
3387 d_offs = auth_range_off;
3389 params.auth_iv_buf = rte_crypto_op_ctod_offset(cop,
3390 uint8_t *, sess->auth_iv_offset);
3391 if (sess->zsk_flag == K_F9) {
3392 uint32_t length_in_bits, num_bytes;
3393 uint8_t *src, direction = 0;
3395 memcpy(iv_buf, rte_pktmbuf_mtod(cop->sym->m_src,
3398 * This is kasumi f9, take direction from
3401 length_in_bits = cop->sym->auth.data.length;
3402 num_bytes = (length_in_bits >> 3);
3403 src = rte_pktmbuf_mtod(cop->sym->m_src, uint8_t *);
3404 find_kasumif9_direction_and_length(src,
3408 length_in_bits -= 64;
3409 cop->sym->auth.data.offset += 64;
3410 d_offs = cop->sym->auth.data.offset;
3411 auth_range_off = d_offs / 8;
3412 cop->sym->auth.data.length = length_in_bits;
3414 /* Store it at end of auth iv */
3415 iv_buf[8] = direction;
3416 params.auth_iv_buf = iv_buf;
3420 d_lens = sym_op->auth.data.length;
3422 params.ctx_buf.vaddr = SESS_PRIV(sess);
3423 params.ctx_buf.dma_addr = sess->ctx_dma_addr;
3425 if (auth_op == CPT_OP_AUTH_GENERATE) {
3426 if (sym_op->auth.digest.data) {
3428 * Digest to be generated
3429 * in separate buffer
3431 params.mac_buf.size =
3433 params.mac_buf.vaddr =
3434 sym_op->auth.digest.data;
3435 params.mac_buf.dma_addr =
3436 sym_op->auth.digest.phys_addr;
3438 uint32_t off = sym_op->auth.data.offset +
3439 sym_op->auth.data.length;
3440 int32_t dlen, space;
3442 m_dst = sym_op->m_dst ?
3443 sym_op->m_dst : sym_op->m_src;
3444 dlen = rte_pktmbuf_pkt_len(m_dst);
3446 space = off + mac_len - dlen;
3448 if (!rte_pktmbuf_append(m_dst, space)) {
3449 CPT_LOG_DP_ERR("Failed to extend "
3450 "mbuf by %uB", space);
3452 goto free_mdata_and_exit;
3455 params.mac_buf.vaddr =
3456 rte_pktmbuf_mtod_offset(m_dst, void *, off);
3457 params.mac_buf.dma_addr =
3458 rte_pktmbuf_iova_offset(m_dst, off);
3459 params.mac_buf.size = mac_len;
3462 /* Need space for storing generated mac */
3463 params.mac_buf.vaddr = (uint8_t *)mdata + space;
3464 params.mac_buf.dma_addr = mphys + space;
3465 params.mac_buf.size = mac_len;
3466 space += RTE_ALIGN_CEIL(mac_len, 8);
3467 op[2] = (uintptr_t)params.mac_buf.vaddr;
3471 params.meta_buf.vaddr = (uint8_t *)mdata + space;
3472 params.meta_buf.dma_addr = mphys + space;
3473 params.meta_buf.size -= space;
3475 /* Out of place processing */
3476 params.src_iov = (void *)src;
3478 /*Store SG I/O in the api for reuse */
3479 if (prepare_iov_from_pkt(m_src, params.src_iov, auth_range_off)) {
3480 CPT_LOG_DP_ERR("Prepare src iov failed");
3482 goto free_mdata_and_exit;
3485 *prep_req = cpt_fc_enc_hmac_prep(flags, d_offs, d_lens, ¶ms, op);
3486 if (unlikely(*prep_req == NULL)) {
3488 goto free_mdata_and_exit;
3495 free_mdata_and_exit:
3496 free_op_meta(mdata, m_info->pool);
3501 #endif /*_CPT_UCODE_H_ */