1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018-2021 NXP
5 #ifndef _DPAAX_IOVA_TABLE_H_
6 #define _DPAAX_IOVA_TABLE_H_
15 #include <sys/types.h>
20 #include <arpa/inet.h>
23 #include <rte_branch_prediction.h>
24 #include <rte_memory.h>
25 #include <rte_malloc.h>
27 struct dpaax_iovat_element {
28 phys_addr_t start; /**< Start address of block of physical pages */
29 size_t len; /**< Difference of end-start for quick access */
30 uint64_t *pages; /**< VA for each physical page in this block */
33 struct dpaax_iova_table {
34 unsigned int count; /**< No. of blocks of contiguous physical pages */
35 struct dpaax_iovat_element entries[0];
38 /* Pointer to the table, which is common for DPAA/DPAA2 and only a single
39 * instance is required across net/crypto/event drivers. This table is
40 * populated iff devices are found on the bus.
42 extern struct dpaax_iova_table *dpaax_iova_table_p;
44 /* Device tree file for memory layout is named 'memory@<addr>' where the 'addr'
45 * is SoC dependent, or even Uboot fixup dependent.
47 #define MEM_NODE_PATH_GLOB "/proc/device-tree/memory[@0-9]*/reg"
48 /* For Virtual Machines memory node is at different path (below) */
49 #define MEM_NODE_PATH_GLOB_VM "/proc/device-tree/memory/reg"
50 /* Device file should be multiple of 16 bytes, each containing 8 byte of addr
51 * and its length. Assuming max of 5 entries.
53 #define MEM_NODE_FILE_LEN ((16 * 5) + 1)
55 /* Table is made up of DPAAX_MEM_SPLIT elements for each contiguous zone. This
56 * helps avoid separate handling for cases where more than one size of hugepage
59 #define DPAAX_MEM_SPLIT (1<<21)
60 #define DPAAX_MEM_SPLIT_MASK ~(DPAAX_MEM_SPLIT - 1) /**< Floor aligned */
61 #define DPAAX_MEM_SPLIT_MASK_OFF (DPAAX_MEM_SPLIT - 1) /**< Offset */
65 int dpaax_iova_table_populate(void);
67 void dpaax_iova_table_depopulate(void);
69 int dpaax_iova_table_update(phys_addr_t paddr, void *vaddr, size_t length);
71 void dpaax_iova_table_dump(void);
73 static inline void *dpaax_iova_table_get_va(phys_addr_t paddr) __rte_hot;
76 dpaax_iova_table_get_va(phys_addr_t paddr) {
77 unsigned int i = 0, index;
79 phys_addr_t paddr_align = paddr & DPAAX_MEM_SPLIT_MASK;
80 size_t offset = paddr & DPAAX_MEM_SPLIT_MASK_OFF;
81 struct dpaax_iovat_element *entry;
83 if (unlikely(dpaax_iova_table_p == NULL))
86 entry = dpaax_iova_table_p->entries;
89 if (unlikely(i > dpaax_iova_table_p->count))
92 if (paddr_align < entry[i].start) {
93 /* Incorrect paddr; Not in memory range */
97 if (paddr_align > (entry[i].start + entry[i].len)) {
102 /* paddr > entry->start && paddr <= entry->(start+len) */
103 index = (paddr_align - entry[i].start)/DPAAX_MEM_SPLIT;
104 /* paddr is within range, but no vaddr entry ever written
107 if ((void *)(uintptr_t)entry[i].pages[index] == NULL)
110 vaddr = (void *)((uintptr_t)entry[i].pages[index] + offset);
117 #endif /* _DPAAX_IOVA_TABLE_H_ */