1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2019 Mellanox Technologies, Ltd
10 #include <rte_mempool.h>
11 #include <rte_malloc.h>
13 #include "mlx5_common.h"
14 #include "mlx5_common_os.h"
15 #include "mlx5_common_utils.h"
16 #include "mlx5_malloc.h"
17 #include "mlx5_common_pci.h"
19 int mlx5_common_logtype;
21 uint8_t haswell_broadwell_cpu;
23 /* In case this is an x86_64 intel processor to check if
24 * we should use relaxed ordering.
26 #ifdef RTE_ARCH_X86_64
28 * This function returns processor identification and feature information
31 * @param eax, ebx, ecx, edx
32 * Pointers to the registers that will hold cpu information.
34 * The main category of information returned.
36 static inline void mlx5_cpu_id(unsigned int level,
37 unsigned int *eax, unsigned int *ebx,
38 unsigned int *ecx, unsigned int *edx)
41 : "=a" (*eax), "=b" (*ebx), "=c" (*ecx), "=d" (*edx)
46 RTE_INIT_PRIO(mlx5_log_init, LOG)
48 mlx5_common_logtype = rte_log_register("pmd.common.mlx5");
49 if (mlx5_common_logtype >= 0)
50 rte_log_set_level(mlx5_common_logtype, RTE_LOG_NOTICE);
53 static bool mlx5_common_initialized;
56 * One time innitialization routine for run-time dependency on glue library
57 * for multiple PMDs. Each mlx5 PMD that depends on mlx5_common module,
58 * must invoke in its constructor.
61 mlx5_common_init(void)
63 if (mlx5_common_initialized)
66 mlx5_glue_constructor();
67 mlx5_common_pci_init();
68 mlx5_common_initialized = true;
72 * This function is responsible of initializing the variable
73 * haswell_broadwell_cpu by checking if the cpu is intel
74 * and reading the data returned from mlx5_cpu_id().
75 * since haswell and broadwell cpus don't have improved performance
76 * when using relaxed ordering we want to check the cpu type before
77 * before deciding whether to enable RO or not.
78 * if the cpu is haswell or broadwell the variable will be set to 1
79 * otherwise it will be 0.
81 RTE_INIT_PRIO(mlx5_is_haswell_broadwell_cpu, LOG)
83 #ifdef RTE_ARCH_X86_64
84 unsigned int broadwell_models[4] = {0x3d, 0x47, 0x4F, 0x56};
85 unsigned int haswell_models[4] = {0x3c, 0x3f, 0x45, 0x46};
86 unsigned int i, model, family, brand_id, vendor;
87 unsigned int signature_intel_ebx = 0x756e6547;
88 unsigned int extended_model;
95 mlx5_cpu_id(0, &eax, &ebx, &ecx, &edx);
99 haswell_broadwell_cpu = 0;
102 mlx5_cpu_id(1, &eax, &ebx, &ecx, &edx);
103 model = (eax >> 4) & 0x0f;
104 family = (eax >> 8) & 0x0f;
105 brand_id = ebx & 0xff;
106 extended_model = (eax >> 12) & 0xf0;
107 /* Check if the processor is Haswell or Broadwell */
108 if (vendor == signature_intel_ebx) {
110 model += extended_model;
111 if (brand_id == 0 && family == 0x6) {
112 for (i = 0; i < RTE_DIM(broadwell_models); i++)
113 if (model == broadwell_models[i]) {
114 haswell_broadwell_cpu = 1;
117 for (i = 0; i < RTE_DIM(haswell_models); i++)
118 if (model == haswell_models[i]) {
119 haswell_broadwell_cpu = 1;
125 haswell_broadwell_cpu = 0;
129 * Allocate page of door-bells and register it using DevX API.
132 * Pointer to the device context.
135 * Pointer to new page on success, NULL otherwise.
137 static struct mlx5_devx_dbr_page *
138 mlx5_alloc_dbr_page(void *ctx)
140 struct mlx5_devx_dbr_page *page;
142 /* Allocate space for door-bell page and management data. */
143 page = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO,
144 sizeof(struct mlx5_devx_dbr_page),
145 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
147 DRV_LOG(ERR, "cannot allocate dbr page");
150 /* Register allocated memory. */
151 page->umem = mlx5_glue->devx_umem_reg(ctx, page->dbrs,
152 MLX5_DBR_PAGE_SIZE, 0);
154 DRV_LOG(ERR, "cannot umem reg dbr page");
162 * Find the next available door-bell, allocate new page if needed.
165 * Pointer to device context.
167 * Pointer to the head of dbr pages list.
168 * @param [out] dbr_page
169 * Door-bell page containing the page data.
172 * Door-bell address offset on success, a negative error value otherwise.
175 mlx5_get_dbr(void *ctx, struct mlx5_dbr_page_list *head,
176 struct mlx5_devx_dbr_page **dbr_page)
178 struct mlx5_devx_dbr_page *page = NULL;
181 LIST_FOREACH(page, head, next)
182 if (page->dbr_count < MLX5_DBR_PER_PAGE)
184 if (!page) { /* No page with free door-bell exists. */
185 page = mlx5_alloc_dbr_page(ctx);
186 if (!page) /* Failed to allocate new page. */
188 LIST_INSERT_HEAD(head, page, next);
190 /* Loop to find bitmap part with clear bit. */
192 i < MLX5_DBR_BITMAP_SIZE && page->dbr_bitmap[i] == UINT64_MAX;
195 /* Find the first clear bit. */
196 MLX5_ASSERT(i < MLX5_DBR_BITMAP_SIZE);
197 j = rte_bsf64(~page->dbr_bitmap[i]);
198 page->dbr_bitmap[i] |= (UINT64_C(1) << j);
201 return (i * CHAR_BIT * sizeof(uint64_t) + j) * MLX5_DBR_SIZE;
205 * Release a door-bell record.
208 * Pointer to the head of dbr pages list.
209 * @param [in] umem_id
210 * UMEM ID of page containing the door-bell record to release.
212 * Offset of door-bell record in page.
215 * 0 on success, a negative error value otherwise.
218 mlx5_release_dbr(struct mlx5_dbr_page_list *head, uint32_t umem_id,
221 struct mlx5_devx_dbr_page *page = NULL;
224 LIST_FOREACH(page, head, next)
225 /* Find the page this address belongs to. */
226 if (mlx5_os_get_umem_id(page->umem) == umem_id)
231 if (!page->dbr_count) {
232 /* Page not used, free it and remove from list. */
233 LIST_REMOVE(page, next);
235 ret = -mlx5_glue->devx_umem_dereg(page->umem);
238 /* Mark in bitmap that this door-bell is not in use. */
239 offset /= MLX5_DBR_SIZE;
243 page->dbr_bitmap[i] &= ~(UINT64_C(1) << j);
249 * Allocate the User Access Region with DevX on specified device.
252 * Infiniband device context to perform allocation on.
253 * @param [in] mapping
254 * MLX5DV_UAR_ALLOC_TYPE_BF - allocate as cached memory with write-combining
255 * attributes (if supported by the host), the
256 * writes to the UAR registers must be followed
257 * by write memory barrier.
258 * MLX5DV_UAR_ALLOC_TYPE_NC - allocate as non-cached nenory, all writes are
259 * promoted to the registers immediately, no
260 * memory barriers needed.
261 * mapping < 0 - the first attempt is performed with MLX5DV_UAR_ALLOC_TYPE_BF,
262 * if this fails the next attempt with MLX5DV_UAR_ALLOC_TYPE_NC
263 * is performed. The drivers specifying negative values should
264 * always provide the write memory barrier operation after UAR
266 * If there is no definitions for the MLX5DV_UAR_ALLOC_TYPE_xx (older rdma
267 * library headers), the caller can specify 0.
270 * UAR object pointer on success, NULL otherwise and rte_errno is set.
273 mlx5_devx_alloc_uar(void *ctx, int mapping)
276 uint32_t retry, uar_mapping;
279 for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
280 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
281 /* Control the mapping type according to the settings. */
282 uar_mapping = (mapping < 0) ?
283 MLX5DV_UAR_ALLOC_TYPE_NC : mapping;
286 * It seems we have no way to control the memory mapping type
287 * for the UAR, the default "Write-Combining" type is supposed.
290 RTE_SET_USED(mapping);
292 uar = mlx5_glue->devx_alloc_uar(ctx, uar_mapping);
293 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
296 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
298 * In some environments like virtual machine the
299 * Write Combining mapped might be not supported and
300 * UAR allocation fails. We tried "Non-Cached" mapping
303 DRV_LOG(WARNING, "Failed to allocate DevX UAR (BF)");
304 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
305 uar = mlx5_glue->devx_alloc_uar(ctx, uar_mapping);
308 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_NC) {
310 * If Verbs/kernel does not support "Non-Cached"
311 * try the "Write-Combining".
313 DRV_LOG(WARNING, "Failed to allocate DevX UAR (NC)");
314 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_BF;
315 uar = mlx5_glue->devx_alloc_uar(ctx, uar_mapping);
319 DRV_LOG(ERR, "Failed to allocate DevX UAR (BF/NC)");
323 base_addr = mlx5_os_get_devx_uar_base_addr(uar);
327 * The UARs are allocated by rdma_core within the
328 * IB device context, on context closure all UARs
329 * will be freed, should be no memory/object leakage.
331 DRV_LOG(WARNING, "Retrying to allocate DevX UAR");
334 /* Check whether we finally succeeded with valid UAR allocation. */
336 DRV_LOG(ERR, "Failed to allocate DevX UAR (NULL base)");
340 * Return void * instead of struct mlx5dv_devx_uar *
341 * is for compatibility with older rdma-core library headers.