1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2019 Mellanox Technologies, Ltd
10 #include <rte_mempool.h>
11 #include <rte_class.h>
12 #include <rte_malloc.h>
13 #include <rte_eal_paging.h>
15 #include "mlx5_common.h"
16 #include "mlx5_common_os.h"
17 #include "mlx5_common_mp.h"
18 #include "mlx5_common_log.h"
19 #include "mlx5_common_defs.h"
20 #include "mlx5_common_private.h"
22 uint8_t haswell_broadwell_cpu;
24 /* Driver type key for new device global syntax. */
25 #define MLX5_DRIVER_KEY "driver"
27 /* Enable extending memsegs when creating a MR. */
28 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
30 /* Device parameter to configure implicit registration of mempool memory. */
31 #define MLX5_MR_MEMPOOL_REG_EN "mr_mempool_reg_en"
33 /* The default memory allocator used in PMD. */
34 #define MLX5_SYS_MEM_EN "sys_mem_en"
37 * Device parameter to force doorbell register mapping
38 * to non-cahed region eliminating the extra write memory barrier.
40 #define MLX5_TX_DB_NC "tx_db_nc"
42 /* In case this is an x86_64 intel processor to check if
43 * we should use relaxed ordering.
45 #ifdef RTE_ARCH_X86_64
47 * This function returns processor identification and feature information
50 * @param eax, ebx, ecx, edx
51 * Pointers to the registers that will hold cpu information.
53 * The main category of information returned.
55 static inline void mlx5_cpu_id(unsigned int level,
56 unsigned int *eax, unsigned int *ebx,
57 unsigned int *ecx, unsigned int *edx)
60 : "=a" (*eax), "=b" (*ebx), "=c" (*ecx), "=d" (*edx)
65 RTE_LOG_REGISTER_DEFAULT(mlx5_common_logtype, NOTICE)
67 /* Head of list of drivers. */
68 static TAILQ_HEAD(mlx5_drivers, mlx5_class_driver) drivers_list =
69 TAILQ_HEAD_INITIALIZER(drivers_list);
71 /* Head of devices. */
72 static TAILQ_HEAD(mlx5_devices, mlx5_common_device) devices_list =
73 TAILQ_HEAD_INITIALIZER(devices_list);
74 static pthread_mutex_t devices_list_lock;
78 unsigned int drv_class;
80 { .name = "vdpa", .drv_class = MLX5_CLASS_VDPA },
81 { .name = "eth", .drv_class = MLX5_CLASS_ETH },
82 /* Keep class "net" for backward compatibility. */
83 { .name = "net", .drv_class = MLX5_CLASS_ETH },
84 { .name = "regex", .drv_class = MLX5_CLASS_REGEX },
85 { .name = "compress", .drv_class = MLX5_CLASS_COMPRESS },
86 { .name = "crypto", .drv_class = MLX5_CLASS_CRYPTO },
90 class_name_to_value(const char *class_name)
94 for (i = 0; i < RTE_DIM(mlx5_classes); i++) {
95 if (strcmp(class_name, mlx5_classes[i].name) == 0)
96 return mlx5_classes[i].drv_class;
101 static struct mlx5_class_driver *
102 driver_get(uint32_t class)
104 struct mlx5_class_driver *driver;
106 TAILQ_FOREACH(driver, &drivers_list, next) {
107 if ((uint32_t)driver->drv_class == class)
114 mlx5_kvargs_process(struct mlx5_kvargs_ctrl *mkvlist, const char *const keys[],
115 arg_handler_t handler, void *opaque_arg)
117 const struct rte_kvargs_pair *pair;
120 MLX5_ASSERT(mkvlist && mkvlist->kvlist);
121 /* Process parameters. */
122 for (i = 0; i < mkvlist->kvlist->count; i++) {
123 pair = &mkvlist->kvlist->pairs[i];
124 for (j = 0; keys[j] != NULL; ++j) {
125 if (strcmp(pair->key, keys[j]) != 0)
127 if ((*handler)(pair->key, pair->value, opaque_arg) < 0)
129 mkvlist->is_used[i] = true;
137 * Prepare a mlx5 kvargs control.
139 * @param[out] mkvlist
140 * Pointer to mlx5 kvargs control.
142 * The input string containing the key/value associations.
145 * 0 on success, a negative errno value otherwise and rte_errno is set.
148 mlx5_kvargs_prepare(struct mlx5_kvargs_ctrl *mkvlist,
149 const struct rte_devargs *devargs)
151 struct rte_kvargs *kvlist;
156 kvlist = rte_kvargs_parse(devargs->args, NULL);
157 if (kvlist == NULL) {
162 * rte_kvargs_parse enable key without value, in mlx5 PMDs we disable
165 for (i = 0; i < kvlist->count; i++) {
166 const struct rte_kvargs_pair *pair = &kvlist->pairs[i];
167 if (pair->value == NULL || *(pair->value) == '\0') {
168 DRV_LOG(ERR, "Key %s is missing value.", pair->key);
169 rte_kvargs_free(kvlist);
174 /* Makes sure all devargs used array is false. */
175 memset(mkvlist, 0, sizeof(*mkvlist));
176 mkvlist->kvlist = kvlist;
177 DRV_LOG(DEBUG, "Parse successfully %u devargs.",
178 mkvlist->kvlist->count);
183 * Release a mlx5 kvargs control.
185 * @param[out] mkvlist
186 * Pointer to mlx5 kvargs control.
189 mlx5_kvargs_release(struct mlx5_kvargs_ctrl *mkvlist)
193 rte_kvargs_free(mkvlist->kvlist);
194 memset(mkvlist, 0, sizeof(*mkvlist));
198 * Validate device arguments list.
199 * It report about the first unknown parameter.
202 * Pointer to mlx5 kvargs control.
205 * 0 on success, a negative errno value otherwise and rte_errno is set.
208 mlx5_kvargs_validate(struct mlx5_kvargs_ctrl *mkvlist)
212 /* Secondary process should not handle devargs. */
213 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
217 for (i = 0; i < mkvlist->kvlist->count; i++) {
218 if (mkvlist->is_used[i] == 0) {
219 DRV_LOG(ERR, "Key \"%s\" "
220 "is unknown for the provided classes.",
221 mkvlist->kvlist->pairs[i].key);
230 * Verify and store value for devargs.
233 * Key argument to verify.
235 * Value associated with key.
240 * 0 on success, a negative errno value otherwise and rte_errno is set.
243 mlx5_common_args_check_handler(const char *key, const char *val, void *opaque)
245 struct mlx5_common_dev_config *config = opaque;
248 if (strcmp(MLX5_DRIVER_KEY, key) == 0 ||
249 strcmp(RTE_DEVARGS_KEY_CLASS, key) == 0)
252 tmp = strtol(val, NULL, 0);
255 DRV_LOG(WARNING, "%s: \"%s\" is an invalid integer.", key, val);
258 if (strcmp(key, MLX5_TX_DB_NC) == 0) {
259 if (tmp != MLX5_TXDB_CACHED &&
260 tmp != MLX5_TXDB_NCACHED &&
261 tmp != MLX5_TXDB_HEURISTIC) {
262 DRV_LOG(ERR, "Invalid Tx doorbell mapping parameter.");
267 } else if (strcmp(key, MLX5_MR_EXT_MEMSEG_EN) == 0) {
268 config->mr_ext_memseg_en = !!tmp;
269 } else if (strcmp(key, MLX5_MR_MEMPOOL_REG_EN) == 0) {
270 config->mr_mempool_reg_en = !!tmp;
271 } else if (strcmp(key, MLX5_SYS_MEM_EN) == 0) {
272 config->sys_mem_en = !!tmp;
278 * Parse common device parameters.
281 * Device arguments structure.
283 * Pointer to device configuration structure.
286 * 0 on success, a negative errno value otherwise and rte_errno is set.
289 mlx5_common_config_get(struct mlx5_kvargs_ctrl *mkvlist,
290 struct mlx5_common_dev_config *config)
292 const char **params = (const char *[]){
293 RTE_DEVARGS_KEY_CLASS,
296 MLX5_MR_EXT_MEMSEG_EN,
298 MLX5_MR_MEMPOOL_REG_EN,
306 config->mr_ext_memseg_en = 1;
307 config->mr_mempool_reg_en = 1;
308 config->sys_mem_en = 0;
309 config->dbnc = MLX5_ARG_UNSET;
310 /* Process common parameters. */
311 ret = mlx5_kvargs_process(mkvlist, params,
312 mlx5_common_args_check_handler, config);
317 DRV_LOG(DEBUG, "mr_ext_memseg_en is %u.", config->mr_ext_memseg_en);
318 DRV_LOG(DEBUG, "mr_mempool_reg_en is %u.", config->mr_mempool_reg_en);
319 DRV_LOG(DEBUG, "sys_mem_en is %u.", config->sys_mem_en);
320 DRV_LOG(DEBUG, "Tx doorbell mapping parameter is %d.", config->dbnc);
325 devargs_class_handler(__rte_unused const char *key,
326 const char *class_names, void *opaque)
335 scratch = strdup(class_names);
336 if (scratch == NULL) {
340 found = strtok_r(scratch, ":", &refstr);
345 /* Extract each individual class name. Multiple
346 * classes can be supplied as class=net:regex:foo:bar.
348 class_val = class_name_to_value(found);
349 /* Check if its a valid class. */
355 found = strtok_r(NULL, ":", &refstr);
356 } while (found != NULL);
360 DRV_LOG(ERR, "Invalid mlx5 class options: %s.\n", class_names);
365 parse_class_options(const struct rte_devargs *devargs,
366 struct mlx5_kvargs_ctrl *mkvlist)
372 if (devargs->cls != NULL && devargs->cls->name != NULL)
373 /* Global syntax, only one class type. */
374 return class_name_to_value(devargs->cls->name);
375 /* Legacy devargs support multiple classes. */
376 rte_kvargs_process(mkvlist->kvlist, RTE_DEVARGS_KEY_CLASS,
377 devargs_class_handler, &ret);
381 static const unsigned int mlx5_class_invalid_combinations[] = {
382 MLX5_CLASS_ETH | MLX5_CLASS_VDPA,
383 /* New class combination should be added here. */
387 is_valid_class_combination(uint32_t user_classes)
391 /* Verify if user specified unsupported combination. */
392 for (i = 0; i < RTE_DIM(mlx5_class_invalid_combinations); i++) {
393 if ((mlx5_class_invalid_combinations[i] & user_classes) ==
394 mlx5_class_invalid_combinations[i])
397 /* Not found any invalid class combination. */
402 mlx5_bus_match(const struct mlx5_class_driver *drv,
403 const struct rte_device *dev)
405 if (mlx5_dev_is_pci(dev))
406 return mlx5_dev_pci_match(drv, dev);
410 static struct mlx5_common_device *
411 to_mlx5_device(const struct rte_device *rte_dev)
413 struct mlx5_common_device *cdev;
415 TAILQ_FOREACH(cdev, &devices_list, next) {
416 if (rte_dev == cdev->dev)
423 mlx5_dev_to_pci_str(const struct rte_device *dev, char *addr, size_t size)
425 struct rte_pci_addr pci_addr = { 0 };
428 if (mlx5_dev_is_pci(dev)) {
429 /* Input might be <BDF>, format PCI address to <DBDF>. */
430 ret = rte_pci_addr_parse(dev->name, &pci_addr);
433 rte_pci_device_name(&pci_addr, addr, size);
436 #ifdef RTE_EXEC_ENV_LINUX
437 return mlx5_auxiliary_get_pci_str(RTE_DEV_TO_AUXILIARY_CONST(dev),
446 * Register the mempool for the protection domain.
449 * Pointer to the mlx5 common device.
451 * Mempool being registered.
454 * 0 on success, (-1) on failure and rte_errno is set.
457 mlx5_dev_mempool_register(struct mlx5_common_device *cdev,
458 struct rte_mempool *mp, bool is_extmem)
460 return mlx5_mr_mempool_register(cdev, mp, is_extmem);
464 * Unregister the mempool from the protection domain.
467 * Pointer to the mlx5 common device.
469 * Mempool being unregistered.
472 mlx5_dev_mempool_unregister(struct mlx5_common_device *cdev,
473 struct rte_mempool *mp)
475 if (mlx5_mr_mempool_unregister(cdev, mp) < 0)
476 DRV_LOG(WARNING, "Failed to unregister mempool %s for PD %p: %s",
477 mp->name, cdev->pd, rte_strerror(rte_errno));
481 * rte_mempool_walk() callback to register mempools for the protection domain.
484 * The mempool being walked.
486 * Pointer to the device shared context.
489 mlx5_dev_mempool_register_cb(struct rte_mempool *mp, void *arg)
491 struct mlx5_common_device *cdev = arg;
494 ret = mlx5_dev_mempool_register(cdev, mp, false);
495 if (ret < 0 && rte_errno != EEXIST)
497 "Failed to register existing mempool %s for PD %p: %s",
498 mp->name, cdev->pd, rte_strerror(rte_errno));
502 * rte_mempool_walk() callback to unregister mempools
503 * from the protection domain.
506 * The mempool being walked.
508 * Pointer to the device shared context.
511 mlx5_dev_mempool_unregister_cb(struct rte_mempool *mp, void *arg)
513 mlx5_dev_mempool_unregister((struct mlx5_common_device *)arg, mp);
517 * Mempool life cycle callback for mlx5 common devices.
520 * Mempool life cycle event.
522 * Associated mempool.
524 * Pointer to a device shared context.
527 mlx5_dev_mempool_event_cb(enum rte_mempool_event event, struct rte_mempool *mp,
530 struct mlx5_common_device *cdev = arg;
533 case RTE_MEMPOOL_EVENT_READY:
534 if (mlx5_dev_mempool_register(cdev, mp, false) < 0)
536 "Failed to register new mempool %s for PD %p: %s",
537 mp->name, cdev->pd, rte_strerror(rte_errno));
539 case RTE_MEMPOOL_EVENT_DESTROY:
540 mlx5_dev_mempool_unregister(cdev, mp);
546 mlx5_dev_mempool_subscribe(struct mlx5_common_device *cdev)
550 if (!cdev->config.mr_mempool_reg_en)
552 rte_rwlock_write_lock(&cdev->mr_scache.mprwlock);
553 if (cdev->mr_scache.mp_cb_registered)
555 /* Callback for this device may be already registered. */
556 ret = rte_mempool_event_callback_register(mlx5_dev_mempool_event_cb,
558 if (ret != 0 && rte_errno != EEXIST)
560 /* Register mempools only once for this device. */
562 rte_mempool_walk(mlx5_dev_mempool_register_cb, cdev);
564 cdev->mr_scache.mp_cb_registered = 1;
566 rte_rwlock_write_unlock(&cdev->mr_scache.mprwlock);
571 mlx5_dev_mempool_unsubscribe(struct mlx5_common_device *cdev)
575 if (!cdev->mr_scache.mp_cb_registered ||
576 !cdev->config.mr_mempool_reg_en)
578 /* Stop watching for mempool events and unregister all mempools. */
579 ret = rte_mempool_event_callback_unregister(mlx5_dev_mempool_event_cb,
582 rte_mempool_walk(mlx5_dev_mempool_unregister_cb, cdev);
586 * Callback for memory event.
596 mlx5_mr_mem_event_cb(enum rte_mem_event event_type, const void *addr,
597 size_t len, void *arg __rte_unused)
599 struct mlx5_common_device *cdev;
601 /* Must be called from the primary process. */
602 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
603 switch (event_type) {
604 case RTE_MEM_EVENT_FREE:
605 pthread_mutex_lock(&devices_list_lock);
606 /* Iterate all the existing mlx5 devices. */
607 TAILQ_FOREACH(cdev, &devices_list, next)
608 mlx5_free_mr_by_addr(&cdev->mr_scache,
609 mlx5_os_get_ctx_device_name
612 pthread_mutex_unlock(&devices_list_lock);
614 case RTE_MEM_EVENT_ALLOC:
621 * Uninitialize all HW global of device context.
624 * Pointer to mlx5 device structure.
627 * 0 on success, a negative errno value otherwise and rte_errno is set.
630 mlx5_dev_hw_global_release(struct mlx5_common_device *cdev)
632 if (cdev->pd != NULL) {
633 claim_zero(mlx5_os_dealloc_pd(cdev->pd));
636 if (cdev->ctx != NULL) {
637 claim_zero(mlx5_glue->close_device(cdev->ctx));
643 * Initialize all HW global of device context.
646 * Pointer to mlx5 device structure.
648 * Chosen classes come from user device arguments.
651 * 0 on success, a negative errno value otherwise and rte_errno is set.
654 mlx5_dev_hw_global_prepare(struct mlx5_common_device *cdev, uint32_t classes)
658 /* Create context device */
659 ret = mlx5_os_open_device(cdev, classes);
662 /* Allocate Protection Domain object and extract its pdn. */
663 ret = mlx5_os_pd_create(cdev);
666 /* All actions taken below are relevant only when DevX is supported */
667 if (cdev->config.devx == 0)
669 /* Query HCA attributes. */
670 ret = mlx5_devx_cmd_query_hca_attr(cdev->ctx, &cdev->config.hca_attr);
672 DRV_LOG(ERR, "Unable to read HCA capabilities.");
678 mlx5_dev_hw_global_release(cdev);
683 mlx5_common_dev_release(struct mlx5_common_device *cdev)
685 pthread_mutex_lock(&devices_list_lock);
686 TAILQ_REMOVE(&devices_list, cdev, next);
687 pthread_mutex_unlock(&devices_list_lock);
688 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
689 if (TAILQ_EMPTY(&devices_list))
690 rte_mem_event_callback_unregister("MLX5_MEM_EVENT_CB",
692 mlx5_dev_mempool_unsubscribe(cdev);
693 mlx5_mr_release_cache(&cdev->mr_scache);
694 mlx5_dev_hw_global_release(cdev);
699 static struct mlx5_common_device *
700 mlx5_common_dev_create(struct rte_device *eal_dev, uint32_t classes,
701 struct mlx5_kvargs_ctrl *mkvlist)
703 struct mlx5_common_device *cdev;
706 cdev = rte_zmalloc("mlx5_common_device", sizeof(*cdev), 0);
708 DRV_LOG(ERR, "Device allocation failure.");
713 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
715 /* Parse device parameters. */
716 ret = mlx5_common_config_get(mkvlist, &cdev->config);
718 DRV_LOG(ERR, "Failed to process device arguments: %s",
719 strerror(rte_errno));
723 mlx5_malloc_mem_select(cdev->config.sys_mem_en);
724 /* Initialize all HW global of device context. */
725 ret = mlx5_dev_hw_global_prepare(cdev, classes);
727 DRV_LOG(ERR, "Failed to initialize device context.");
731 /* Initialize global MR cache resources and update its functions. */
732 ret = mlx5_mr_create_cache(&cdev->mr_scache, eal_dev->numa_node);
734 DRV_LOG(ERR, "Failed to initialize global MR share cache.");
735 mlx5_dev_hw_global_release(cdev);
739 /* Register callback function for global shared MR cache management. */
740 if (TAILQ_EMPTY(&devices_list))
741 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
742 mlx5_mr_mem_event_cb, NULL);
744 pthread_mutex_lock(&devices_list_lock);
745 TAILQ_INSERT_HEAD(&devices_list, cdev, next);
746 pthread_mutex_unlock(&devices_list_lock);
751 * Validate common devargs when probing again.
753 * When common device probing again, it cannot change its configurations.
754 * If user ask non compatible configurations in devargs, it is error.
755 * This function checks the match between:
756 * - Common device configurations requested by probe again devargs.
757 * - Existing common device configurations.
760 * Pointer to mlx5 device structure.
762 * Pointer to mlx5 kvargs control, can be NULL if there is no devargs.
765 * 0 on success, a negative errno value otherwise and rte_errno is set.
768 mlx5_common_probe_again_args_validate(struct mlx5_common_device *cdev,
769 struct mlx5_kvargs_ctrl *mkvlist)
771 struct mlx5_common_dev_config *config;
774 /* Secondary process should not handle devargs. */
775 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
777 /* Probe again doesn't have to generate devargs. */
780 config = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
781 sizeof(struct mlx5_common_dev_config),
782 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
783 if (config == NULL) {
788 * Creates a temporary common configure structure according to new
789 * devargs attached in probing again.
791 ret = mlx5_common_config_get(mkvlist, config);
793 DRV_LOG(ERR, "Failed to process device configure: %s",
794 strerror(rte_errno));
799 * Checks the match between the temporary structure and the existing
800 * common device structure.
802 if (cdev->config.mr_ext_memseg_en ^ config->mr_ext_memseg_en) {
803 DRV_LOG(ERR, "\"mr_ext_memseg_en\" "
804 "configuration mismatch for device %s.",
808 if (cdev->config.mr_mempool_reg_en ^ config->mr_mempool_reg_en) {
809 DRV_LOG(ERR, "\"mr_mempool_reg_en\" "
810 "configuration mismatch for device %s.",
814 if (cdev->config.sys_mem_en ^ config->sys_mem_en) {
816 "\"sys_mem_en\" configuration mismatch for device %s.",
820 if (cdev->config.dbnc ^ config->dbnc) {
821 DRV_LOG(ERR, "\"dbnc\" configuration mismatch for device %s.",
834 drivers_remove(struct mlx5_common_device *cdev, uint32_t enabled_classes)
836 struct mlx5_class_driver *driver;
837 int local_ret = -ENODEV;
841 while (enabled_classes) {
842 driver = driver_get(RTE_BIT64(i));
843 if (driver != NULL) {
844 local_ret = driver->remove(cdev);
846 cdev->classes_loaded &= ~RTE_BIT64(i);
850 enabled_classes &= ~RTE_BIT64(i);
853 if (local_ret != 0 && ret == 0)
859 drivers_probe(struct mlx5_common_device *cdev, uint32_t user_classes,
860 struct mlx5_kvargs_ctrl *mkvlist)
862 struct mlx5_class_driver *driver;
863 uint32_t enabled_classes = 0;
867 TAILQ_FOREACH(driver, &drivers_list, next) {
868 if ((driver->drv_class & user_classes) == 0)
870 if (!mlx5_bus_match(driver, cdev->dev))
872 already_loaded = cdev->classes_loaded & driver->drv_class;
873 if (already_loaded && driver->probe_again == 0) {
874 DRV_LOG(ERR, "Device %s is already probed",
879 ret = driver->probe(cdev, mkvlist);
881 DRV_LOG(ERR, "Failed to load driver %s",
885 enabled_classes |= driver->drv_class;
888 cdev->classes_loaded |= enabled_classes;
893 * Need to remove only drivers which were not probed before this probe
894 * instance, but have already been probed before this failure.
896 enabled_classes &= ~cdev->classes_loaded;
897 drivers_remove(cdev, enabled_classes);
902 mlx5_common_dev_probe(struct rte_device *eal_dev)
904 struct mlx5_common_device *cdev;
905 struct mlx5_kvargs_ctrl mkvlist;
906 struct mlx5_kvargs_ctrl *mkvlist_p = NULL;
907 uint32_t classes = 0;
908 bool new_device = false;
911 DRV_LOG(INFO, "probe device \"%s\".", eal_dev->name);
912 if (eal_dev->devargs != NULL)
913 mkvlist_p = &mkvlist;
914 ret = mlx5_kvargs_prepare(mkvlist_p, eal_dev->devargs);
916 DRV_LOG(ERR, "Unsupported device arguments: %s",
917 eal_dev->devargs->args);
920 ret = parse_class_options(eal_dev->devargs, mkvlist_p);
922 DRV_LOG(ERR, "Unsupported mlx5 class type: %s",
923 eal_dev->devargs->args);
928 /* Default to net class. */
929 classes = MLX5_CLASS_ETH;
931 * MLX5 common driver supports probing again in two scenarios:
932 * - Add new driver under existing common device (regardless of the
933 * driver's own support in probing again).
934 * - Transfer the probing again support of the drivers themselves.
936 * In both scenarios it uses in the existing device. here it looks for
937 * device that match to rte device, if it exists, the request classes
938 * were probed with this device.
940 cdev = to_mlx5_device(eal_dev);
942 /* It isn't probing again, creates a new device. */
943 cdev = mlx5_common_dev_create(eal_dev, classes, mkvlist_p);
950 /* It is probing again, validate common devargs match. */
951 ret = mlx5_common_probe_again_args_validate(cdev, mkvlist_p);
954 "Probe again parameters aren't compatible : %s",
955 strerror(rte_errno));
960 * Validate combination here.
961 * For new device, the classes_loaded field is 0 and it check only
962 * the classes given as user device arguments.
964 ret = is_valid_class_combination(classes | cdev->classes_loaded);
966 DRV_LOG(ERR, "Unsupported mlx5 classes combination.");
969 ret = drivers_probe(cdev, classes, mkvlist_p);
973 * Validate that all devargs have been used, unused key -> unknown Key.
974 * When probe again validate is failed, the added drivers aren't removed
975 * here but when device is released.
977 ret = mlx5_kvargs_validate(mkvlist_p);
980 mlx5_kvargs_release(mkvlist_p);
985 * For new device, classes_loaded is always 0 before
986 * drivers_probe function.
988 if (cdev->classes_loaded)
989 drivers_remove(cdev, cdev->classes_loaded);
990 mlx5_common_dev_release(cdev);
992 mlx5_kvargs_release(mkvlist_p);
997 mlx5_common_dev_remove(struct rte_device *eal_dev)
999 struct mlx5_common_device *cdev;
1002 cdev = to_mlx5_device(eal_dev);
1005 /* Matching device found, cleanup and unload drivers. */
1006 ret = drivers_remove(cdev, cdev->classes_loaded);
1008 mlx5_common_dev_release(cdev);
1013 * Callback to DMA map external memory to a device.
1016 * Pointer to the generic device.
1018 * Starting virtual address of memory to be mapped.
1020 * Starting IOVA address of memory to be mapped.
1022 * Length of memory segment being mapped.
1025 * 0 on success, negative value on error.
1028 mlx5_common_dev_dma_map(struct rte_device *rte_dev, void *addr,
1029 uint64_t iova __rte_unused, size_t len)
1031 struct mlx5_common_device *dev;
1034 dev = to_mlx5_device(rte_dev);
1037 "Unable to find matching mlx5 device to device %s",
1042 mr = mlx5_create_mr_ext(dev->pd, (uintptr_t)addr, len,
1043 SOCKET_ID_ANY, dev->mr_scache.reg_mr_cb);
1045 DRV_LOG(WARNING, "Device %s unable to DMA map", rte_dev->name);
1049 rte_rwlock_write_lock(&dev->mr_scache.rwlock);
1050 LIST_INSERT_HEAD(&dev->mr_scache.mr_list, mr, mr);
1051 /* Insert to the global cache table. */
1052 mlx5_mr_insert_cache(&dev->mr_scache, mr);
1053 rte_rwlock_write_unlock(&dev->mr_scache.rwlock);
1058 * Callback to DMA unmap external memory to a device.
1061 * Pointer to the generic device.
1063 * Starting virtual address of memory to be unmapped.
1065 * Starting IOVA address of memory to be unmapped.
1067 * Length of memory segment being unmapped.
1070 * 0 on success, negative value on error.
1073 mlx5_common_dev_dma_unmap(struct rte_device *rte_dev, void *addr,
1074 uint64_t iova __rte_unused, size_t len __rte_unused)
1076 struct mlx5_common_device *dev;
1077 struct mr_cache_entry entry;
1080 dev = to_mlx5_device(rte_dev);
1083 "Unable to find matching mlx5 device to device %s.",
1088 rte_rwlock_read_lock(&dev->mr_scache.rwlock);
1089 mr = mlx5_mr_lookup_list(&dev->mr_scache, &entry, (uintptr_t)addr);
1091 rte_rwlock_read_unlock(&dev->mr_scache.rwlock);
1093 "Address 0x%" PRIxPTR " wasn't registered to device %s",
1094 (uintptr_t)addr, rte_dev->name);
1098 LIST_REMOVE(mr, mr);
1099 DRV_LOG(DEBUG, "MR(%p) is removed from list.", (void *)mr);
1100 mlx5_mr_free(mr, dev->mr_scache.dereg_mr_cb);
1101 mlx5_mr_rebuild_cache(&dev->mr_scache);
1103 * No explicit wmb is needed after updating dev_gen due to
1104 * store-release ordering in unlock that provides the
1105 * implicit barrier at the software visible level.
1107 ++dev->mr_scache.dev_gen;
1108 DRV_LOG(DEBUG, "Broadcasting local cache flush, gen=%d.",
1109 dev->mr_scache.dev_gen);
1110 rte_rwlock_read_unlock(&dev->mr_scache.rwlock);
1115 mlx5_class_driver_register(struct mlx5_class_driver *driver)
1117 mlx5_common_driver_on_register_pci(driver);
1118 TAILQ_INSERT_TAIL(&drivers_list, driver, next);
1121 static void mlx5_common_driver_init(void)
1123 mlx5_common_pci_init();
1124 #ifdef RTE_EXEC_ENV_LINUX
1125 mlx5_common_auxiliary_init();
1129 static bool mlx5_common_initialized;
1132 * One time initialization routine for run-time dependency on glue library
1133 * for multiple PMDs. Each mlx5 PMD that depends on mlx5_common module,
1134 * must invoke in its constructor.
1137 mlx5_common_init(void)
1139 if (mlx5_common_initialized)
1142 pthread_mutex_init(&devices_list_lock, NULL);
1143 mlx5_glue_constructor();
1144 mlx5_common_driver_init();
1145 mlx5_common_initialized = true;
1149 * This function is responsible of initializing the variable
1150 * haswell_broadwell_cpu by checking if the cpu is intel
1151 * and reading the data returned from mlx5_cpu_id().
1152 * since haswell and broadwell cpus don't have improved performance
1153 * when using relaxed ordering we want to check the cpu type before
1154 * before deciding whether to enable RO or not.
1155 * if the cpu is haswell or broadwell the variable will be set to 1
1156 * otherwise it will be 0.
1158 RTE_INIT_PRIO(mlx5_is_haswell_broadwell_cpu, LOG)
1160 #ifdef RTE_ARCH_X86_64
1161 unsigned int broadwell_models[4] = {0x3d, 0x47, 0x4F, 0x56};
1162 unsigned int haswell_models[4] = {0x3c, 0x3f, 0x45, 0x46};
1163 unsigned int i, model, family, brand_id, vendor;
1164 unsigned int signature_intel_ebx = 0x756e6547;
1165 unsigned int extended_model;
1166 unsigned int eax = 0;
1167 unsigned int ebx = 0;
1168 unsigned int ecx = 0;
1169 unsigned int edx = 0;
1172 mlx5_cpu_id(0, &eax, &ebx, &ecx, &edx);
1175 if (max_level < 1) {
1176 haswell_broadwell_cpu = 0;
1179 mlx5_cpu_id(1, &eax, &ebx, &ecx, &edx);
1180 model = (eax >> 4) & 0x0f;
1181 family = (eax >> 8) & 0x0f;
1182 brand_id = ebx & 0xff;
1183 extended_model = (eax >> 12) & 0xf0;
1184 /* Check if the processor is Haswell or Broadwell */
1185 if (vendor == signature_intel_ebx) {
1187 model += extended_model;
1188 if (brand_id == 0 && family == 0x6) {
1189 for (i = 0; i < RTE_DIM(broadwell_models); i++)
1190 if (model == broadwell_models[i]) {
1191 haswell_broadwell_cpu = 1;
1194 for (i = 0; i < RTE_DIM(haswell_models); i++)
1195 if (model == haswell_models[i]) {
1196 haswell_broadwell_cpu = 1;
1202 haswell_broadwell_cpu = 0;
1206 * Allocate the User Access Region with DevX on specified device.
1207 * This routine handles the following UAR allocation issues:
1209 * - Try to allocate the UAR with the most appropriate memory mapping
1210 * type from the ones supported by the host.
1212 * - Try to allocate the UAR with non-NULL base address OFED 5.0.x and
1213 * Upstream rdma_core before v29 returned the NULL as UAR base address
1214 * if UAR was not the first object in the UAR page.
1215 * It caused the PMD failure and we should try to get another UAR till
1216 * we get the first one with non-NULL base address returned.
1219 * Pointer to mlx5 device structure to perform allocation on its context.
1222 * UAR object pointer on success, NULL otherwise and rte_errno is set.
1225 mlx5_devx_alloc_uar(struct mlx5_common_device *cdev)
1228 uint32_t retry, uar_mapping;
1231 for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
1232 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
1233 /* Control the mapping type according to the settings. */
1234 uar_mapping = (cdev->config.dbnc == MLX5_TXDB_NCACHED) ?
1235 MLX5DV_UAR_ALLOC_TYPE_NC : MLX5DV_UAR_ALLOC_TYPE_BF;
1238 * It seems we have no way to control the memory mapping type
1239 * for the UAR, the default "Write-Combining" type is supposed.
1243 uar = mlx5_glue->devx_alloc_uar(cdev->ctx, uar_mapping);
1244 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
1245 if (!uar && uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
1247 * In some environments like virtual machine the
1248 * Write Combining mapped might be not supported and
1249 * UAR allocation fails. We tried "Non-Cached" mapping
1252 DRV_LOG(DEBUG, "Failed to allocate DevX UAR (BF)");
1253 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
1254 uar = mlx5_glue->devx_alloc_uar(cdev->ctx, uar_mapping);
1255 } else if (!uar && uar_mapping == MLX5DV_UAR_ALLOC_TYPE_NC) {
1257 * If Verbs/kernel does not support "Non-Cached"
1258 * try the "Write-Combining".
1260 DRV_LOG(DEBUG, "Failed to allocate DevX UAR (NC)");
1261 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_BF;
1262 uar = mlx5_glue->devx_alloc_uar(cdev->ctx, uar_mapping);
1266 DRV_LOG(ERR, "Failed to allocate DevX UAR (BF/NC)");
1270 base_addr = mlx5_os_get_devx_uar_base_addr(uar);
1274 * The UARs are allocated by rdma_core within the
1275 * IB device context, on context closure all UARs
1276 * will be freed, should be no memory/object leakage.
1278 DRV_LOG(DEBUG, "Retrying to allocate DevX UAR");
1281 /* Check whether we finally succeeded with valid UAR allocation. */
1283 DRV_LOG(ERR, "Failed to allocate DevX UAR (NULL base)");
1287 * Return void * instead of struct mlx5dv_devx_uar *
1288 * is for compatibility with older rdma-core library headers.
1295 mlx5_devx_uar_release(struct mlx5_uar *uar)
1297 if (uar->obj != NULL)
1298 mlx5_glue->devx_free_uar(uar->obj);
1299 memset(uar, 0, sizeof(*uar));
1303 mlx5_devx_uar_prepare(struct mlx5_common_device *cdev, struct mlx5_uar *uar)
1305 off_t uar_mmap_offset;
1306 const size_t page_size = rte_mem_page_size();
1310 if (page_size == (size_t)-1) {
1311 DRV_LOG(ERR, "Failed to get mem page size");
1315 uar_obj = mlx5_devx_alloc_uar(cdev);
1316 if (uar_obj == NULL || mlx5_os_get_devx_uar_reg_addr(uar_obj) == NULL) {
1318 DRV_LOG(ERR, "Failed to allocate UAR.");
1322 uar_mmap_offset = mlx5_os_get_devx_uar_mmap_offset(uar_obj);
1323 base_addr = mlx5_os_get_devx_uar_base_addr(uar_obj);
1324 uar->dbnc = mlx5_db_map_type_get(uar_mmap_offset, page_size);
1325 uar->bf_db.db = mlx5_os_get_devx_uar_reg_addr(uar_obj);
1326 uar->cq_db.db = RTE_PTR_ADD(base_addr, MLX5_CQ_DOORBELL);
1328 rte_spinlock_init(&uar->bf_sl);
1329 rte_spinlock_init(&uar->cq_sl);
1330 uar->bf_db.sl_p = &uar->bf_sl;
1331 uar->cq_db.sl_p = &uar->cq_sl;
1332 #endif /* RTE_ARCH_64 */
1336 RTE_PMD_EXPORT_NAME(mlx5_common_driver, __COUNTER__);