1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2019 Mellanox Technologies, Ltd
10 #include <rte_mempool.h>
11 #include <rte_class.h>
12 #include <rte_malloc.h>
14 #include "mlx5_common.h"
15 #include "mlx5_common_os.h"
16 #include "mlx5_common_log.h"
17 #include "mlx5_common_private.h"
19 uint8_t haswell_broadwell_cpu;
21 /* In case this is an x86_64 intel processor to check if
22 * we should use relaxed ordering.
24 #ifdef RTE_ARCH_X86_64
26 * This function returns processor identification and feature information
29 * @param eax, ebx, ecx, edx
30 * Pointers to the registers that will hold cpu information.
32 * The main category of information returned.
34 static inline void mlx5_cpu_id(unsigned int level,
35 unsigned int *eax, unsigned int *ebx,
36 unsigned int *ecx, unsigned int *edx)
39 : "=a" (*eax), "=b" (*ebx), "=c" (*ecx), "=d" (*edx)
44 RTE_LOG_REGISTER_DEFAULT(mlx5_common_logtype, NOTICE)
46 /* Head of list of drivers. */
47 static TAILQ_HEAD(mlx5_drivers, mlx5_class_driver) drivers_list =
48 TAILQ_HEAD_INITIALIZER(drivers_list);
50 /* Head of devices. */
51 static TAILQ_HEAD(mlx5_devices, mlx5_common_device) devices_list =
52 TAILQ_HEAD_INITIALIZER(devices_list);
56 unsigned int drv_class;
58 { .name = "vdpa", .drv_class = MLX5_CLASS_VDPA },
59 { .name = "eth", .drv_class = MLX5_CLASS_ETH },
60 /* Keep class "net" for backward compatibility. */
61 { .name = "net", .drv_class = MLX5_CLASS_ETH },
62 { .name = "regex", .drv_class = MLX5_CLASS_REGEX },
63 { .name = "compress", .drv_class = MLX5_CLASS_COMPRESS },
64 { .name = "crypto", .drv_class = MLX5_CLASS_CRYPTO },
68 class_name_to_value(const char *class_name)
72 for (i = 0; i < RTE_DIM(mlx5_classes); i++) {
73 if (strcmp(class_name, mlx5_classes[i].name) == 0)
74 return mlx5_classes[i].drv_class;
79 static struct mlx5_class_driver *
80 driver_get(uint32_t class)
82 struct mlx5_class_driver *driver;
84 TAILQ_FOREACH(driver, &drivers_list, next) {
85 if ((uint32_t)driver->drv_class == class)
92 devargs_class_handler(__rte_unused const char *key,
93 const char *class_names, void *opaque)
102 scratch = strdup(class_names);
103 if (scratch == NULL) {
107 found = strtok_r(scratch, ":", &refstr);
112 /* Extract each individual class name. Multiple
113 * classes can be supplied as class=net:regex:foo:bar.
115 class_val = class_name_to_value(found);
116 /* Check if its a valid class. */
122 found = strtok_r(NULL, ":", &refstr);
123 } while (found != NULL);
127 DRV_LOG(ERR, "Invalid mlx5 class options: %s.\n", class_names);
132 parse_class_options(const struct rte_devargs *devargs)
134 struct rte_kvargs *kvlist;
139 if (devargs->cls != NULL && devargs->cls->name != NULL)
140 /* Global syntax, only one class type. */
141 return class_name_to_value(devargs->cls->name);
142 /* Legacy devargs support multiple classes. */
143 kvlist = rte_kvargs_parse(devargs->args, NULL);
146 rte_kvargs_process(kvlist, RTE_DEVARGS_KEY_CLASS,
147 devargs_class_handler, &ret);
148 rte_kvargs_free(kvlist);
152 static const unsigned int mlx5_class_invalid_combinations[] = {
153 MLX5_CLASS_ETH | MLX5_CLASS_VDPA,
154 /* New class combination should be added here. */
158 is_valid_class_combination(uint32_t user_classes)
162 /* Verify if user specified unsupported combination. */
163 for (i = 0; i < RTE_DIM(mlx5_class_invalid_combinations); i++) {
164 if ((mlx5_class_invalid_combinations[i] & user_classes) ==
165 mlx5_class_invalid_combinations[i])
168 /* Not found any invalid class combination. */
173 device_class_enabled(const struct mlx5_common_device *device, uint32_t class)
175 return (device->classes_loaded & class) > 0;
179 mlx5_bus_match(const struct mlx5_class_driver *drv,
180 const struct rte_device *dev)
182 if (mlx5_dev_is_pci(dev))
183 return mlx5_dev_pci_match(drv, dev);
187 static struct mlx5_common_device *
188 to_mlx5_device(const struct rte_device *rte_dev)
190 struct mlx5_common_device *dev;
192 TAILQ_FOREACH(dev, &devices_list, next) {
193 if (rte_dev == dev->dev)
200 mlx5_dev_to_pci_str(const struct rte_device *dev, char *addr, size_t size)
202 struct rte_pci_addr pci_addr = { 0 };
205 if (mlx5_dev_is_pci(dev)) {
206 /* Input might be <BDF>, format PCI address to <DBDF>. */
207 ret = rte_pci_addr_parse(dev->name, &pci_addr);
210 rte_pci_device_name(&pci_addr, addr, size);
213 #ifdef RTE_EXEC_ENV_LINUX
214 return mlx5_auxiliary_get_pci_str(RTE_DEV_TO_AUXILIARY_CONST(dev),
223 dev_release(struct mlx5_common_device *dev)
225 TAILQ_REMOVE(&devices_list, dev, next);
230 drivers_remove(struct mlx5_common_device *dev, uint32_t enabled_classes)
232 struct mlx5_class_driver *driver;
233 int local_ret = -ENODEV;
237 enabled_classes &= dev->classes_loaded;
238 while (enabled_classes) {
239 driver = driver_get(RTE_BIT64(i));
240 if (driver != NULL) {
241 local_ret = driver->remove(dev->dev);
243 dev->classes_loaded &= ~RTE_BIT64(i);
247 enabled_classes &= ~RTE_BIT64(i);
250 if (local_ret != 0 && ret == 0)
256 drivers_probe(struct mlx5_common_device *dev, uint32_t user_classes)
258 struct mlx5_class_driver *driver;
259 uint32_t enabled_classes = 0;
263 TAILQ_FOREACH(driver, &drivers_list, next) {
264 if ((driver->drv_class & user_classes) == 0)
266 if (!mlx5_bus_match(driver, dev->dev))
268 already_loaded = dev->classes_loaded & driver->drv_class;
269 if (already_loaded && driver->probe_again == 0) {
270 DRV_LOG(ERR, "Device %s is already probed",
275 ret = driver->probe(dev->dev);
277 DRV_LOG(ERR, "Failed to load driver %s",
281 enabled_classes |= driver->drv_class;
283 dev->classes_loaded |= enabled_classes;
286 /* Only unload drivers which are enabled which were enabled
287 * in this probe instance.
289 drivers_remove(dev, enabled_classes);
294 mlx5_common_dev_probe(struct rte_device *eal_dev)
296 struct mlx5_common_device *dev;
297 uint32_t classes = 0;
298 bool new_device = false;
301 DRV_LOG(INFO, "probe device \"%s\".", eal_dev->name);
302 ret = parse_class_options(eal_dev->devargs);
304 DRV_LOG(ERR, "Unsupported mlx5 class type: %s",
305 eal_dev->devargs->args);
310 /* Default to net class. */
311 classes = MLX5_CLASS_ETH;
312 dev = to_mlx5_device(eal_dev);
314 dev = rte_zmalloc("mlx5_common_device", sizeof(*dev), 0);
318 TAILQ_INSERT_HEAD(&devices_list, dev, next);
322 * Validate combination here.
323 * For new device, the classes_loaded field is 0 and it check only
324 * the classes given as user device arguments.
326 ret = is_valid_class_combination(classes | dev->classes_loaded);
328 DRV_LOG(ERR, "Unsupported mlx5 classes combination.");
331 ret = drivers_probe(dev, classes);
342 mlx5_common_dev_remove(struct rte_device *eal_dev)
344 struct mlx5_common_device *dev;
347 dev = to_mlx5_device(eal_dev);
350 /* Matching device found, cleanup and unload drivers. */
351 ret = drivers_remove(dev, dev->classes_loaded);
358 mlx5_common_dev_dma_map(struct rte_device *dev, void *addr, uint64_t iova,
361 struct mlx5_class_driver *driver = NULL;
362 struct mlx5_class_driver *temp;
363 struct mlx5_common_device *mdev;
366 mdev = to_mlx5_device(dev);
369 TAILQ_FOREACH(driver, &drivers_list, next) {
370 if (!device_class_enabled(mdev, driver->drv_class) ||
371 driver->dma_map == NULL)
373 ret = driver->dma_map(dev, addr, iova, len);
379 TAILQ_FOREACH(temp, &drivers_list, next) {
382 if (device_class_enabled(mdev, temp->drv_class) &&
383 temp->dma_map && temp->dma_unmap)
384 temp->dma_unmap(dev, addr, iova, len);
390 mlx5_common_dev_dma_unmap(struct rte_device *dev, void *addr, uint64_t iova,
393 struct mlx5_class_driver *driver;
394 struct mlx5_common_device *mdev;
395 int local_ret = -EINVAL;
398 mdev = to_mlx5_device(dev);
401 /* There is no unmap error recovery in current implementation. */
402 TAILQ_FOREACH_REVERSE(driver, &drivers_list, mlx5_drivers, next) {
403 if (!device_class_enabled(mdev, driver->drv_class) ||
404 driver->dma_unmap == NULL)
406 local_ret = driver->dma_unmap(dev, addr, iova, len);
407 if (local_ret && (ret == 0))
416 mlx5_class_driver_register(struct mlx5_class_driver *driver)
418 mlx5_common_driver_on_register_pci(driver);
419 TAILQ_INSERT_TAIL(&drivers_list, driver, next);
422 static void mlx5_common_driver_init(void)
424 mlx5_common_pci_init();
425 #ifdef RTE_EXEC_ENV_LINUX
426 mlx5_common_auxiliary_init();
430 static bool mlx5_common_initialized;
433 * One time innitialization routine for run-time dependency on glue library
434 * for multiple PMDs. Each mlx5 PMD that depends on mlx5_common module,
435 * must invoke in its constructor.
438 mlx5_common_init(void)
440 if (mlx5_common_initialized)
443 mlx5_glue_constructor();
444 mlx5_common_driver_init();
445 mlx5_common_initialized = true;
449 * This function is responsible of initializing the variable
450 * haswell_broadwell_cpu by checking if the cpu is intel
451 * and reading the data returned from mlx5_cpu_id().
452 * since haswell and broadwell cpus don't have improved performance
453 * when using relaxed ordering we want to check the cpu type before
454 * before deciding whether to enable RO or not.
455 * if the cpu is haswell or broadwell the variable will be set to 1
456 * otherwise it will be 0.
458 RTE_INIT_PRIO(mlx5_is_haswell_broadwell_cpu, LOG)
460 #ifdef RTE_ARCH_X86_64
461 unsigned int broadwell_models[4] = {0x3d, 0x47, 0x4F, 0x56};
462 unsigned int haswell_models[4] = {0x3c, 0x3f, 0x45, 0x46};
463 unsigned int i, model, family, brand_id, vendor;
464 unsigned int signature_intel_ebx = 0x756e6547;
465 unsigned int extended_model;
466 unsigned int eax = 0;
467 unsigned int ebx = 0;
468 unsigned int ecx = 0;
469 unsigned int edx = 0;
472 mlx5_cpu_id(0, &eax, &ebx, &ecx, &edx);
476 haswell_broadwell_cpu = 0;
479 mlx5_cpu_id(1, &eax, &ebx, &ecx, &edx);
480 model = (eax >> 4) & 0x0f;
481 family = (eax >> 8) & 0x0f;
482 brand_id = ebx & 0xff;
483 extended_model = (eax >> 12) & 0xf0;
484 /* Check if the processor is Haswell or Broadwell */
485 if (vendor == signature_intel_ebx) {
487 model += extended_model;
488 if (brand_id == 0 && family == 0x6) {
489 for (i = 0; i < RTE_DIM(broadwell_models); i++)
490 if (model == broadwell_models[i]) {
491 haswell_broadwell_cpu = 1;
494 for (i = 0; i < RTE_DIM(haswell_models); i++)
495 if (model == haswell_models[i]) {
496 haswell_broadwell_cpu = 1;
502 haswell_broadwell_cpu = 0;
506 * Allocate the User Access Region with DevX on specified device.
509 * Infiniband device context to perform allocation on.
510 * @param [in] mapping
511 * MLX5DV_UAR_ALLOC_TYPE_BF - allocate as cached memory with write-combining
512 * attributes (if supported by the host), the
513 * writes to the UAR registers must be followed
514 * by write memory barrier.
515 * MLX5DV_UAR_ALLOC_TYPE_NC - allocate as non-cached nenory, all writes are
516 * promoted to the registers immediately, no
517 * memory barriers needed.
518 * mapping < 0 - the first attempt is performed with MLX5DV_UAR_ALLOC_TYPE_BF,
519 * if this fails the next attempt with MLX5DV_UAR_ALLOC_TYPE_NC
520 * is performed. The drivers specifying negative values should
521 * always provide the write memory barrier operation after UAR
523 * If there is no definitions for the MLX5DV_UAR_ALLOC_TYPE_xx (older rdma
524 * library headers), the caller can specify 0.
527 * UAR object pointer on success, NULL otherwise and rte_errno is set.
530 mlx5_devx_alloc_uar(void *ctx, int mapping)
533 uint32_t retry, uar_mapping;
536 for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
537 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
538 /* Control the mapping type according to the settings. */
539 uar_mapping = (mapping < 0) ?
540 MLX5DV_UAR_ALLOC_TYPE_NC : mapping;
543 * It seems we have no way to control the memory mapping type
544 * for the UAR, the default "Write-Combining" type is supposed.
547 RTE_SET_USED(mapping);
549 uar = mlx5_glue->devx_alloc_uar(ctx, uar_mapping);
550 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
553 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
555 * In some environments like virtual machine the
556 * Write Combining mapped might be not supported and
557 * UAR allocation fails. We tried "Non-Cached" mapping
560 DRV_LOG(WARNING, "Failed to allocate DevX UAR (BF)");
561 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
562 uar = mlx5_glue->devx_alloc_uar(ctx, uar_mapping);
565 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_NC) {
567 * If Verbs/kernel does not support "Non-Cached"
568 * try the "Write-Combining".
570 DRV_LOG(WARNING, "Failed to allocate DevX UAR (NC)");
571 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_BF;
572 uar = mlx5_glue->devx_alloc_uar(ctx, uar_mapping);
576 DRV_LOG(ERR, "Failed to allocate DevX UAR (BF/NC)");
580 base_addr = mlx5_os_get_devx_uar_base_addr(uar);
584 * The UARs are allocated by rdma_core within the
585 * IB device context, on context closure all UARs
586 * will be freed, should be no memory/object leakage.
588 DRV_LOG(WARNING, "Retrying to allocate DevX UAR");
591 /* Check whether we finally succeeded with valid UAR allocation. */
593 DRV_LOG(ERR, "Failed to allocate DevX UAR (NULL base)");
597 * Return void * instead of struct mlx5dv_devx_uar *
598 * is for compatibility with older rdma-core library headers.
604 RTE_PMD_EXPORT_NAME(mlx5_common_driver, __COUNTER__);