1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2019 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_COMMON_H_
6 #define RTE_PMD_MLX5_COMMON_H_
11 #include <rte_debug.h>
12 #include <rte_atomic.h>
13 #include <rte_rwlock.h>
15 #include <rte_kvargs.h>
16 #include <rte_devargs.h>
17 #include <rte_bitops.h>
18 #include <rte_lcore.h>
19 #include <rte_spinlock.h>
20 #include <rte_os_shim.h>
23 #include "mlx5_devx_cmds.h"
24 #include "mlx5_common_os.h"
26 /* Reported driver name. */
27 #define MLX5_PCI_DRIVER_NAME "mlx5_pci"
28 #define MLX5_AUXILIARY_DRIVER_NAME "mlx5_auxiliary"
30 /* Bit-field manipulation. */
31 #define BITFIELD_DECLARE(bf, type, size) \
32 type bf[(((size_t)(size) / (sizeof(type) * CHAR_BIT)) + \
33 !!((size_t)(size) % (sizeof(type) * CHAR_BIT)))]
34 #define BITFIELD_DEFINE(bf, type, size) \
35 BITFIELD_DECLARE((bf), type, (size)) = { 0 }
36 #define BITFIELD_SET(bf, b) \
37 (void)((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] |= \
38 ((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT))))
39 #define BITFIELD_RESET(bf, b) \
40 (void)((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] &= \
41 ~((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT))))
42 #define BITFIELD_ISSET(bf, b) \
43 !!(((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] & \
44 ((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT)))))
47 * Helper macros to work around __VA_ARGS__ limitations in a C99 compliant
50 #define PMD_DRV_LOG_STRIP(a, b) a
51 #define PMD_DRV_LOG_OPAREN (
52 #define PMD_DRV_LOG_CPAREN )
53 #define PMD_DRV_LOG_COMMA ,
55 /* Return the file name part of a path. */
56 static inline const char *
57 pmd_drv_log_basename(const char *s)
67 #define PMD_DRV_LOG___(level, type, name, ...) \
68 rte_log(RTE_LOG_ ## level, \
71 RTE_FMT_HEAD(__VA_ARGS__,), \
72 RTE_FMT_TAIL(__VA_ARGS__,)))
74 #ifdef RTE_LIBRTE_MLX5_DEBUG
76 #define PMD_DRV_LOG__(level, type, name, ...) \
77 PMD_DRV_LOG___(level, type, name, "%s:%u: %s(): " __VA_ARGS__)
78 #define PMD_DRV_LOG_(level, type, name, s, ...) \
79 PMD_DRV_LOG__(level, type, name,\
80 s "\n" PMD_DRV_LOG_COMMA \
81 pmd_drv_log_basename(__FILE__) PMD_DRV_LOG_COMMA \
82 __LINE__ PMD_DRV_LOG_COMMA \
86 #else /* RTE_LIBRTE_MLX5_DEBUG */
87 #define PMD_DRV_LOG__(level, type, name, ...) \
88 PMD_DRV_LOG___(level, type, name, __VA_ARGS__)
89 #define PMD_DRV_LOG_(level, type, name, s, ...) \
90 PMD_DRV_LOG__(level, type, name, s "\n", __VA_ARGS__)
92 #endif /* RTE_LIBRTE_MLX5_DEBUG */
94 /* claim_zero() does not perform any check when debugging is disabled. */
95 #ifdef RTE_LIBRTE_MLX5_DEBUG
97 #define MLX5_ASSERT(exp) RTE_VERIFY(exp)
98 #define claim_zero(...) MLX5_ASSERT((__VA_ARGS__) == 0)
99 #define claim_nonzero(...) MLX5_ASSERT((__VA_ARGS__) != 0)
101 #else /* RTE_LIBRTE_MLX5_DEBUG */
103 #define MLX5_ASSERT(exp) RTE_ASSERT(exp)
104 #define claim_zero(...) (__VA_ARGS__)
105 #define claim_nonzero(...) (__VA_ARGS__)
107 #endif /* RTE_LIBRTE_MLX5_DEBUG */
109 /* Allocate a buffer on the stack and fill it with a printf format string. */
110 #define MKSTR(name, ...) \
111 int mkstr_size_##name = snprintf(NULL, 0, "" __VA_ARGS__); \
112 char name[mkstr_size_##name + 1]; \
114 memset(name, 0, mkstr_size_##name + 1); \
115 snprintf(name, sizeof(name), "" __VA_ARGS__)
118 PCI_VENDOR_ID_MELLANOX = 0x15b3,
122 PCI_DEVICE_ID_MELLANOX_CONNECTX4 = 0x1013,
123 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF = 0x1014,
124 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX = 0x1015,
125 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF = 0x1016,
126 PCI_DEVICE_ID_MELLANOX_CONNECTX5 = 0x1017,
127 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF = 0x1018,
128 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX = 0x1019,
129 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF = 0x101a,
130 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF = 0xa2d2,
131 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF = 0xa2d3,
132 PCI_DEVICE_ID_MELLANOX_CONNECTX6 = 0x101b,
133 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF = 0x101c,
134 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX = 0x101d,
135 PCI_DEVICE_ID_MELLANOX_CONNECTXVF = 0x101e,
136 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF = 0xa2d6,
137 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX = 0x101f,
138 PCI_DEVICE_ID_MELLANOX_CONNECTX7 = 0x1021,
139 PCI_DEVICE_ID_MELLANOX_CONNECTX7BF = 0Xa2dc,
142 /* Maximum number of simultaneous unicast MAC addresses. */
143 #define MLX5_MAX_UC_MAC_ADDRESSES 128
144 /* Maximum number of simultaneous Multicast MAC addresses. */
145 #define MLX5_MAX_MC_MAC_ADDRESSES 128
146 /* Maximum number of simultaneous MAC addresses. */
147 #define MLX5_MAX_MAC_ADDRESSES \
148 (MLX5_MAX_UC_MAC_ADDRESSES + MLX5_MAX_MC_MAC_ADDRESSES)
150 /* Recognized Infiniband device physical port name types. */
151 enum mlx5_nl_phys_port_name_type {
152 MLX5_PHYS_PORT_NAME_TYPE_NOTSET = 0, /* Not set. */
153 MLX5_PHYS_PORT_NAME_TYPE_LEGACY, /* before kernel ver < 5.0 */
154 MLX5_PHYS_PORT_NAME_TYPE_UPLINK, /* p0, kernel ver >= 5.0 */
155 MLX5_PHYS_PORT_NAME_TYPE_PFVF, /* pf0vf0, kernel ver >= 5.0 */
156 MLX5_PHYS_PORT_NAME_TYPE_PFHPF, /* pf0, kernel ver >= 5.7, HPF rep */
157 MLX5_PHYS_PORT_NAME_TYPE_PFSF, /* pf0sf0, kernel ver >= 5.0 */
158 MLX5_PHYS_PORT_NAME_TYPE_UNKNOWN, /* Unrecognized. */
161 /** Switch information returned by mlx5_nl_switch_info(). */
162 struct mlx5_switch_info {
163 uint32_t master:1; /**< Master device. */
164 uint32_t representor:1; /**< Representor device. */
165 enum mlx5_nl_phys_port_name_type name_type; /** < Port name type. */
166 int32_t ctrl_num; /**< Controller number (valid for c#pf#vf# format). */
167 int32_t pf_num; /**< PF number (valid for pfxvfx format only). */
168 int32_t port_name; /**< Representor port name. */
169 uint64_t switch_id; /**< Switch identifier. */
173 enum mlx5_cqe_status {
174 MLX5_CQE_STATUS_SW_OWN = -1,
175 MLX5_CQE_STATUS_HW_OWN = -2,
176 MLX5_CQE_STATUS_ERR = -3,
180 * Check whether CQE is valid.
185 * Size of completion queue.
192 static __rte_always_inline enum mlx5_cqe_status
193 check_cqe(volatile struct mlx5_cqe *cqe, const uint16_t cqes_n,
196 const uint16_t idx = ci & cqes_n;
197 const uint8_t op_own = cqe->op_own;
198 const uint8_t op_owner = MLX5_CQE_OWNER(op_own);
199 const uint8_t op_code = MLX5_CQE_OPCODE(op_own);
201 if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
202 return MLX5_CQE_STATUS_HW_OWN;
204 if (unlikely(op_code == MLX5_CQE_RESP_ERR ||
205 op_code == MLX5_CQE_REQ_ERR))
206 return MLX5_CQE_STATUS_ERR;
207 return MLX5_CQE_STATUS_SW_OWN;
211 * Get PCI address <DBDF> string from EAL device.
214 * The output address buffer string
216 * The output buffer size
219 * - Negative value and rte_errno is set otherwise.
221 int mlx5_dev_to_pci_str(const struct rte_device *dev, char *addr, size_t size);
224 * Get PCI address from sysfs of a PCI-related device.
226 * @param[in] dev_path
227 * The sysfs path should not point to the direct plain PCI device.
228 * Instead, the node "/device/" is used to access the real device.
229 * @param[out] pci_addr
230 * Parsed PCI address.
234 * - Negative value and rte_errno is set otherwise.
237 int mlx5_get_pci_addr(const char *dev_path, struct rte_pci_addr *pci_addr);
240 * Get kernel network interface name from sysfs IB device path.
242 * @param[in] ibdev_path
243 * The sysfs path to IB device.
245 * Interface name output of size IF_NAMESIZE.
249 * - Negative value and rte_errno is set otherwise.
252 int mlx5_get_ifname_sysfs(const char *ibdev_path, char *ifname);
255 int mlx5_auxiliary_get_child_name(const char *dev, const char *node,
256 char *child, size_t size);
260 MLX5_CLASS_ETH = RTE_BIT64(0),
261 MLX5_CLASS_VDPA = RTE_BIT64(1),
262 MLX5_CLASS_REGEX = RTE_BIT64(2),
263 MLX5_CLASS_COMPRESS = RTE_BIT64(3),
264 MLX5_CLASS_CRYPTO = RTE_BIT64(4),
267 #define MLX5_DBR_SIZE RTE_CACHE_LINE_SIZE
269 /* devX creation object */
270 struct mlx5_devx_obj {
271 void *obj; /* The DV object. */
272 int id; /* The object ID. */
275 /* UMR memory buffer used to define 1 entry in indirect mkey. */
283 void mlx5_translate_port_name(const char *port_name_in,
284 struct mlx5_switch_info *port_info_out);
285 void mlx5_glue_constructor(void);
287 void *mlx5_devx_alloc_uar(void *ctx, int mapping);
288 extern uint8_t haswell_broadwell_cpu;
291 void mlx5_common_init(void);
294 * Common Driver Interface
296 * ConnectX common driver supports multiple classes: net, vDPA, regex, crypto
297 * and compress devices. This layer enables creating such multiple classes
298 * on a single device by allowing to bind multiple class-specific device
299 * drivers to attach to the common driver.
301 * ------------ ------------- -------------- ----------------- ------------
302 * | mlx5 net | | mlx5 vdpa | | mlx5 regex | | mlx5 compress | | mlx5 ... |
303 * | driver | | driver | | driver | | driver | | drivers |
304 * ------------ ------------- -------------- ----------------- ------------
311 * ----------- -----------------
313 * | pci dev | | auxiliary dev |
314 * ----------- -----------------
316 * - mlx5 PCI bus driver binds to mlx5 PCI devices defined by PCI ID table
317 * of all related devices.
318 * - mlx5 class driver such as net, vDPA, regex defines its specific
319 * PCI ID table and mlx5 bus driver probes matching class drivers.
320 * - mlx5 common driver is central place that validates supported
321 * class combinations.
322 * - mlx5 common driver hides bus difference by resolving device address
323 * from devargs, locating target RDMA device and probing with it.
327 * Device configuration structure.
329 * Merged configuration from:
331 * - Device capabilities,
332 * - User device parameters disabled features.
334 struct mlx5_common_dev_config {
335 int dbnc; /* Skip doorbell register write barrier. */
336 unsigned int devx:1; /* Whether devx interface is available or not. */
337 unsigned int sys_mem_en:1; /* The default memory allocator. */
338 unsigned int mr_mempool_reg_en:1;
339 /* Allow/prevent implicit mempool memory registration. */
340 unsigned int mr_ext_memseg_en:1;
341 /* Whether memseg should be extended for MR creation. */
344 struct mlx5_common_device {
345 struct rte_device *dev;
346 TAILQ_ENTRY(mlx5_common_device) next;
347 uint32_t classes_loaded;
348 void *ctx; /* Verbs/DV/DevX context. */
349 struct mlx5_common_dev_config config; /* Device configuration. */
353 * Initialization function for the driver called during device probing.
355 typedef int (mlx5_class_driver_probe_t)(struct mlx5_common_device *dev);
358 * Uninitialization function for the driver called during hot-unplugging.
360 typedef int (mlx5_class_driver_remove_t)(struct mlx5_common_device *dev);
363 * Driver-specific DMA mapping. After a successful call the device
364 * will be able to read/write from/to this segment.
367 * Pointer to the device.
369 * Starting virtual address of memory to be mapped.
371 * Starting IOVA address of memory to be mapped.
373 * Length of memory segment being mapped.
376 * - Negative value and rte_errno is set otherwise.
378 typedef int (mlx5_class_driver_dma_map_t)(struct rte_device *dev, void *addr,
379 uint64_t iova, size_t len);
382 * Driver-specific DMA un-mapping. After a successful call the device
383 * will not be able to read/write from/to this segment.
386 * Pointer to the device.
388 * Starting virtual address of memory to be unmapped.
390 * Starting IOVA address of memory to be unmapped.
392 * Length of memory segment being unmapped.
395 * - Negative value and rte_errno is set otherwise.
397 typedef int (mlx5_class_driver_dma_unmap_t)(struct rte_device *dev, void *addr,
398 uint64_t iova, size_t len);
400 /** Device already probed can be probed again to check for new ports. */
401 #define MLX5_DRV_PROBE_AGAIN 0x0004
404 * A structure describing a mlx5 common class driver.
406 struct mlx5_class_driver {
407 TAILQ_ENTRY(mlx5_class_driver) next;
408 enum mlx5_class drv_class; /**< Class of this driver. */
409 const char *name; /**< Driver name. */
410 mlx5_class_driver_probe_t *probe; /**< Device probe function. */
411 mlx5_class_driver_remove_t *remove; /**< Device remove function. */
412 mlx5_class_driver_dma_map_t *dma_map; /**< Device DMA map function. */
413 mlx5_class_driver_dma_unmap_t *dma_unmap;
414 /**< Device DMA unmap function. */
415 const struct rte_pci_id *id_table; /**< ID table, NULL terminated. */
416 uint32_t probe_again:1;
417 /**< Device already probed can be probed again to check new device. */
418 uint32_t intr_lsc:1; /**< Supports link state interrupt. */
419 uint32_t intr_rmv:1; /**< Supports device remove interrupt. */
423 * Register a mlx5 device driver.
426 * A pointer to a mlx5_driver structure describing the driver
431 mlx5_class_driver_register(struct mlx5_class_driver *driver);
434 * Test device is a PCI bus device.
440 * - True on device devargs is a PCI bus device.
445 mlx5_dev_is_pci(const struct rte_device *dev);
447 /* mlx5_common_os.c */
449 int mlx5_os_open_device(struct mlx5_common_device *cdev, uint32_t classes);
451 #endif /* RTE_PMD_MLX5_COMMON_H_ */