1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2019 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_COMMON_H_
6 #define RTE_PMD_MLX5_COMMON_H_
11 #include <rte_debug.h>
12 #include <rte_atomic.h>
14 #include <rte_kvargs.h>
15 #include <rte_devargs.h>
16 #include <rte_bitops.h>
19 #include "mlx5_devx_cmds.h"
22 /* Bit-field manipulation. */
23 #define BITFIELD_DECLARE(bf, type, size) \
24 type bf[(((size_t)(size) / (sizeof(type) * CHAR_BIT)) + \
25 !!((size_t)(size) % (sizeof(type) * CHAR_BIT)))]
26 #define BITFIELD_DEFINE(bf, type, size) \
27 BITFIELD_DECLARE((bf), type, (size)) = { 0 }
28 #define BITFIELD_SET(bf, b) \
29 (void)((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] |= \
30 ((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT))))
31 #define BITFIELD_RESET(bf, b) \
32 (void)((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] &= \
33 ~((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT))))
34 #define BITFIELD_ISSET(bf, b) \
35 !!(((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] & \
36 ((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT)))))
39 * Helper macros to work around __VA_ARGS__ limitations in a C99 compliant
42 #define PMD_DRV_LOG_STRIP(a, b) a
43 #define PMD_DRV_LOG_OPAREN (
44 #define PMD_DRV_LOG_CPAREN )
45 #define PMD_DRV_LOG_COMMA ,
47 /* Return the file name part of a path. */
48 static inline const char *
49 pmd_drv_log_basename(const char *s)
59 #define PMD_DRV_LOG___(level, type, name, ...) \
60 rte_log(RTE_LOG_ ## level, \
63 RTE_FMT_HEAD(__VA_ARGS__,), \
64 RTE_FMT_TAIL(__VA_ARGS__,)))
67 * When debugging is enabled (MLX5_DEBUG not defined), file, line and function
68 * information replace the driver name (MLX5_DRIVER_NAME) in log messages.
70 #ifdef RTE_LIBRTE_MLX5_DEBUG
72 #define PMD_DRV_LOG__(level, type, name, ...) \
73 PMD_DRV_LOG___(level, type, name, "%s:%u: %s(): " __VA_ARGS__)
74 #define PMD_DRV_LOG_(level, type, name, s, ...) \
75 PMD_DRV_LOG__(level, type, name,\
76 s "\n" PMD_DRV_LOG_COMMA \
77 pmd_drv_log_basename(__FILE__) PMD_DRV_LOG_COMMA \
78 __LINE__ PMD_DRV_LOG_COMMA \
82 #else /* RTE_LIBRTE_MLX5_DEBUG */
83 #define PMD_DRV_LOG__(level, type, name, ...) \
84 PMD_DRV_LOG___(level, type, name, __VA_ARGS__)
85 #define PMD_DRV_LOG_(level, type, name, s, ...) \
86 PMD_DRV_LOG__(level, type, name, s "\n", __VA_ARGS__)
88 #endif /* RTE_LIBRTE_MLX5_DEBUG */
90 /* claim_zero() does not perform any check when debugging is disabled. */
91 #ifdef RTE_LIBRTE_MLX5_DEBUG
93 #define DEBUG(...) DRV_LOG(DEBUG, __VA_ARGS__)
94 #define MLX5_ASSERT(exp) RTE_VERIFY(exp)
95 #define claim_zero(...) MLX5_ASSERT((__VA_ARGS__) == 0)
96 #define claim_nonzero(...) MLX5_ASSERT((__VA_ARGS__) != 0)
98 #else /* RTE_LIBRTE_MLX5_DEBUG */
100 #define DEBUG(...) (void)0
101 #define MLX5_ASSERT(exp) RTE_ASSERT(exp)
102 #define claim_zero(...) (__VA_ARGS__)
103 #define claim_nonzero(...) (__VA_ARGS__)
105 #endif /* RTE_LIBRTE_MLX5_DEBUG */
107 /* Allocate a buffer on the stack and fill it with a printf format string. */
108 #define MKSTR(name, ...) \
109 int mkstr_size_##name = snprintf(NULL, 0, "" __VA_ARGS__); \
110 char name[mkstr_size_##name + 1]; \
112 snprintf(name, sizeof(name), "" __VA_ARGS__)
115 PCI_VENDOR_ID_MELLANOX = 0x15b3,
119 PCI_DEVICE_ID_MELLANOX_CONNECTX4 = 0x1013,
120 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF = 0x1014,
121 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX = 0x1015,
122 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF = 0x1016,
123 PCI_DEVICE_ID_MELLANOX_CONNECTX5 = 0x1017,
124 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF = 0x1018,
125 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX = 0x1019,
126 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF = 0x101a,
127 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF = 0xa2d2,
128 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF = 0xa2d3,
129 PCI_DEVICE_ID_MELLANOX_CONNECTX6 = 0x101b,
130 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF = 0x101c,
131 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX = 0x101d,
132 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF = 0x101e,
133 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF = 0xa2d6,
134 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX = 0x101f,
137 /* Maximum number of simultaneous unicast MAC addresses. */
138 #define MLX5_MAX_UC_MAC_ADDRESSES 128
139 /* Maximum number of simultaneous Multicast MAC addresses. */
140 #define MLX5_MAX_MC_MAC_ADDRESSES 128
141 /* Maximum number of simultaneous MAC addresses. */
142 #define MLX5_MAX_MAC_ADDRESSES \
143 (MLX5_MAX_UC_MAC_ADDRESSES + MLX5_MAX_MC_MAC_ADDRESSES)
145 /* Recognized Infiniband device physical port name types. */
146 enum mlx5_nl_phys_port_name_type {
147 MLX5_PHYS_PORT_NAME_TYPE_NOTSET = 0, /* Not set. */
148 MLX5_PHYS_PORT_NAME_TYPE_LEGACY, /* before kernel ver < 5.0 */
149 MLX5_PHYS_PORT_NAME_TYPE_UPLINK, /* p0, kernel ver >= 5.0 */
150 MLX5_PHYS_PORT_NAME_TYPE_PFVF, /* pf0vf0, kernel ver >= 5.0 */
151 MLX5_PHYS_PORT_NAME_TYPE_PFHPF, /* pf0, kernel ver >= 5.7, HPF rep */
152 MLX5_PHYS_PORT_NAME_TYPE_UNKNOWN, /* Unrecognized. */
155 /** Switch information returned by mlx5_nl_switch_info(). */
156 struct mlx5_switch_info {
157 uint32_t master:1; /**< Master device. */
158 uint32_t representor:1; /**< Representor device. */
159 enum mlx5_nl_phys_port_name_type name_type; /** < Port name type. */
160 int32_t pf_num; /**< PF number (valid for pfxvfx format only). */
161 int32_t port_name; /**< Representor port name. */
162 uint64_t switch_id; /**< Switch identifier. */
166 enum mlx5_cqe_status {
167 MLX5_CQE_STATUS_SW_OWN = -1,
168 MLX5_CQE_STATUS_HW_OWN = -2,
169 MLX5_CQE_STATUS_ERR = -3,
173 * Check whether CQE is valid.
178 * Size of completion queue.
185 static __rte_always_inline enum mlx5_cqe_status
186 check_cqe(volatile struct mlx5_cqe *cqe, const uint16_t cqes_n,
189 const uint16_t idx = ci & cqes_n;
190 const uint8_t op_own = cqe->op_own;
191 const uint8_t op_owner = MLX5_CQE_OWNER(op_own);
192 const uint8_t op_code = MLX5_CQE_OPCODE(op_own);
194 if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
195 return MLX5_CQE_STATUS_HW_OWN;
197 if (unlikely(op_code == MLX5_CQE_RESP_ERR ||
198 op_code == MLX5_CQE_REQ_ERR))
199 return MLX5_CQE_STATUS_ERR;
200 return MLX5_CQE_STATUS_SW_OWN;
204 int mlx5_dev_to_pci_addr(const char *dev_path, struct rte_pci_addr *pci_addr);
206 int mlx5_get_ifname_sysfs(const char *ibdev_path, char *ifname);
209 #define MLX5_CLASS_ARG_NAME "class"
213 MLX5_CLASS_NET = RTE_BIT64(0),
214 MLX5_CLASS_VDPA = RTE_BIT64(1),
215 MLX5_CLASS_REGEX = RTE_BIT64(2),
218 #define MLX5_DBR_SIZE RTE_CACHE_LINE_SIZE
219 #define MLX5_DBR_PER_PAGE 64
220 /* Must be >= CHAR_BIT * sizeof(uint64_t) */
221 #define MLX5_DBR_PAGE_SIZE (MLX5_DBR_PER_PAGE * MLX5_DBR_SIZE)
222 /* Page size must be >= 512. */
223 #define MLX5_DBR_BITMAP_SIZE (MLX5_DBR_PER_PAGE / (CHAR_BIT * sizeof(uint64_t)))
225 struct mlx5_devx_dbr_page {
226 /* Door-bell records, must be first member in structure. */
227 uint8_t dbrs[MLX5_DBR_PAGE_SIZE];
228 LIST_ENTRY(mlx5_devx_dbr_page) next; /* Pointer to the next element. */
230 uint32_t dbr_count; /* Number of door-bell records in use. */
231 /* 1 bit marks matching door-bell is in use. */
232 uint64_t dbr_bitmap[MLX5_DBR_BITMAP_SIZE];
235 /* devX creation object */
236 struct mlx5_devx_obj {
237 void *obj; /* The DV object. */
238 int id; /* The object ID. */
241 /* UMR memory buffer used to define 1 entry in indirect mkey. */
248 LIST_HEAD(mlx5_dbr_page_list, mlx5_devx_dbr_page);
251 void mlx5_translate_port_name(const char *port_name_in,
252 struct mlx5_switch_info *port_info_out);
253 void mlx5_glue_constructor(void);
255 int64_t mlx5_get_dbr(void *ctx, struct mlx5_dbr_page_list *head,
256 struct mlx5_devx_dbr_page **dbr_page);
258 int32_t mlx5_release_dbr(struct mlx5_dbr_page_list *head, uint32_t umem_id,
260 extern uint8_t haswell_broadwell_cpu;
263 void mlx5_common_init(void);
265 #endif /* RTE_PMD_MLX5_COMMON_H_ */