1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2019 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_COMMON_H_
6 #define RTE_PMD_MLX5_COMMON_H_
11 #include <rte_debug.h>
12 #include <rte_atomic.h>
14 #include <rte_kvargs.h>
15 #include <rte_devargs.h>
16 #include <rte_bitops.h>
17 #include <rte_os_shim.h>
20 #include "mlx5_devx_cmds.h"
21 #include "mlx5_common_os.h"
23 /* Reported driver name. */
24 #define MLX5_PCI_DRIVER_NAME "mlx5_pci"
26 /* Bit-field manipulation. */
27 #define BITFIELD_DECLARE(bf, type, size) \
28 type bf[(((size_t)(size) / (sizeof(type) * CHAR_BIT)) + \
29 !!((size_t)(size) % (sizeof(type) * CHAR_BIT)))]
30 #define BITFIELD_DEFINE(bf, type, size) \
31 BITFIELD_DECLARE((bf), type, (size)) = { 0 }
32 #define BITFIELD_SET(bf, b) \
33 (void)((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] |= \
34 ((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT))))
35 #define BITFIELD_RESET(bf, b) \
36 (void)((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] &= \
37 ~((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT))))
38 #define BITFIELD_ISSET(bf, b) \
39 !!(((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] & \
40 ((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT)))))
43 * Helper macros to work around __VA_ARGS__ limitations in a C99 compliant
46 #define PMD_DRV_LOG_STRIP(a, b) a
47 #define PMD_DRV_LOG_OPAREN (
48 #define PMD_DRV_LOG_CPAREN )
49 #define PMD_DRV_LOG_COMMA ,
51 /* Return the file name part of a path. */
52 static inline const char *
53 pmd_drv_log_basename(const char *s)
63 #define PMD_DRV_LOG___(level, type, name, ...) \
64 rte_log(RTE_LOG_ ## level, \
67 RTE_FMT_HEAD(__VA_ARGS__,), \
68 RTE_FMT_TAIL(__VA_ARGS__,)))
70 #ifdef RTE_LIBRTE_MLX5_DEBUG
72 #define PMD_DRV_LOG__(level, type, name, ...) \
73 PMD_DRV_LOG___(level, type, name, "%s:%u: %s(): " __VA_ARGS__)
74 #define PMD_DRV_LOG_(level, type, name, s, ...) \
75 PMD_DRV_LOG__(level, type, name,\
76 s "\n" PMD_DRV_LOG_COMMA \
77 pmd_drv_log_basename(__FILE__) PMD_DRV_LOG_COMMA \
78 __LINE__ PMD_DRV_LOG_COMMA \
82 #else /* RTE_LIBRTE_MLX5_DEBUG */
83 #define PMD_DRV_LOG__(level, type, name, ...) \
84 PMD_DRV_LOG___(level, type, name, __VA_ARGS__)
85 #define PMD_DRV_LOG_(level, type, name, s, ...) \
86 PMD_DRV_LOG__(level, type, name, s "\n", __VA_ARGS__)
88 #endif /* RTE_LIBRTE_MLX5_DEBUG */
90 /* claim_zero() does not perform any check when debugging is disabled. */
91 #ifdef RTE_LIBRTE_MLX5_DEBUG
93 #define MLX5_ASSERT(exp) RTE_VERIFY(exp)
94 #define claim_zero(...) MLX5_ASSERT((__VA_ARGS__) == 0)
95 #define claim_nonzero(...) MLX5_ASSERT((__VA_ARGS__) != 0)
97 #else /* RTE_LIBRTE_MLX5_DEBUG */
99 #define MLX5_ASSERT(exp) RTE_ASSERT(exp)
100 #define claim_zero(...) (__VA_ARGS__)
101 #define claim_nonzero(...) (__VA_ARGS__)
103 #endif /* RTE_LIBRTE_MLX5_DEBUG */
105 /* Allocate a buffer on the stack and fill it with a printf format string. */
106 #define MKSTR(name, ...) \
107 int mkstr_size_##name = snprintf(NULL, 0, "" __VA_ARGS__); \
108 char name[mkstr_size_##name + 1]; \
110 snprintf(name, sizeof(name), "" __VA_ARGS__)
113 PCI_VENDOR_ID_MELLANOX = 0x15b3,
117 PCI_DEVICE_ID_MELLANOX_CONNECTX4 = 0x1013,
118 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF = 0x1014,
119 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX = 0x1015,
120 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF = 0x1016,
121 PCI_DEVICE_ID_MELLANOX_CONNECTX5 = 0x1017,
122 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF = 0x1018,
123 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX = 0x1019,
124 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF = 0x101a,
125 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF = 0xa2d2,
126 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF = 0xa2d3,
127 PCI_DEVICE_ID_MELLANOX_CONNECTX6 = 0x101b,
128 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF = 0x101c,
129 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX = 0x101d,
130 PCI_DEVICE_ID_MELLANOX_CONNECTXVF = 0x101e,
131 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF = 0xa2d6,
132 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX = 0x101f,
133 PCI_DEVICE_ID_MELLANOX_CONNECTX7 = 0x1021,
134 PCI_DEVICE_ID_MELLANOX_CONNECTX7BF = 0Xa2dc,
137 /* Maximum number of simultaneous unicast MAC addresses. */
138 #define MLX5_MAX_UC_MAC_ADDRESSES 128
139 /* Maximum number of simultaneous Multicast MAC addresses. */
140 #define MLX5_MAX_MC_MAC_ADDRESSES 128
141 /* Maximum number of simultaneous MAC addresses. */
142 #define MLX5_MAX_MAC_ADDRESSES \
143 (MLX5_MAX_UC_MAC_ADDRESSES + MLX5_MAX_MC_MAC_ADDRESSES)
145 /* Recognized Infiniband device physical port name types. */
146 enum mlx5_nl_phys_port_name_type {
147 MLX5_PHYS_PORT_NAME_TYPE_NOTSET = 0, /* Not set. */
148 MLX5_PHYS_PORT_NAME_TYPE_LEGACY, /* before kernel ver < 5.0 */
149 MLX5_PHYS_PORT_NAME_TYPE_UPLINK, /* p0, kernel ver >= 5.0 */
150 MLX5_PHYS_PORT_NAME_TYPE_PFVF, /* pf0vf0, kernel ver >= 5.0 */
151 MLX5_PHYS_PORT_NAME_TYPE_PFHPF, /* pf0, kernel ver >= 5.7, HPF rep */
152 MLX5_PHYS_PORT_NAME_TYPE_PFSF, /* pf0sf0, kernel ver >= 5.0 */
153 MLX5_PHYS_PORT_NAME_TYPE_UNKNOWN, /* Unrecognized. */
156 /** Switch information returned by mlx5_nl_switch_info(). */
157 struct mlx5_switch_info {
158 uint32_t master:1; /**< Master device. */
159 uint32_t representor:1; /**< Representor device. */
160 enum mlx5_nl_phys_port_name_type name_type; /** < Port name type. */
161 int32_t ctrl_num; /**< Controller number (valid for c#pf#vf# format). */
162 int32_t pf_num; /**< PF number (valid for pfxvfx format only). */
163 int32_t port_name; /**< Representor port name. */
164 uint64_t switch_id; /**< Switch identifier. */
168 enum mlx5_cqe_status {
169 MLX5_CQE_STATUS_SW_OWN = -1,
170 MLX5_CQE_STATUS_HW_OWN = -2,
171 MLX5_CQE_STATUS_ERR = -3,
175 * Check whether CQE is valid.
180 * Size of completion queue.
187 static __rte_always_inline enum mlx5_cqe_status
188 check_cqe(volatile struct mlx5_cqe *cqe, const uint16_t cqes_n,
191 const uint16_t idx = ci & cqes_n;
192 const uint8_t op_own = cqe->op_own;
193 const uint8_t op_owner = MLX5_CQE_OWNER(op_own);
194 const uint8_t op_code = MLX5_CQE_OPCODE(op_own);
196 if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
197 return MLX5_CQE_STATUS_HW_OWN;
199 if (unlikely(op_code == MLX5_CQE_RESP_ERR ||
200 op_code == MLX5_CQE_REQ_ERR))
201 return MLX5_CQE_STATUS_ERR;
202 return MLX5_CQE_STATUS_SW_OWN;
206 int mlx5_dev_to_pci_addr(const char *dev_path, struct rte_pci_addr *pci_addr);
208 int mlx5_get_ifname_sysfs(const char *ibdev_path, char *ifname);
213 MLX5_CLASS_NET = RTE_BIT64(0),
214 MLX5_CLASS_VDPA = RTE_BIT64(1),
215 MLX5_CLASS_REGEX = RTE_BIT64(2),
216 MLX5_CLASS_COMPRESS = RTE_BIT64(3),
219 #define MLX5_DBR_SIZE RTE_CACHE_LINE_SIZE
221 /* devX creation object */
222 struct mlx5_devx_obj {
223 void *obj; /* The DV object. */
224 int id; /* The object ID. */
227 /* UMR memory buffer used to define 1 entry in indirect mkey. */
235 void mlx5_translate_port_name(const char *port_name_in,
236 struct mlx5_switch_info *port_info_out);
237 void mlx5_glue_constructor(void);
239 void *mlx5_devx_alloc_uar(void *ctx, int mapping);
240 extern uint8_t haswell_broadwell_cpu;
243 void mlx5_common_init(void);
245 #endif /* RTE_PMD_MLX5_COMMON_H_ */