1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2019 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_COMMON_H_
6 #define RTE_PMD_MLX5_COMMON_H_
11 #include <rte_debug.h>
12 #include <rte_atomic.h>
14 #include <rte_kvargs.h>
15 #include <rte_devargs.h>
16 #include <rte_bitops.h>
17 #include <rte_lcore.h>
18 #include <rte_spinlock.h>
19 #include <rte_os_shim.h>
22 #include "mlx5_devx_cmds.h"
23 #include "mlx5_common_os.h"
25 /* Reported driver name. */
26 #define MLX5_PCI_DRIVER_NAME "mlx5_pci"
28 /* Bit-field manipulation. */
29 #define BITFIELD_DECLARE(bf, type, size) \
30 type bf[(((size_t)(size) / (sizeof(type) * CHAR_BIT)) + \
31 !!((size_t)(size) % (sizeof(type) * CHAR_BIT)))]
32 #define BITFIELD_DEFINE(bf, type, size) \
33 BITFIELD_DECLARE((bf), type, (size)) = { 0 }
34 #define BITFIELD_SET(bf, b) \
35 (void)((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] |= \
36 ((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT))))
37 #define BITFIELD_RESET(bf, b) \
38 (void)((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] &= \
39 ~((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT))))
40 #define BITFIELD_ISSET(bf, b) \
41 !!(((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] & \
42 ((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT)))))
45 * Helper macros to work around __VA_ARGS__ limitations in a C99 compliant
48 #define PMD_DRV_LOG_STRIP(a, b) a
49 #define PMD_DRV_LOG_OPAREN (
50 #define PMD_DRV_LOG_CPAREN )
51 #define PMD_DRV_LOG_COMMA ,
53 /* Return the file name part of a path. */
54 static inline const char *
55 pmd_drv_log_basename(const char *s)
65 #define PMD_DRV_LOG___(level, type, name, ...) \
66 rte_log(RTE_LOG_ ## level, \
69 RTE_FMT_HEAD(__VA_ARGS__,), \
70 RTE_FMT_TAIL(__VA_ARGS__,)))
72 #ifdef RTE_LIBRTE_MLX5_DEBUG
74 #define PMD_DRV_LOG__(level, type, name, ...) \
75 PMD_DRV_LOG___(level, type, name, "%s:%u: %s(): " __VA_ARGS__)
76 #define PMD_DRV_LOG_(level, type, name, s, ...) \
77 PMD_DRV_LOG__(level, type, name,\
78 s "\n" PMD_DRV_LOG_COMMA \
79 pmd_drv_log_basename(__FILE__) PMD_DRV_LOG_COMMA \
80 __LINE__ PMD_DRV_LOG_COMMA \
84 #else /* RTE_LIBRTE_MLX5_DEBUG */
85 #define PMD_DRV_LOG__(level, type, name, ...) \
86 PMD_DRV_LOG___(level, type, name, __VA_ARGS__)
87 #define PMD_DRV_LOG_(level, type, name, s, ...) \
88 PMD_DRV_LOG__(level, type, name, s "\n", __VA_ARGS__)
90 #endif /* RTE_LIBRTE_MLX5_DEBUG */
92 /* claim_zero() does not perform any check when debugging is disabled. */
93 #ifdef RTE_LIBRTE_MLX5_DEBUG
95 #define MLX5_ASSERT(exp) RTE_VERIFY(exp)
96 #define claim_zero(...) MLX5_ASSERT((__VA_ARGS__) == 0)
97 #define claim_nonzero(...) MLX5_ASSERT((__VA_ARGS__) != 0)
99 #else /* RTE_LIBRTE_MLX5_DEBUG */
101 #define MLX5_ASSERT(exp) RTE_ASSERT(exp)
102 #define claim_zero(...) (__VA_ARGS__)
103 #define claim_nonzero(...) (__VA_ARGS__)
105 #endif /* RTE_LIBRTE_MLX5_DEBUG */
107 /* Allocate a buffer on the stack and fill it with a printf format string. */
108 #define MKSTR(name, ...) \
109 int mkstr_size_##name = snprintf(NULL, 0, "" __VA_ARGS__); \
110 char name[mkstr_size_##name + 1]; \
112 snprintf(name, sizeof(name), "" __VA_ARGS__)
115 PCI_VENDOR_ID_MELLANOX = 0x15b3,
119 PCI_DEVICE_ID_MELLANOX_CONNECTX4 = 0x1013,
120 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF = 0x1014,
121 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX = 0x1015,
122 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF = 0x1016,
123 PCI_DEVICE_ID_MELLANOX_CONNECTX5 = 0x1017,
124 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF = 0x1018,
125 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX = 0x1019,
126 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF = 0x101a,
127 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF = 0xa2d2,
128 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF = 0xa2d3,
129 PCI_DEVICE_ID_MELLANOX_CONNECTX6 = 0x101b,
130 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF = 0x101c,
131 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX = 0x101d,
132 PCI_DEVICE_ID_MELLANOX_CONNECTXVF = 0x101e,
133 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF = 0xa2d6,
134 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX = 0x101f,
135 PCI_DEVICE_ID_MELLANOX_CONNECTX7 = 0x1021,
136 PCI_DEVICE_ID_MELLANOX_CONNECTX7BF = 0Xa2dc,
139 /* Maximum number of simultaneous unicast MAC addresses. */
140 #define MLX5_MAX_UC_MAC_ADDRESSES 128
141 /* Maximum number of simultaneous Multicast MAC addresses. */
142 #define MLX5_MAX_MC_MAC_ADDRESSES 128
143 /* Maximum number of simultaneous MAC addresses. */
144 #define MLX5_MAX_MAC_ADDRESSES \
145 (MLX5_MAX_UC_MAC_ADDRESSES + MLX5_MAX_MC_MAC_ADDRESSES)
147 /* Recognized Infiniband device physical port name types. */
148 enum mlx5_nl_phys_port_name_type {
149 MLX5_PHYS_PORT_NAME_TYPE_NOTSET = 0, /* Not set. */
150 MLX5_PHYS_PORT_NAME_TYPE_LEGACY, /* before kernel ver < 5.0 */
151 MLX5_PHYS_PORT_NAME_TYPE_UPLINK, /* p0, kernel ver >= 5.0 */
152 MLX5_PHYS_PORT_NAME_TYPE_PFVF, /* pf0vf0, kernel ver >= 5.0 */
153 MLX5_PHYS_PORT_NAME_TYPE_PFHPF, /* pf0, kernel ver >= 5.7, HPF rep */
154 MLX5_PHYS_PORT_NAME_TYPE_PFSF, /* pf0sf0, kernel ver >= 5.0 */
155 MLX5_PHYS_PORT_NAME_TYPE_UNKNOWN, /* Unrecognized. */
158 /** Switch information returned by mlx5_nl_switch_info(). */
159 struct mlx5_switch_info {
160 uint32_t master:1; /**< Master device. */
161 uint32_t representor:1; /**< Representor device. */
162 enum mlx5_nl_phys_port_name_type name_type; /** < Port name type. */
163 int32_t ctrl_num; /**< Controller number (valid for c#pf#vf# format). */
164 int32_t pf_num; /**< PF number (valid for pfxvfx format only). */
165 int32_t port_name; /**< Representor port name. */
166 uint64_t switch_id; /**< Switch identifier. */
170 enum mlx5_cqe_status {
171 MLX5_CQE_STATUS_SW_OWN = -1,
172 MLX5_CQE_STATUS_HW_OWN = -2,
173 MLX5_CQE_STATUS_ERR = -3,
177 * Check whether CQE is valid.
182 * Size of completion queue.
189 static __rte_always_inline enum mlx5_cqe_status
190 check_cqe(volatile struct mlx5_cqe *cqe, const uint16_t cqes_n,
193 const uint16_t idx = ci & cqes_n;
194 const uint8_t op_own = cqe->op_own;
195 const uint8_t op_owner = MLX5_CQE_OWNER(op_own);
196 const uint8_t op_code = MLX5_CQE_OPCODE(op_own);
198 if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
199 return MLX5_CQE_STATUS_HW_OWN;
201 if (unlikely(op_code == MLX5_CQE_RESP_ERR ||
202 op_code == MLX5_CQE_REQ_ERR))
203 return MLX5_CQE_STATUS_ERR;
204 return MLX5_CQE_STATUS_SW_OWN;
208 int mlx5_dev_to_pci_addr(const char *dev_path, struct rte_pci_addr *pci_addr);
210 int mlx5_get_ifname_sysfs(const char *ibdev_path, char *ifname);
215 MLX5_CLASS_ETH = RTE_BIT64(0),
216 MLX5_CLASS_VDPA = RTE_BIT64(1),
217 MLX5_CLASS_REGEX = RTE_BIT64(2),
218 MLX5_CLASS_COMPRESS = RTE_BIT64(3),
219 MLX5_CLASS_CRYPTO = RTE_BIT64(4),
222 #define MLX5_DBR_SIZE RTE_CACHE_LINE_SIZE
224 /* devX creation object */
225 struct mlx5_devx_obj {
226 void *obj; /* The DV object. */
227 int id; /* The object ID. */
230 /* UMR memory buffer used to define 1 entry in indirect mkey. */
238 void mlx5_translate_port_name(const char *port_name_in,
239 struct mlx5_switch_info *port_info_out);
240 void mlx5_glue_constructor(void);
242 void *mlx5_devx_alloc_uar(void *ctx, int mapping);
243 extern uint8_t haswell_broadwell_cpu;
246 void mlx5_common_init(void);
249 * Common Driver Interface
251 * ConnectX common driver supports multiple classes: net, vDPA, regex, crypto
252 * and compress devices. This layer enables creating such multiple classes
253 * on a single device by allowing to bind multiple class-specific device
254 * drivers to attach to the common driver.
256 * ------------ ------------- -------------- ----------------- ------------
257 * | mlx5 net | | mlx5 vdpa | | mlx5 regex | | mlx5 compress | | mlx5 ... |
258 * | driver | | driver | | driver | | driver | | drivers |
259 * ------------ ------------- -------------- ----------------- ------------
266 * ----------- -----------------
268 * | pci dev | | auxiliary dev |
269 * ----------- -----------------
271 * - mlx5 PCI bus driver binds to mlx5 PCI devices defined by PCI ID table
272 * of all related devices.
273 * - mlx5 class driver such as net, vDPA, regex defines its specific
274 * PCI ID table and mlx5 bus driver probes matching class drivers.
275 * - mlx5 common driver is central place that validates supported
276 * class combinations.
277 * - mlx5 common driver hides bus difference by resolving device address
278 * from devargs, locating target RDMA device and probing with it.
282 * Initialization function for the driver called during device probing.
284 typedef int (mlx5_class_driver_probe_t)(struct rte_device *dev);
287 * Uninitialization function for the driver called during hot-unplugging.
289 typedef int (mlx5_class_driver_remove_t)(struct rte_device *dev);
292 * Driver-specific DMA mapping. After a successful call the device
293 * will be able to read/write from/to this segment.
296 * Pointer to the device.
298 * Starting virtual address of memory to be mapped.
300 * Starting IOVA address of memory to be mapped.
302 * Length of memory segment being mapped.
305 * - Negative value and rte_errno is set otherwise.
307 typedef int (mlx5_class_driver_dma_map_t)(struct rte_device *dev, void *addr,
308 uint64_t iova, size_t len);
311 * Driver-specific DMA un-mapping. After a successful call the device
312 * will not be able to read/write from/to this segment.
315 * Pointer to the device.
317 * Starting virtual address of memory to be unmapped.
319 * Starting IOVA address of memory to be unmapped.
321 * Length of memory segment being unmapped.
324 * - Negative value and rte_errno is set otherwise.
326 typedef int (mlx5_class_driver_dma_unmap_t)(struct rte_device *dev, void *addr,
327 uint64_t iova, size_t len);
329 /** Device already probed can be probed again to check for new ports. */
330 #define MLX5_DRV_PROBE_AGAIN 0x0004
333 * A structure describing a mlx5 common class driver.
335 struct mlx5_class_driver {
336 TAILQ_ENTRY(mlx5_class_driver) next;
337 enum mlx5_class drv_class; /**< Class of this driver. */
338 const char *name; /**< Driver name. */
339 mlx5_class_driver_probe_t *probe; /**< Device probe function. */
340 mlx5_class_driver_remove_t *remove; /**< Device remove function. */
341 mlx5_class_driver_dma_map_t *dma_map; /**< Device DMA map function. */
342 mlx5_class_driver_dma_unmap_t *dma_unmap;
343 /**< Device DMA unmap function. */
344 const struct rte_pci_id *id_table; /**< ID table, NULL terminated. */
345 uint32_t probe_again:1;
346 /**< Device already probed can be probed again to check new device. */
347 uint32_t intr_lsc:1; /**< Supports link state interrupt. */
348 uint32_t intr_rmv:1; /**< Supports device remove interrupt. */
352 * Register a mlx5 device driver.
355 * A pointer to a mlx5_driver structure describing the driver
360 mlx5_class_driver_register(struct mlx5_class_driver *driver);
363 * Test device is a PCI bus device.
369 * - True on device devargs is a PCI bus device.
374 mlx5_dev_is_pci(const struct rte_device *dev);
376 #endif /* RTE_PMD_MLX5_COMMON_H_ */