1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2019 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_COMMON_H_
6 #define RTE_PMD_MLX5_COMMON_H_
12 #include <rte_atomic.h>
19 * Helper macros to work around __VA_ARGS__ limitations in a C99 compliant
22 #define PMD_DRV_LOG_STRIP(a, b) a
23 #define PMD_DRV_LOG_OPAREN (
24 #define PMD_DRV_LOG_CPAREN )
25 #define PMD_DRV_LOG_COMMA ,
27 /* Return the file name part of a path. */
28 static inline const char *
29 pmd_drv_log_basename(const char *s)
39 #define PMD_DRV_LOG___(level, type, name, ...) \
40 rte_log(RTE_LOG_ ## level, \
43 RTE_FMT_HEAD(__VA_ARGS__,), \
44 RTE_FMT_TAIL(__VA_ARGS__,)))
47 * When debugging is enabled (NDEBUG not defined), file, line and function
48 * information replace the driver name (MLX5_DRIVER_NAME) in log messages.
52 #define PMD_DRV_LOG__(level, type, name, ...) \
53 PMD_DRV_LOG___(level, type, name, "%s:%u: %s(): " __VA_ARGS__)
54 #define PMD_DRV_LOG_(level, type, name, s, ...) \
55 PMD_DRV_LOG__(level, type, name,\
56 s "\n" PMD_DRV_LOG_COMMA \
57 pmd_drv_log_basename(__FILE__) PMD_DRV_LOG_COMMA \
58 __LINE__ PMD_DRV_LOG_COMMA \
63 #define PMD_DRV_LOG__(level, type, name, ...) \
64 PMD_DRV_LOG___(level, type, name, __VA_ARGS__)
65 #define PMD_DRV_LOG_(level, type, name, s, ...) \
66 PMD_DRV_LOG__(level, type, name, s "\n", __VA_ARGS__)
70 /* claim_zero() does not perform any check when debugging is disabled. */
73 #define DEBUG(...) DRV_LOG(DEBUG, __VA_ARGS__)
74 #define claim_zero(...) assert((__VA_ARGS__) == 0)
75 #define claim_nonzero(...) assert((__VA_ARGS__) != 0)
79 #define DEBUG(...) (void)0
80 #define claim_zero(...) (__VA_ARGS__)
81 #define claim_nonzero(...) (__VA_ARGS__)
85 /* Allocate a buffer on the stack and fill it with a printf format string. */
86 #define MKSTR(name, ...) \
87 int mkstr_size_##name = snprintf(NULL, 0, "" __VA_ARGS__); \
88 char name[mkstr_size_##name + 1]; \
90 snprintf(name, sizeof(name), "" __VA_ARGS__)
93 PCI_VENDOR_ID_MELLANOX = 0x15b3,
97 PCI_DEVICE_ID_MELLANOX_CONNECTX4 = 0x1013,
98 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF = 0x1014,
99 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX = 0x1015,
100 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF = 0x1016,
101 PCI_DEVICE_ID_MELLANOX_CONNECTX5 = 0x1017,
102 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF = 0x1018,
103 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX = 0x1019,
104 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF = 0x101a,
105 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF = 0xa2d2,
106 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF = 0xa2d3,
107 PCI_DEVICE_ID_MELLANOX_CONNECTX6 = 0x101b,
108 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF = 0x101c,
109 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX = 0x101d,
110 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF = 0x101e,
114 enum mlx5_cqe_status {
115 MLX5_CQE_STATUS_SW_OWN = -1,
116 MLX5_CQE_STATUS_HW_OWN = -2,
117 MLX5_CQE_STATUS_ERR = -3,
121 * Check whether CQE is valid.
126 * Size of completion queue.
133 static __rte_always_inline enum mlx5_cqe_status
134 check_cqe(volatile struct mlx5_cqe *cqe, const uint16_t cqes_n,
137 const uint16_t idx = ci & cqes_n;
138 const uint8_t op_own = cqe->op_own;
139 const uint8_t op_owner = MLX5_CQE_OWNER(op_own);
140 const uint8_t op_code = MLX5_CQE_OPCODE(op_own);
142 if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
143 return MLX5_CQE_STATUS_HW_OWN;
145 if (unlikely(op_code == MLX5_CQE_RESP_ERR ||
146 op_code == MLX5_CQE_REQ_ERR))
147 return MLX5_CQE_STATUS_ERR;
148 return MLX5_CQE_STATUS_SW_OWN;
151 int mlx5_dev_to_pci_addr(const char *dev_path, struct rte_pci_addr *pci_addr);
153 #endif /* RTE_PMD_MLX5_COMMON_H_ */