1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2019 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_COMMON_H_
6 #define RTE_PMD_MLX5_COMMON_H_
11 #include <rte_debug.h>
12 #include <rte_atomic.h>
14 #include <rte_kvargs.h>
15 #include <rte_devargs.h>
20 /* Bit-field manipulation. */
21 #define BITFIELD_DECLARE(bf, type, size) \
22 type bf[(((size_t)(size) / (sizeof(type) * CHAR_BIT)) + \
23 !!((size_t)(size) % (sizeof(type) * CHAR_BIT)))]
24 #define BITFIELD_DEFINE(bf, type, size) \
25 BITFIELD_DECLARE((bf), type, (size)) = { 0 }
26 #define BITFIELD_SET(bf, b) \
27 (void)((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] |= \
28 ((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT))))
29 #define BITFIELD_RESET(bf, b) \
30 (void)((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] &= \
31 ~((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT))))
32 #define BITFIELD_ISSET(bf, b) \
33 !!(((bf)[((b) / (sizeof((bf)[0]) * CHAR_BIT))] & \
34 ((size_t)1 << ((b) % (sizeof((bf)[0]) * CHAR_BIT)))))
37 * Helper macros to work around __VA_ARGS__ limitations in a C99 compliant
40 #define PMD_DRV_LOG_STRIP(a, b) a
41 #define PMD_DRV_LOG_OPAREN (
42 #define PMD_DRV_LOG_CPAREN )
43 #define PMD_DRV_LOG_COMMA ,
45 /* Return the file name part of a path. */
46 static inline const char *
47 pmd_drv_log_basename(const char *s)
57 #define PMD_DRV_LOG___(level, type, name, ...) \
58 rte_log(RTE_LOG_ ## level, \
61 RTE_FMT_HEAD(__VA_ARGS__,), \
62 RTE_FMT_TAIL(__VA_ARGS__,)))
65 * When debugging is enabled (MLX5_DEBUG not defined), file, line and function
66 * information replace the driver name (MLX5_DRIVER_NAME) in log messages.
68 #ifdef RTE_LIBRTE_MLX5_DEBUG
70 #define PMD_DRV_LOG__(level, type, name, ...) \
71 PMD_DRV_LOG___(level, type, name, "%s:%u: %s(): " __VA_ARGS__)
72 #define PMD_DRV_LOG_(level, type, name, s, ...) \
73 PMD_DRV_LOG__(level, type, name,\
74 s "\n" PMD_DRV_LOG_COMMA \
75 pmd_drv_log_basename(__FILE__) PMD_DRV_LOG_COMMA \
76 __LINE__ PMD_DRV_LOG_COMMA \
80 #else /* RTE_LIBRTE_MLX5_DEBUG */
81 #define PMD_DRV_LOG__(level, type, name, ...) \
82 PMD_DRV_LOG___(level, type, name, __VA_ARGS__)
83 #define PMD_DRV_LOG_(level, type, name, s, ...) \
84 PMD_DRV_LOG__(level, type, name, s "\n", __VA_ARGS__)
86 #endif /* RTE_LIBRTE_MLX5_DEBUG */
88 /* claim_zero() does not perform any check when debugging is disabled. */
89 #ifdef RTE_LIBRTE_MLX5_DEBUG
91 #define DEBUG(...) DRV_LOG(DEBUG, __VA_ARGS__)
92 #define MLX5_ASSERT(exp) RTE_VERIFY(exp)
93 #define claim_zero(...) MLX5_ASSERT((__VA_ARGS__) == 0)
94 #define claim_nonzero(...) MLX5_ASSERT((__VA_ARGS__) != 0)
96 #else /* RTE_LIBRTE_MLX5_DEBUG */
98 #define DEBUG(...) (void)0
99 #define MLX5_ASSERT(exp) RTE_ASSERT(exp)
100 #define claim_zero(...) (__VA_ARGS__)
101 #define claim_nonzero(...) (__VA_ARGS__)
103 #endif /* RTE_LIBRTE_MLX5_DEBUG */
105 /* Allocate a buffer on the stack and fill it with a printf format string. */
106 #define MKSTR(name, ...) \
107 int mkstr_size_##name = snprintf(NULL, 0, "" __VA_ARGS__); \
108 char name[mkstr_size_##name + 1]; \
110 snprintf(name, sizeof(name), "" __VA_ARGS__)
113 PCI_VENDOR_ID_MELLANOX = 0x15b3,
117 PCI_DEVICE_ID_MELLANOX_CONNECTX4 = 0x1013,
118 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF = 0x1014,
119 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX = 0x1015,
120 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF = 0x1016,
121 PCI_DEVICE_ID_MELLANOX_CONNECTX5 = 0x1017,
122 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF = 0x1018,
123 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX = 0x1019,
124 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF = 0x101a,
125 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF = 0xa2d2,
126 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF = 0xa2d3,
127 PCI_DEVICE_ID_MELLANOX_CONNECTX6 = 0x101b,
128 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF = 0x101c,
129 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX = 0x101d,
130 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF = 0x101e,
131 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF = 0xa2d6,
134 /* Maximum number of simultaneous unicast MAC addresses. */
135 #define MLX5_MAX_UC_MAC_ADDRESSES 128
136 /* Maximum number of simultaneous Multicast MAC addresses. */
137 #define MLX5_MAX_MC_MAC_ADDRESSES 128
138 /* Maximum number of simultaneous MAC addresses. */
139 #define MLX5_MAX_MAC_ADDRESSES \
140 (MLX5_MAX_UC_MAC_ADDRESSES + MLX5_MAX_MC_MAC_ADDRESSES)
142 /* Recognized Infiniband device physical port name types. */
143 enum mlx5_nl_phys_port_name_type {
144 MLX5_PHYS_PORT_NAME_TYPE_NOTSET = 0, /* Not set. */
145 MLX5_PHYS_PORT_NAME_TYPE_LEGACY, /* before kernel ver < 5.0 */
146 MLX5_PHYS_PORT_NAME_TYPE_UPLINK, /* p0, kernel ver >= 5.0 */
147 MLX5_PHYS_PORT_NAME_TYPE_PFVF, /* pf0vf0, kernel ver >= 5.0 */
148 MLX5_PHYS_PORT_NAME_TYPE_UNKNOWN, /* Unrecognized. */
151 /** Switch information returned by mlx5_nl_switch_info(). */
152 struct mlx5_switch_info {
153 uint32_t master:1; /**< Master device. */
154 uint32_t representor:1; /**< Representor device. */
155 enum mlx5_nl_phys_port_name_type name_type; /** < Port name type. */
156 int32_t pf_num; /**< PF number (valid for pfxvfx format only). */
157 int32_t port_name; /**< Representor port name. */
158 uint64_t switch_id; /**< Switch identifier. */
162 enum mlx5_cqe_status {
163 MLX5_CQE_STATUS_SW_OWN = -1,
164 MLX5_CQE_STATUS_HW_OWN = -2,
165 MLX5_CQE_STATUS_ERR = -3,
169 * Check whether CQE is valid.
174 * Size of completion queue.
181 static __rte_always_inline enum mlx5_cqe_status
182 check_cqe(volatile struct mlx5_cqe *cqe, const uint16_t cqes_n,
185 const uint16_t idx = ci & cqes_n;
186 const uint8_t op_own = cqe->op_own;
187 const uint8_t op_owner = MLX5_CQE_OWNER(op_own);
188 const uint8_t op_code = MLX5_CQE_OPCODE(op_own);
190 if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
191 return MLX5_CQE_STATUS_HW_OWN;
193 if (unlikely(op_code == MLX5_CQE_RESP_ERR ||
194 op_code == MLX5_CQE_REQ_ERR))
195 return MLX5_CQE_STATUS_ERR;
196 return MLX5_CQE_STATUS_SW_OWN;
199 int mlx5_dev_to_pci_addr(const char *dev_path, struct rte_pci_addr *pci_addr);
201 #define MLX5_CLASS_ARG_NAME "class"
209 enum mlx5_class mlx5_class_get(struct rte_devargs *devargs);
210 void mlx5_translate_port_name(const char *port_name_in,
211 struct mlx5_switch_info *port_info_out);
213 #endif /* RTE_PMD_MLX5_COMMON_H_ */