1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 6WIND S.A.
3 * Copyright 2018 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_COMMON_MR_H_
7 #define RTE_PMD_MLX5_COMMON_MR_H_
11 #include <sys/queue.h>
14 #include <rte_rwlock.h>
15 #include <rte_bitmap.h>
17 #include <rte_memory.h>
19 #include "mlx5_glue.h"
20 #include "mlx5_common_mp.h"
21 #include "mlx5_common_defs.h"
23 /* mlx5 PMD MR struct. */
28 void *obj; /* verbs mr object or devx umem object. */
29 struct mlx5_devx_obj *mkey; /* devx mkey object. */
33 * mr operations typedef
35 typedef int (*mlx5_reg_mr_t)(void *pd, void *addr, size_t length,
36 struct mlx5_pmd_mr *pmd_mr);
37 typedef void (*mlx5_dereg_mr_t)(struct mlx5_pmd_mr *pmd_mr);
39 /* Memory Region object. */
41 LIST_ENTRY(mlx5_mr) mr; /**< Pointer to the prev/next entry. */
42 struct mlx5_pmd_mr pmd_mr; /* PMD memory region. */
43 const struct rte_memseg_list *msl;
44 int ms_base_idx; /* Start index of msl->memseg_arr[]. */
45 int ms_n; /* Number of memsegs in use. */
46 uint32_t ms_bmp_n; /* Number of bits in memsegs bit-mask. */
47 struct rte_bitmap *ms_bmp; /* Bit-mask of memsegs belonged to MR. */
50 /* Cache entry for Memory Region. */
51 struct mr_cache_entry {
52 uintptr_t start; /* Start address of MR. */
53 uintptr_t end; /* End address of MR. */
54 uint32_t lkey; /* rte_cpu_to_be_32(lkey). */
57 /* MR Cache table for Binary search. */
58 struct mlx5_mr_btree {
59 uint16_t len; /* Number of entries. */
60 uint16_t size; /* Total number of entries. */
61 int overflow; /* Mark failure of table expansion. */
62 struct mr_cache_entry (*table)[];
65 struct mlx5_common_device;
67 /* Per-queue MR control descriptor. */
69 struct mlx5_common_device *cdev; /* Pointer to the mlx5 common device.*/
70 uint32_t *dev_gen_ptr; /* Generation number of device to poll. */
71 uint32_t cur_gen; /* Generation number saved to flush caches. */
72 uint16_t mru; /* Index of last hit entry in top-half cache. */
73 uint16_t head; /* Index of the oldest entry in top-half cache. */
74 struct mr_cache_entry cache[MLX5_MR_CACHE_N]; /* Cache for top-half. */
75 struct mlx5_mr_btree cache_bh; /* Cache for bottom-half. */
78 LIST_HEAD(mlx5_mr_list, mlx5_mr);
79 LIST_HEAD(mlx5_mempool_reg_list, mlx5_mempool_reg);
81 /* Global per-device MR cache. */
82 struct mlx5_mr_share_cache {
83 uint32_t dev_gen; /* Generation number to flush local caches. */
84 rte_rwlock_t rwlock; /* MR cache Lock. */
85 rte_rwlock_t mprwlock; /* Mempool Registration Lock. */
86 uint8_t mp_cb_registered; /* Mempool are Registered. */
87 struct mlx5_mr_btree cache; /* Global MR cache table. */
88 struct mlx5_mr_list mr_list; /* Registered MR list. */
89 struct mlx5_mr_list mr_free_list; /* Freed MR list. */
90 struct mlx5_mempool_reg_list mempool_reg_list; /* Mempool database. */
91 mlx5_reg_mr_t reg_mr_cb; /* Callback to reg_mr func */
92 mlx5_dereg_mr_t dereg_mr_cb; /* Callback to dereg_mr func */
95 /* Multi-Packet RQ buffer header. */
96 struct mlx5_mprq_buf {
97 struct rte_mempool *mp;
98 uint16_t refcnt; /* Atomically accessed refcnt. */
99 struct rte_mbuf_ext_shared_info shinfos[];
101 * Shared information per stride.
102 * More memory will be allocated for the first stride head-room and for
105 } __rte_cache_aligned;
108 void mlx5_mprq_buf_free_cb(void *addr, void *opaque);
111 * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which the
112 * cloned mbuf is allocated is returned instead.
118 * Memory pool where data is located for given mbuf.
120 static inline struct rte_mempool *
121 mlx5_mb2mp(struct rte_mbuf *buf)
123 if (unlikely(RTE_MBUF_CLONED(buf)))
124 return rte_mbuf_from_indirect(buf)->pool;
129 * Look up LKey from given lookup table by linear search. Firstly look up the
130 * last-hit entry. If miss, the entire array is searched. If found, update the
131 * last-hit index and return LKey.
134 * Pointer to lookup table.
135 * @param[in,out] cached_idx
136 * Pointer to last-hit index.
138 * Size of lookup table.
143 * Searched LKey on success, UINT32_MAX on no match.
145 static __rte_always_inline uint32_t
146 mlx5_mr_lookup_lkey(struct mr_cache_entry *lkp_tbl, uint16_t *cached_idx,
147 uint16_t n, uintptr_t addr)
151 if (likely(addr >= lkp_tbl[*cached_idx].start &&
152 addr < lkp_tbl[*cached_idx].end))
153 return lkp_tbl[*cached_idx].lkey;
154 for (idx = 0; idx < n && lkp_tbl[idx].start != 0; ++idx) {
155 if (addr >= lkp_tbl[idx].start &&
156 addr < lkp_tbl[idx].end) {
159 return lkp_tbl[idx].lkey;
166 void mlx5_mr_flush_local_cache(struct mlx5_mr_ctrl *mr_ctrl);
169 * Bottom-half of LKey search on. If supported, lookup for the address from
170 * the mempool. Otherwise, search in old mechanism caches.
173 * Pointer to per-queue MR control structure.
178 * Searched LKey on success, UINT32_MAX on no match.
181 uint32_t mlx5_mr_mb2mr_bh(struct mlx5_mr_ctrl *mr_ctrl, struct rte_mbuf *mbuf);
184 * Query LKey from a packet buffer.
187 * Pointer to per-queue MR control structure.
192 * Searched LKey on success, UINT32_MAX on no match.
194 static __rte_always_inline uint32_t
195 mlx5_mr_mb2mr(struct mlx5_mr_ctrl *mr_ctrl, struct rte_mbuf *mbuf)
199 /* Check generation bit to see if there's any change on existing MRs. */
200 if (unlikely(*mr_ctrl->dev_gen_ptr != mr_ctrl->cur_gen))
201 mlx5_mr_flush_local_cache(mr_ctrl);
202 /* Linear search on MR cache array. */
203 lkey = mlx5_mr_lookup_lkey(mr_ctrl->cache, &mr_ctrl->mru,
204 MLX5_MR_CACHE_N, (uintptr_t)mbuf->buf_addr);
205 if (likely(lkey != UINT32_MAX))
207 /* Take slower bottom-half on miss. */
208 return mlx5_mr_mb2mr_bh(mr_ctrl, mbuf);
211 /* mlx5_common_mr.c */
214 int mlx5_mr_ctrl_init(struct mlx5_mr_ctrl *mr_ctrl,
215 struct mlx5_common_device *cdev, int socket);
217 void mlx5_mr_btree_free(struct mlx5_mr_btree *bt);
218 void mlx5_mr_btree_dump(struct mlx5_mr_btree *bt __rte_unused);
220 uint32_t mlx5_mr_mempool2mr_bh(struct mlx5_mr_share_cache *share_cache,
221 struct mlx5_mr_ctrl *mr_ctrl,
222 struct rte_mempool *mp, uintptr_t addr);
223 void mlx5_mr_release_cache(struct mlx5_mr_share_cache *mr_cache);
224 int mlx5_mr_create_cache(struct mlx5_mr_share_cache *share_cache, int socket);
225 void mlx5_mr_dump_cache(struct mlx5_mr_share_cache *share_cache __rte_unused);
226 void mlx5_mr_rebuild_cache(struct mlx5_mr_share_cache *share_cache);
227 void mlx5_free_mr_by_addr(struct mlx5_mr_share_cache *share_cache,
228 const char *ibdev_name, const void *addr, size_t len);
229 int mlx5_mr_insert_cache(struct mlx5_mr_share_cache *share_cache,
232 mlx5_mr_lookup_list(struct mlx5_mr_share_cache *share_cache,
233 struct mr_cache_entry *entry, uintptr_t addr);
235 mlx5_create_mr_ext(void *pd, uintptr_t addr, size_t len, int socket_id,
236 mlx5_reg_mr_t reg_mr_cb);
237 void mlx5_mr_free(struct mlx5_mr *mr, mlx5_dereg_mr_t dereg_mr_cb);
240 mlx5_mr_create(struct mlx5_common_device *cdev,
241 struct mlx5_mr_share_cache *share_cache,
242 struct mr_cache_entry *entry, uintptr_t addr);
244 /* mlx5_common_verbs.c */
248 mlx5_common_verbs_reg_mr(void *pd, void *addr, size_t length,
249 struct mlx5_pmd_mr *pmd_mr);
252 mlx5_common_verbs_dereg_mr(struct mlx5_pmd_mr *pmd_mr);
255 mlx5_os_set_reg_mr_cb(mlx5_reg_mr_t *reg_mr_cb, mlx5_dereg_mr_t *dereg_mr_cb);
259 mlx5_mr_mempool_register(struct mlx5_common_device *cdev,
260 struct rte_mempool *mp);
263 mlx5_mr_mempool_unregister(struct mlx5_common_device *cdev,
264 struct rte_mempool *mp);
266 #endif /* RTE_PMD_MLX5_COMMON_MR_H_ */