drivers/common/mlx5/mlx5_devx_cmds.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2018 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <unistd.h>
   6
   7 #include <rte_errno.h>
   8 #include <rte_malloc.h>
   9 #include <rte_eal_paging.h>
  10
  11 #include "mlx5_prm.h"
  12 #include "mlx5_devx_cmds.h"
  13 #include "mlx5_common_log.h"
  14 #include "mlx5_malloc.h"
  15
  16 static void *
  17 mlx5_devx_get_hca_cap(void *ctx, uint32_t *in, uint32_t *out,
  18                       int *err, uint32_t flags)
  19 {
  20         const size_t size_in = MLX5_ST_SZ_DW(query_hca_cap_in) * sizeof(int);
  21         const size_t size_out = MLX5_ST_SZ_DW(query_hca_cap_out) * sizeof(int);
  22         int status, syndrome, rc;
  23
  24         if (err)
  25                 *err = 0;
  26         memset(in, 0, size_in);
  27         memset(out, 0, size_out);
  28         MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
  29         MLX5_SET(query_hca_cap_in, in, op_mod, flags);
  30         rc = mlx5_glue->devx_general_cmd(ctx, in, size_in, out, size_out);
  31         if (rc) {
  32                 DRV_LOG(ERR,
  33                         "Failed to query devx HCA capabilities func %#02x",
  34                         flags >> 1);
  35                 if (err)
  36                         *err = rc > 0 ? -rc : rc;
  37                 return NULL;
  38         }
  39         status = MLX5_GET(query_hca_cap_out, out, status);
  40         syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
  41         if (status) {
  42                 DRV_LOG(ERR,
  43                         "Failed to query devx HCA capabilities func %#02x status %x, syndrome = %x",
  44                         flags >> 1, status, syndrome);
  45                 if (err)
  46                         *err = -1;
  47                 return NULL;
  48         }
  49         return MLX5_ADDR_OF(query_hca_cap_out, out, capability);
  50 }
  51
  52 /**
  53  * Perform read access to the registers. Reads data from register
  54  * and writes ones to the specified buffer.
  55  *
  56  * @param[in] ctx
  57  *   Context returned from mlx5 open_device() glue function.
  58  * @param[in] reg_id
  59  *   Register identifier according to the PRM.
  60  * @param[in] arg
  61  *   Register access auxiliary parameter according to the PRM.
  62  * @param[out] data
  63  *   Pointer to the buffer to store read data.
  64  * @param[in] dw_cnt
  65  *   Buffer size in double words.
  66  *
  67  * @return
  68  *   0 on success, a negative value otherwise.
  69  */
  70 int
  71 mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg,
  72                             uint32_t *data, uint32_t dw_cnt)
  73 {
  74         uint32_t in[MLX5_ST_SZ_DW(access_register_in)]   = {0};
  75         uint32_t out[MLX5_ST_SZ_DW(access_register_out) +
  76                      MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0};
  77         int status, rc;
  78
  79         MLX5_ASSERT(data && dw_cnt);
  80         MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX);
  81         if (dw_cnt  > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) {
  82                 DRV_LOG(ERR, "Not enough  buffer for register read data");
  83                 return -1;
  84         }
  85         MLX5_SET(access_register_in, in, opcode,
  86                  MLX5_CMD_OP_ACCESS_REGISTER_USER);
  87         MLX5_SET(access_register_in, in, op_mod,
  88                                         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ);
  89         MLX5_SET(access_register_in, in, register_id, reg_id);
  90         MLX5_SET(access_register_in, in, argument, arg);
  91         rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out,
  92                                          MLX5_ST_SZ_BYTES(access_register_out) +
  93                                          sizeof(uint32_t) * dw_cnt);
  94         if (rc)
  95                 goto error;
  96         status = MLX5_GET(access_register_out, out, status);
  97         if (status) {
  98                 int syndrome = MLX5_GET(access_register_out, out, syndrome);
  99
 100                 DRV_LOG(DEBUG, "Failed to read access NIC register 0x%X, "
 101                                "status %x, syndrome = %x",
 102                                reg_id, status, syndrome);
 103                 return -1;
 104         }
 105         memcpy(data, &out[MLX5_ST_SZ_DW(access_register_out)],
 106                dw_cnt * sizeof(uint32_t));
 107         return 0;
 108 error:
 109         rc = (rc > 0) ? -rc : rc;
 110         return rc;
 111 }
 112
 113 /**
 114  * Perform write access to the registers.
 115  *
 116  * @param[in] ctx
 117  *   Context returned from mlx5 open_device() glue function.
 118  * @param[in] reg_id
 119  *   Register identifier according to the PRM.
 120  * @param[in] arg
 121  *   Register access auxiliary parameter according to the PRM.
 122  * @param[out] data
 123  *   Pointer to the buffer containing data to write.
 124  * @param[in] dw_cnt
 125  *   Buffer size in double words (32bit units).
 126  *
 127  * @return
 128  *   0 on success, a negative value otherwise.
 129  */
 130 int
 131 mlx5_devx_cmd_register_write(void *ctx, uint16_t reg_id, uint32_t arg,
 132                              uint32_t *data, uint32_t dw_cnt)
 133 {
 134         uint32_t in[MLX5_ST_SZ_DW(access_register_in) +
 135                     MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0};
 136         uint32_t out[MLX5_ST_SZ_DW(access_register_out)] = {0};
 137         int status, rc;
 138         void *ptr;
 139
 140         MLX5_ASSERT(data && dw_cnt);
 141         MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX);
 142         if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) {
 143                 DRV_LOG(ERR, "Data to write exceeds max size");
 144                 return -1;
 145         }
 146         MLX5_SET(access_register_in, in, opcode,
 147                  MLX5_CMD_OP_ACCESS_REGISTER_USER);
 148         MLX5_SET(access_register_in, in, op_mod,
 149                  MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE);
 150         MLX5_SET(access_register_in, in, register_id, reg_id);
 151         MLX5_SET(access_register_in, in, argument, arg);
 152         ptr = MLX5_ADDR_OF(access_register_in, in, register_data);
 153         memcpy(ptr, data, dw_cnt * sizeof(uint32_t));
 154         rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
 155
 156         rc = mlx5_glue->devx_general_cmd(ctx, in,
 157                                          MLX5_ST_SZ_BYTES(access_register_in) +
 158                                          dw_cnt * sizeof(uint32_t),
 159                                          out, sizeof(out));
 160         if (rc)
 161                 goto error;
 162         status = MLX5_GET(access_register_out, out, status);
 163         if (status) {
 164                 int syndrome = MLX5_GET(access_register_out, out, syndrome);
 165
 166                 DRV_LOG(DEBUG, "Failed to write access NIC register 0x%X, "
 167                                "status %x, syndrome = %x",
 168                                reg_id, status, syndrome);
 169                 return -1;
 170         }
 171         return 0;
 172 error:
 173         rc = (rc > 0) ? -rc : rc;
 174         return rc;
 175 }
 176
 177 /**
 178  * Allocate flow counters via devx interface.
 179  *
 180  * @param[in] ctx
 181  *   Context returned from mlx5 open_device() glue function.
 182  * @param dcs
 183  *   Pointer to counters properties structure to be filled by the routine.
 184  * @param bulk_n_128
 185  *   Bulk counter numbers in 128 counters units.
 186  *
 187  * @return
 188  *   Pointer to counter object on success, a negative value otherwise and
 189  *   rte_errno is set.
 190  */
 191 struct mlx5_devx_obj *
 192 mlx5_devx_cmd_flow_counter_alloc(void *ctx, uint32_t bulk_n_128)
 193 {
 194         struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs),
 195                                                 0, SOCKET_ID_ANY);
 196         uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)]   = {0};
 197         uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0};
 198
 199         if (!dcs) {
 200                 rte_errno = ENOMEM;
 201                 return NULL;
 202         }
 203         MLX5_SET(alloc_flow_counter_in, in, opcode,
 204                  MLX5_CMD_OP_ALLOC_FLOW_COUNTER);
 205         MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128);
 206         dcs->obj = mlx5_glue->devx_obj_create(ctx, in,
 207                                               sizeof(in), out, sizeof(out));
 208         if (!dcs->obj) {
 209                 DRV_LOG(ERR, "Can't allocate counters - error %d", errno);
 210                 rte_errno = errno;
 211                 mlx5_free(dcs);
 212                 return NULL;
 213         }
 214         dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id);
 215         return dcs;
 216 }
 217
 218 /**
 219  * Query flow counters values.
 220  *
 221  * @param[in] dcs
 222  *   devx object that was obtained from mlx5_devx_cmd_fc_alloc.
 223  * @param[in] clear
 224  *   Whether hardware should clear the counters after the query or not.
 225  * @param[in] n_counters
 226  *   0 in case of 1 counter to read, otherwise the counter number to read.
 227  *  @param pkts
 228  *   The number of packets that matched the flow.
 229  *  @param bytes
 230  *    The number of bytes that matched the flow.
 231  *  @param mkey
 232  *   The mkey key for batch query.
 233  *  @param addr
 234  *    The address in the mkey range for batch query.
 235  *  @param cmd_comp
 236  *   The completion object for asynchronous batch query.
 237  *  @param async_id
 238  *    The ID to be returned in the asynchronous batch query response.
 239  *
 240  * @return
 241  *   0 on success, a negative value otherwise.
 242  */
 243 int
 244 mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs,
 245                                  int clear, uint32_t n_counters,
 246                                  uint64_t *pkts, uint64_t *bytes,
 247                                  uint32_t mkey, void *addr,
 248                                  void *cmd_comp,
 249                                  uint64_t async_id)
 250 {
 251         int out_len = MLX5_ST_SZ_BYTES(query_flow_counter_out) +
 252                         MLX5_ST_SZ_BYTES(traffic_counter);
 253         uint32_t out[out_len];
 254         uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0};
 255         void *stats;
 256         int rc;
 257
 258         MLX5_SET(query_flow_counter_in, in, opcode,
 259                  MLX5_CMD_OP_QUERY_FLOW_COUNTER);
 260         MLX5_SET(query_flow_counter_in, in, op_mod, 0);
 261         MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id);
 262         MLX5_SET(query_flow_counter_in, in, clear, !!clear);
 263
 264         if (n_counters) {
 265                 MLX5_SET(query_flow_counter_in, in, num_of_counters,
 266                          n_counters);
 267                 MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1);
 268                 MLX5_SET(query_flow_counter_in, in, mkey, mkey);
 269                 MLX5_SET64(query_flow_counter_in, in, address,
 270                            (uint64_t)(uintptr_t)addr);
 271         }
 272         if (!cmd_comp)
 273                 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out,
 274                                                out_len);
 275         else
 276                 rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in),
 277                                                      out_len, async_id,
 278                                                      cmd_comp);
 279         if (rc) {
 280                 DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc);
 281                 rte_errno = rc;
 282                 return -rc;
 283         }
 284         if (!n_counters) {
 285                 stats = MLX5_ADDR_OF(query_flow_counter_out,
 286                                      out, flow_statistics);
 287                 *pkts = MLX5_GET64(traffic_counter, stats, packets);
 288                 *bytes = MLX5_GET64(traffic_counter, stats, octets);
 289         }
 290         return 0;
 291 }
 292
 293 /**
 294  * Create a new mkey.
 295  *
 296  * @param[in] ctx
 297  *   Context returned from mlx5 open_device() glue function.
 298  * @param[in] attr
 299  *   Attributes of the requested mkey.
 300  *
 301  * @return
 302  *   Pointer to Devx mkey on success, a negative value otherwise and rte_errno
 303  *   is set.
 304  */
 305 struct mlx5_devx_obj *
 306 mlx5_devx_cmd_mkey_create(void *ctx,
 307                           struct mlx5_devx_mkey_attr *attr)
 308 {
 309         struct mlx5_klm *klm_array = attr->klm_array;
 310         int klm_num = attr->klm_num;
 311         int in_size_dw = MLX5_ST_SZ_DW(create_mkey_in) +
 312                      (klm_num ? RTE_ALIGN(klm_num, 4) : 0) * MLX5_ST_SZ_DW(klm);
 313         uint32_t in[in_size_dw];
 314         uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0};
 315         void *mkc;
 316         struct mlx5_devx_obj *mkey = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mkey),
 317                                                  0, SOCKET_ID_ANY);
 318         size_t pgsize;
 319         uint32_t translation_size;
 320
 321         if (!mkey) {
 322                 rte_errno = ENOMEM;
 323                 return NULL;
 324         }
 325         memset(in, 0, in_size_dw * 4);
 326         pgsize = rte_mem_page_size();
 327         if (pgsize == (size_t)-1) {
 328                 mlx5_free(mkey);
 329                 DRV_LOG(ERR, "Failed to get page size");
 330                 rte_errno = ENOMEM;
 331                 return NULL;
 332         }
 333         MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY);
 334         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 335         if (klm_num > 0) {
 336                 int i;
 337                 uint8_t *klm = (uint8_t *)MLX5_ADDR_OF(create_mkey_in, in,
 338                                                        klm_pas_mtt);
 339                 translation_size = RTE_ALIGN(klm_num, 4);
 340                 for (i = 0; i < klm_num; i++) {
 341                         MLX5_SET(klm, klm, byte_count, klm_array[i].byte_count);
 342                         MLX5_SET(klm, klm, mkey, klm_array[i].mkey);
 343                         MLX5_SET64(klm, klm, address, klm_array[i].address);
 344                         klm += MLX5_ST_SZ_BYTES(klm);
 345                 }
 346                 for (; i < (int)translation_size; i++) {
 347                         MLX5_SET(klm, klm, mkey, 0x0);
 348                         MLX5_SET64(klm, klm, address, 0x0);
 349                         klm += MLX5_ST_SZ_BYTES(klm);
 350                 }
 351                 MLX5_SET(mkc, mkc, access_mode_1_0, attr->log_entity_size ?
 352                          MLX5_MKC_ACCESS_MODE_KLM_FBS :
 353                          MLX5_MKC_ACCESS_MODE_KLM);
 354                 MLX5_SET(mkc, mkc, log_page_size, attr->log_entity_size);
 355         } else {
 356                 translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16;
 357                 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
 358                 MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize));
 359         }
 360         MLX5_SET(create_mkey_in, in, translations_octword_actual_size,
 361                  translation_size);
 362         MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id);
 363         MLX5_SET(create_mkey_in, in, pg_access, attr->pg_access);
 364         MLX5_SET(mkc, mkc, lw, 0x1);
 365         MLX5_SET(mkc, mkc, lr, 0x1);
 366         if (attr->set_remote_rw) {
 367                 MLX5_SET(mkc, mkc, rw, 0x1);
 368                 MLX5_SET(mkc, mkc, rr, 0x1);
 369         }
 370         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 371         MLX5_SET(mkc, mkc, pd, attr->pd);
 372         MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF);
 373         MLX5_SET(mkc, mkc, umr_en, attr->umr_en);
 374         MLX5_SET(mkc, mkc, translations_octword_size, translation_size);
 375         MLX5_SET(mkc, mkc, relaxed_ordering_write,
 376                  attr->relaxed_ordering_write);
 377         MLX5_SET(mkc, mkc, relaxed_ordering_read, attr->relaxed_ordering_read);
 378         MLX5_SET64(mkc, mkc, start_addr, attr->addr);
 379         MLX5_SET64(mkc, mkc, len, attr->size);
 380         MLX5_SET(mkc, mkc, crypto_en, attr->crypto_en);
 381         if (attr->crypto_en) {
 382                 MLX5_SET(mkc, mkc, bsf_en, attr->crypto_en);
 383                 MLX5_SET(mkc, mkc, bsf_octword_size, 4);
 384         }
 385         mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out,
 386                                                sizeof(out));
 387         if (!mkey->obj) {
 388                 DRV_LOG(ERR, "Can't create %sdirect mkey - error %d",
 389                         klm_num ? "an in" : "a ", errno);
 390                 rte_errno = errno;
 391                 mlx5_free(mkey);
 392                 return NULL;
 393         }
 394         mkey->id = MLX5_GET(create_mkey_out, out, mkey_index);
 395         mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF);
 396         return mkey;
 397 }
 398
 399 /**
 400  * Get status of devx command response.
 401  * Mainly used for asynchronous commands.
 402  *
 403  * @param[in] out
 404  *   The out response buffer.
 405  *
 406  * @return
 407  *   0 on success, non-zero value otherwise.
 408  */
 409 int
 410 mlx5_devx_get_out_command_status(void *out)
 411 {
 412         int status;
 413
 414         if (!out)
 415                 return -EINVAL;
 416         status = MLX5_GET(query_flow_counter_out, out, status);
 417         if (status) {
 418                 int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome);
 419
 420                 DRV_LOG(ERR, "Bad DevX status %x, syndrome = %x", status,
 421                         syndrome);
 422         }
 423         return status;
 424 }
 425
 426 /**
 427  * Destroy any object allocated by a Devx API.
 428  *
 429  * @param[in] obj
 430  *   Pointer to a general object.
 431  *
 432  * @return
 433  *   0 on success, a negative value otherwise.
 434  */
 435 int
 436 mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj)
 437 {
 438         int ret;
 439
 440         if (!obj)
 441                 return 0;
 442         ret =  mlx5_glue->devx_obj_destroy(obj->obj);
 443         mlx5_free(obj);
 444         return ret;
 445 }
 446
 447 /**
 448  * Query NIC vport context.
 449  * Fills minimal inline attribute.
 450  *
 451  * @param[in] ctx
 452  *   ibv contexts returned from mlx5dv_open_device.
 453  * @param[in] vport
 454  *   vport index
 455  * @param[out] attr
 456  *   Attributes device values.
 457  *
 458  * @return
 459  *   0 on success, a negative value otherwise.
 460  */
 461 static int
 462 mlx5_devx_cmd_query_nic_vport_context(void *ctx,
 463                                       unsigned int vport,
 464                                       struct mlx5_hca_attr *attr)
 465 {
 466         uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0};
 467         uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0};
 468         void *vctx;
 469         int status, syndrome, rc;
 470
 471         /* Query NIC vport context to determine inline mode. */
 472         MLX5_SET(query_nic_vport_context_in, in, opcode,
 473                  MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT);
 474         MLX5_SET(query_nic_vport_context_in, in, vport_number, vport);
 475         if (vport)
 476                 MLX5_SET(query_nic_vport_context_in, in, other_vport, 1);
 477         rc = mlx5_glue->devx_general_cmd(ctx,
 478                                          in, sizeof(in),
 479                                          out, sizeof(out));
 480         if (rc)
 481                 goto error;
 482         status = MLX5_GET(query_nic_vport_context_out, out, status);
 483         syndrome = MLX5_GET(query_nic_vport_context_out, out, syndrome);
 484         if (status) {
 485                 DRV_LOG(DEBUG, "Failed to query NIC vport context, "
 486                         "status %x, syndrome = %x", status, syndrome);
 487                 return -1;
 488         }
 489         vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out,
 490                             nic_vport_context);
 491         attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx,
 492                                            min_wqe_inline_mode);
 493         return 0;
 494 error:
 495         rc = (rc > 0) ? -rc : rc;
 496         return rc;
 497 }
 498
 499 /**
 500  * Query NIC vDPA attributes.
 501  *
 502  * @param[in] ctx
 503  *   Context returned from mlx5 open_device() glue function.
 504  * @param[out] vdpa_attr
 505  *   vDPA Attributes structure to fill.
 506  */
 507 static void
 508 mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx,
 509                                   struct mlx5_hca_vdpa_attr *vdpa_attr)
 510 {
 511         uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)];
 512         uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)];
 513         void *hcattr;
 514
 515         hcattr = mlx5_devx_get_hca_cap(ctx, in, out, NULL,
 516                         MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION |
 517                         MLX5_HCA_CAP_OPMOD_GET_CUR);
 518         if (!hcattr) {
 519                 RTE_LOG(DEBUG, PMD, "Failed to query devx VDPA capabilities");
 520                 vdpa_attr->valid = 0;
 521         } else {
 522                 vdpa_attr->valid = 1;
 523                 vdpa_attr->desc_tunnel_offload_type =
 524                         MLX5_GET(virtio_emulation_cap, hcattr,
 525                                  desc_tunnel_offload_type);
 526                 vdpa_attr->eth_frame_offload_type =
 527                         MLX5_GET(virtio_emulation_cap, hcattr,
 528                                  eth_frame_offload_type);
 529                 vdpa_attr->virtio_version_1_0 =
 530                         MLX5_GET(virtio_emulation_cap, hcattr,
 531                                  virtio_version_1_0);
 532                 vdpa_attr->tso_ipv4 = MLX5_GET(virtio_emulation_cap, hcattr,
 533                                                tso_ipv4);
 534                 vdpa_attr->tso_ipv6 = MLX5_GET(virtio_emulation_cap, hcattr,
 535                                                tso_ipv6);
 536                 vdpa_attr->tx_csum = MLX5_GET(virtio_emulation_cap, hcattr,
 537                                               tx_csum);
 538                 vdpa_attr->rx_csum = MLX5_GET(virtio_emulation_cap, hcattr,
 539                                               rx_csum);
 540                 vdpa_attr->event_mode = MLX5_GET(virtio_emulation_cap, hcattr,
 541                                                  event_mode);
 542                 vdpa_attr->virtio_queue_type =
 543                         MLX5_GET(virtio_emulation_cap, hcattr,
 544                                  virtio_queue_type);
 545                 vdpa_attr->log_doorbell_stride =
 546                         MLX5_GET(virtio_emulation_cap, hcattr,
 547                                  log_doorbell_stride);
 548                 vdpa_attr->log_doorbell_bar_size =
 549                         MLX5_GET(virtio_emulation_cap, hcattr,
 550                                  log_doorbell_bar_size);
 551                 vdpa_attr->doorbell_bar_offset =
 552                         MLX5_GET64(virtio_emulation_cap, hcattr,
 553                                    doorbell_bar_offset);
 554                 vdpa_attr->max_num_virtio_queues =
 555                         MLX5_GET(virtio_emulation_cap, hcattr,
 556                                  max_num_virtio_queues);
 557                 vdpa_attr->umems[0].a = MLX5_GET(virtio_emulation_cap, hcattr,
 558                                                  umem_1_buffer_param_a);
 559                 vdpa_attr->umems[0].b = MLX5_GET(virtio_emulation_cap, hcattr,
 560                                                  umem_1_buffer_param_b);
 561                 vdpa_attr->umems[1].a = MLX5_GET(virtio_emulation_cap, hcattr,
 562                                                  umem_2_buffer_param_a);
 563                 vdpa_attr->umems[1].b = MLX5_GET(virtio_emulation_cap, hcattr,
 564                                                  umem_2_buffer_param_b);
 565                 vdpa_attr->umems[2].a = MLX5_GET(virtio_emulation_cap, hcattr,
 566                                                  umem_3_buffer_param_a);
 567                 vdpa_attr->umems[2].b = MLX5_GET(virtio_emulation_cap, hcattr,
 568                                                  umem_3_buffer_param_b);
 569         }
 570 }
 571
 572 int
 573 mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj,
 574                                   uint32_t ids[], uint32_t num)
 575 {
 576         uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
 577         uint32_t out[MLX5_ST_SZ_DW(create_flex_parser_out)] = {0};
 578         void *hdr = MLX5_ADDR_OF(create_flex_parser_out, in, hdr);
 579         void *flex = MLX5_ADDR_OF(create_flex_parser_out, out, flex);
 580         void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table);
 581         int ret;
 582         uint32_t idx = 0;
 583         uint32_t i;
 584
 585         if (num > MLX5_GRAPH_NODE_SAMPLE_NUM) {
 586                 rte_errno = EINVAL;
 587                 DRV_LOG(ERR, "Too many sample IDs to be fetched.");
 588                 return -rte_errno;
 589         }
 590         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
 591                  MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
 592         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
 593                  MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH);
 594         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, flex_obj->id);
 595         ret = mlx5_glue->devx_obj_query(flex_obj->obj, in, sizeof(in),
 596                                         out, sizeof(out));
 597         if (ret) {
 598                 rte_errno = ret;
 599                 DRV_LOG(ERR, "Failed to query sample IDs with object %p.",
 600                         (void *)flex_obj);
 601                 return -rte_errno;
 602         }
 603         for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) {
 604                 void *s_off = (void *)((char *)sample + i *
 605                               MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample));
 606                 uint32_t en;
 607
 608                 en = MLX5_GET(parse_graph_flow_match_sample, s_off,
 609                               flow_match_sample_en);
 610                 if (!en)
 611                         continue;
 612                 ids[idx++] = MLX5_GET(parse_graph_flow_match_sample, s_off,
 613                                   flow_match_sample_field_id);
 614         }
 615         if (num != idx) {
 616                 rte_errno = EINVAL;
 617                 DRV_LOG(ERR, "Number of sample IDs are not as expected.");
 618                 return -rte_errno;
 619         }
 620         return ret;
 621 }
 622
 623 struct mlx5_devx_obj *
 624 mlx5_devx_cmd_create_flex_parser(void *ctx,
 625                                  struct mlx5_devx_graph_node_attr *data)
 626 {
 627         uint32_t in[MLX5_ST_SZ_DW(create_flex_parser_in)] = {0};
 628         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
 629         void *hdr = MLX5_ADDR_OF(create_flex_parser_in, in, hdr);
 630         void *flex = MLX5_ADDR_OF(create_flex_parser_in, in, flex);
 631         void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table);
 632         void *in_arc = MLX5_ADDR_OF(parse_graph_flex, flex, input_arc);
 633         void *out_arc = MLX5_ADDR_OF(parse_graph_flex, flex, output_arc);
 634         struct mlx5_devx_obj *parse_flex_obj = mlx5_malloc
 635                      (MLX5_MEM_ZERO, sizeof(*parse_flex_obj), 0, SOCKET_ID_ANY);
 636         uint32_t i;
 637
 638         if (!parse_flex_obj) {
 639                 DRV_LOG(ERR, "Failed to allocate flex parser data.");
 640                 rte_errno = ENOMEM;
 641                 return NULL;
 642         }
 643         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
 644                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
 645         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
 646                  MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH);
 647         MLX5_SET(parse_graph_flex, flex, header_length_mode,
 648                  data->header_length_mode);
 649         MLX5_SET64(parse_graph_flex, flex, modify_field_select,
 650                    data->modify_field_select);
 651         MLX5_SET(parse_graph_flex, flex, header_length_base_value,
 652                  data->header_length_base_value);
 653         MLX5_SET(parse_graph_flex, flex, header_length_field_offset,
 654                  data->header_length_field_offset);
 655         MLX5_SET(parse_graph_flex, flex, header_length_field_shift,
 656                  data->header_length_field_shift);
 657         MLX5_SET(parse_graph_flex, flex, next_header_field_offset,
 658                  data->next_header_field_offset);
 659         MLX5_SET(parse_graph_flex, flex, next_header_field_size,
 660                  data->next_header_field_size);
 661         MLX5_SET(parse_graph_flex, flex, header_length_field_mask,
 662                  data->header_length_field_mask);
 663         for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) {
 664                 struct mlx5_devx_match_sample_attr *s = &data->sample[i];
 665                 void *s_off = (void *)((char *)sample + i *
 666                               MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample));
 667
 668                 if (!s->flow_match_sample_en)
 669                         continue;
 670                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 671                          flow_match_sample_en, !!s->flow_match_sample_en);
 672                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 673                          flow_match_sample_field_offset,
 674                          s->flow_match_sample_field_offset);
 675                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 676                          flow_match_sample_offset_mode,
 677                          s->flow_match_sample_offset_mode);
 678                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 679                          flow_match_sample_field_offset_mask,
 680                          s->flow_match_sample_field_offset_mask);
 681                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 682                          flow_match_sample_field_offset_shift,
 683                          s->flow_match_sample_field_offset_shift);
 684                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 685                          flow_match_sample_field_base_offset,
 686                          s->flow_match_sample_field_base_offset);
 687                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 688                          flow_match_sample_tunnel_mode,
 689                          s->flow_match_sample_tunnel_mode);
 690         }
 691         for (i = 0; i < MLX5_GRAPH_NODE_ARC_NUM; i++) {
 692                 struct mlx5_devx_graph_arc_attr *ia = &data->in[i];
 693                 struct mlx5_devx_graph_arc_attr *oa = &data->out[i];
 694                 void *in_off = (void *)((char *)in_arc + i *
 695                               MLX5_ST_SZ_BYTES(parse_graph_arc));
 696                 void *out_off = (void *)((char *)out_arc + i *
 697                               MLX5_ST_SZ_BYTES(parse_graph_arc));
 698
 699                 if (ia->arc_parse_graph_node != 0) {
 700                         MLX5_SET(parse_graph_arc, in_off,
 701                                  compare_condition_value,
 702                                  ia->compare_condition_value);
 703                         MLX5_SET(parse_graph_arc, in_off, start_inner_tunnel,
 704                                  ia->start_inner_tunnel);
 705                         MLX5_SET(parse_graph_arc, in_off, arc_parse_graph_node,
 706                                  ia->arc_parse_graph_node);
 707                         MLX5_SET(parse_graph_arc, in_off,
 708                                  parse_graph_node_handle,
 709                                  ia->parse_graph_node_handle);
 710                 }
 711                 if (oa->arc_parse_graph_node != 0) {
 712                         MLX5_SET(parse_graph_arc, out_off,
 713                                  compare_condition_value,
 714                                  oa->compare_condition_value);
 715                         MLX5_SET(parse_graph_arc, out_off, start_inner_tunnel,
 716                                  oa->start_inner_tunnel);
 717                         MLX5_SET(parse_graph_arc, out_off, arc_parse_graph_node,
 718                                  oa->arc_parse_graph_node);
 719                         MLX5_SET(parse_graph_arc, out_off,
 720                                  parse_graph_node_handle,
 721                                  oa->parse_graph_node_handle);
 722                 }
 723         }
 724         parse_flex_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
 725                                                          out, sizeof(out));
 726         if (!parse_flex_obj->obj) {
 727                 rte_errno = errno;
 728                 DRV_LOG(ERR, "Failed to create FLEX PARSE GRAPH object "
 729                         "by using DevX.");
 730                 mlx5_free(parse_flex_obj);
 731                 return NULL;
 732         }
 733         parse_flex_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
 734         return parse_flex_obj;
 735 }
 736
 737 static int
 738 mlx5_devx_cmd_query_hca_parse_graph_node_cap
 739         (void *ctx, struct mlx5_hca_flex_attr *attr)
 740 {
 741         uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)];
 742         uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)];
 743         void *hcattr;
 744         int rc;
 745
 746         hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
 747                         MLX5_GET_HCA_CAP_OP_MOD_PARSE_GRAPH_NODE_CAP |
 748                         MLX5_HCA_CAP_OPMOD_GET_CUR);
 749         if (!hcattr)
 750                 return rc;
 751         attr->node_in = MLX5_GET(parse_graph_node_cap, hcattr, node_in);
 752         attr->node_out = MLX5_GET(parse_graph_node_cap, hcattr, node_out);
 753         attr->header_length_mode = MLX5_GET(parse_graph_node_cap, hcattr,
 754                                             header_length_mode);
 755         attr->sample_offset_mode = MLX5_GET(parse_graph_node_cap, hcattr,
 756                                             sample_offset_mode);
 757         attr->max_num_arc_in = MLX5_GET(parse_graph_node_cap, hcattr,
 758                                         max_num_arc_in);
 759         attr->max_num_arc_out = MLX5_GET(parse_graph_node_cap, hcattr,
 760                                          max_num_arc_out);
 761         attr->max_num_sample = MLX5_GET(parse_graph_node_cap, hcattr,
 762                                         max_num_sample);
 763         attr->sample_id_in_out = MLX5_GET(parse_graph_node_cap, hcattr,
 764                                           sample_id_in_out);
 765         attr->max_base_header_length = MLX5_GET(parse_graph_node_cap, hcattr,
 766                                                 max_base_header_length);
 767         attr->max_sample_base_offset = MLX5_GET(parse_graph_node_cap, hcattr,
 768                                                 max_sample_base_offset);
 769         attr->max_next_header_offset = MLX5_GET(parse_graph_node_cap, hcattr,
 770                                                 max_next_header_offset);
 771         attr->header_length_mask_width = MLX5_GET(parse_graph_node_cap, hcattr,
 772                                                   header_length_mask_width);
 773         /* Get the max supported samples from HCA CAP 2 */
 774         hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
 775                         MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 |
 776                         MLX5_HCA_CAP_OPMOD_GET_CUR);
 777         if (!hcattr)
 778                 return rc;
 779         attr->max_num_prog_sample =
 780                 MLX5_GET(cmd_hca_cap_2, hcattr, max_num_prog_sample_field);
 781         return 0;
 782 }
 783
 784 static int
 785 mlx5_devx_query_pkt_integrity_match(void *hcattr)
 786 {
 787         return MLX5_GET(flow_table_nic_cap, hcattr,
 788                         ft_field_support_2_nic_receive.inner_l3_ok) &&
 789                MLX5_GET(flow_table_nic_cap, hcattr,
 790                         ft_field_support_2_nic_receive.inner_l4_ok) &&
 791                MLX5_GET(flow_table_nic_cap, hcattr,
 792                         ft_field_support_2_nic_receive.outer_l3_ok) &&
 793                MLX5_GET(flow_table_nic_cap, hcattr,
 794                         ft_field_support_2_nic_receive.outer_l4_ok) &&
 795                MLX5_GET(flow_table_nic_cap, hcattr,
 796                         ft_field_support_2_nic_receive
 797                                 .inner_ipv4_checksum_ok) &&
 798                MLX5_GET(flow_table_nic_cap, hcattr,
 799                         ft_field_support_2_nic_receive.inner_l4_checksum_ok) &&
 800                MLX5_GET(flow_table_nic_cap, hcattr,
 801                         ft_field_support_2_nic_receive
 802                                 .outer_ipv4_checksum_ok) &&
 803                MLX5_GET(flow_table_nic_cap, hcattr,
 804                         ft_field_support_2_nic_receive.outer_l4_checksum_ok);
 805 }
 806
 807 /**
 808  * Query HCA attributes.
 809  * Using those attributes we can check on run time if the device
 810  * is having the required capabilities.
 811  *
 812  * @param[in] ctx
 813  *   Context returned from mlx5 open_device() glue function.
 814  * @param[out] attr
 815  *   Attributes device values.
 816  *
 817  * @return
 818  *   0 on success, a negative value otherwise.
 819  */
 820 int
 821 mlx5_devx_cmd_query_hca_attr(void *ctx,
 822                              struct mlx5_hca_attr *attr)
 823 {
 824         uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0};
 825         uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0};
 826         uint64_t general_obj_types_supported = 0;
 827         void *hcattr;
 828         int rc, i;
 829
 830         hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
 831                         MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE |
 832                         MLX5_HCA_CAP_OPMOD_GET_CUR);
 833         if (!hcattr)
 834                 return rc;
 835         attr->flow_counter_bulk_alloc_bitmap =
 836                         MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc);
 837         attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr,
 838                                             flow_counters_dump);
 839         attr->log_max_rqt_size = MLX5_GET(cmd_hca_cap, hcattr,
 840                                           log_max_rqt_size);
 841         attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager);
 842         attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin);
 843         attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr,
 844                                                 log_max_hairpin_queues);
 845         attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr,
 846                                                     log_max_hairpin_wq_data_sz);
 847         attr->log_max_hairpin_num_packets = MLX5_GET
 848                 (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz);
 849         attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id);
 850         attr->relaxed_ordering_write = MLX5_GET(cmd_hca_cap, hcattr,
 851                                                 relaxed_ordering_write);
 852         attr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr,
 853                                                relaxed_ordering_read);
 854         attr->access_register_user = MLX5_GET(cmd_hca_cap, hcattr,
 855                                               access_register_user);
 856         attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr,
 857                                           eth_net_offloads);
 858         attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt);
 859         attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr,
 860                                                flex_parser_protocols);
 861         attr->max_geneve_tlv_options = MLX5_GET(cmd_hca_cap, hcattr,
 862                         max_geneve_tlv_options);
 863         attr->max_geneve_tlv_option_data_len = MLX5_GET(cmd_hca_cap, hcattr,
 864                         max_geneve_tlv_option_data_len);
 865         attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos);
 866         attr->qos.flow_meter_aso_sup = !!(MLX5_GET64(cmd_hca_cap, hcattr,
 867                                          general_obj_types) &
 868                               MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO);
 869         attr->vdpa.valid = !!(MLX5_GET64(cmd_hca_cap, hcattr,
 870                                          general_obj_types) &
 871                               MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q);
 872         attr->vdpa.queue_counters_valid = !!(MLX5_GET64(cmd_hca_cap, hcattr,
 873                                                         general_obj_types) &
 874                                   MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS);
 875         attr->parse_graph_flex_node = !!(MLX5_GET64(cmd_hca_cap, hcattr,
 876                                          general_obj_types) &
 877                               MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE);
 878         attr->wqe_index_ignore = MLX5_GET(cmd_hca_cap, hcattr,
 879                                           wqe_index_ignore_cap);
 880         attr->cross_channel = MLX5_GET(cmd_hca_cap, hcattr, cd);
 881         attr->non_wire_sq = MLX5_GET(cmd_hca_cap, hcattr, non_wire_sq);
 882         attr->log_max_static_sq_wq = MLX5_GET(cmd_hca_cap, hcattr,
 883                                               log_max_static_sq_wq);
 884         attr->num_lag_ports = MLX5_GET(cmd_hca_cap, hcattr, num_lag_ports);
 885         attr->dev_freq_khz = MLX5_GET(cmd_hca_cap, hcattr,
 886                                       device_frequency_khz);
 887         attr->scatter_fcs_w_decap_disable =
 888                 MLX5_GET(cmd_hca_cap, hcattr, scatter_fcs_w_decap_disable);
 889         attr->roce = MLX5_GET(cmd_hca_cap, hcattr, roce);
 890         attr->rq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, rq_ts_format);
 891         attr->sq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, sq_ts_format);
 892         attr->steering_format_version =
 893                 MLX5_GET(cmd_hca_cap, hcattr, steering_format_version);
 894         attr->regexp_params = MLX5_GET(cmd_hca_cap, hcattr, regexp_params);
 895         attr->regexp_version = MLX5_GET(cmd_hca_cap, hcattr, regexp_version);
 896         attr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr,
 897                                                regexp_num_of_engines);
 898         /* Read the general_obj_types bitmap and extract the relevant bits. */
 899         general_obj_types_supported = MLX5_GET64(cmd_hca_cap, hcattr,
 900                                                  general_obj_types);
 901         attr->vdpa.valid = !!(general_obj_types_supported &
 902                               MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q);
 903         attr->vdpa.queue_counters_valid =
 904                         !!(general_obj_types_supported &
 905                            MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS);
 906         attr->parse_graph_flex_node =
 907                         !!(general_obj_types_supported &
 908                            MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE);
 909         attr->flow_hit_aso = !!(general_obj_types_supported &
 910                                 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO);
 911         attr->geneve_tlv_opt = !!(general_obj_types_supported &
 912                                   MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT);
 913         attr->dek = !!(general_obj_types_supported &
 914                        MLX5_GENERAL_OBJ_TYPES_CAP_DEK);
 915         attr->import_kek = !!(general_obj_types_supported &
 916                               MLX5_GENERAL_OBJ_TYPES_CAP_IMPORT_KEK);
 917         attr->credential = !!(general_obj_types_supported &
 918                               MLX5_GENERAL_OBJ_TYPES_CAP_CREDENTIAL);
 919         attr->crypto_login = !!(general_obj_types_supported &
 920                                 MLX5_GENERAL_OBJ_TYPES_CAP_CRYPTO_LOGIN);
 921         /* Add reading of other GENERAL_OBJ_TYPES_CAP bits above this line. */
 922         attr->log_max_cq = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq);
 923         attr->log_max_qp = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp);
 924         attr->log_max_cq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq_sz);
 925         attr->log_max_qp_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp_sz);
 926         attr->log_max_mrw_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_mrw_sz);
 927         attr->log_max_pd = MLX5_GET(cmd_hca_cap, hcattr, log_max_pd);
 928         attr->log_max_srq = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq);
 929         attr->log_max_srq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq_sz);
 930         attr->reg_c_preserve =
 931                 MLX5_GET(cmd_hca_cap, hcattr, reg_c_preserve);
 932         attr->mmo_regex_qp_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_qp);
 933         attr->mmo_regex_sq_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_sq);
 934         attr->mmo_dma_sq_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_sq);
 935         attr->mmo_compress_sq_en = MLX5_GET(cmd_hca_cap, hcattr,
 936                         compress_mmo_sq);
 937         attr->mmo_decompress_sq_en = MLX5_GET(cmd_hca_cap, hcattr,
 938                         decompress_mmo_sq);
 939         attr->mmo_dma_qp_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_qp);
 940         attr->mmo_compress_qp_en = MLX5_GET(cmd_hca_cap, hcattr,
 941                         compress_mmo_qp);
 942         attr->mmo_decompress_qp_en = MLX5_GET(cmd_hca_cap, hcattr,
 943                         decompress_mmo_qp);
 944         attr->compress_min_block_size = MLX5_GET(cmd_hca_cap, hcattr,
 945                                                  compress_min_block_size);
 946         attr->log_max_mmo_dma = MLX5_GET(cmd_hca_cap, hcattr, log_dma_mmo_size);
 947         attr->log_max_mmo_compress = MLX5_GET(cmd_hca_cap, hcattr,
 948                                               log_compress_mmo_size);
 949         attr->log_max_mmo_decompress = MLX5_GET(cmd_hca_cap, hcattr,
 950                                                 log_decompress_mmo_size);
 951         attr->cqe_compression = MLX5_GET(cmd_hca_cap, hcattr, cqe_compression);
 952         attr->mini_cqe_resp_flow_tag = MLX5_GET(cmd_hca_cap, hcattr,
 953                                                 mini_cqe_resp_flow_tag);
 954         attr->mini_cqe_resp_l3_l4_tag = MLX5_GET(cmd_hca_cap, hcattr,
 955                                                  mini_cqe_resp_l3_l4_tag);
 956         attr->umr_indirect_mkey_disabled =
 957                 MLX5_GET(cmd_hca_cap, hcattr, umr_indirect_mkey_disabled);
 958         attr->umr_modify_entity_size_disabled =
 959                 MLX5_GET(cmd_hca_cap, hcattr, umr_modify_entity_size_disabled);
 960         attr->crypto = MLX5_GET(cmd_hca_cap, hcattr, crypto);
 961         if (attr->crypto)
 962                 attr->aes_xts = MLX5_GET(cmd_hca_cap, hcattr, aes_xts);
 963         attr->ct_offload = !!(MLX5_GET64(cmd_hca_cap, hcattr,
 964                                          general_obj_types) &
 965                               MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD);
 966         if (attr->qos.sup) {
 967                 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
 968                                 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP |
 969                                 MLX5_HCA_CAP_OPMOD_GET_CUR);
 970                 if (!hcattr) {
 971                         DRV_LOG(DEBUG, "Failed to query devx QOS capabilities");
 972                         return rc;
 973                 }
 974                 attr->qos.flow_meter_old =
 975                                 MLX5_GET(qos_cap, hcattr, flow_meter_old);
 976                 attr->qos.log_max_flow_meter =
 977                                 MLX5_GET(qos_cap, hcattr, log_max_flow_meter);
 978                 attr->qos.flow_meter_reg_c_ids =
 979                                 MLX5_GET(qos_cap, hcattr, flow_meter_reg_id);
 980                 attr->qos.flow_meter =
 981                                 MLX5_GET(qos_cap, hcattr, flow_meter);
 982                 attr->qos.packet_pacing =
 983                                 MLX5_GET(qos_cap, hcattr, packet_pacing);
 984                 attr->qos.wqe_rate_pp =
 985                                 MLX5_GET(qos_cap, hcattr, wqe_rate_pp);
 986                 if (attr->qos.flow_meter_aso_sup) {
 987                         attr->qos.log_meter_aso_granularity =
 988                                 MLX5_GET(qos_cap, hcattr,
 989                                         log_meter_aso_granularity);
 990                         attr->qos.log_meter_aso_max_alloc =
 991                                 MLX5_GET(qos_cap, hcattr,
 992                                         log_meter_aso_max_alloc);
 993                         attr->qos.log_max_num_meter_aso =
 994                                 MLX5_GET(qos_cap, hcattr,
 995                                         log_max_num_meter_aso);
 996                 }
 997         }
 998         /*
 999          * Flex item support needs max_num_prog_sample_field
1000          * from the Capabilities 2 table for PARSE_GRAPH_NODE
1001          */
1002         if (attr->parse_graph_flex_node) {
1003                 rc = mlx5_devx_cmd_query_hca_parse_graph_node_cap
1004                         (ctx, &attr->flex);
1005                 if (rc)
1006                         return -1;
1007         }
1008         if (attr->vdpa.valid)
1009                 mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa);
1010         if (!attr->eth_net_offloads)
1011                 return 0;
1012         /* Query Flow Sampler Capability From FLow Table Properties Layout. */
1013         hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1014                         MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE |
1015                         MLX5_HCA_CAP_OPMOD_GET_CUR);
1016         if (!hcattr) {
1017                 attr->log_max_ft_sampler_num = 0;
1018                 return rc;
1019         }
1020         attr->log_max_ft_sampler_num = MLX5_GET
1021                 (flow_table_nic_cap, hcattr,
1022                  flow_table_properties_nic_receive.log_max_ft_sampler_num);
1023         attr->flow.tunnel_header_0_1 = MLX5_GET
1024                 (flow_table_nic_cap, hcattr,
1025                  ft_field_support_2_nic_receive.tunnel_header_0_1);
1026         attr->pkt_integrity_match = mlx5_devx_query_pkt_integrity_match(hcattr);
1027         attr->inner_ipv4_ihl = MLX5_GET
1028                 (flow_table_nic_cap, hcattr,
1029                  ft_field_support_2_nic_receive.inner_ipv4_ihl);
1030         attr->outer_ipv4_ihl = MLX5_GET
1031                 (flow_table_nic_cap, hcattr,
1032                  ft_field_support_2_nic_receive.outer_ipv4_ihl);
1033         /* Query HCA offloads for Ethernet protocol. */
1034         hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1035                         MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS |
1036                         MLX5_HCA_CAP_OPMOD_GET_CUR);
1037         if (!hcattr) {
1038                 attr->eth_net_offloads = 0;
1039                 return rc;
1040         }
1041         attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps,
1042                                          hcattr, wqe_vlan_insert);
1043         attr->csum_cap = MLX5_GET(per_protocol_networking_offload_caps,
1044                                          hcattr, csum_cap);
1045         attr->vlan_cap = MLX5_GET(per_protocol_networking_offload_caps,
1046                                          hcattr, vlan_cap);
1047         attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr,
1048                                  lro_cap);
1049         attr->max_lso_cap = MLX5_GET(per_protocol_networking_offload_caps,
1050                                  hcattr, max_lso_cap);
1051         attr->scatter_fcs = MLX5_GET(per_protocol_networking_offload_caps,
1052                                  hcattr, scatter_fcs);
1053         attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps,
1054                                         hcattr, tunnel_lro_gre);
1055         attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps,
1056                                           hcattr, tunnel_lro_vxlan);
1057         attr->swp = MLX5_GET(per_protocol_networking_offload_caps,
1058                                           hcattr, swp);
1059         attr->tunnel_stateless_gre =
1060                                 MLX5_GET(per_protocol_networking_offload_caps,
1061                                           hcattr, tunnel_stateless_gre);
1062         attr->tunnel_stateless_vxlan =
1063                                 MLX5_GET(per_protocol_networking_offload_caps,
1064                                           hcattr, tunnel_stateless_vxlan);
1065         attr->swp_csum = MLX5_GET(per_protocol_networking_offload_caps,
1066                                           hcattr, swp_csum);
1067         attr->swp_lso = MLX5_GET(per_protocol_networking_offload_caps,
1068                                           hcattr, swp_lso);
1069         attr->lro_max_msg_sz_mode = MLX5_GET
1070                                         (per_protocol_networking_offload_caps,
1071                                          hcattr, lro_max_msg_sz_mode);
1072         for (i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) {
1073                 attr->lro_timer_supported_periods[i] =
1074                         MLX5_GET(per_protocol_networking_offload_caps, hcattr,
1075                                  lro_timer_supported_periods[i]);
1076         }
1077         attr->lro_min_mss_size = MLX5_GET(per_protocol_networking_offload_caps,
1078                                           hcattr, lro_min_mss_size);
1079         attr->tunnel_stateless_geneve_rx =
1080                             MLX5_GET(per_protocol_networking_offload_caps,
1081                                      hcattr, tunnel_stateless_geneve_rx);
1082         attr->geneve_max_opt_len =
1083                     MLX5_GET(per_protocol_networking_offload_caps,
1084                              hcattr, max_geneve_opt_len);
1085         attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps,
1086                                          hcattr, wqe_inline_mode);
1087         attr->tunnel_stateless_gtp = MLX5_GET
1088                                         (per_protocol_networking_offload_caps,
1089                                          hcattr, tunnel_stateless_gtp);
1090         attr->rss_ind_tbl_cap = MLX5_GET
1091                                         (per_protocol_networking_offload_caps,
1092                                          hcattr, rss_ind_tbl_cap);
1093         /* Query HCA attribute for ROCE. */
1094         if (attr->roce) {
1095                 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1096                                 MLX5_GET_HCA_CAP_OP_MOD_ROCE |
1097                                 MLX5_HCA_CAP_OPMOD_GET_CUR);
1098                 if (!hcattr) {
1099                         DRV_LOG(DEBUG,
1100                                 "Failed to query devx HCA ROCE capabilities");
1101                         return rc;
1102                 }
1103                 attr->qp_ts_format = MLX5_GET(roce_caps, hcattr, qp_ts_format);
1104         }
1105         if (attr->eth_virt &&
1106             attr->wqe_inline_mode == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT) {
1107                 rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr);
1108                 if (rc) {
1109                         attr->eth_virt = 0;
1110                         goto error;
1111                 }
1112         }
1113         return 0;
1114 error:
1115         rc = (rc > 0) ? -rc : rc;
1116         return rc;
1117 }
1118
1119 /**
1120  * Query TIS transport domain from QP verbs object using DevX API.
1121  *
1122  * @param[in] qp
1123  *   Pointer to verbs QP returned by ibv_create_qp .
1124  * @param[in] tis_num
1125  *   TIS number of TIS to query.
1126  * @param[out] tis_td
1127  *   Pointer to TIS transport domain variable, to be set by the routine.
1128  *
1129  * @return
1130  *   0 on success, a negative value otherwise.
1131  */
1132 int
1133 mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num,
1134                               uint32_t *tis_td)
1135 {
1136 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
1137         uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0};
1138         uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0};
1139         int rc;
1140         void *tis_ctx;
1141
1142         MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS);
1143         MLX5_SET(query_tis_in, in, tisn, tis_num);
1144         rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out));
1145         if (rc) {
1146                 DRV_LOG(ERR, "Failed to query QP using DevX");
1147                 return -rc;
1148         };
1149         tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context);
1150         *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain);
1151         return 0;
1152 #else
1153         (void)qp;
1154         (void)tis_num;
1155         (void)tis_td;
1156         return -ENOTSUP;
1157 #endif
1158 }
1159
1160 /**
1161  * Fill WQ data for DevX API command.
1162  * Utility function for use when creating DevX objects containing a WQ.
1163  *
1164  * @param[in] wq_ctx
1165  *   Pointer to WQ context to fill with data.
1166  * @param [in] wq_attr
1167  *   Pointer to WQ attributes structure to fill in WQ context.
1168  */
1169 static void
1170 devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr)
1171 {
1172         MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type);
1173         MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature);
1174         MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode);
1175         MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave);
1176         MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge);
1177         MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size);
1178         MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset);
1179         MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm);
1180         MLX5_SET(wq, wq_ctx, pd, wq_attr->pd);
1181         MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page);
1182         MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr);
1183         MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter);
1184         MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter);
1185         MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride);
1186         if (wq_attr->log_wq_pg_sz > MLX5_ADAPTER_PAGE_SHIFT)
1187                 MLX5_SET(wq, wq_ctx, log_wq_pg_sz,
1188                          wq_attr->log_wq_pg_sz - MLX5_ADAPTER_PAGE_SHIFT);
1189         MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz);
1190         MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid);
1191         MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid);
1192         MLX5_SET(wq, wq_ctx, log_hairpin_num_packets,
1193                  wq_attr->log_hairpin_num_packets);
1194         MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz);
1195         MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides,
1196                  wq_attr->single_wqe_log_num_of_strides);
1197         MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en);
1198         MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes,
1199                  wq_attr->single_stride_log_num_of_bytes);
1200         MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id);
1201         MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id);
1202         MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset);
1203 }
1204
1205 /**
1206  * Create RQ using DevX API.
1207  *
1208  * @param[in] ctx
1209  *   Context returned from mlx5 open_device() glue function.
1210  * @param [in] rq_attr
1211  *   Pointer to create RQ attributes structure.
1212  * @param [in] socket
1213  *   CPU socket ID for allocations.
1214  *
1215  * @return
1216  *   The DevX object created, NULL otherwise and rte_errno is set.
1217  */
1218 struct mlx5_devx_obj *
1219 mlx5_devx_cmd_create_rq(void *ctx,
1220                         struct mlx5_devx_create_rq_attr *rq_attr,
1221                         int socket)
1222 {
1223         uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0};
1224         uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0};
1225         void *rq_ctx, *wq_ctx;
1226         struct mlx5_devx_wq_attr *wq_attr;
1227         struct mlx5_devx_obj *rq = NULL;
1228
1229         rq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rq), 0, socket);
1230         if (!rq) {
1231                 DRV_LOG(ERR, "Failed to allocate RQ data");
1232                 rte_errno = ENOMEM;
1233                 return NULL;
1234         }
1235         MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ);
1236         rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx);
1237         MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky);
1238         MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en);
1239         MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);
1240         MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);
1241         MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type);
1242         MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
1243         MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en);
1244         MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin);
1245         MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index);
1246         MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn);
1247         MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
1248         MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn);
1249         MLX5_SET(sqc, rq_ctx, ts_format, rq_attr->ts_format);
1250         wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);
1251         wq_attr = &rq_attr->wq_attr;
1252         devx_cmd_fill_wq_data(wq_ctx, wq_attr);
1253         rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1254                                                   out, sizeof(out));
1255         if (!rq->obj) {
1256                 DRV_LOG(ERR, "Failed to create RQ using DevX");
1257                 rte_errno = errno;
1258                 mlx5_free(rq);
1259                 return NULL;
1260         }
1261         rq->id = MLX5_GET(create_rq_out, out, rqn);
1262         return rq;
1263 }
1264
1265 /**
1266  * Modify RQ using DevX API.
1267  *
1268  * @param[in] rq
1269  *   Pointer to RQ object structure.
1270  * @param [in] rq_attr
1271  *   Pointer to modify RQ attributes structure.
1272  *
1273  * @return
1274  *   0 on success, a negative errno value otherwise and rte_errno is set.
1275  */
1276 int
1277 mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,
1278                         struct mlx5_devx_modify_rq_attr *rq_attr)
1279 {
1280         uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0};
1281         uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0};
1282         void *rq_ctx, *wq_ctx;
1283         int ret;
1284
1285         MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ);
1286         MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state);
1287         MLX5_SET(modify_rq_in, in, rqn, rq->id);
1288         MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask);
1289         rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1290         MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
1291         if (rq_attr->modify_bitmask &
1292                         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS)
1293                 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);
1294         if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD)
1295                 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);
1296         if (rq_attr->modify_bitmask &
1297                         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID)
1298                 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
1299         MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq);
1300         MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca);
1301         if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) {
1302                 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);
1303                 MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm);
1304         }
1305         ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in),
1306                                          out, sizeof(out));
1307         if (ret) {
1308                 DRV_LOG(ERR, "Failed to modify RQ using DevX");
1309                 rte_errno = errno;
1310                 return -errno;
1311         }
1312         return ret;
1313 }
1314
1315 /**
1316  * Create TIR using DevX API.
1317  *
1318  * @param[in] ctx
1319  *  Context returned from mlx5 open_device() glue function.
1320  * @param [in] tir_attr
1321  *   Pointer to TIR attributes structure.
1322  *
1323  * @return
1324  *   The DevX object created, NULL otherwise and rte_errno is set.
1325  */
1326 struct mlx5_devx_obj *
1327 mlx5_devx_cmd_create_tir(void *ctx,
1328                          struct mlx5_devx_tir_attr *tir_attr)
1329 {
1330         uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
1331         uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0};
1332         void *tir_ctx, *outer, *inner, *rss_key;
1333         struct mlx5_devx_obj *tir = NULL;
1334
1335         tir = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tir), 0, SOCKET_ID_ANY);
1336         if (!tir) {
1337                 DRV_LOG(ERR, "Failed to allocate TIR data");
1338                 rte_errno = ENOMEM;
1339                 return NULL;
1340         }
1341         MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR);
1342         tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx);
1343         MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type);
1344         MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs,
1345                  tir_attr->lro_timeout_period_usecs);
1346         MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask);
1347         MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz);
1348         MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn);
1349         MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric);
1350         MLX5_SET(tirc, tir_ctx, tunneled_offload_en,
1351                  tir_attr->tunneled_offload_en);
1352         MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table);
1353         MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn);
1354         MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block);
1355         MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain);
1356         rss_key = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_toeplitz_key);
1357         memcpy(rss_key, tir_attr->rx_hash_toeplitz_key, MLX5_RSS_HASH_KEY_LEN);
1358         outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer);
1359         MLX5_SET(rx_hash_field_select, outer, l3_prot_type,
1360                  tir_attr->rx_hash_field_selector_outer.l3_prot_type);
1361         MLX5_SET(rx_hash_field_select, outer, l4_prot_type,
1362                  tir_attr->rx_hash_field_selector_outer.l4_prot_type);
1363         MLX5_SET(rx_hash_field_select, outer, selected_fields,
1364                  tir_attr->rx_hash_field_selector_outer.selected_fields);
1365         inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner);
1366         MLX5_SET(rx_hash_field_select, inner, l3_prot_type,
1367                  tir_attr->rx_hash_field_selector_inner.l3_prot_type);
1368         MLX5_SET(rx_hash_field_select, inner, l4_prot_type,
1369                  tir_attr->rx_hash_field_selector_inner.l4_prot_type);
1370         MLX5_SET(rx_hash_field_select, inner, selected_fields,
1371                  tir_attr->rx_hash_field_selector_inner.selected_fields);
1372         tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1373                                                    out, sizeof(out));
1374         if (!tir->obj) {
1375                 DRV_LOG(ERR, "Failed to create TIR using DevX");
1376                 rte_errno = errno;
1377                 mlx5_free(tir);
1378                 return NULL;
1379         }
1380         tir->id = MLX5_GET(create_tir_out, out, tirn);
1381         return tir;
1382 }
1383
1384 /**
1385  * Modify TIR using DevX API.
1386  *
1387  * @param[in] tir
1388  *   Pointer to TIR DevX object structure.
1389  * @param [in] modify_tir_attr
1390  *   Pointer to TIR modification attributes structure.
1391  *
1392  * @return
1393  *   0 on success, a negative errno value otherwise and rte_errno is set.
1394  */
1395 int
1396 mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir,
1397                          struct mlx5_devx_modify_tir_attr *modify_tir_attr)
1398 {
1399         struct mlx5_devx_tir_attr *tir_attr = &modify_tir_attr->tir;
1400         uint32_t in[MLX5_ST_SZ_DW(modify_tir_in)] = {0};
1401         uint32_t out[MLX5_ST_SZ_DW(modify_tir_out)] = {0};
1402         void *tir_ctx;
1403         int ret;
1404
1405         MLX5_SET(modify_tir_in, in, opcode, MLX5_CMD_OP_MODIFY_TIR);
1406         MLX5_SET(modify_tir_in, in, tirn, modify_tir_attr->tirn);
1407         MLX5_SET64(modify_tir_in, in, modify_bitmask,
1408                    modify_tir_attr->modify_bitmask);
1409         tir_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1410         if (modify_tir_attr->modify_bitmask &
1411                         MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO) {
1412                 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs,
1413                          tir_attr->lro_timeout_period_usecs);
1414                 MLX5_SET(tirc, tir_ctx, lro_enable_mask,
1415                          tir_attr->lro_enable_mask);
1416                 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz,
1417                          tir_attr->lro_max_msg_sz);
1418         }
1419         if (modify_tir_attr->modify_bitmask &
1420                         MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE)
1421                 MLX5_SET(tirc, tir_ctx, indirect_table,
1422                          tir_attr->indirect_table);
1423         if (modify_tir_attr->modify_bitmask &
1424                         MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH) {
1425                 int i;
1426                 void *outer, *inner;
1427
1428                 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric,
1429                          tir_attr->rx_hash_symmetric);
1430                 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn);
1431                 for (i = 0; i < 10; i++) {
1432                         MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i],
1433                                  tir_attr->rx_hash_toeplitz_key[i]);
1434                 }
1435                 outer = MLX5_ADDR_OF(tirc, tir_ctx,
1436                                      rx_hash_field_selector_outer);
1437                 MLX5_SET(rx_hash_field_select, outer, l3_prot_type,
1438                          tir_attr->rx_hash_field_selector_outer.l3_prot_type);
1439                 MLX5_SET(rx_hash_field_select, outer, l4_prot_type,
1440                          tir_attr->rx_hash_field_selector_outer.l4_prot_type);
1441                 MLX5_SET
1442                 (rx_hash_field_select, outer, selected_fields,
1443                  tir_attr->rx_hash_field_selector_outer.selected_fields);
1444                 inner = MLX5_ADDR_OF(tirc, tir_ctx,
1445                                      rx_hash_field_selector_inner);
1446                 MLX5_SET(rx_hash_field_select, inner, l3_prot_type,
1447                          tir_attr->rx_hash_field_selector_inner.l3_prot_type);
1448                 MLX5_SET(rx_hash_field_select, inner, l4_prot_type,
1449                          tir_attr->rx_hash_field_selector_inner.l4_prot_type);
1450                 MLX5_SET
1451                 (rx_hash_field_select, inner, selected_fields,
1452                  tir_attr->rx_hash_field_selector_inner.selected_fields);
1453         }
1454         if (modify_tir_attr->modify_bitmask &
1455             MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN) {
1456                 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block);
1457         }
1458         ret = mlx5_glue->devx_obj_modify(tir->obj, in, sizeof(in),
1459                                          out, sizeof(out));
1460         if (ret) {
1461                 DRV_LOG(ERR, "Failed to modify TIR using DevX");
1462                 rte_errno = errno;
1463                 return -errno;
1464         }
1465         return ret;
1466 }
1467
1468 /**
1469  * Create RQT using DevX API.
1470  *
1471  * @param[in] ctx
1472  *   Context returned from mlx5 open_device() glue function.
1473  * @param [in] rqt_attr
1474  *   Pointer to RQT attributes structure.
1475  *
1476  * @return
1477  *   The DevX object created, NULL otherwise and rte_errno is set.
1478  */
1479 struct mlx5_devx_obj *
1480 mlx5_devx_cmd_create_rqt(void *ctx,
1481                          struct mlx5_devx_rqt_attr *rqt_attr)
1482 {
1483         uint32_t *in = NULL;
1484         uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) +
1485                          rqt_attr->rqt_actual_size * sizeof(uint32_t);
1486         uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0};
1487         void *rqt_ctx;
1488         struct mlx5_devx_obj *rqt = NULL;
1489         int i;
1490
1491         in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY);
1492         if (!in) {
1493                 DRV_LOG(ERR, "Failed to allocate RQT IN data");
1494                 rte_errno = ENOMEM;
1495                 return NULL;
1496         }
1497         rqt = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt), 0, SOCKET_ID_ANY);
1498         if (!rqt) {
1499                 DRV_LOG(ERR, "Failed to allocate RQT data");
1500                 rte_errno = ENOMEM;
1501                 mlx5_free(in);
1502                 return NULL;
1503         }
1504         MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
1505         rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1506         MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type);
1507         MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size);
1508         MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size);
1509         for (i = 0; i < rqt_attr->rqt_actual_size; i++)
1510                 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]);
1511         rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out));
1512         mlx5_free(in);
1513         if (!rqt->obj) {
1514                 DRV_LOG(ERR, "Failed to create RQT using DevX");
1515                 rte_errno = errno;
1516                 mlx5_free(rqt);
1517                 return NULL;
1518         }
1519         rqt->id = MLX5_GET(create_rqt_out, out, rqtn);
1520         return rqt;
1521 }
1522
1523 /**
1524  * Modify RQT using DevX API.
1525  *
1526  * @param[in] rqt
1527  *   Pointer to RQT DevX object structure.
1528  * @param [in] rqt_attr
1529  *   Pointer to RQT attributes structure.
1530  *
1531  * @return
1532  *   0 on success, a negative errno value otherwise and rte_errno is set.
1533  */
1534 int
1535 mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt,
1536                          struct mlx5_devx_rqt_attr *rqt_attr)
1537 {
1538         uint32_t inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) +
1539                          rqt_attr->rqt_actual_size * sizeof(uint32_t);
1540         uint32_t out[MLX5_ST_SZ_DW(modify_rqt_out)] = {0};
1541         uint32_t *in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY);
1542         void *rqt_ctx;
1543         int i;
1544         int ret;
1545
1546         if (!in) {
1547                 DRV_LOG(ERR, "Failed to allocate RQT modify IN data.");
1548                 rte_errno = ENOMEM;
1549                 return -ENOMEM;
1550         }
1551         MLX5_SET(modify_rqt_in, in, opcode, MLX5_CMD_OP_MODIFY_RQT);
1552         MLX5_SET(modify_rqt_in, in, rqtn, rqt->id);
1553         MLX5_SET64(modify_rqt_in, in, modify_bitmask, 0x1);
1554         rqt_ctx = MLX5_ADDR_OF(modify_rqt_in, in, rqt_context);
1555         MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type);
1556         MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size);
1557         MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size);
1558         for (i = 0; i < rqt_attr->rqt_actual_size; i++)
1559                 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]);
1560         ret = mlx5_glue->devx_obj_modify(rqt->obj, in, inlen, out, sizeof(out));
1561         mlx5_free(in);
1562         if (ret) {
1563                 DRV_LOG(ERR, "Failed to modify RQT using DevX.");
1564                 rte_errno = errno;
1565                 return -rte_errno;
1566         }
1567         return ret;
1568 }
1569
1570 /**
1571  * Create SQ using DevX API.
1572  *
1573  * @param[in] ctx
1574  *   Context returned from mlx5 open_device() glue function.
1575  * @param [in] sq_attr
1576  *   Pointer to SQ attributes structure.
1577  * @param [in] socket
1578  *   CPU socket ID for allocations.
1579  *
1580  * @return
1581  *   The DevX object created, NULL otherwise and rte_errno is set.
1582  **/
1583 struct mlx5_devx_obj *
1584 mlx5_devx_cmd_create_sq(void *ctx,
1585                         struct mlx5_devx_create_sq_attr *sq_attr)
1586 {
1587         uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0};
1588         uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0};
1589         void *sq_ctx;
1590         void *wq_ctx;
1591         struct mlx5_devx_wq_attr *wq_attr;
1592         struct mlx5_devx_obj *sq = NULL;
1593
1594         sq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sq), 0, SOCKET_ID_ANY);
1595         if (!sq) {
1596                 DRV_LOG(ERR, "Failed to allocate SQ data");
1597                 rte_errno = ENOMEM;
1598                 return NULL;
1599         }
1600         MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ);
1601         sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx);
1602         MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky);
1603         MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master);
1604         MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre);
1605         MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en);
1606         MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe,
1607                  sq_attr->allow_multi_pkt_send_wqe);
1608         MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode,
1609                  sq_attr->min_wqe_inline_mode);
1610         MLX5_SET(sqc, sq_ctx, state, sq_attr->state);
1611         MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr);
1612         MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp);
1613         MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin);
1614         MLX5_SET(sqc, sq_ctx, non_wire, sq_attr->non_wire);
1615         MLX5_SET(sqc, sq_ctx, static_sq_wq, sq_attr->static_sq_wq);
1616         MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index);
1617         MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn);
1618         MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index,
1619                  sq_attr->packet_pacing_rate_limit_index);
1620         MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz);
1621         MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num);
1622         MLX5_SET(sqc, sq_ctx, ts_format, sq_attr->ts_format);
1623         wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq);
1624         wq_attr = &sq_attr->wq_attr;
1625         devx_cmd_fill_wq_data(wq_ctx, wq_attr);
1626         sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1627                                              out, sizeof(out));
1628         if (!sq->obj) {
1629                 DRV_LOG(ERR, "Failed to create SQ using DevX");
1630                 rte_errno = errno;
1631                 mlx5_free(sq);
1632                 return NULL;
1633         }
1634         sq->id = MLX5_GET(create_sq_out, out, sqn);
1635         return sq;
1636 }
1637
1638 /**
1639  * Modify SQ using DevX API.
1640  *
1641  * @param[in] sq
1642  *   Pointer to SQ object structure.
1643  * @param [in] sq_attr
1644  *   Pointer to SQ attributes structure.
1645  *
1646  * @return
1647  *   0 on success, a negative errno value otherwise and rte_errno is set.
1648  */
1649 int
1650 mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq,
1651                         struct mlx5_devx_modify_sq_attr *sq_attr)
1652 {
1653         uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0};
1654         uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0};
1655         void *sq_ctx;
1656         int ret;
1657
1658         MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ);
1659         MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state);
1660         MLX5_SET(modify_sq_in, in, sqn, sq->id);
1661         sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1662         MLX5_SET(sqc, sq_ctx, state, sq_attr->state);
1663         MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq);
1664         MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca);
1665         ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in),
1666                                          out, sizeof(out));
1667         if (ret) {
1668                 DRV_LOG(ERR, "Failed to modify SQ using DevX");
1669                 rte_errno = errno;
1670                 return -rte_errno;
1671         }
1672         return ret;
1673 }
1674
1675 /**
1676  * Create TIS using DevX API.
1677  *
1678  * @param[in] ctx
1679  *   Context returned from mlx5 open_device() glue function.
1680  * @param [in] tis_attr
1681  *   Pointer to TIS attributes structure.
1682  *
1683  * @return
1684  *   The DevX object created, NULL otherwise and rte_errno is set.
1685  */
1686 struct mlx5_devx_obj *
1687 mlx5_devx_cmd_create_tis(void *ctx,
1688                          struct mlx5_devx_tis_attr *tis_attr)
1689 {
1690         uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
1691         uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0};
1692         struct mlx5_devx_obj *tis = NULL;
1693         void *tis_ctx;
1694
1695         tis = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tis), 0, SOCKET_ID_ANY);
1696         if (!tis) {
1697                 DRV_LOG(ERR, "Failed to allocate TIS object");
1698                 rte_errno = ENOMEM;
1699                 return NULL;
1700         }
1701         MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS);
1702         tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx);
1703         MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity,
1704                  tis_attr->strict_lag_tx_port_affinity);
1705         MLX5_SET(tisc, tis_ctx, lag_tx_port_affinity,
1706                  tis_attr->lag_tx_port_affinity);
1707         MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio);
1708         MLX5_SET(tisc, tis_ctx, transport_domain,
1709                  tis_attr->transport_domain);
1710         tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1711                                               out, sizeof(out));
1712         if (!tis->obj) {
1713                 DRV_LOG(ERR, "Failed to create TIS using DevX");
1714                 rte_errno = errno;
1715                 mlx5_free(tis);
1716                 return NULL;
1717         }
1718         tis->id = MLX5_GET(create_tis_out, out, tisn);
1719         return tis;
1720 }
1721
1722 /**
1723  * Create transport domain using DevX API.
1724  *
1725  * @param[in] ctx
1726  *   Context returned from mlx5 open_device() glue function.
1727  * @return
1728  *   The DevX object created, NULL otherwise and rte_errno is set.
1729  */
1730 struct mlx5_devx_obj *
1731 mlx5_devx_cmd_create_td(void *ctx)
1732 {
1733         uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0};
1734         uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0};
1735         struct mlx5_devx_obj *td = NULL;
1736
1737         td = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*td), 0, SOCKET_ID_ANY);
1738         if (!td) {
1739                 DRV_LOG(ERR, "Failed to allocate TD object");
1740                 rte_errno = ENOMEM;
1741                 return NULL;
1742         }
1743         MLX5_SET(alloc_transport_domain_in, in, opcode,
1744                  MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN);
1745         td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1746                                              out, sizeof(out));
1747         if (!td->obj) {
1748                 DRV_LOG(ERR, "Failed to create TIS using DevX");
1749                 rte_errno = errno;
1750                 mlx5_free(td);
1751                 return NULL;
1752         }
1753         td->id = MLX5_GET(alloc_transport_domain_out, out,
1754                            transport_domain);
1755         return td;
1756 }
1757
1758 /**
1759  * Dump all flows to file.
1760  *
1761  * @param[in] fdb_domain
1762  *   FDB domain.
1763  * @param[in] rx_domain
1764  *   RX domain.
1765  * @param[in] tx_domain
1766  *   TX domain.
1767  * @param[out] file
1768  *   Pointer to file stream.
1769  *
1770  * @return
1771  *   0 on success, a nagative value otherwise.
1772  */
1773 int
1774 mlx5_devx_cmd_flow_dump(void *fdb_domain __rte_unused,
1775                         void *rx_domain __rte_unused,
1776                         void *tx_domain __rte_unused, FILE *file __rte_unused)
1777 {
1778         int ret = 0;
1779
1780 #ifdef HAVE_MLX5_DR_FLOW_DUMP
1781         if (fdb_domain) {
1782                 ret = mlx5_glue->dr_dump_domain(file, fdb_domain);
1783                 if (ret)
1784                         return ret;
1785         }
1786         MLX5_ASSERT(rx_domain);
1787         ret = mlx5_glue->dr_dump_domain(file, rx_domain);
1788         if (ret)
1789                 return ret;
1790         MLX5_ASSERT(tx_domain);
1791         ret = mlx5_glue->dr_dump_domain(file, tx_domain);
1792 #else
1793         ret = ENOTSUP;
1794 #endif
1795         return -ret;
1796 }
1797
1798 int
1799 mlx5_devx_cmd_flow_single_dump(void *rule_info __rte_unused,
1800                         FILE *file __rte_unused)
1801 {
1802         int ret = 0;
1803 #ifdef HAVE_MLX5_DR_FLOW_DUMP_RULE
1804         if (rule_info)
1805                 ret = mlx5_glue->dr_dump_rule(file, rule_info);
1806 #else
1807         ret = ENOTSUP;
1808 #endif
1809         return -ret;
1810 }
1811
1812 /*
1813  * Create CQ using DevX API.
1814  *
1815  * @param[in] ctx
1816  *   Context returned from mlx5 open_device() glue function.
1817  * @param [in] attr
1818  *   Pointer to CQ attributes structure.
1819  *
1820  * @return
1821  *   The DevX object created, NULL otherwise and rte_errno is set.
1822  */
1823 struct mlx5_devx_obj *
1824 mlx5_devx_cmd_create_cq(void *ctx, struct mlx5_devx_cq_attr *attr)
1825 {
1826         uint32_t in[MLX5_ST_SZ_DW(create_cq_in)] = {0};
1827         uint32_t out[MLX5_ST_SZ_DW(create_cq_out)] = {0};
1828         struct mlx5_devx_obj *cq_obj = mlx5_malloc(MLX5_MEM_ZERO,
1829                                                    sizeof(*cq_obj),
1830                                                    0, SOCKET_ID_ANY);
1831         void *cqctx = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1832
1833         if (!cq_obj) {
1834                 DRV_LOG(ERR, "Failed to allocate CQ object memory.");
1835                 rte_errno = ENOMEM;
1836                 return NULL;
1837         }
1838         MLX5_SET(create_cq_in, in, opcode, MLX5_CMD_OP_CREATE_CQ);
1839         if (attr->db_umem_valid) {
1840                 MLX5_SET(cqc, cqctx, dbr_umem_valid, attr->db_umem_valid);
1841                 MLX5_SET(cqc, cqctx, dbr_umem_id, attr->db_umem_id);
1842                 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_umem_offset);
1843         } else {
1844                 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_addr);
1845         }
1846         MLX5_SET(cqc, cqctx, cqe_sz, (RTE_CACHE_LINE_SIZE == 128) ?
1847                                      MLX5_CQE_SIZE_128B : MLX5_CQE_SIZE_64B);
1848         MLX5_SET(cqc, cqctx, cc, attr->use_first_only);
1849         MLX5_SET(cqc, cqctx, oi, attr->overrun_ignore);
1850         MLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size);
1851         if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT)
1852                 MLX5_SET(cqc, cqctx, log_page_size,
1853                          attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT);
1854         MLX5_SET(cqc, cqctx, c_eqn, attr->eqn);
1855         MLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id);
1856         MLX5_SET(cqc, cqctx, cqe_comp_en, !!attr->cqe_comp_en);
1857         MLX5_SET(cqc, cqctx, mini_cqe_res_format, attr->mini_cqe_res_format);
1858         MLX5_SET(cqc, cqctx, mini_cqe_res_format_ext,
1859                  attr->mini_cqe_res_format_ext);
1860         if (attr->q_umem_valid) {
1861                 MLX5_SET(create_cq_in, in, cq_umem_valid, attr->q_umem_valid);
1862                 MLX5_SET(create_cq_in, in, cq_umem_id, attr->q_umem_id);
1863                 MLX5_SET64(create_cq_in, in, cq_umem_offset,
1864                            attr->q_umem_offset);
1865         }
1866         cq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
1867                                                  sizeof(out));
1868         if (!cq_obj->obj) {
1869                 rte_errno = errno;
1870                 DRV_LOG(ERR, "Failed to create CQ using DevX errno=%d.", errno);
1871                 mlx5_free(cq_obj);
1872                 return NULL;
1873         }
1874         cq_obj->id = MLX5_GET(create_cq_out, out, cqn);
1875         return cq_obj;
1876 }
1877
1878 /**
1879  * Create VIRTQ using DevX API.
1880  *
1881  * @param[in] ctx
1882  *   Context returned from mlx5 open_device() glue function.
1883  * @param [in] attr
1884  *   Pointer to VIRTQ attributes structure.
1885  *
1886  * @return
1887  *   The DevX object created, NULL otherwise and rte_errno is set.
1888  */
1889 struct mlx5_devx_obj *
1890 mlx5_devx_cmd_create_virtq(void *ctx,
1891                            struct mlx5_devx_virtq_attr *attr)
1892 {
1893         uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0};
1894         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
1895         struct mlx5_devx_obj *virtq_obj = mlx5_malloc(MLX5_MEM_ZERO,
1896                                                      sizeof(*virtq_obj),
1897                                                      0, SOCKET_ID_ANY);
1898         void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq);
1899         void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr);
1900         void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context);
1901
1902         if (!virtq_obj) {
1903                 DRV_LOG(ERR, "Failed to allocate virtq data.");
1904                 rte_errno = ENOMEM;
1905                 return NULL;
1906         }
1907         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
1908                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
1909         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
1910                  MLX5_GENERAL_OBJ_TYPE_VIRTQ);
1911         MLX5_SET16(virtio_net_q, virtq, hw_available_index,
1912                    attr->hw_available_index);
1913         MLX5_SET16(virtio_net_q, virtq, hw_used_index, attr->hw_used_index);
1914         MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4);
1915         MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6);
1916         MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum);
1917         MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum);
1918         MLX5_SET16(virtio_q, virtctx, virtio_version_1_0,
1919                    attr->virtio_version_1_0);
1920         MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode);
1921         MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id);
1922         MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr);
1923         MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr);
1924         MLX5_SET64(virtio_q, virtctx, available_addr, attr->available_addr);
1925         MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index);
1926         MLX5_SET16(virtio_q, virtctx, queue_size, attr->q_size);
1927         MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey);
1928         MLX5_SET(virtio_q, virtctx, umem_1_id, attr->umems[0].id);
1929         MLX5_SET(virtio_q, virtctx, umem_1_size, attr->umems[0].size);
1930         MLX5_SET64(virtio_q, virtctx, umem_1_offset, attr->umems[0].offset);
1931         MLX5_SET(virtio_q, virtctx, umem_2_id, attr->umems[1].id);
1932         MLX5_SET(virtio_q, virtctx, umem_2_size, attr->umems[1].size);
1933         MLX5_SET64(virtio_q, virtctx, umem_2_offset, attr->umems[1].offset);
1934         MLX5_SET(virtio_q, virtctx, umem_3_id, attr->umems[2].id);
1935         MLX5_SET(virtio_q, virtctx, umem_3_size, attr->umems[2].size);
1936         MLX5_SET64(virtio_q, virtctx, umem_3_offset, attr->umems[2].offset);
1937         MLX5_SET(virtio_q, virtctx, counter_set_id, attr->counters_obj_id);
1938         MLX5_SET(virtio_q, virtctx, pd, attr->pd);
1939         MLX5_SET(virtio_q, virtctx, queue_period_mode, attr->hw_latency_mode);
1940         MLX5_SET(virtio_q, virtctx, queue_period_us, attr->hw_max_latency_us);
1941         MLX5_SET(virtio_q, virtctx, queue_max_count, attr->hw_max_pending_comp);
1942         MLX5_SET(virtio_net_q, virtq, tisn_or_qpn, attr->tis_id);
1943         virtq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
1944                                                     sizeof(out));
1945         if (!virtq_obj->obj) {
1946                 rte_errno = errno;
1947                 DRV_LOG(ERR, "Failed to create VIRTQ Obj using DevX.");
1948                 mlx5_free(virtq_obj);
1949                 return NULL;
1950         }
1951         virtq_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
1952         return virtq_obj;
1953 }
1954
1955 /**
1956  * Modify VIRTQ using DevX API.
1957  *
1958  * @param[in] virtq_obj
1959  *   Pointer to virtq object structure.
1960  * @param [in] attr
1961  *   Pointer to modify virtq attributes structure.
1962  *
1963  * @return
1964  *   0 on success, a negative errno value otherwise and rte_errno is set.
1965  */
1966 int
1967 mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj,
1968                            struct mlx5_devx_virtq_attr *attr)
1969 {
1970         uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0};
1971         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
1972         void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq);
1973         void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr);
1974         void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context);
1975         int ret;
1976
1977         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
1978                  MLX5_CMD_OP_MODIFY_GENERAL_OBJECT);
1979         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
1980                  MLX5_GENERAL_OBJ_TYPE_VIRTQ);
1981         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id);
1982         MLX5_SET64(virtio_net_q, virtq, modify_field_select, attr->type);
1983         MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index);
1984         switch (attr->type) {
1985         case MLX5_VIRTQ_MODIFY_TYPE_STATE:
1986                 MLX5_SET16(virtio_net_q, virtq, state, attr->state);
1987                 break;
1988         case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS:
1989                 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_mkey,
1990                          attr->dirty_bitmap_mkey);
1991                 MLX5_SET64(virtio_net_q, virtq, dirty_bitmap_addr,
1992                          attr->dirty_bitmap_addr);
1993                 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_size,
1994                          attr->dirty_bitmap_size);
1995                 break;
1996         case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE:
1997                 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_dump_enable,
1998                          attr->dirty_bitmap_dump_enable);
1999                 break;
2000         default:
2001                 rte_errno = EINVAL;
2002                 return -rte_errno;
2003         }
2004         ret = mlx5_glue->devx_obj_modify(virtq_obj->obj, in, sizeof(in),
2005                                          out, sizeof(out));
2006         if (ret) {
2007                 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX.");
2008                 rte_errno = errno;
2009                 return -rte_errno;
2010         }
2011         return ret;
2012 }
2013
2014 /**
2015  * Query VIRTQ using DevX API.
2016  *
2017  * @param[in] virtq_obj
2018  *   Pointer to virtq object structure.
2019  * @param [in/out] attr
2020  *   Pointer to virtq attributes structure.
2021  *
2022  * @return
2023  *   0 on success, a negative errno value otherwise and rte_errno is set.
2024  */
2025 int
2026 mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj,
2027                            struct mlx5_devx_virtq_attr *attr)
2028 {
2029         uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
2030         uint32_t out[MLX5_ST_SZ_DW(query_virtq_out)] = {0};
2031         void *hdr = MLX5_ADDR_OF(query_virtq_out, in, hdr);
2032         void *virtq = MLX5_ADDR_OF(query_virtq_out, out, virtq);
2033         int ret;
2034
2035         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2036                  MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
2037         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2038                  MLX5_GENERAL_OBJ_TYPE_VIRTQ);
2039         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id);
2040         ret = mlx5_glue->devx_obj_query(virtq_obj->obj, in, sizeof(in),
2041                                          out, sizeof(out));
2042         if (ret) {
2043                 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX.");
2044                 rte_errno = errno;
2045                 return -errno;
2046         }
2047         attr->hw_available_index = MLX5_GET16(virtio_net_q, virtq,
2048                                               hw_available_index);
2049         attr->hw_used_index = MLX5_GET16(virtio_net_q, virtq, hw_used_index);
2050         attr->state = MLX5_GET16(virtio_net_q, virtq, state);
2051         attr->error_type = MLX5_GET16(virtio_net_q, virtq,
2052                                       virtio_q_context.error_type);
2053         return ret;
2054 }
2055
2056 /**
2057  * Create QP using DevX API.
2058  *
2059  * @param[in] ctx
2060  *   Context returned from mlx5 open_device() glue function.
2061  * @param [in] attr
2062  *   Pointer to QP attributes structure.
2063  *
2064  * @return
2065  *   The DevX object created, NULL otherwise and rte_errno is set.
2066  */
2067 struct mlx5_devx_obj *
2068 mlx5_devx_cmd_create_qp(void *ctx,
2069                         struct mlx5_devx_qp_attr *attr)
2070 {
2071         uint32_t in[MLX5_ST_SZ_DW(create_qp_in)] = {0};
2072         uint32_t out[MLX5_ST_SZ_DW(create_qp_out)] = {0};
2073         struct mlx5_devx_obj *qp_obj = mlx5_malloc(MLX5_MEM_ZERO,
2074                                                    sizeof(*qp_obj),
2075                                                    0, SOCKET_ID_ANY);
2076         void *qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
2077
2078         if (!qp_obj) {
2079                 DRV_LOG(ERR, "Failed to allocate QP data.");
2080                 rte_errno = ENOMEM;
2081                 return NULL;
2082         }
2083         MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP);
2084         MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC);
2085         MLX5_SET(qpc, qpc, pd, attr->pd);
2086         MLX5_SET(qpc, qpc, ts_format, attr->ts_format);
2087         MLX5_SET(qpc, qpc, user_index, attr->user_index);
2088         if (attr->uar_index) {
2089                 if (attr->mmo) {
2090                         void *qpc_ext_and_pas_list = MLX5_ADDR_OF(create_qp_in,
2091                                 in, qpc_extension_and_pas_list);
2092                         void *qpc_ext = MLX5_ADDR_OF(qpc_extension_and_pas_list,
2093                                 qpc_ext_and_pas_list, qpc_data_extension);
2094                         MLX5_SET(qpc_extension, qpc_ext, mmo, 1);
2095                 }
2096                 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
2097                 MLX5_SET(qpc, qpc, uar_page, attr->uar_index);
2098                 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT)
2099                         MLX5_SET(qpc, qpc, log_page_size,
2100                                  attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT);
2101                 if (attr->sq_size) {
2102                         MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->sq_size));
2103                         MLX5_SET(qpc, qpc, cqn_snd, attr->cqn);
2104                         MLX5_SET(qpc, qpc, log_sq_size,
2105                                  rte_log2_u32(attr->sq_size));
2106                 } else {
2107                         MLX5_SET(qpc, qpc, no_sq, 1);
2108                 }
2109                 if (attr->rq_size) {
2110                         MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->rq_size));
2111                         MLX5_SET(qpc, qpc, cqn_rcv, attr->cqn);
2112                         MLX5_SET(qpc, qpc, log_rq_stride, attr->log_rq_stride -
2113                                  MLX5_LOG_RQ_STRIDE_SHIFT);
2114                         MLX5_SET(qpc, qpc, log_rq_size,
2115                                  rte_log2_u32(attr->rq_size));
2116                         MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ);
2117                 } else {
2118                         MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ);
2119                 }
2120                 if (attr->dbr_umem_valid) {
2121                         MLX5_SET(qpc, qpc, dbr_umem_valid,
2122                                  attr->dbr_umem_valid);
2123                         MLX5_SET(qpc, qpc, dbr_umem_id, attr->dbr_umem_id);
2124                 }
2125                 MLX5_SET64(qpc, qpc, dbr_addr, attr->dbr_address);
2126                 MLX5_SET64(create_qp_in, in, wq_umem_offset,
2127                            attr->wq_umem_offset);
2128                 MLX5_SET(create_qp_in, in, wq_umem_id, attr->wq_umem_id);
2129                 MLX5_SET(create_qp_in, in, wq_umem_valid, 1);
2130         } else {
2131                 /* Special QP to be managed by FW - no SQ\RQ\CQ\UAR\DB rec. */
2132                 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ);
2133                 MLX5_SET(qpc, qpc, no_sq, 1);
2134         }
2135         qp_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
2136                                                  sizeof(out));
2137         if (!qp_obj->obj) {
2138                 rte_errno = errno;
2139                 DRV_LOG(ERR, "Failed to create QP Obj using DevX.");
2140                 mlx5_free(qp_obj);
2141                 return NULL;
2142         }
2143         qp_obj->id = MLX5_GET(create_qp_out, out, qpn);
2144         return qp_obj;
2145 }
2146
2147 /**
2148  * Modify QP using DevX API.
2149  * Currently supports only force loop-back QP.
2150  *
2151  * @param[in] qp
2152  *   Pointer to QP object structure.
2153  * @param [in] qp_st_mod_op
2154  *   The QP state modification operation.
2155  * @param [in] remote_qp_id
2156  *   The remote QP ID for MLX5_CMD_OP_INIT2RTR_QP operation.
2157  *
2158  * @return
2159  *   0 on success, a negative errno value otherwise and rte_errno is set.
2160  */
2161 int
2162 mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op,
2163                               uint32_t remote_qp_id)
2164 {
2165         union {
2166                 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)];
2167                 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)];
2168                 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)];
2169         } in;
2170         union {
2171                 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)];
2172                 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)];
2173                 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)];
2174         } out;
2175         void *qpc;
2176         int ret;
2177         unsigned int inlen;
2178         unsigned int outlen;
2179
2180         memset(&in, 0, sizeof(in));
2181         memset(&out, 0, sizeof(out));
2182         MLX5_SET(rst2init_qp_in, &in, opcode, qp_st_mod_op);
2183         switch (qp_st_mod_op) {
2184         case MLX5_CMD_OP_RST2INIT_QP:
2185                 MLX5_SET(rst2init_qp_in, &in, qpn, qp->id);
2186                 qpc = MLX5_ADDR_OF(rst2init_qp_in, &in, qpc);
2187                 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1);
2188                 MLX5_SET(qpc, qpc, rre, 1);
2189                 MLX5_SET(qpc, qpc, rwe, 1);
2190                 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
2191                 inlen = sizeof(in.rst2init);
2192                 outlen = sizeof(out.rst2init);
2193                 break;
2194         case MLX5_CMD_OP_INIT2RTR_QP:
2195                 MLX5_SET(init2rtr_qp_in, &in, qpn, qp->id);
2196                 qpc = MLX5_ADDR_OF(init2rtr_qp_in, &in, qpc);
2197                 MLX5_SET(qpc, qpc, primary_address_path.fl, 1);
2198                 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1);
2199                 MLX5_SET(qpc, qpc, mtu, 1);
2200                 MLX5_SET(qpc, qpc, log_msg_max, 30);
2201                 MLX5_SET(qpc, qpc, remote_qpn, remote_qp_id);
2202                 MLX5_SET(qpc, qpc, min_rnr_nak, 0);
2203                 inlen = sizeof(in.init2rtr);
2204                 outlen = sizeof(out.init2rtr);
2205                 break;
2206         case MLX5_CMD_OP_RTR2RTS_QP:
2207                 qpc = MLX5_ADDR_OF(rtr2rts_qp_in, &in, qpc);
2208                 MLX5_SET(rtr2rts_qp_in, &in, qpn, qp->id);
2209                 MLX5_SET(qpc, qpc, primary_address_path.ack_timeout, 14);
2210                 MLX5_SET(qpc, qpc, log_ack_req_freq, 0);
2211                 MLX5_SET(qpc, qpc, retry_count, 7);
2212                 MLX5_SET(qpc, qpc, rnr_retry, 7);
2213                 inlen = sizeof(in.rtr2rts);
2214                 outlen = sizeof(out.rtr2rts);
2215                 break;
2216         default:
2217                 DRV_LOG(ERR, "Invalid or unsupported QP modify op %u.",
2218                         qp_st_mod_op);
2219                 rte_errno = EINVAL;
2220                 return -rte_errno;
2221         }
2222         ret = mlx5_glue->devx_obj_modify(qp->obj, &in, inlen, &out, outlen);
2223         if (ret) {
2224                 DRV_LOG(ERR, "Failed to modify QP using DevX.");
2225                 rte_errno = errno;
2226                 return -rte_errno;
2227         }
2228         return ret;
2229 }
2230
2231 struct mlx5_devx_obj *
2232 mlx5_devx_cmd_create_virtio_q_counters(void *ctx)
2233 {
2234         uint32_t in[MLX5_ST_SZ_DW(create_virtio_q_counters_in)] = {0};
2235         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2236         struct mlx5_devx_obj *couners_obj = mlx5_malloc(MLX5_MEM_ZERO,
2237                                                        sizeof(*couners_obj), 0,
2238                                                        SOCKET_ID_ANY);
2239         void *hdr = MLX5_ADDR_OF(create_virtio_q_counters_in, in, hdr);
2240
2241         if (!couners_obj) {
2242                 DRV_LOG(ERR, "Failed to allocate virtio queue counters data.");
2243                 rte_errno = ENOMEM;
2244                 return NULL;
2245         }
2246         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2247                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2248         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2249                  MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS);
2250         couners_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
2251                                                       sizeof(out));
2252         if (!couners_obj->obj) {
2253                 rte_errno = errno;
2254                 DRV_LOG(ERR, "Failed to create virtio queue counters Obj using"
2255                         " DevX.");
2256                 mlx5_free(couners_obj);
2257                 return NULL;
2258         }
2259         couners_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2260         return couners_obj;
2261 }
2262
2263 int
2264 mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj,
2265                                    struct mlx5_devx_virtio_q_couners_attr *attr)
2266 {
2267         uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
2268         uint32_t out[MLX5_ST_SZ_DW(query_virtio_q_counters_out)] = {0};
2269         void *hdr = MLX5_ADDR_OF(query_virtio_q_counters_out, in, hdr);
2270         void *virtio_q_counters = MLX5_ADDR_OF(query_virtio_q_counters_out, out,
2271                                                virtio_q_counters);
2272         int ret;
2273
2274         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2275                  MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
2276         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2277                  MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS);
2278         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, couners_obj->id);
2279         ret = mlx5_glue->devx_obj_query(couners_obj->obj, in, sizeof(in), out,
2280                                         sizeof(out));
2281         if (ret) {
2282                 DRV_LOG(ERR, "Failed to query virtio q counters using DevX.");
2283                 rte_errno = errno;
2284                 return -errno;
2285         }
2286         attr->received_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters,
2287                                          received_desc);
2288         attr->completed_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters,
2289                                           completed_desc);
2290         attr->error_cqes = MLX5_GET(virtio_q_counters, virtio_q_counters,
2291                                     error_cqes);
2292         attr->bad_desc_errors = MLX5_GET(virtio_q_counters, virtio_q_counters,
2293                                          bad_desc_errors);
2294         attr->exceed_max_chain = MLX5_GET(virtio_q_counters, virtio_q_counters,
2295                                           exceed_max_chain);
2296         attr->invalid_buffer = MLX5_GET(virtio_q_counters, virtio_q_counters,
2297                                         invalid_buffer);
2298         return ret;
2299 }
2300
2301 /**
2302  * Create general object of type FLOW_HIT_ASO using DevX API.
2303  *
2304  * @param[in] ctx
2305  *   Context returned from mlx5 open_device() glue function.
2306  * @param [in] pd
2307  *   PD value to associate the FLOW_HIT_ASO object with.
2308  *
2309  * @return
2310  *   The DevX object created, NULL otherwise and rte_errno is set.
2311  */
2312 struct mlx5_devx_obj *
2313 mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, uint32_t pd)
2314 {
2315         uint32_t in[MLX5_ST_SZ_DW(create_flow_hit_aso_in)] = {0};
2316         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2317         struct mlx5_devx_obj *flow_hit_aso_obj = NULL;
2318         void *ptr = NULL;
2319
2320         flow_hit_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*flow_hit_aso_obj),
2321                                        0, SOCKET_ID_ANY);
2322         if (!flow_hit_aso_obj) {
2323                 DRV_LOG(ERR, "Failed to allocate FLOW_HIT_ASO object data");
2324                 rte_errno = ENOMEM;
2325                 return NULL;
2326         }
2327         ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, hdr);
2328         MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2329                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2330         MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2331                  MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO);
2332         ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, flow_hit_aso);
2333         MLX5_SET(flow_hit_aso, ptr, access_pd, pd);
2334         flow_hit_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2335                                                            out, sizeof(out));
2336         if (!flow_hit_aso_obj->obj) {
2337                 rte_errno = errno;
2338                 DRV_LOG(ERR, "Failed to create FLOW_HIT_ASO obj using DevX.");
2339                 mlx5_free(flow_hit_aso_obj);
2340                 return NULL;
2341         }
2342         flow_hit_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2343         return flow_hit_aso_obj;
2344 }
2345
2346 /*
2347  * Create PD using DevX API.
2348  *
2349  * @param[in] ctx
2350  *   Context returned from mlx5 open_device() glue function.
2351  *
2352  * @return
2353  *   The DevX object created, NULL otherwise and rte_errno is set.
2354  */
2355 struct mlx5_devx_obj *
2356 mlx5_devx_cmd_alloc_pd(void *ctx)
2357 {
2358         struct mlx5_devx_obj *ppd =
2359                 mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ppd), 0, SOCKET_ID_ANY);
2360         u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {0};
2361         u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {0};
2362
2363         if (!ppd) {
2364                 DRV_LOG(ERR, "Failed to allocate PD data.");
2365                 rte_errno = ENOMEM;
2366                 return NULL;
2367         }
2368         MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD);
2369         ppd->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2370                                 out, sizeof(out));
2371         if (!ppd->obj) {
2372                 mlx5_free(ppd);
2373                 DRV_LOG(ERR, "Failed to allocate PD Obj using DevX.");
2374                 rte_errno = errno;
2375                 return NULL;
2376         }
2377         ppd->id = MLX5_GET(alloc_pd_out, out, pd);
2378         return ppd;
2379 }
2380
2381 /**
2382  * Create general object of type FLOW_METER_ASO using DevX API.
2383  *
2384  * @param[in] ctx
2385  *   Context returned from mlx5 open_device() glue function.
2386  * @param [in] pd
2387  *   PD value to associate the FLOW_METER_ASO object with.
2388  * @param [in] log_obj_size
2389  *   log_obj_size define to allocate number of 2 * meters
2390  *   in one FLOW_METER_ASO object.
2391  *
2392  * @return
2393  *   The DevX object created, NULL otherwise and rte_errno is set.
2394  */
2395 struct mlx5_devx_obj *
2396 mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx, uint32_t pd,
2397                                                 uint32_t log_obj_size)
2398 {
2399         uint32_t in[MLX5_ST_SZ_DW(create_flow_meter_aso_in)] = {0};
2400         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)];
2401         struct mlx5_devx_obj *flow_meter_aso_obj;
2402         void *ptr;
2403
2404         flow_meter_aso_obj = mlx5_malloc(MLX5_MEM_ZERO,
2405                                                 sizeof(*flow_meter_aso_obj),
2406                                                 0, SOCKET_ID_ANY);
2407         if (!flow_meter_aso_obj) {
2408                 DRV_LOG(ERR, "Failed to allocate FLOW_METER_ASO object data");
2409                 rte_errno = ENOMEM;
2410                 return NULL;
2411         }
2412         ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, hdr);
2413         MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2414                 MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2415         MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2416                 MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO);
2417         MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range,
2418                 log_obj_size);
2419         ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, flow_meter_aso);
2420         MLX5_SET(flow_meter_aso, ptr, access_pd, pd);
2421         flow_meter_aso_obj->obj = mlx5_glue->devx_obj_create(
2422                                                         ctx, in, sizeof(in),
2423                                                         out, sizeof(out));
2424         if (!flow_meter_aso_obj->obj) {
2425                 rte_errno = errno;
2426                 DRV_LOG(ERR, "Failed to create FLOW_METER_ASO obj using DevX.");
2427                 mlx5_free(flow_meter_aso_obj);
2428                 return NULL;
2429         }
2430         flow_meter_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr,
2431                                                                 out, obj_id);
2432         return flow_meter_aso_obj;
2433 }
2434
2435 /*
2436  * Create general object of type CONN_TRACK_OFFLOAD using DevX API.
2437  *
2438  * @param[in] ctx
2439  *   Context returned from mlx5 open_device() glue function.
2440  * @param [in] pd
2441  *   PD value to associate the CONN_TRACK_OFFLOAD ASO object with.
2442  * @param [in] log_obj_size
2443  *   log_obj_size to allocate its power of 2 * objects
2444  *   in one CONN_TRACK_OFFLOAD bulk allocation.
2445  *
2446  * @return
2447  *   The DevX object created, NULL otherwise and rte_errno is set.
2448  */
2449 struct mlx5_devx_obj *
2450 mlx5_devx_cmd_create_conn_track_offload_obj(void *ctx, uint32_t pd,
2451                                             uint32_t log_obj_size)
2452 {
2453         uint32_t in[MLX5_ST_SZ_DW(create_conn_track_aso_in)] = {0};
2454         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)];
2455         struct mlx5_devx_obj *ct_aso_obj;
2456         void *ptr;
2457
2458         ct_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ct_aso_obj),
2459                                  0, SOCKET_ID_ANY);
2460         if (!ct_aso_obj) {
2461                 DRV_LOG(ERR, "Failed to allocate CONN_TRACK_OFFLOAD object.");
2462                 rte_errno = ENOMEM;
2463                 return NULL;
2464         }
2465         ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, hdr);
2466         MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2467                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2468         MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2469                  MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD);
2470         MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range, log_obj_size);
2471         ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, conn_track_offload);
2472         MLX5_SET(conn_track_offload, ptr, conn_track_aso_access_pd, pd);
2473         ct_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2474                                                      out, sizeof(out));
2475         if (!ct_aso_obj->obj) {
2476                 rte_errno = errno;
2477                 DRV_LOG(ERR, "Failed to create CONN_TRACK_OFFLOAD obj by using DevX.");
2478                 mlx5_free(ct_aso_obj);
2479                 return NULL;
2480         }
2481         ct_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2482         return ct_aso_obj;
2483 }
2484
2485 /**
2486  * Create general object of type GENEVE TLV option using DevX API.
2487  *
2488  * @param[in] ctx
2489  *   Context returned from mlx5 open_device() glue function.
2490  * @param [in] class
2491  *   TLV option variable value of class
2492  * @param [in] type
2493  *   TLV option variable value of type
2494  * @param [in] len
2495  *   TLV option variable value of len
2496  *
2497  * @return
2498  *   The DevX object created, NULL otherwise and rte_errno is set.
2499  */
2500 struct mlx5_devx_obj *
2501 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx,
2502                 uint16_t class, uint8_t type, uint8_t len)
2503 {
2504         uint32_t in[MLX5_ST_SZ_DW(create_geneve_tlv_option_in)] = {0};
2505         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2506         struct mlx5_devx_obj *geneve_tlv_opt_obj = mlx5_malloc(MLX5_MEM_ZERO,
2507                                                    sizeof(*geneve_tlv_opt_obj),
2508                                                    0, SOCKET_ID_ANY);
2509
2510         if (!geneve_tlv_opt_obj) {
2511                 DRV_LOG(ERR, "Failed to allocate geneve tlv option object.");
2512                 rte_errno = ENOMEM;
2513                 return NULL;
2514         }
2515         void *hdr = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, hdr);
2516         void *opt = MLX5_ADDR_OF(create_geneve_tlv_option_in, in,
2517                         geneve_tlv_opt);
2518         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2519                         MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2520         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2521                  MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT);
2522         MLX5_SET(geneve_tlv_option, opt, option_class,
2523                         rte_be_to_cpu_16(class));
2524         MLX5_SET(geneve_tlv_option, opt, option_type, type);
2525         MLX5_SET(geneve_tlv_option, opt, option_data_length, len);
2526         geneve_tlv_opt_obj->obj = mlx5_glue->devx_obj_create(ctx, in,
2527                                         sizeof(in), out, sizeof(out));
2528         if (!geneve_tlv_opt_obj->obj) {
2529                 rte_errno = errno;
2530                 DRV_LOG(ERR, "Failed to create Geneve tlv option "
2531                                 "Obj using DevX.");
2532                 mlx5_free(geneve_tlv_opt_obj);
2533                 return NULL;
2534         }
2535         geneve_tlv_opt_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2536         return geneve_tlv_opt_obj;
2537 }
2538
2539 int
2540 mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id)
2541 {
2542 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2543         uint32_t in[MLX5_ST_SZ_DW(query_rq_in)] = {0};
2544         uint32_t out[MLX5_ST_SZ_DW(query_rq_out)] = {0};
2545         int rc;
2546         void *rq_ctx;
2547
2548         MLX5_SET(query_rq_in, in, opcode, MLX5_CMD_OP_QUERY_RQ);
2549         MLX5_SET(query_rq_in, in, rqn, ((struct ibv_wq *)wq)->wq_num);
2550         rc = mlx5_glue->devx_wq_query(wq, in, sizeof(in), out, sizeof(out));
2551         if (rc) {
2552                 rte_errno = errno;
2553                 DRV_LOG(ERR, "Failed to query WQ counter set ID using DevX - "
2554                         "rc = %d, errno = %d.", rc, errno);
2555                 return -rc;
2556         };
2557         rq_ctx = MLX5_ADDR_OF(query_rq_out, out, rq_context);
2558         *counter_set_id = MLX5_GET(rqc, rq_ctx, counter_set_id);
2559         return 0;
2560 #else
2561         (void)wq;
2562         (void)counter_set_id;
2563         return -ENOTSUP;
2564 #endif
2565 }
2566
2567 /*
2568  * Allocate queue counters via devx interface.
2569  *
2570  * @param[in] ctx
2571  *   Context returned from mlx5 open_device() glue function.
2572  *
2573  * @return
2574  *   Pointer to counter object on success, a NULL value otherwise and
2575  *   rte_errno is set.
2576  */
2577 struct mlx5_devx_obj *
2578 mlx5_devx_cmd_queue_counter_alloc(void *ctx)
2579 {
2580         struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 0,
2581                                                 SOCKET_ID_ANY);
2582         uint32_t in[MLX5_ST_SZ_DW(alloc_q_counter_in)]   = {0};
2583         uint32_t out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {0};
2584
2585         if (!dcs) {
2586                 rte_errno = ENOMEM;
2587                 return NULL;
2588         }
2589         MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER);
2590         dcs->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
2591                                               sizeof(out));
2592         if (!dcs->obj) {
2593                 DRV_LOG(DEBUG, "Can't allocate q counter set by DevX - error "
2594                         "%d.", errno);
2595                 rte_errno = errno;
2596                 mlx5_free(dcs);
2597                 return NULL;
2598         }
2599         dcs->id = MLX5_GET(alloc_q_counter_out, out, counter_set_id);
2600         return dcs;
2601 }
2602
2603 /**
2604  * Query queue counters values.
2605  *
2606  * @param[in] dcs
2607  *   devx object of the queue counter set.
2608  * @param[in] clear
2609  *   Whether hardware should clear the counters after the query or not.
2610  *  @param[out] out_of_buffers
2611  *   Number of dropped occurred due to lack of WQE for the associated QPs/RQs.
2612  *
2613  * @return
2614  *   0 on success, a negative value otherwise.
2615  */
2616 int
2617 mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear,
2618                                   uint32_t *out_of_buffers)
2619 {
2620         uint32_t out[MLX5_ST_SZ_BYTES(query_q_counter_out)] = {0};
2621         uint32_t in[MLX5_ST_SZ_DW(query_q_counter_in)] = {0};
2622         int rc;
2623
2624         MLX5_SET(query_q_counter_in, in, opcode,
2625                  MLX5_CMD_OP_QUERY_Q_COUNTER);
2626         MLX5_SET(query_q_counter_in, in, op_mod, 0);
2627         MLX5_SET(query_q_counter_in, in, counter_set_id, dcs->id);
2628         MLX5_SET(query_q_counter_in, in, clear, !!clear);
2629         rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out,
2630                                        sizeof(out));
2631         if (rc) {
2632                 DRV_LOG(ERR, "Failed to query devx q counter set - rc %d", rc);
2633                 rte_errno = rc;
2634                 return -rc;
2635         }
2636         *out_of_buffers = MLX5_GET(query_q_counter_out, out, out_of_buffer);
2637         return 0;
2638 }
2639
2640 /**
2641  * Create general object of type DEK using DevX API.
2642  *
2643  * @param[in] ctx
2644  *   Context returned from mlx5 open_device() glue function.
2645  * @param [in] attr
2646  *   Pointer to DEK attributes structure.
2647  *
2648  * @return
2649  *   The DevX object created, NULL otherwise and rte_errno is set.
2650  */
2651 struct mlx5_devx_obj *
2652 mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr)
2653 {
2654         uint32_t in[MLX5_ST_SZ_DW(create_dek_in)] = {0};
2655         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2656         struct mlx5_devx_obj *dek_obj = NULL;
2657         void *ptr = NULL, *key_addr = NULL;
2658
2659         dek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dek_obj),
2660                               0, SOCKET_ID_ANY);
2661         if (dek_obj == NULL) {
2662                 DRV_LOG(ERR, "Failed to allocate DEK object data");
2663                 rte_errno = ENOMEM;
2664                 return NULL;
2665         }
2666         ptr = MLX5_ADDR_OF(create_dek_in, in, hdr);
2667         MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2668                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2669         MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2670                  MLX5_GENERAL_OBJ_TYPE_DEK);
2671         ptr = MLX5_ADDR_OF(create_dek_in, in, dek);
2672         MLX5_SET(dek, ptr, key_size, attr->key_size);
2673         MLX5_SET(dek, ptr, has_keytag, attr->has_keytag);
2674         MLX5_SET(dek, ptr, key_purpose, attr->key_purpose);
2675         MLX5_SET(dek, ptr, pd, attr->pd);
2676         MLX5_SET64(dek, ptr, opaque, attr->opaque);
2677         key_addr = MLX5_ADDR_OF(dek, ptr, key);
2678         memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE);
2679         dek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2680                                                   out, sizeof(out));
2681         if (dek_obj->obj == NULL) {
2682                 rte_errno = errno;
2683                 DRV_LOG(ERR, "Failed to create DEK obj using DevX.");
2684                 mlx5_free(dek_obj);
2685                 return NULL;
2686         }
2687         dek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2688         return dek_obj;
2689 }
2690
2691 /**
2692  * Create general object of type IMPORT_KEK using DevX API.
2693  *
2694  * @param[in] ctx
2695  *   Context returned from mlx5 open_device() glue function.
2696  * @param [in] attr
2697  *   Pointer to IMPORT_KEK attributes structure.
2698  *
2699  * @return
2700  *   The DevX object created, NULL otherwise and rte_errno is set.
2701  */
2702 struct mlx5_devx_obj *
2703 mlx5_devx_cmd_create_import_kek_obj(void *ctx,
2704                                     struct mlx5_devx_import_kek_attr *attr)
2705 {
2706         uint32_t in[MLX5_ST_SZ_DW(create_import_kek_in)] = {0};
2707         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2708         struct mlx5_devx_obj *import_kek_obj = NULL;
2709         void *ptr = NULL, *key_addr = NULL;
2710
2711         import_kek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*import_kek_obj),
2712                                      0, SOCKET_ID_ANY);
2713         if (import_kek_obj == NULL) {
2714                 DRV_LOG(ERR, "Failed to allocate IMPORT_KEK object data");
2715                 rte_errno = ENOMEM;
2716                 return NULL;
2717         }
2718         ptr = MLX5_ADDR_OF(create_import_kek_in, in, hdr);
2719         MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2720                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2721         MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2722                  MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK);
2723         ptr = MLX5_ADDR_OF(create_import_kek_in, in, import_kek);
2724         MLX5_SET(import_kek, ptr, key_size, attr->key_size);
2725         key_addr = MLX5_ADDR_OF(import_kek, ptr, key);
2726         memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE);
2727         import_kek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2728                                                          out, sizeof(out));
2729         if (import_kek_obj->obj == NULL) {
2730                 rte_errno = errno;
2731                 DRV_LOG(ERR, "Failed to create IMPORT_KEK object using DevX.");
2732                 mlx5_free(import_kek_obj);
2733                 return NULL;
2734         }
2735         import_kek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2736         return import_kek_obj;
2737 }
2738
2739 /**
2740  * Create general object of type CREDENTIAL using DevX API.
2741  *
2742  * @param[in] ctx
2743  *   Context returned from mlx5 open_device() glue function.
2744  * @param [in] attr
2745  *   Pointer to CREDENTIAL attributes structure.
2746  *
2747  * @return
2748  *   The DevX object created, NULL otherwise and rte_errno is set.
2749  */
2750 struct mlx5_devx_obj *
2751 mlx5_devx_cmd_create_credential_obj(void *ctx,
2752                                     struct mlx5_devx_credential_attr *attr)
2753 {
2754         uint32_t in[MLX5_ST_SZ_DW(create_credential_in)] = {0};
2755         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2756         struct mlx5_devx_obj *credential_obj = NULL;
2757         void *ptr = NULL, *credential_addr = NULL;
2758
2759         credential_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*credential_obj),
2760                                      0, SOCKET_ID_ANY);
2761         if (credential_obj == NULL) {
2762                 DRV_LOG(ERR, "Failed to allocate CREDENTIAL object data");
2763                 rte_errno = ENOMEM;
2764                 return NULL;
2765         }
2766         ptr = MLX5_ADDR_OF(create_credential_in, in, hdr);
2767         MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2768                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2769         MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2770                  MLX5_GENERAL_OBJ_TYPE_CREDENTIAL);
2771         ptr = MLX5_ADDR_OF(create_credential_in, in, credential);
2772         MLX5_SET(credential, ptr, credential_role, attr->credential_role);
2773         credential_addr = MLX5_ADDR_OF(credential, ptr, credential);
2774         memcpy(credential_addr, (void *)(attr->credential),
2775                MLX5_CRYPTO_CREDENTIAL_SIZE);
2776         credential_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2777                                                          out, sizeof(out));
2778         if (credential_obj->obj == NULL) {
2779                 rte_errno = errno;
2780                 DRV_LOG(ERR, "Failed to create CREDENTIAL object using DevX.");
2781                 mlx5_free(credential_obj);
2782                 return NULL;
2783         }
2784         credential_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2785         return credential_obj;
2786 }
2787
2788 /**
2789  * Create general object of type CRYPTO_LOGIN using DevX API.
2790  *
2791  * @param[in] ctx
2792  *   Context returned from mlx5 open_device() glue function.
2793  * @param [in] attr
2794  *   Pointer to CRYPTO_LOGIN attributes structure.
2795  *
2796  * @return
2797  *   The DevX object created, NULL otherwise and rte_errno is set.
2798  */
2799 struct mlx5_devx_obj *
2800 mlx5_devx_cmd_create_crypto_login_obj(void *ctx,
2801                                       struct mlx5_devx_crypto_login_attr *attr)
2802 {
2803         uint32_t in[MLX5_ST_SZ_DW(create_crypto_login_in)] = {0};
2804         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2805         struct mlx5_devx_obj *crypto_login_obj = NULL;
2806         void *ptr = NULL, *credential_addr = NULL;
2807
2808         crypto_login_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*crypto_login_obj),
2809                                        0, SOCKET_ID_ANY);
2810         if (crypto_login_obj == NULL) {
2811                 DRV_LOG(ERR, "Failed to allocate CRYPTO_LOGIN object data");
2812                 rte_errno = ENOMEM;
2813                 return NULL;
2814         }
2815         ptr = MLX5_ADDR_OF(create_crypto_login_in, in, hdr);
2816         MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2817                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2818         MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2819                  MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN);
2820         ptr = MLX5_ADDR_OF(create_crypto_login_in, in, crypto_login);
2821         MLX5_SET(crypto_login, ptr, credential_pointer,
2822                  attr->credential_pointer);
2823         MLX5_SET(crypto_login, ptr, session_import_kek_ptr,
2824                  attr->session_import_kek_ptr);
2825         credential_addr = MLX5_ADDR_OF(crypto_login, ptr, credential);
2826         memcpy(credential_addr, (void *)(attr->credential),
2827                MLX5_CRYPTO_CREDENTIAL_SIZE);
2828         crypto_login_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2829                                                            out, sizeof(out));
2830         if (crypto_login_obj->obj == NULL) {
2831                 rte_errno = errno;
2832                 DRV_LOG(ERR, "Failed to create CRYPTO_LOGIN obj using DevX.");
2833                 mlx5_free(crypto_login_obj);
2834                 return NULL;
2835         }
2836         crypto_login_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2837         return crypto_login_obj;
2838 }
2839
2840 /**
2841  * Query LAG context.
2842  *
2843  * @param[in] ctx
2844  *   Pointer to ibv_context, returned from mlx5dv_open_device.
2845  * @param[out] lag_ctx
2846  *   Pointer to struct mlx5_devx_lag_context, to be set by the routine.
2847  *
2848  * @return
2849  *   0 on success, a negative value otherwise.
2850  */
2851 int
2852 mlx5_devx_cmd_query_lag(void *ctx,
2853                         struct mlx5_devx_lag_context *lag_ctx)
2854 {
2855         uint32_t in[MLX5_ST_SZ_DW(query_lag_in)] = {0};
2856         uint32_t out[MLX5_ST_SZ_DW(query_lag_out)] = {0};
2857         void *lctx;
2858         int rc;
2859
2860         MLX5_SET(query_lag_in, in, opcode, MLX5_CMD_OP_QUERY_LAG);
2861         rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
2862         if (rc)
2863                 goto error;
2864         lctx = MLX5_ADDR_OF(query_lag_out, out, context);
2865         lag_ctx->fdb_selection_mode = MLX5_GET(lag_context, lctx,
2866                                                fdb_selection_mode);
2867         lag_ctx->port_select_mode = MLX5_GET(lag_context, lctx,
2868                                                port_select_mode);
2869         lag_ctx->lag_state = MLX5_GET(lag_context, lctx, lag_state);
2870         lag_ctx->tx_remap_affinity_2 = MLX5_GET(lag_context, lctx,
2871                                                 tx_remap_affinity_2);
2872         lag_ctx->tx_remap_affinity_1 = MLX5_GET(lag_context, lctx,
2873                                                 tx_remap_affinity_1);
2874         return 0;
2875 error:
2876         rc = (rc > 0) ? -rc : rc;
2877         return rc;
2878 }