1 // SPDX-License-Identifier: BSD-3-Clause
2 /* Copyright 2018 Mellanox Technologies, Ltd */
7 #include <rte_malloc.h>
8 #include <rte_eal_paging.h>
11 #include "mlx5_devx_cmds.h"
12 #include "mlx5_common_utils.h"
13 #include "mlx5_malloc.h"
17 * Perform read access to the registers. Reads data from register
18 * and writes ones to the specified buffer.
21 * Context returned from mlx5 open_device() glue function.
23 * Register identifier according to the PRM.
25 * Register access auxiliary parameter according to the PRM.
27 * Pointer to the buffer to store read data.
29 * Buffer size in double words.
32 * 0 on success, a negative value otherwise.
35 mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg,
36 uint32_t *data, uint32_t dw_cnt)
38 uint32_t in[MLX5_ST_SZ_DW(access_register_in)] = {0};
39 uint32_t out[MLX5_ST_SZ_DW(access_register_out) +
40 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0};
43 MLX5_ASSERT(data && dw_cnt);
44 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX);
45 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) {
46 DRV_LOG(ERR, "Not enough buffer for register read data");
49 MLX5_SET(access_register_in, in, opcode,
50 MLX5_CMD_OP_ACCESS_REGISTER_USER);
51 MLX5_SET(access_register_in, in, op_mod,
52 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ);
53 MLX5_SET(access_register_in, in, register_id, reg_id);
54 MLX5_SET(access_register_in, in, argument, arg);
55 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out,
56 MLX5_ST_SZ_DW(access_register_out) *
57 sizeof(uint32_t) + dw_cnt);
60 status = MLX5_GET(access_register_out, out, status);
62 int syndrome = MLX5_GET(access_register_out, out, syndrome);
64 DRV_LOG(DEBUG, "Failed to access NIC register 0x%X, "
65 "status %x, syndrome = %x",
66 reg_id, status, syndrome);
69 memcpy(data, &out[MLX5_ST_SZ_DW(access_register_out)],
70 dw_cnt * sizeof(uint32_t));
73 rc = (rc > 0) ? -rc : rc;
78 * Allocate flow counters via devx interface.
81 * Context returned from mlx5 open_device() glue function.
83 * Pointer to counters properties structure to be filled by the routine.
85 * Bulk counter numbers in 128 counters units.
88 * Pointer to counter object on success, a negative value otherwise and
91 struct mlx5_devx_obj *
92 mlx5_devx_cmd_flow_counter_alloc(void *ctx, uint32_t bulk_n_128)
94 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs),
96 uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0};
97 uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0};
103 MLX5_SET(alloc_flow_counter_in, in, opcode,
104 MLX5_CMD_OP_ALLOC_FLOW_COUNTER);
105 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128);
106 dcs->obj = mlx5_glue->devx_obj_create(ctx, in,
107 sizeof(in), out, sizeof(out));
109 DRV_LOG(ERR, "Can't allocate counters - error %d", errno);
114 dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id);
119 * Query flow counters values.
122 * devx object that was obtained from mlx5_devx_cmd_fc_alloc.
124 * Whether hardware should clear the counters after the query or not.
125 * @param[in] n_counters
126 * 0 in case of 1 counter to read, otherwise the counter number to read.
128 * The number of packets that matched the flow.
130 * The number of bytes that matched the flow.
132 * The mkey key for batch query.
134 * The address in the mkey range for batch query.
136 * The completion object for asynchronous batch query.
138 * The ID to be returned in the asynchronous batch query response.
141 * 0 on success, a negative value otherwise.
144 mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs,
145 int clear, uint32_t n_counters,
146 uint64_t *pkts, uint64_t *bytes,
147 uint32_t mkey, void *addr,
151 int out_len = MLX5_ST_SZ_BYTES(query_flow_counter_out) +
152 MLX5_ST_SZ_BYTES(traffic_counter);
153 uint32_t out[out_len];
154 uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0};
158 MLX5_SET(query_flow_counter_in, in, opcode,
159 MLX5_CMD_OP_QUERY_FLOW_COUNTER);
160 MLX5_SET(query_flow_counter_in, in, op_mod, 0);
161 MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id);
162 MLX5_SET(query_flow_counter_in, in, clear, !!clear);
165 MLX5_SET(query_flow_counter_in, in, num_of_counters,
167 MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1);
168 MLX5_SET(query_flow_counter_in, in, mkey, mkey);
169 MLX5_SET64(query_flow_counter_in, in, address,
170 (uint64_t)(uintptr_t)addr);
173 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out,
176 rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in),
180 DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc);
185 stats = MLX5_ADDR_OF(query_flow_counter_out,
186 out, flow_statistics);
187 *pkts = MLX5_GET64(traffic_counter, stats, packets);
188 *bytes = MLX5_GET64(traffic_counter, stats, octets);
197 * Context returned from mlx5 open_device() glue function.
199 * Attributes of the requested mkey.
202 * Pointer to Devx mkey on success, a negative value otherwise and rte_errno
205 struct mlx5_devx_obj *
206 mlx5_devx_cmd_mkey_create(void *ctx,
207 struct mlx5_devx_mkey_attr *attr)
209 struct mlx5_klm *klm_array = attr->klm_array;
210 int klm_num = attr->klm_num;
211 int in_size_dw = MLX5_ST_SZ_DW(create_mkey_in) +
212 (klm_num ? RTE_ALIGN(klm_num, 4) : 0) * MLX5_ST_SZ_DW(klm);
213 uint32_t in[in_size_dw];
214 uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0};
216 struct mlx5_devx_obj *mkey = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mkey),
219 uint32_t translation_size;
225 memset(in, 0, in_size_dw * 4);
226 pgsize = rte_mem_page_size();
227 if (pgsize == (size_t)-1) {
229 DRV_LOG(ERR, "Failed to get page size");
233 MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY);
234 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
237 uint8_t *klm = (uint8_t *)MLX5_ADDR_OF(create_mkey_in, in,
239 translation_size = RTE_ALIGN(klm_num, 4);
240 for (i = 0; i < klm_num; i++) {
241 MLX5_SET(klm, klm, byte_count, klm_array[i].byte_count);
242 MLX5_SET(klm, klm, mkey, klm_array[i].mkey);
243 MLX5_SET64(klm, klm, address, klm_array[i].address);
244 klm += MLX5_ST_SZ_BYTES(klm);
246 for (; i < (int)translation_size; i++) {
247 MLX5_SET(klm, klm, mkey, 0x0);
248 MLX5_SET64(klm, klm, address, 0x0);
249 klm += MLX5_ST_SZ_BYTES(klm);
251 MLX5_SET(mkc, mkc, access_mode_1_0, attr->log_entity_size ?
252 MLX5_MKC_ACCESS_MODE_KLM_FBS :
253 MLX5_MKC_ACCESS_MODE_KLM);
254 MLX5_SET(mkc, mkc, log_page_size, attr->log_entity_size);
256 translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16;
257 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
258 MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize));
260 MLX5_SET(create_mkey_in, in, translations_octword_actual_size,
262 MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id);
263 MLX5_SET(create_mkey_in, in, pg_access, attr->pg_access);
264 MLX5_SET(mkc, mkc, lw, 0x1);
265 MLX5_SET(mkc, mkc, lr, 0x1);
266 MLX5_SET(mkc, mkc, qpn, 0xffffff);
267 MLX5_SET(mkc, mkc, pd, attr->pd);
268 MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF);
269 MLX5_SET(mkc, mkc, translations_octword_size, translation_size);
270 MLX5_SET(mkc, mkc, relaxed_ordering_write,
271 attr->relaxed_ordering_write);
272 MLX5_SET(mkc, mkc, relaxed_ordering_read,
273 attr->relaxed_ordering_read);
274 MLX5_SET64(mkc, mkc, start_addr, attr->addr);
275 MLX5_SET64(mkc, mkc, len, attr->size);
276 mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out,
279 DRV_LOG(ERR, "Can't create %sdirect mkey - error %d\n",
280 klm_num ? "an in" : "a ", errno);
285 mkey->id = MLX5_GET(create_mkey_out, out, mkey_index);
286 mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF);
291 * Get status of devx command response.
292 * Mainly used for asynchronous commands.
295 * The out response buffer.
298 * 0 on success, non-zero value otherwise.
301 mlx5_devx_get_out_command_status(void *out)
307 status = MLX5_GET(query_flow_counter_out, out, status);
309 int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome);
311 DRV_LOG(ERR, "Bad devX status %x, syndrome = %x", status,
318 * Destroy any object allocated by a Devx API.
321 * Pointer to a general object.
324 * 0 on success, a negative value otherwise.
327 mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj)
333 ret = mlx5_glue->devx_obj_destroy(obj->obj);
339 * Query NIC vport context.
340 * Fills minimal inline attribute.
343 * ibv contexts returned from mlx5dv_open_device.
347 * Attributes device values.
350 * 0 on success, a negative value otherwise.
353 mlx5_devx_cmd_query_nic_vport_context(void *ctx,
355 struct mlx5_hca_attr *attr)
357 uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0};
358 uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0};
360 int status, syndrome, rc;
362 /* Query NIC vport context to determine inline mode. */
363 MLX5_SET(query_nic_vport_context_in, in, opcode,
364 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT);
365 MLX5_SET(query_nic_vport_context_in, in, vport_number, vport);
367 MLX5_SET(query_nic_vport_context_in, in, other_vport, 1);
368 rc = mlx5_glue->devx_general_cmd(ctx,
373 status = MLX5_GET(query_nic_vport_context_out, out, status);
374 syndrome = MLX5_GET(query_nic_vport_context_out, out, syndrome);
376 DRV_LOG(DEBUG, "Failed to query NIC vport context, "
377 "status %x, syndrome = %x",
381 vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out,
383 attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx,
384 min_wqe_inline_mode);
387 rc = (rc > 0) ? -rc : rc;
392 * Query NIC vDPA attributes.
395 * Context returned from mlx5 open_device() glue function.
396 * @param[out] vdpa_attr
397 * vDPA Attributes structure to fill.
400 mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx,
401 struct mlx5_hca_vdpa_attr *vdpa_attr)
403 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0};
404 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0};
405 void *hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
406 int status, syndrome, rc;
408 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
409 MLX5_SET(query_hca_cap_in, in, op_mod,
410 MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION |
411 MLX5_HCA_CAP_OPMOD_GET_CUR);
412 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
413 status = MLX5_GET(query_hca_cap_out, out, status);
414 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
416 RTE_LOG(DEBUG, PMD, "Failed to query devx VDPA capabilities,"
417 " status %x, syndrome = %x", status, syndrome);
418 vdpa_attr->valid = 0;
420 vdpa_attr->valid = 1;
421 vdpa_attr->desc_tunnel_offload_type =
422 MLX5_GET(virtio_emulation_cap, hcattr,
423 desc_tunnel_offload_type);
424 vdpa_attr->eth_frame_offload_type =
425 MLX5_GET(virtio_emulation_cap, hcattr,
426 eth_frame_offload_type);
427 vdpa_attr->virtio_version_1_0 =
428 MLX5_GET(virtio_emulation_cap, hcattr,
430 vdpa_attr->tso_ipv4 = MLX5_GET(virtio_emulation_cap, hcattr,
432 vdpa_attr->tso_ipv6 = MLX5_GET(virtio_emulation_cap, hcattr,
434 vdpa_attr->tx_csum = MLX5_GET(virtio_emulation_cap, hcattr,
436 vdpa_attr->rx_csum = MLX5_GET(virtio_emulation_cap, hcattr,
438 vdpa_attr->event_mode = MLX5_GET(virtio_emulation_cap, hcattr,
440 vdpa_attr->virtio_queue_type =
441 MLX5_GET(virtio_emulation_cap, hcattr,
443 vdpa_attr->log_doorbell_stride =
444 MLX5_GET(virtio_emulation_cap, hcattr,
445 log_doorbell_stride);
446 vdpa_attr->log_doorbell_bar_size =
447 MLX5_GET(virtio_emulation_cap, hcattr,
448 log_doorbell_bar_size);
449 vdpa_attr->doorbell_bar_offset =
450 MLX5_GET64(virtio_emulation_cap, hcattr,
451 doorbell_bar_offset);
452 vdpa_attr->max_num_virtio_queues =
453 MLX5_GET(virtio_emulation_cap, hcattr,
454 max_num_virtio_queues);
455 vdpa_attr->umems[0].a = MLX5_GET(virtio_emulation_cap, hcattr,
456 umem_1_buffer_param_a);
457 vdpa_attr->umems[0].b = MLX5_GET(virtio_emulation_cap, hcattr,
458 umem_1_buffer_param_b);
459 vdpa_attr->umems[1].a = MLX5_GET(virtio_emulation_cap, hcattr,
460 umem_2_buffer_param_a);
461 vdpa_attr->umems[1].b = MLX5_GET(virtio_emulation_cap, hcattr,
462 umem_2_buffer_param_b);
463 vdpa_attr->umems[2].a = MLX5_GET(virtio_emulation_cap, hcattr,
464 umem_3_buffer_param_a);
465 vdpa_attr->umems[2].b = MLX5_GET(virtio_emulation_cap, hcattr,
466 umem_3_buffer_param_b);
471 mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj,
472 uint32_t ids[], uint32_t num)
474 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
475 uint32_t out[MLX5_ST_SZ_DW(create_flex_parser_out)] = {0};
476 void *hdr = MLX5_ADDR_OF(create_flex_parser_out, in, hdr);
477 void *flex = MLX5_ADDR_OF(create_flex_parser_out, out, flex);
478 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table);
483 if (num > MLX5_GRAPH_NODE_SAMPLE_NUM) {
485 DRV_LOG(ERR, "Too many sample IDs to be fetched.");
488 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
489 MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
490 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
491 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH);
492 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, flex_obj->id);
493 ret = mlx5_glue->devx_obj_query(flex_obj->obj, in, sizeof(in),
497 DRV_LOG(ERR, "Failed to query sample IDs with object %p.",
501 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) {
502 void *s_off = (void *)((char *)sample + i *
503 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample));
506 en = MLX5_GET(parse_graph_flow_match_sample, s_off,
507 flow_match_sample_en);
510 ids[idx++] = MLX5_GET(parse_graph_flow_match_sample, s_off,
511 flow_match_sample_field_id);
515 DRV_LOG(ERR, "Number of sample IDs are not as expected.");
522 struct mlx5_devx_obj *
523 mlx5_devx_cmd_create_flex_parser(void *ctx,
524 struct mlx5_devx_graph_node_attr *data)
526 uint32_t in[MLX5_ST_SZ_DW(create_flex_parser_in)] = {0};
527 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
528 void *hdr = MLX5_ADDR_OF(create_flex_parser_in, in, hdr);
529 void *flex = MLX5_ADDR_OF(create_flex_parser_in, in, flex);
530 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table);
531 void *in_arc = MLX5_ADDR_OF(parse_graph_flex, flex, input_arc);
532 void *out_arc = MLX5_ADDR_OF(parse_graph_flex, flex, output_arc);
533 struct mlx5_devx_obj *parse_flex_obj = mlx5_malloc
534 (MLX5_MEM_ZERO, sizeof(*parse_flex_obj), 0, SOCKET_ID_ANY);
537 if (!parse_flex_obj) {
538 DRV_LOG(ERR, "Failed to allocate flex parser data.");
542 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
543 MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
544 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
545 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH);
546 MLX5_SET(parse_graph_flex, flex, header_length_mode,
547 data->header_length_mode);
548 MLX5_SET(parse_graph_flex, flex, header_length_base_value,
549 data->header_length_base_value);
550 MLX5_SET(parse_graph_flex, flex, header_length_field_offset,
551 data->header_length_field_offset);
552 MLX5_SET(parse_graph_flex, flex, header_length_field_shift,
553 data->header_length_field_shift);
554 MLX5_SET(parse_graph_flex, flex, header_length_field_mask,
555 data->header_length_field_mask);
556 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) {
557 struct mlx5_devx_match_sample_attr *s = &data->sample[i];
558 void *s_off = (void *)((char *)sample + i *
559 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample));
561 if (!s->flow_match_sample_en)
563 MLX5_SET(parse_graph_flow_match_sample, s_off,
564 flow_match_sample_en, !!s->flow_match_sample_en);
565 MLX5_SET(parse_graph_flow_match_sample, s_off,
566 flow_match_sample_field_offset,
567 s->flow_match_sample_field_offset);
568 MLX5_SET(parse_graph_flow_match_sample, s_off,
569 flow_match_sample_offset_mode,
570 s->flow_match_sample_offset_mode);
571 MLX5_SET(parse_graph_flow_match_sample, s_off,
572 flow_match_sample_field_offset_mask,
573 s->flow_match_sample_field_offset_mask);
574 MLX5_SET(parse_graph_flow_match_sample, s_off,
575 flow_match_sample_field_offset_shift,
576 s->flow_match_sample_field_offset_shift);
577 MLX5_SET(parse_graph_flow_match_sample, s_off,
578 flow_match_sample_field_base_offset,
579 s->flow_match_sample_field_base_offset);
580 MLX5_SET(parse_graph_flow_match_sample, s_off,
581 flow_match_sample_tunnel_mode,
582 s->flow_match_sample_tunnel_mode);
584 for (i = 0; i < MLX5_GRAPH_NODE_ARC_NUM; i++) {
585 struct mlx5_devx_graph_arc_attr *ia = &data->in[i];
586 struct mlx5_devx_graph_arc_attr *oa = &data->out[i];
587 void *in_off = (void *)((char *)in_arc + i *
588 MLX5_ST_SZ_BYTES(parse_graph_arc));
589 void *out_off = (void *)((char *)out_arc + i *
590 MLX5_ST_SZ_BYTES(parse_graph_arc));
592 if (ia->arc_parse_graph_node != 0) {
593 MLX5_SET(parse_graph_arc, in_off,
594 compare_condition_value,
595 ia->compare_condition_value);
596 MLX5_SET(parse_graph_arc, in_off, start_inner_tunnel,
597 ia->start_inner_tunnel);
598 MLX5_SET(parse_graph_arc, in_off, arc_parse_graph_node,
599 ia->arc_parse_graph_node);
600 MLX5_SET(parse_graph_arc, in_off,
601 parse_graph_node_handle,
602 ia->parse_graph_node_handle);
604 if (oa->arc_parse_graph_node != 0) {
605 MLX5_SET(parse_graph_arc, out_off,
606 compare_condition_value,
607 oa->compare_condition_value);
608 MLX5_SET(parse_graph_arc, out_off, start_inner_tunnel,
609 oa->start_inner_tunnel);
610 MLX5_SET(parse_graph_arc, out_off, arc_parse_graph_node,
611 oa->arc_parse_graph_node);
612 MLX5_SET(parse_graph_arc, out_off,
613 parse_graph_node_handle,
614 oa->parse_graph_node_handle);
617 parse_flex_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
619 if (!parse_flex_obj->obj) {
621 DRV_LOG(ERR, "Failed to create FLEX PARSE GRAPH object "
623 mlx5_free(parse_flex_obj);
626 parse_flex_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
627 return parse_flex_obj;
631 * Query HCA attributes.
632 * Using those attributes we can check on run time if the device
633 * is having the required capabilities.
636 * Context returned from mlx5 open_device() glue function.
638 * Attributes device values.
641 * 0 on success, a negative value otherwise.
644 mlx5_devx_cmd_query_hca_attr(void *ctx,
645 struct mlx5_hca_attr *attr)
647 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0};
648 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0};
650 int status, syndrome, rc, i;
652 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
653 MLX5_SET(query_hca_cap_in, in, op_mod,
654 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE |
655 MLX5_HCA_CAP_OPMOD_GET_CUR);
657 rc = mlx5_glue->devx_general_cmd(ctx,
658 in, sizeof(in), out, sizeof(out));
661 status = MLX5_GET(query_hca_cap_out, out, status);
662 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
664 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, "
665 "status %x, syndrome = %x",
669 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
670 attr->flow_counter_bulk_alloc_bitmap =
671 MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc);
672 attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr,
674 attr->log_max_rqt_size = MLX5_GET(cmd_hca_cap, hcattr,
676 attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager);
677 attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin);
678 attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr,
679 log_max_hairpin_queues);
680 attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr,
681 log_max_hairpin_wq_data_sz);
682 attr->log_max_hairpin_num_packets = MLX5_GET
683 (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz);
684 attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id);
685 attr->relaxed_ordering_write = MLX5_GET(cmd_hca_cap, hcattr,
686 relaxed_ordering_write);
687 attr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr,
688 relaxed_ordering_read);
689 attr->access_register_user = MLX5_GET(cmd_hca_cap, hcattr,
690 access_register_user);
691 attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr,
693 attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt);
694 attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr,
695 flex_parser_protocols);
696 attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos);
697 attr->vdpa.valid = !!(MLX5_GET64(cmd_hca_cap, hcattr,
699 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q);
700 attr->vdpa.queue_counters_valid = !!(MLX5_GET64(cmd_hca_cap, hcattr,
702 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS);
703 attr->parse_graph_flex_node = !!(MLX5_GET64(cmd_hca_cap, hcattr,
705 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE);
706 attr->wqe_index_ignore = MLX5_GET(cmd_hca_cap, hcattr,
707 wqe_index_ignore_cap);
708 attr->cross_channel = MLX5_GET(cmd_hca_cap, hcattr, cd);
709 attr->non_wire_sq = MLX5_GET(cmd_hca_cap, hcattr, non_wire_sq);
710 attr->log_max_static_sq_wq = MLX5_GET(cmd_hca_cap, hcattr,
711 log_max_static_sq_wq);
712 attr->num_lag_ports = MLX5_GET(cmd_hca_cap, hcattr, num_lag_ports);
713 attr->dev_freq_khz = MLX5_GET(cmd_hca_cap, hcattr,
714 device_frequency_khz);
715 attr->scatter_fcs_w_decap_disable =
716 MLX5_GET(cmd_hca_cap, hcattr, scatter_fcs_w_decap_disable);
717 attr->regex = MLX5_GET(cmd_hca_cap, hcattr, regexp);
718 attr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr,
719 regexp_num_of_engines);
720 attr->flow_hit_aso = !!(MLX5_GET64(cmd_hca_cap, hcattr,
722 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO);
723 attr->log_max_cq = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq);
724 attr->log_max_qp = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp);
725 attr->log_max_cq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq_sz);
726 attr->log_max_qp_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp_sz);
727 attr->log_max_mrw_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_mrw_sz);
728 attr->log_max_pd = MLX5_GET(cmd_hca_cap, hcattr, log_max_pd);
729 attr->log_max_srq = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq);
730 attr->log_max_srq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq_sz);
732 MLX5_SET(query_hca_cap_in, in, op_mod,
733 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP |
734 MLX5_HCA_CAP_OPMOD_GET_CUR);
735 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in),
740 DRV_LOG(DEBUG, "Failed to query devx QOS capabilities,"
741 " status %x, syndrome = %x",
745 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
746 attr->qos.srtcm_sup =
747 MLX5_GET(qos_cap, hcattr, flow_meter_srtcm);
748 attr->qos.log_max_flow_meter =
749 MLX5_GET(qos_cap, hcattr, log_max_flow_meter);
750 attr->qos.flow_meter_reg_c_ids =
751 MLX5_GET(qos_cap, hcattr, flow_meter_reg_id);
752 attr->qos.flow_meter_reg_share =
753 MLX5_GET(qos_cap, hcattr, flow_meter_reg_share);
754 attr->qos.packet_pacing =
755 MLX5_GET(qos_cap, hcattr, packet_pacing);
756 attr->qos.wqe_rate_pp =
757 MLX5_GET(qos_cap, hcattr, wqe_rate_pp);
759 if (attr->vdpa.valid)
760 mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa);
761 if (!attr->eth_net_offloads)
764 /* Query Flow Sampler Capability From FLow Table Properties Layout. */
765 memset(in, 0, sizeof(in));
766 memset(out, 0, sizeof(out));
767 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
768 MLX5_SET(query_hca_cap_in, in, op_mod,
769 MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE |
770 MLX5_HCA_CAP_OPMOD_GET_CUR);
772 rc = mlx5_glue->devx_general_cmd(ctx,
777 status = MLX5_GET(query_hca_cap_out, out, status);
778 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
780 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, "
781 "status %x, syndrome = %x",
783 attr->log_max_ft_sampler_num = 0;
786 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
787 attr->log_max_ft_sampler_num =
788 MLX5_GET(flow_table_nic_cap,
789 hcattr, flow_table_properties.log_max_ft_sampler_num);
791 /* Query HCA offloads for Ethernet protocol. */
792 memset(in, 0, sizeof(in));
793 memset(out, 0, sizeof(out));
794 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
795 MLX5_SET(query_hca_cap_in, in, op_mod,
796 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS |
797 MLX5_HCA_CAP_OPMOD_GET_CUR);
799 rc = mlx5_glue->devx_general_cmd(ctx,
803 attr->eth_net_offloads = 0;
806 status = MLX5_GET(query_hca_cap_out, out, status);
807 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
809 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, "
810 "status %x, syndrome = %x",
812 attr->eth_net_offloads = 0;
815 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
816 attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps,
817 hcattr, wqe_vlan_insert);
818 attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr,
820 attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps,
821 hcattr, tunnel_lro_gre);
822 attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps,
823 hcattr, tunnel_lro_vxlan);
824 attr->lro_max_msg_sz_mode = MLX5_GET
825 (per_protocol_networking_offload_caps,
826 hcattr, lro_max_msg_sz_mode);
827 for (i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) {
828 attr->lro_timer_supported_periods[i] =
829 MLX5_GET(per_protocol_networking_offload_caps, hcattr,
830 lro_timer_supported_periods[i]);
832 attr->lro_min_mss_size = MLX5_GET(per_protocol_networking_offload_caps,
833 hcattr, lro_min_mss_size);
834 attr->tunnel_stateless_geneve_rx =
835 MLX5_GET(per_protocol_networking_offload_caps,
836 hcattr, tunnel_stateless_geneve_rx);
837 attr->geneve_max_opt_len =
838 MLX5_GET(per_protocol_networking_offload_caps,
839 hcattr, max_geneve_opt_len);
840 attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps,
841 hcattr, wqe_inline_mode);
842 attr->tunnel_stateless_gtp = MLX5_GET
843 (per_protocol_networking_offload_caps,
844 hcattr, tunnel_stateless_gtp);
845 attr->rss_ind_tbl_cap = MLX5_GET
846 (per_protocol_networking_offload_caps,
847 hcattr, rss_ind_tbl_cap);
848 if (attr->wqe_inline_mode != MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
850 if (attr->eth_virt) {
851 rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr);
859 rc = (rc > 0) ? -rc : rc;
864 * Query TIS transport domain from QP verbs object using DevX API.
867 * Pointer to verbs QP returned by ibv_create_qp .
869 * TIS number of TIS to query.
871 * Pointer to TIS transport domain variable, to be set by the routine.
874 * 0 on success, a negative value otherwise.
877 mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num,
880 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
881 uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0};
882 uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0};
886 MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS);
887 MLX5_SET(query_tis_in, in, tisn, tis_num);
888 rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out));
890 DRV_LOG(ERR, "Failed to query QP using DevX");
893 tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context);
894 *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain);
905 * Fill WQ data for DevX API command.
906 * Utility function for use when creating DevX objects containing a WQ.
909 * Pointer to WQ context to fill with data.
910 * @param [in] wq_attr
911 * Pointer to WQ attributes structure to fill in WQ context.
914 devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr)
916 MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type);
917 MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature);
918 MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode);
919 MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave);
920 MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge);
921 MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size);
922 MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset);
923 MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm);
924 MLX5_SET(wq, wq_ctx, pd, wq_attr->pd);
925 MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page);
926 MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr);
927 MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter);
928 MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter);
929 MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride);
930 MLX5_SET(wq, wq_ctx, log_wq_pg_sz, wq_attr->log_wq_pg_sz);
931 MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz);
932 MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid);
933 MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid);
934 MLX5_SET(wq, wq_ctx, log_hairpin_num_packets,
935 wq_attr->log_hairpin_num_packets);
936 MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz);
937 MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides,
938 wq_attr->single_wqe_log_num_of_strides);
939 MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en);
940 MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes,
941 wq_attr->single_stride_log_num_of_bytes);
942 MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id);
943 MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id);
944 MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset);
948 * Create RQ using DevX API.
951 * Context returned from mlx5 open_device() glue function.
952 * @param [in] rq_attr
953 * Pointer to create RQ attributes structure.
955 * CPU socket ID for allocations.
958 * The DevX object created, NULL otherwise and rte_errno is set.
960 struct mlx5_devx_obj *
961 mlx5_devx_cmd_create_rq(void *ctx,
962 struct mlx5_devx_create_rq_attr *rq_attr,
965 uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0};
966 uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0};
967 void *rq_ctx, *wq_ctx;
968 struct mlx5_devx_wq_attr *wq_attr;
969 struct mlx5_devx_obj *rq = NULL;
971 rq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rq), 0, socket);
973 DRV_LOG(ERR, "Failed to allocate RQ data");
977 MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ);
978 rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx);
979 MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky);
980 MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en);
981 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);
982 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);
983 MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type);
984 MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
985 MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en);
986 MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin);
987 MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index);
988 MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn);
989 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
990 MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn);
991 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);
992 wq_attr = &rq_attr->wq_attr;
993 devx_cmd_fill_wq_data(wq_ctx, wq_attr);
994 rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
997 DRV_LOG(ERR, "Failed to create RQ using DevX");
1002 rq->id = MLX5_GET(create_rq_out, out, rqn);
1007 * Modify RQ using DevX API.
1010 * Pointer to RQ object structure.
1011 * @param [in] rq_attr
1012 * Pointer to modify RQ attributes structure.
1015 * 0 on success, a negative errno value otherwise and rte_errno is set.
1018 mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,
1019 struct mlx5_devx_modify_rq_attr *rq_attr)
1021 uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0};
1022 uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0};
1023 void *rq_ctx, *wq_ctx;
1026 MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ);
1027 MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state);
1028 MLX5_SET(modify_rq_in, in, rqn, rq->id);
1029 MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask);
1030 rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1031 MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
1032 if (rq_attr->modify_bitmask &
1033 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS)
1034 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);
1035 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD)
1036 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);
1037 if (rq_attr->modify_bitmask &
1038 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID)
1039 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
1040 MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq);
1041 MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca);
1042 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) {
1043 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);
1044 MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm);
1046 ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in),
1049 DRV_LOG(ERR, "Failed to modify RQ using DevX");
1057 * Create TIR using DevX API.
1060 * Context returned from mlx5 open_device() glue function.
1061 * @param [in] tir_attr
1062 * Pointer to TIR attributes structure.
1065 * The DevX object created, NULL otherwise and rte_errno is set.
1067 struct mlx5_devx_obj *
1068 mlx5_devx_cmd_create_tir(void *ctx,
1069 struct mlx5_devx_tir_attr *tir_attr)
1071 uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
1072 uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0};
1073 void *tir_ctx, *outer, *inner, *rss_key;
1074 struct mlx5_devx_obj *tir = NULL;
1076 tir = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tir), 0, SOCKET_ID_ANY);
1078 DRV_LOG(ERR, "Failed to allocate TIR data");
1082 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR);
1083 tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx);
1084 MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type);
1085 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs,
1086 tir_attr->lro_timeout_period_usecs);
1087 MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask);
1088 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz);
1089 MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn);
1090 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric);
1091 MLX5_SET(tirc, tir_ctx, tunneled_offload_en,
1092 tir_attr->tunneled_offload_en);
1093 MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table);
1094 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn);
1095 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block);
1096 MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain);
1097 rss_key = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_toeplitz_key);
1098 memcpy(rss_key, tir_attr->rx_hash_toeplitz_key, MLX5_RSS_HASH_KEY_LEN);
1099 outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer);
1100 MLX5_SET(rx_hash_field_select, outer, l3_prot_type,
1101 tir_attr->rx_hash_field_selector_outer.l3_prot_type);
1102 MLX5_SET(rx_hash_field_select, outer, l4_prot_type,
1103 tir_attr->rx_hash_field_selector_outer.l4_prot_type);
1104 MLX5_SET(rx_hash_field_select, outer, selected_fields,
1105 tir_attr->rx_hash_field_selector_outer.selected_fields);
1106 inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner);
1107 MLX5_SET(rx_hash_field_select, inner, l3_prot_type,
1108 tir_attr->rx_hash_field_selector_inner.l3_prot_type);
1109 MLX5_SET(rx_hash_field_select, inner, l4_prot_type,
1110 tir_attr->rx_hash_field_selector_inner.l4_prot_type);
1111 MLX5_SET(rx_hash_field_select, inner, selected_fields,
1112 tir_attr->rx_hash_field_selector_inner.selected_fields);
1113 tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1116 DRV_LOG(ERR, "Failed to create TIR using DevX");
1121 tir->id = MLX5_GET(create_tir_out, out, tirn);
1126 * Modify TIR using DevX API.
1129 * Pointer to TIR DevX object structure.
1130 * @param [in] modify_tir_attr
1131 * Pointer to TIR modification attributes structure.
1134 * 0 on success, a negative errno value otherwise and rte_errno is set.
1137 mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir,
1138 struct mlx5_devx_modify_tir_attr *modify_tir_attr)
1140 struct mlx5_devx_tir_attr *tir_attr = &modify_tir_attr->tir;
1141 uint32_t in[MLX5_ST_SZ_DW(modify_tir_in)] = {0};
1142 uint32_t out[MLX5_ST_SZ_DW(modify_tir_out)] = {0};
1146 MLX5_SET(modify_tir_in, in, opcode, MLX5_CMD_OP_MODIFY_TIR);
1147 MLX5_SET(modify_tir_in, in, tirn, modify_tir_attr->tirn);
1148 MLX5_SET64(modify_tir_in, in, modify_bitmask,
1149 modify_tir_attr->modify_bitmask);
1150 tir_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1151 if (modify_tir_attr->modify_bitmask &
1152 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO) {
1153 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs,
1154 tir_attr->lro_timeout_period_usecs);
1155 MLX5_SET(tirc, tir_ctx, lro_enable_mask,
1156 tir_attr->lro_enable_mask);
1157 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz,
1158 tir_attr->lro_max_msg_sz);
1160 if (modify_tir_attr->modify_bitmask &
1161 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE)
1162 MLX5_SET(tirc, tir_ctx, indirect_table,
1163 tir_attr->indirect_table);
1164 if (modify_tir_attr->modify_bitmask &
1165 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH) {
1167 void *outer, *inner;
1169 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric,
1170 tir_attr->rx_hash_symmetric);
1171 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn);
1172 for (i = 0; i < 10; i++) {
1173 MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i],
1174 tir_attr->rx_hash_toeplitz_key[i]);
1176 outer = MLX5_ADDR_OF(tirc, tir_ctx,
1177 rx_hash_field_selector_outer);
1178 MLX5_SET(rx_hash_field_select, outer, l3_prot_type,
1179 tir_attr->rx_hash_field_selector_outer.l3_prot_type);
1180 MLX5_SET(rx_hash_field_select, outer, l4_prot_type,
1181 tir_attr->rx_hash_field_selector_outer.l4_prot_type);
1183 (rx_hash_field_select, outer, selected_fields,
1184 tir_attr->rx_hash_field_selector_outer.selected_fields);
1185 inner = MLX5_ADDR_OF(tirc, tir_ctx,
1186 rx_hash_field_selector_inner);
1187 MLX5_SET(rx_hash_field_select, inner, l3_prot_type,
1188 tir_attr->rx_hash_field_selector_inner.l3_prot_type);
1189 MLX5_SET(rx_hash_field_select, inner, l4_prot_type,
1190 tir_attr->rx_hash_field_selector_inner.l4_prot_type);
1192 (rx_hash_field_select, inner, selected_fields,
1193 tir_attr->rx_hash_field_selector_inner.selected_fields);
1195 if (modify_tir_attr->modify_bitmask &
1196 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN) {
1197 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block);
1199 ret = mlx5_glue->devx_obj_modify(tir->obj, in, sizeof(in),
1202 DRV_LOG(ERR, "Failed to modify TIR using DevX");
1210 * Create RQT using DevX API.
1213 * Context returned from mlx5 open_device() glue function.
1214 * @param [in] rqt_attr
1215 * Pointer to RQT attributes structure.
1218 * The DevX object created, NULL otherwise and rte_errno is set.
1220 struct mlx5_devx_obj *
1221 mlx5_devx_cmd_create_rqt(void *ctx,
1222 struct mlx5_devx_rqt_attr *rqt_attr)
1224 uint32_t *in = NULL;
1225 uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) +
1226 rqt_attr->rqt_actual_size * sizeof(uint32_t);
1227 uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0};
1229 struct mlx5_devx_obj *rqt = NULL;
1232 in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY);
1234 DRV_LOG(ERR, "Failed to allocate RQT IN data");
1238 rqt = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt), 0, SOCKET_ID_ANY);
1240 DRV_LOG(ERR, "Failed to allocate RQT data");
1245 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
1246 rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1247 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type);
1248 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size);
1249 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size);
1250 for (i = 0; i < rqt_attr->rqt_actual_size; i++)
1251 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]);
1252 rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out));
1255 DRV_LOG(ERR, "Failed to create RQT using DevX");
1260 rqt->id = MLX5_GET(create_rqt_out, out, rqtn);
1265 * Modify RQT using DevX API.
1268 * Pointer to RQT DevX object structure.
1269 * @param [in] rqt_attr
1270 * Pointer to RQT attributes structure.
1273 * 0 on success, a negative errno value otherwise and rte_errno is set.
1276 mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt,
1277 struct mlx5_devx_rqt_attr *rqt_attr)
1279 uint32_t inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) +
1280 rqt_attr->rqt_actual_size * sizeof(uint32_t);
1281 uint32_t out[MLX5_ST_SZ_DW(modify_rqt_out)] = {0};
1282 uint32_t *in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY);
1288 DRV_LOG(ERR, "Failed to allocate RQT modify IN data.");
1292 MLX5_SET(modify_rqt_in, in, opcode, MLX5_CMD_OP_MODIFY_RQT);
1293 MLX5_SET(modify_rqt_in, in, rqtn, rqt->id);
1294 MLX5_SET64(modify_rqt_in, in, modify_bitmask, 0x1);
1295 rqt_ctx = MLX5_ADDR_OF(modify_rqt_in, in, rqt_context);
1296 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type);
1297 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size);
1298 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size);
1299 for (i = 0; i < rqt_attr->rqt_actual_size; i++)
1300 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]);
1301 ret = mlx5_glue->devx_obj_modify(rqt->obj, in, inlen, out, sizeof(out));
1304 DRV_LOG(ERR, "Failed to modify RQT using DevX.");
1312 * Create SQ using DevX API.
1315 * Context returned from mlx5 open_device() glue function.
1316 * @param [in] sq_attr
1317 * Pointer to SQ attributes structure.
1318 * @param [in] socket
1319 * CPU socket ID for allocations.
1322 * The DevX object created, NULL otherwise and rte_errno is set.
1324 struct mlx5_devx_obj *
1325 mlx5_devx_cmd_create_sq(void *ctx,
1326 struct mlx5_devx_create_sq_attr *sq_attr)
1328 uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0};
1329 uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0};
1332 struct mlx5_devx_wq_attr *wq_attr;
1333 struct mlx5_devx_obj *sq = NULL;
1335 sq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sq), 0, SOCKET_ID_ANY);
1337 DRV_LOG(ERR, "Failed to allocate SQ data");
1341 MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ);
1342 sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx);
1343 MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky);
1344 MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master);
1345 MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre);
1346 MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en);
1347 MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe,
1348 sq_attr->allow_multi_pkt_send_wqe);
1349 MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode,
1350 sq_attr->min_wqe_inline_mode);
1351 MLX5_SET(sqc, sq_ctx, state, sq_attr->state);
1352 MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr);
1353 MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp);
1354 MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin);
1355 MLX5_SET(sqc, sq_ctx, non_wire, sq_attr->non_wire);
1356 MLX5_SET(sqc, sq_ctx, static_sq_wq, sq_attr->static_sq_wq);
1357 MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index);
1358 MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn);
1359 MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index,
1360 sq_attr->packet_pacing_rate_limit_index);
1361 MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz);
1362 MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num);
1363 wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq);
1364 wq_attr = &sq_attr->wq_attr;
1365 devx_cmd_fill_wq_data(wq_ctx, wq_attr);
1366 sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1369 DRV_LOG(ERR, "Failed to create SQ using DevX");
1374 sq->id = MLX5_GET(create_sq_out, out, sqn);
1379 * Modify SQ using DevX API.
1382 * Pointer to SQ object structure.
1383 * @param [in] sq_attr
1384 * Pointer to SQ attributes structure.
1387 * 0 on success, a negative errno value otherwise and rte_errno is set.
1390 mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq,
1391 struct mlx5_devx_modify_sq_attr *sq_attr)
1393 uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0};
1394 uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0};
1398 MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ);
1399 MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state);
1400 MLX5_SET(modify_sq_in, in, sqn, sq->id);
1401 sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1402 MLX5_SET(sqc, sq_ctx, state, sq_attr->state);
1403 MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq);
1404 MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca);
1405 ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in),
1408 DRV_LOG(ERR, "Failed to modify SQ using DevX");
1416 * Create TIS using DevX API.
1419 * Context returned from mlx5 open_device() glue function.
1420 * @param [in] tis_attr
1421 * Pointer to TIS attributes structure.
1424 * The DevX object created, NULL otherwise and rte_errno is set.
1426 struct mlx5_devx_obj *
1427 mlx5_devx_cmd_create_tis(void *ctx,
1428 struct mlx5_devx_tis_attr *tis_attr)
1430 uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
1431 uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0};
1432 struct mlx5_devx_obj *tis = NULL;
1435 tis = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tis), 0, SOCKET_ID_ANY);
1437 DRV_LOG(ERR, "Failed to allocate TIS object");
1441 MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS);
1442 tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx);
1443 MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity,
1444 tis_attr->strict_lag_tx_port_affinity);
1445 MLX5_SET(tisc, tis_ctx, lag_tx_port_affinity,
1446 tis_attr->lag_tx_port_affinity);
1447 MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio);
1448 MLX5_SET(tisc, tis_ctx, transport_domain,
1449 tis_attr->transport_domain);
1450 tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1453 DRV_LOG(ERR, "Failed to create TIS using DevX");
1458 tis->id = MLX5_GET(create_tis_out, out, tisn);
1463 * Create transport domain using DevX API.
1466 * Context returned from mlx5 open_device() glue function.
1468 * The DevX object created, NULL otherwise and rte_errno is set.
1470 struct mlx5_devx_obj *
1471 mlx5_devx_cmd_create_td(void *ctx)
1473 uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0};
1474 uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0};
1475 struct mlx5_devx_obj *td = NULL;
1477 td = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*td), 0, SOCKET_ID_ANY);
1479 DRV_LOG(ERR, "Failed to allocate TD object");
1483 MLX5_SET(alloc_transport_domain_in, in, opcode,
1484 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN);
1485 td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1488 DRV_LOG(ERR, "Failed to create TIS using DevX");
1493 td->id = MLX5_GET(alloc_transport_domain_out, out,
1499 * Dump all flows to file.
1501 * @param[in] fdb_domain
1503 * @param[in] rx_domain
1505 * @param[in] tx_domain
1508 * Pointer to file stream.
1511 * 0 on success, a nagative value otherwise.
1514 mlx5_devx_cmd_flow_dump(void *fdb_domain __rte_unused,
1515 void *rx_domain __rte_unused,
1516 void *tx_domain __rte_unused, FILE *file __rte_unused)
1520 #ifdef HAVE_MLX5_DR_FLOW_DUMP
1522 ret = mlx5_glue->dr_dump_domain(file, fdb_domain);
1526 MLX5_ASSERT(rx_domain);
1527 ret = mlx5_glue->dr_dump_domain(file, rx_domain);
1530 MLX5_ASSERT(tx_domain);
1531 ret = mlx5_glue->dr_dump_domain(file, tx_domain);
1539 * Create CQ using DevX API.
1542 * Context returned from mlx5 open_device() glue function.
1544 * Pointer to CQ attributes structure.
1547 * The DevX object created, NULL otherwise and rte_errno is set.
1549 struct mlx5_devx_obj *
1550 mlx5_devx_cmd_create_cq(void *ctx, struct mlx5_devx_cq_attr *attr)
1552 uint32_t in[MLX5_ST_SZ_DW(create_cq_in)] = {0};
1553 uint32_t out[MLX5_ST_SZ_DW(create_cq_out)] = {0};
1554 struct mlx5_devx_obj *cq_obj = mlx5_malloc(MLX5_MEM_ZERO,
1557 void *cqctx = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1560 DRV_LOG(ERR, "Failed to allocate CQ object memory.");
1564 MLX5_SET(create_cq_in, in, opcode, MLX5_CMD_OP_CREATE_CQ);
1565 if (attr->db_umem_valid) {
1566 MLX5_SET(cqc, cqctx, dbr_umem_valid, attr->db_umem_valid);
1567 MLX5_SET(cqc, cqctx, dbr_umem_id, attr->db_umem_id);
1568 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_umem_offset);
1570 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_addr);
1572 MLX5_SET(cqc, cqctx, cqe_sz, attr->cqe_size);
1573 MLX5_SET(cqc, cqctx, cc, attr->use_first_only);
1574 MLX5_SET(cqc, cqctx, oi, attr->overrun_ignore);
1575 MLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size);
1576 MLX5_SET(cqc, cqctx, log_page_size, attr->log_page_size -
1577 MLX5_ADAPTER_PAGE_SHIFT);
1578 MLX5_SET(cqc, cqctx, c_eqn, attr->eqn);
1579 MLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id);
1580 MLX5_SET(cqc, cqctx, cqe_comp_en, !!attr->cqe_comp_en);
1581 MLX5_SET(cqc, cqctx, mini_cqe_res_format,
1582 attr->mini_cqe_res_format);
1583 MLX5_SET(cqc, cqctx, mini_cqe_res_format_ext,
1584 attr->mini_cqe_res_format_ext);
1585 MLX5_SET(cqc, cqctx, cqe_sz, attr->cqe_size);
1586 if (attr->q_umem_valid) {
1587 MLX5_SET(create_cq_in, in, cq_umem_valid, attr->q_umem_valid);
1588 MLX5_SET(create_cq_in, in, cq_umem_id, attr->q_umem_id);
1589 MLX5_SET64(create_cq_in, in, cq_umem_offset,
1590 attr->q_umem_offset);
1592 cq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
1596 DRV_LOG(ERR, "Failed to create CQ using DevX errno=%d.", errno);
1600 cq_obj->id = MLX5_GET(create_cq_out, out, cqn);
1605 * Create VIRTQ using DevX API.
1608 * Context returned from mlx5 open_device() glue function.
1610 * Pointer to VIRTQ attributes structure.
1613 * The DevX object created, NULL otherwise and rte_errno is set.
1615 struct mlx5_devx_obj *
1616 mlx5_devx_cmd_create_virtq(void *ctx,
1617 struct mlx5_devx_virtq_attr *attr)
1619 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0};
1620 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
1621 struct mlx5_devx_obj *virtq_obj = mlx5_malloc(MLX5_MEM_ZERO,
1624 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq);
1625 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr);
1626 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context);
1629 DRV_LOG(ERR, "Failed to allocate virtq data.");
1633 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
1634 MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
1635 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
1636 MLX5_GENERAL_OBJ_TYPE_VIRTQ);
1637 MLX5_SET16(virtio_net_q, virtq, hw_available_index,
1638 attr->hw_available_index);
1639 MLX5_SET16(virtio_net_q, virtq, hw_used_index, attr->hw_used_index);
1640 MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4);
1641 MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6);
1642 MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum);
1643 MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum);
1644 MLX5_SET16(virtio_q, virtctx, virtio_version_1_0,
1645 attr->virtio_version_1_0);
1646 MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode);
1647 MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id);
1648 MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr);
1649 MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr);
1650 MLX5_SET64(virtio_q, virtctx, available_addr, attr->available_addr);
1651 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index);
1652 MLX5_SET16(virtio_q, virtctx, queue_size, attr->q_size);
1653 MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey);
1654 MLX5_SET(virtio_q, virtctx, umem_1_id, attr->umems[0].id);
1655 MLX5_SET(virtio_q, virtctx, umem_1_size, attr->umems[0].size);
1656 MLX5_SET64(virtio_q, virtctx, umem_1_offset, attr->umems[0].offset);
1657 MLX5_SET(virtio_q, virtctx, umem_2_id, attr->umems[1].id);
1658 MLX5_SET(virtio_q, virtctx, umem_2_size, attr->umems[1].size);
1659 MLX5_SET64(virtio_q, virtctx, umem_2_offset, attr->umems[1].offset);
1660 MLX5_SET(virtio_q, virtctx, umem_3_id, attr->umems[2].id);
1661 MLX5_SET(virtio_q, virtctx, umem_3_size, attr->umems[2].size);
1662 MLX5_SET64(virtio_q, virtctx, umem_3_offset, attr->umems[2].offset);
1663 MLX5_SET(virtio_q, virtctx, counter_set_id, attr->counters_obj_id);
1664 MLX5_SET(virtio_q, virtctx, pd, attr->pd);
1665 MLX5_SET(virtio_net_q, virtq, tisn_or_qpn, attr->tis_id);
1666 virtq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
1668 if (!virtq_obj->obj) {
1670 DRV_LOG(ERR, "Failed to create VIRTQ Obj using DevX.");
1671 mlx5_free(virtq_obj);
1674 virtq_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
1679 * Modify VIRTQ using DevX API.
1681 * @param[in] virtq_obj
1682 * Pointer to virtq object structure.
1684 * Pointer to modify virtq attributes structure.
1687 * 0 on success, a negative errno value otherwise and rte_errno is set.
1690 mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj,
1691 struct mlx5_devx_virtq_attr *attr)
1693 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0};
1694 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
1695 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq);
1696 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr);
1697 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context);
1700 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
1701 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT);
1702 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
1703 MLX5_GENERAL_OBJ_TYPE_VIRTQ);
1704 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id);
1705 MLX5_SET64(virtio_net_q, virtq, modify_field_select, attr->type);
1706 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index);
1707 switch (attr->type) {
1708 case MLX5_VIRTQ_MODIFY_TYPE_STATE:
1709 MLX5_SET16(virtio_net_q, virtq, state, attr->state);
1711 case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS:
1712 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_mkey,
1713 attr->dirty_bitmap_mkey);
1714 MLX5_SET64(virtio_net_q, virtq, dirty_bitmap_addr,
1715 attr->dirty_bitmap_addr);
1716 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_size,
1717 attr->dirty_bitmap_size);
1719 case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE:
1720 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_dump_enable,
1721 attr->dirty_bitmap_dump_enable);
1727 ret = mlx5_glue->devx_obj_modify(virtq_obj->obj, in, sizeof(in),
1730 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX.");
1738 * Query VIRTQ using DevX API.
1740 * @param[in] virtq_obj
1741 * Pointer to virtq object structure.
1742 * @param [in/out] attr
1743 * Pointer to virtq attributes structure.
1746 * 0 on success, a negative errno value otherwise and rte_errno is set.
1749 mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj,
1750 struct mlx5_devx_virtq_attr *attr)
1752 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
1753 uint32_t out[MLX5_ST_SZ_DW(query_virtq_out)] = {0};
1754 void *hdr = MLX5_ADDR_OF(query_virtq_out, in, hdr);
1755 void *virtq = MLX5_ADDR_OF(query_virtq_out, out, virtq);
1758 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
1759 MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
1760 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
1761 MLX5_GENERAL_OBJ_TYPE_VIRTQ);
1762 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id);
1763 ret = mlx5_glue->devx_obj_query(virtq_obj->obj, in, sizeof(in),
1766 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX.");
1770 attr->hw_available_index = MLX5_GET16(virtio_net_q, virtq,
1771 hw_available_index);
1772 attr->hw_used_index = MLX5_GET16(virtio_net_q, virtq, hw_used_index);
1773 attr->state = MLX5_GET16(virtio_net_q, virtq, state);
1774 attr->error_type = MLX5_GET16(virtio_net_q, virtq,
1775 virtio_q_context.error_type);
1780 * Create QP using DevX API.
1783 * Context returned from mlx5 open_device() glue function.
1785 * Pointer to QP attributes structure.
1788 * The DevX object created, NULL otherwise and rte_errno is set.
1790 struct mlx5_devx_obj *
1791 mlx5_devx_cmd_create_qp(void *ctx,
1792 struct mlx5_devx_qp_attr *attr)
1794 uint32_t in[MLX5_ST_SZ_DW(create_qp_in)] = {0};
1795 uint32_t out[MLX5_ST_SZ_DW(create_qp_out)] = {0};
1796 struct mlx5_devx_obj *qp_obj = mlx5_malloc(MLX5_MEM_ZERO,
1799 void *qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1802 DRV_LOG(ERR, "Failed to allocate QP data.");
1806 MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP);
1807 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC);
1808 MLX5_SET(qpc, qpc, pd, attr->pd);
1809 if (attr->uar_index) {
1810 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
1811 MLX5_SET(qpc, qpc, uar_page, attr->uar_index);
1812 MLX5_SET(qpc, qpc, log_page_size, attr->log_page_size -
1813 MLX5_ADAPTER_PAGE_SHIFT);
1814 if (attr->sq_size) {
1815 MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->sq_size));
1816 MLX5_SET(qpc, qpc, cqn_snd, attr->cqn);
1817 MLX5_SET(qpc, qpc, log_sq_size,
1818 rte_log2_u32(attr->sq_size));
1820 MLX5_SET(qpc, qpc, no_sq, 1);
1822 if (attr->rq_size) {
1823 MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->rq_size));
1824 MLX5_SET(qpc, qpc, cqn_rcv, attr->cqn);
1825 MLX5_SET(qpc, qpc, log_rq_stride, attr->log_rq_stride -
1826 MLX5_LOG_RQ_STRIDE_SHIFT);
1827 MLX5_SET(qpc, qpc, log_rq_size,
1828 rte_log2_u32(attr->rq_size));
1829 MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ);
1831 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ);
1833 if (attr->dbr_umem_valid) {
1834 MLX5_SET(qpc, qpc, dbr_umem_valid,
1835 attr->dbr_umem_valid);
1836 MLX5_SET(qpc, qpc, dbr_umem_id, attr->dbr_umem_id);
1838 MLX5_SET64(qpc, qpc, dbr_addr, attr->dbr_address);
1839 MLX5_SET64(create_qp_in, in, wq_umem_offset,
1840 attr->wq_umem_offset);
1841 MLX5_SET(create_qp_in, in, wq_umem_id, attr->wq_umem_id);
1842 MLX5_SET(create_qp_in, in, wq_umem_valid, 1);
1844 /* Special QP to be managed by FW - no SQ\RQ\CQ\UAR\DB rec. */
1845 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ);
1846 MLX5_SET(qpc, qpc, no_sq, 1);
1848 qp_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
1852 DRV_LOG(ERR, "Failed to create QP Obj using DevX.");
1856 qp_obj->id = MLX5_GET(create_qp_out, out, qpn);
1861 * Modify QP using DevX API.
1862 * Currently supports only force loop-back QP.
1865 * Pointer to QP object structure.
1866 * @param [in] qp_st_mod_op
1867 * The QP state modification operation.
1868 * @param [in] remote_qp_id
1869 * The remote QP ID for MLX5_CMD_OP_INIT2RTR_QP operation.
1872 * 0 on success, a negative errno value otherwise and rte_errno is set.
1875 mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op,
1876 uint32_t remote_qp_id)
1879 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)];
1880 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)];
1881 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)];
1884 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)];
1885 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)];
1886 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)];
1891 unsigned int outlen;
1893 memset(&in, 0, sizeof(in));
1894 memset(&out, 0, sizeof(out));
1895 MLX5_SET(rst2init_qp_in, &in, opcode, qp_st_mod_op);
1896 switch (qp_st_mod_op) {
1897 case MLX5_CMD_OP_RST2INIT_QP:
1898 MLX5_SET(rst2init_qp_in, &in, qpn, qp->id);
1899 qpc = MLX5_ADDR_OF(rst2init_qp_in, &in, qpc);
1900 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1);
1901 MLX5_SET(qpc, qpc, rre, 1);
1902 MLX5_SET(qpc, qpc, rwe, 1);
1903 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
1904 inlen = sizeof(in.rst2init);
1905 outlen = sizeof(out.rst2init);
1907 case MLX5_CMD_OP_INIT2RTR_QP:
1908 MLX5_SET(init2rtr_qp_in, &in, qpn, qp->id);
1909 qpc = MLX5_ADDR_OF(init2rtr_qp_in, &in, qpc);
1910 MLX5_SET(qpc, qpc, primary_address_path.fl, 1);
1911 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1);
1912 MLX5_SET(qpc, qpc, mtu, 1);
1913 MLX5_SET(qpc, qpc, log_msg_max, 30);
1914 MLX5_SET(qpc, qpc, remote_qpn, remote_qp_id);
1915 MLX5_SET(qpc, qpc, min_rnr_nak, 0);
1916 inlen = sizeof(in.init2rtr);
1917 outlen = sizeof(out.init2rtr);
1919 case MLX5_CMD_OP_RTR2RTS_QP:
1920 qpc = MLX5_ADDR_OF(rtr2rts_qp_in, &in, qpc);
1921 MLX5_SET(rtr2rts_qp_in, &in, qpn, qp->id);
1922 MLX5_SET(qpc, qpc, primary_address_path.ack_timeout, 14);
1923 MLX5_SET(qpc, qpc, log_ack_req_freq, 0);
1924 MLX5_SET(qpc, qpc, retry_count, 7);
1925 MLX5_SET(qpc, qpc, rnr_retry, 7);
1926 inlen = sizeof(in.rtr2rts);
1927 outlen = sizeof(out.rtr2rts);
1930 DRV_LOG(ERR, "Invalid or unsupported QP modify op %u.",
1935 ret = mlx5_glue->devx_obj_modify(qp->obj, &in, inlen, &out, outlen);
1937 DRV_LOG(ERR, "Failed to modify QP using DevX.");
1944 struct mlx5_devx_obj *
1945 mlx5_devx_cmd_create_virtio_q_counters(void *ctx)
1947 uint32_t in[MLX5_ST_SZ_DW(create_virtio_q_counters_in)] = {0};
1948 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
1949 struct mlx5_devx_obj *couners_obj = mlx5_malloc(MLX5_MEM_ZERO,
1950 sizeof(*couners_obj), 0,
1952 void *hdr = MLX5_ADDR_OF(create_virtio_q_counters_in, in, hdr);
1955 DRV_LOG(ERR, "Failed to allocate virtio queue counters data.");
1959 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
1960 MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
1961 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
1962 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS);
1963 couners_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
1965 if (!couners_obj->obj) {
1967 DRV_LOG(ERR, "Failed to create virtio queue counters Obj using"
1969 mlx5_free(couners_obj);
1972 couners_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
1977 mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj,
1978 struct mlx5_devx_virtio_q_couners_attr *attr)
1980 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
1981 uint32_t out[MLX5_ST_SZ_DW(query_virtio_q_counters_out)] = {0};
1982 void *hdr = MLX5_ADDR_OF(query_virtio_q_counters_out, in, hdr);
1983 void *virtio_q_counters = MLX5_ADDR_OF(query_virtio_q_counters_out, out,
1987 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
1988 MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
1989 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
1990 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS);
1991 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, couners_obj->id);
1992 ret = mlx5_glue->devx_obj_query(couners_obj->obj, in, sizeof(in), out,
1995 DRV_LOG(ERR, "Failed to query virtio q counters using DevX.");
1999 attr->received_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters,
2001 attr->completed_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters,
2003 attr->error_cqes = MLX5_GET(virtio_q_counters, virtio_q_counters,
2005 attr->bad_desc_errors = MLX5_GET(virtio_q_counters, virtio_q_counters,
2007 attr->exceed_max_chain = MLX5_GET(virtio_q_counters, virtio_q_counters,
2009 attr->invalid_buffer = MLX5_GET(virtio_q_counters, virtio_q_counters,
2015 * Create general object of type FLOW_HIT_ASO using DevX API.
2018 * Context returned from mlx5 open_device() glue function.
2020 * PD value to associate the FLOW_HIT_ASO object with.
2023 * The DevX object created, NULL otherwise and rte_errno is set.
2025 struct mlx5_devx_obj *
2026 mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, uint32_t pd)
2028 uint32_t in[MLX5_ST_SZ_DW(create_flow_hit_aso_in)] = {0};
2029 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2030 struct mlx5_devx_obj *flow_hit_aso_obj = NULL;
2033 flow_hit_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*flow_hit_aso_obj),
2035 if (!flow_hit_aso_obj) {
2036 DRV_LOG(ERR, "Failed to allocate FLOW_HIT_ASO object data");
2040 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, hdr);
2041 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2042 MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2043 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2044 MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO);
2045 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, flow_hit_aso);
2046 MLX5_SET(flow_hit_aso, ptr, access_pd, pd);
2047 flow_hit_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2049 if (!flow_hit_aso_obj->obj) {
2051 DRV_LOG(ERR, "Failed to create FLOW_HIT_ASO obj using DevX.");
2052 mlx5_free(flow_hit_aso_obj);
2055 flow_hit_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2056 return flow_hit_aso_obj;
2060 * Create PD using DevX API.
2063 * Context returned from mlx5 open_device() glue function.
2066 * The DevX object created, NULL otherwise and rte_errno is set.
2068 struct mlx5_devx_obj *
2069 mlx5_devx_cmd_alloc_pd(void *ctx)
2071 struct mlx5_devx_obj *ppd =
2072 mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ppd), 0, SOCKET_ID_ANY);
2073 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {0};
2074 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {0};
2077 DRV_LOG(ERR, "Failed to allocate PD data.");
2081 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD);
2082 ppd->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2086 DRV_LOG(ERR, "Failed to allocate PD Obj using DevX.");
2090 ppd->id = MLX5_GET(alloc_pd_out, out, pd);