1 // SPDX-License-Identifier: BSD-3-Clause
2 /* Copyright 2018 Mellanox Technologies, Ltd */
7 #include <rte_malloc.h>
8 #include <rte_eal_paging.h>
11 #include "mlx5_devx_cmds.h"
12 #include "mlx5_common_utils.h"
13 #include "mlx5_malloc.h"
17 * Perform read access to the registers. Reads data from register
18 * and writes ones to the specified buffer.
21 * Context returned from mlx5 open_device() glue function.
23 * Register identifier according to the PRM.
25 * Register access auxiliary parameter according to the PRM.
27 * Pointer to the buffer to store read data.
29 * Buffer size in double words.
32 * 0 on success, a negative value otherwise.
35 mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg,
36 uint32_t *data, uint32_t dw_cnt)
38 uint32_t in[MLX5_ST_SZ_DW(access_register_in)] = {0};
39 uint32_t out[MLX5_ST_SZ_DW(access_register_out) +
40 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0};
43 MLX5_ASSERT(data && dw_cnt);
44 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX);
45 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) {
46 DRV_LOG(ERR, "Not enough buffer for register read data");
49 MLX5_SET(access_register_in, in, opcode,
50 MLX5_CMD_OP_ACCESS_REGISTER_USER);
51 MLX5_SET(access_register_in, in, op_mod,
52 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ);
53 MLX5_SET(access_register_in, in, register_id, reg_id);
54 MLX5_SET(access_register_in, in, argument, arg);
55 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out,
56 MLX5_ST_SZ_BYTES(access_register_out) +
57 sizeof(uint32_t) * dw_cnt);
60 status = MLX5_GET(access_register_out, out, status);
62 int syndrome = MLX5_GET(access_register_out, out, syndrome);
64 DRV_LOG(DEBUG, "Failed to access NIC register 0x%X, "
65 "status %x, syndrome = %x",
66 reg_id, status, syndrome);
69 memcpy(data, &out[MLX5_ST_SZ_DW(access_register_out)],
70 dw_cnt * sizeof(uint32_t));
73 rc = (rc > 0) ? -rc : rc;
78 * Allocate flow counters via devx interface.
81 * Context returned from mlx5 open_device() glue function.
83 * Pointer to counters properties structure to be filled by the routine.
85 * Bulk counter numbers in 128 counters units.
88 * Pointer to counter object on success, a negative value otherwise and
91 struct mlx5_devx_obj *
92 mlx5_devx_cmd_flow_counter_alloc(void *ctx, uint32_t bulk_n_128)
94 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs),
96 uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0};
97 uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0};
103 MLX5_SET(alloc_flow_counter_in, in, opcode,
104 MLX5_CMD_OP_ALLOC_FLOW_COUNTER);
105 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128);
106 dcs->obj = mlx5_glue->devx_obj_create(ctx, in,
107 sizeof(in), out, sizeof(out));
109 DRV_LOG(ERR, "Can't allocate counters - error %d", errno);
114 dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id);
119 * Query flow counters values.
122 * devx object that was obtained from mlx5_devx_cmd_fc_alloc.
124 * Whether hardware should clear the counters after the query or not.
125 * @param[in] n_counters
126 * 0 in case of 1 counter to read, otherwise the counter number to read.
128 * The number of packets that matched the flow.
130 * The number of bytes that matched the flow.
132 * The mkey key for batch query.
134 * The address in the mkey range for batch query.
136 * The completion object for asynchronous batch query.
138 * The ID to be returned in the asynchronous batch query response.
141 * 0 on success, a negative value otherwise.
144 mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs,
145 int clear, uint32_t n_counters,
146 uint64_t *pkts, uint64_t *bytes,
147 uint32_t mkey, void *addr,
151 int out_len = MLX5_ST_SZ_BYTES(query_flow_counter_out) +
152 MLX5_ST_SZ_BYTES(traffic_counter);
153 uint32_t out[out_len];
154 uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0};
158 MLX5_SET(query_flow_counter_in, in, opcode,
159 MLX5_CMD_OP_QUERY_FLOW_COUNTER);
160 MLX5_SET(query_flow_counter_in, in, op_mod, 0);
161 MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id);
162 MLX5_SET(query_flow_counter_in, in, clear, !!clear);
165 MLX5_SET(query_flow_counter_in, in, num_of_counters,
167 MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1);
168 MLX5_SET(query_flow_counter_in, in, mkey, mkey);
169 MLX5_SET64(query_flow_counter_in, in, address,
170 (uint64_t)(uintptr_t)addr);
173 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out,
176 rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in),
180 DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc);
185 stats = MLX5_ADDR_OF(query_flow_counter_out,
186 out, flow_statistics);
187 *pkts = MLX5_GET64(traffic_counter, stats, packets);
188 *bytes = MLX5_GET64(traffic_counter, stats, octets);
197 * Context returned from mlx5 open_device() glue function.
199 * Attributes of the requested mkey.
202 * Pointer to Devx mkey on success, a negative value otherwise and rte_errno
205 struct mlx5_devx_obj *
206 mlx5_devx_cmd_mkey_create(void *ctx,
207 struct mlx5_devx_mkey_attr *attr)
209 struct mlx5_klm *klm_array = attr->klm_array;
210 int klm_num = attr->klm_num;
211 int in_size_dw = MLX5_ST_SZ_DW(create_mkey_in) +
212 (klm_num ? RTE_ALIGN(klm_num, 4) : 0) * MLX5_ST_SZ_DW(klm);
213 uint32_t in[in_size_dw];
214 uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0};
216 struct mlx5_devx_obj *mkey = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mkey),
219 uint32_t translation_size;
225 memset(in, 0, in_size_dw * 4);
226 pgsize = rte_mem_page_size();
227 if (pgsize == (size_t)-1) {
229 DRV_LOG(ERR, "Failed to get page size");
233 MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY);
234 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
237 uint8_t *klm = (uint8_t *)MLX5_ADDR_OF(create_mkey_in, in,
239 translation_size = RTE_ALIGN(klm_num, 4);
240 for (i = 0; i < klm_num; i++) {
241 MLX5_SET(klm, klm, byte_count, klm_array[i].byte_count);
242 MLX5_SET(klm, klm, mkey, klm_array[i].mkey);
243 MLX5_SET64(klm, klm, address, klm_array[i].address);
244 klm += MLX5_ST_SZ_BYTES(klm);
246 for (; i < (int)translation_size; i++) {
247 MLX5_SET(klm, klm, mkey, 0x0);
248 MLX5_SET64(klm, klm, address, 0x0);
249 klm += MLX5_ST_SZ_BYTES(klm);
251 MLX5_SET(mkc, mkc, access_mode_1_0, attr->log_entity_size ?
252 MLX5_MKC_ACCESS_MODE_KLM_FBS :
253 MLX5_MKC_ACCESS_MODE_KLM);
254 MLX5_SET(mkc, mkc, log_page_size, attr->log_entity_size);
256 translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16;
257 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
258 MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize));
260 MLX5_SET(create_mkey_in, in, translations_octword_actual_size,
262 MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id);
263 MLX5_SET(create_mkey_in, in, pg_access, attr->pg_access);
264 MLX5_SET(mkc, mkc, lw, 0x1);
265 MLX5_SET(mkc, mkc, lr, 0x1);
266 MLX5_SET(mkc, mkc, qpn, 0xffffff);
267 MLX5_SET(mkc, mkc, pd, attr->pd);
268 MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF);
269 MLX5_SET(mkc, mkc, umr_en, attr->umr_en);
270 MLX5_SET(mkc, mkc, translations_octword_size, translation_size);
271 MLX5_SET(mkc, mkc, relaxed_ordering_write,
272 attr->relaxed_ordering_write);
273 MLX5_SET(mkc, mkc, relaxed_ordering_read, attr->relaxed_ordering_read);
274 MLX5_SET64(mkc, mkc, start_addr, attr->addr);
275 MLX5_SET64(mkc, mkc, len, attr->size);
276 mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out,
279 DRV_LOG(ERR, "Can't create %sdirect mkey - error %d",
280 klm_num ? "an in" : "a ", errno);
285 mkey->id = MLX5_GET(create_mkey_out, out, mkey_index);
286 mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF);
291 * Get status of devx command response.
292 * Mainly used for asynchronous commands.
295 * The out response buffer.
298 * 0 on success, non-zero value otherwise.
301 mlx5_devx_get_out_command_status(void *out)
307 status = MLX5_GET(query_flow_counter_out, out, status);
309 int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome);
311 DRV_LOG(ERR, "Bad DevX status %x, syndrome = %x", status,
318 * Destroy any object allocated by a Devx API.
321 * Pointer to a general object.
324 * 0 on success, a negative value otherwise.
327 mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj)
333 ret = mlx5_glue->devx_obj_destroy(obj->obj);
339 * Query NIC vport context.
340 * Fills minimal inline attribute.
343 * ibv contexts returned from mlx5dv_open_device.
347 * Attributes device values.
350 * 0 on success, a negative value otherwise.
353 mlx5_devx_cmd_query_nic_vport_context(void *ctx,
355 struct mlx5_hca_attr *attr)
357 uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0};
358 uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0};
360 int status, syndrome, rc;
362 /* Query NIC vport context to determine inline mode. */
363 MLX5_SET(query_nic_vport_context_in, in, opcode,
364 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT);
365 MLX5_SET(query_nic_vport_context_in, in, vport_number, vport);
367 MLX5_SET(query_nic_vport_context_in, in, other_vport, 1);
368 rc = mlx5_glue->devx_general_cmd(ctx,
373 status = MLX5_GET(query_nic_vport_context_out, out, status);
374 syndrome = MLX5_GET(query_nic_vport_context_out, out, syndrome);
376 DRV_LOG(DEBUG, "Failed to query NIC vport context, "
377 "status %x, syndrome = %x", status, syndrome);
380 vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out,
382 attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx,
383 min_wqe_inline_mode);
386 rc = (rc > 0) ? -rc : rc;
391 * Query NIC vDPA attributes.
394 * Context returned from mlx5 open_device() glue function.
395 * @param[out] vdpa_attr
396 * vDPA Attributes structure to fill.
399 mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx,
400 struct mlx5_hca_vdpa_attr *vdpa_attr)
402 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0};
403 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0};
404 void *hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
405 int status, syndrome, rc;
407 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
408 MLX5_SET(query_hca_cap_in, in, op_mod,
409 MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION |
410 MLX5_HCA_CAP_OPMOD_GET_CUR);
411 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
412 status = MLX5_GET(query_hca_cap_out, out, status);
413 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
415 RTE_LOG(DEBUG, PMD, "Failed to query devx VDPA capabilities,"
416 " status %x, syndrome = %x", status, syndrome);
417 vdpa_attr->valid = 0;
419 vdpa_attr->valid = 1;
420 vdpa_attr->desc_tunnel_offload_type =
421 MLX5_GET(virtio_emulation_cap, hcattr,
422 desc_tunnel_offload_type);
423 vdpa_attr->eth_frame_offload_type =
424 MLX5_GET(virtio_emulation_cap, hcattr,
425 eth_frame_offload_type);
426 vdpa_attr->virtio_version_1_0 =
427 MLX5_GET(virtio_emulation_cap, hcattr,
429 vdpa_attr->tso_ipv4 = MLX5_GET(virtio_emulation_cap, hcattr,
431 vdpa_attr->tso_ipv6 = MLX5_GET(virtio_emulation_cap, hcattr,
433 vdpa_attr->tx_csum = MLX5_GET(virtio_emulation_cap, hcattr,
435 vdpa_attr->rx_csum = MLX5_GET(virtio_emulation_cap, hcattr,
437 vdpa_attr->event_mode = MLX5_GET(virtio_emulation_cap, hcattr,
439 vdpa_attr->virtio_queue_type =
440 MLX5_GET(virtio_emulation_cap, hcattr,
442 vdpa_attr->log_doorbell_stride =
443 MLX5_GET(virtio_emulation_cap, hcattr,
444 log_doorbell_stride);
445 vdpa_attr->log_doorbell_bar_size =
446 MLX5_GET(virtio_emulation_cap, hcattr,
447 log_doorbell_bar_size);
448 vdpa_attr->doorbell_bar_offset =
449 MLX5_GET64(virtio_emulation_cap, hcattr,
450 doorbell_bar_offset);
451 vdpa_attr->max_num_virtio_queues =
452 MLX5_GET(virtio_emulation_cap, hcattr,
453 max_num_virtio_queues);
454 vdpa_attr->umems[0].a = MLX5_GET(virtio_emulation_cap, hcattr,
455 umem_1_buffer_param_a);
456 vdpa_attr->umems[0].b = MLX5_GET(virtio_emulation_cap, hcattr,
457 umem_1_buffer_param_b);
458 vdpa_attr->umems[1].a = MLX5_GET(virtio_emulation_cap, hcattr,
459 umem_2_buffer_param_a);
460 vdpa_attr->umems[1].b = MLX5_GET(virtio_emulation_cap, hcattr,
461 umem_2_buffer_param_b);
462 vdpa_attr->umems[2].a = MLX5_GET(virtio_emulation_cap, hcattr,
463 umem_3_buffer_param_a);
464 vdpa_attr->umems[2].b = MLX5_GET(virtio_emulation_cap, hcattr,
465 umem_3_buffer_param_b);
470 mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj,
471 uint32_t ids[], uint32_t num)
473 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
474 uint32_t out[MLX5_ST_SZ_DW(create_flex_parser_out)] = {0};
475 void *hdr = MLX5_ADDR_OF(create_flex_parser_out, in, hdr);
476 void *flex = MLX5_ADDR_OF(create_flex_parser_out, out, flex);
477 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table);
482 if (num > MLX5_GRAPH_NODE_SAMPLE_NUM) {
484 DRV_LOG(ERR, "Too many sample IDs to be fetched.");
487 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
488 MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
489 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
490 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH);
491 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, flex_obj->id);
492 ret = mlx5_glue->devx_obj_query(flex_obj->obj, in, sizeof(in),
496 DRV_LOG(ERR, "Failed to query sample IDs with object %p.",
500 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) {
501 void *s_off = (void *)((char *)sample + i *
502 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample));
505 en = MLX5_GET(parse_graph_flow_match_sample, s_off,
506 flow_match_sample_en);
509 ids[idx++] = MLX5_GET(parse_graph_flow_match_sample, s_off,
510 flow_match_sample_field_id);
514 DRV_LOG(ERR, "Number of sample IDs are not as expected.");
521 struct mlx5_devx_obj *
522 mlx5_devx_cmd_create_flex_parser(void *ctx,
523 struct mlx5_devx_graph_node_attr *data)
525 uint32_t in[MLX5_ST_SZ_DW(create_flex_parser_in)] = {0};
526 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
527 void *hdr = MLX5_ADDR_OF(create_flex_parser_in, in, hdr);
528 void *flex = MLX5_ADDR_OF(create_flex_parser_in, in, flex);
529 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table);
530 void *in_arc = MLX5_ADDR_OF(parse_graph_flex, flex, input_arc);
531 void *out_arc = MLX5_ADDR_OF(parse_graph_flex, flex, output_arc);
532 struct mlx5_devx_obj *parse_flex_obj = mlx5_malloc
533 (MLX5_MEM_ZERO, sizeof(*parse_flex_obj), 0, SOCKET_ID_ANY);
536 if (!parse_flex_obj) {
537 DRV_LOG(ERR, "Failed to allocate flex parser data.");
541 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
542 MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
543 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
544 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH);
545 MLX5_SET(parse_graph_flex, flex, header_length_mode,
546 data->header_length_mode);
547 MLX5_SET(parse_graph_flex, flex, header_length_base_value,
548 data->header_length_base_value);
549 MLX5_SET(parse_graph_flex, flex, header_length_field_offset,
550 data->header_length_field_offset);
551 MLX5_SET(parse_graph_flex, flex, header_length_field_shift,
552 data->header_length_field_shift);
553 MLX5_SET(parse_graph_flex, flex, header_length_field_mask,
554 data->header_length_field_mask);
555 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) {
556 struct mlx5_devx_match_sample_attr *s = &data->sample[i];
557 void *s_off = (void *)((char *)sample + i *
558 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample));
560 if (!s->flow_match_sample_en)
562 MLX5_SET(parse_graph_flow_match_sample, s_off,
563 flow_match_sample_en, !!s->flow_match_sample_en);
564 MLX5_SET(parse_graph_flow_match_sample, s_off,
565 flow_match_sample_field_offset,
566 s->flow_match_sample_field_offset);
567 MLX5_SET(parse_graph_flow_match_sample, s_off,
568 flow_match_sample_offset_mode,
569 s->flow_match_sample_offset_mode);
570 MLX5_SET(parse_graph_flow_match_sample, s_off,
571 flow_match_sample_field_offset_mask,
572 s->flow_match_sample_field_offset_mask);
573 MLX5_SET(parse_graph_flow_match_sample, s_off,
574 flow_match_sample_field_offset_shift,
575 s->flow_match_sample_field_offset_shift);
576 MLX5_SET(parse_graph_flow_match_sample, s_off,
577 flow_match_sample_field_base_offset,
578 s->flow_match_sample_field_base_offset);
579 MLX5_SET(parse_graph_flow_match_sample, s_off,
580 flow_match_sample_tunnel_mode,
581 s->flow_match_sample_tunnel_mode);
583 for (i = 0; i < MLX5_GRAPH_NODE_ARC_NUM; i++) {
584 struct mlx5_devx_graph_arc_attr *ia = &data->in[i];
585 struct mlx5_devx_graph_arc_attr *oa = &data->out[i];
586 void *in_off = (void *)((char *)in_arc + i *
587 MLX5_ST_SZ_BYTES(parse_graph_arc));
588 void *out_off = (void *)((char *)out_arc + i *
589 MLX5_ST_SZ_BYTES(parse_graph_arc));
591 if (ia->arc_parse_graph_node != 0) {
592 MLX5_SET(parse_graph_arc, in_off,
593 compare_condition_value,
594 ia->compare_condition_value);
595 MLX5_SET(parse_graph_arc, in_off, start_inner_tunnel,
596 ia->start_inner_tunnel);
597 MLX5_SET(parse_graph_arc, in_off, arc_parse_graph_node,
598 ia->arc_parse_graph_node);
599 MLX5_SET(parse_graph_arc, in_off,
600 parse_graph_node_handle,
601 ia->parse_graph_node_handle);
603 if (oa->arc_parse_graph_node != 0) {
604 MLX5_SET(parse_graph_arc, out_off,
605 compare_condition_value,
606 oa->compare_condition_value);
607 MLX5_SET(parse_graph_arc, out_off, start_inner_tunnel,
608 oa->start_inner_tunnel);
609 MLX5_SET(parse_graph_arc, out_off, arc_parse_graph_node,
610 oa->arc_parse_graph_node);
611 MLX5_SET(parse_graph_arc, out_off,
612 parse_graph_node_handle,
613 oa->parse_graph_node_handle);
616 parse_flex_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
618 if (!parse_flex_obj->obj) {
620 DRV_LOG(ERR, "Failed to create FLEX PARSE GRAPH object "
622 mlx5_free(parse_flex_obj);
625 parse_flex_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
626 return parse_flex_obj;
630 * Query HCA attributes.
631 * Using those attributes we can check on run time if the device
632 * is having the required capabilities.
635 * Context returned from mlx5 open_device() glue function.
637 * Attributes device values.
640 * 0 on success, a negative value otherwise.
643 mlx5_devx_cmd_query_hca_attr(void *ctx,
644 struct mlx5_hca_attr *attr)
646 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0};
647 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0};
649 int status, syndrome, rc, i;
651 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
652 MLX5_SET(query_hca_cap_in, in, op_mod,
653 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE |
654 MLX5_HCA_CAP_OPMOD_GET_CUR);
656 rc = mlx5_glue->devx_general_cmd(ctx,
657 in, sizeof(in), out, sizeof(out));
660 status = MLX5_GET(query_hca_cap_out, out, status);
661 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
663 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, "
664 "status %x, syndrome = %x", status, syndrome);
667 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
668 attr->flow_counter_bulk_alloc_bitmap =
669 MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc);
670 attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr,
672 attr->log_max_rqt_size = MLX5_GET(cmd_hca_cap, hcattr,
674 attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager);
675 attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin);
676 attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr,
677 log_max_hairpin_queues);
678 attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr,
679 log_max_hairpin_wq_data_sz);
680 attr->log_max_hairpin_num_packets = MLX5_GET
681 (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz);
682 attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id);
683 attr->relaxed_ordering_write = MLX5_GET(cmd_hca_cap, hcattr,
684 relaxed_ordering_write);
685 attr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr,
686 relaxed_ordering_read);
687 attr->access_register_user = MLX5_GET(cmd_hca_cap, hcattr,
688 access_register_user);
689 attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr,
691 attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt);
692 attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr,
693 flex_parser_protocols);
694 attr->max_geneve_tlv_options = MLX5_GET(cmd_hca_cap, hcattr,
695 max_geneve_tlv_options);
696 attr->max_geneve_tlv_option_data_len = MLX5_GET(cmd_hca_cap, hcattr,
697 max_geneve_tlv_option_data_len);
698 attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos);
699 attr->vdpa.valid = !!(MLX5_GET64(cmd_hca_cap, hcattr,
701 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q);
702 attr->vdpa.queue_counters_valid = !!(MLX5_GET64(cmd_hca_cap, hcattr,
704 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS);
705 attr->parse_graph_flex_node = !!(MLX5_GET64(cmd_hca_cap, hcattr,
707 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE);
708 attr->wqe_index_ignore = MLX5_GET(cmd_hca_cap, hcattr,
709 wqe_index_ignore_cap);
710 attr->cross_channel = MLX5_GET(cmd_hca_cap, hcattr, cd);
711 attr->non_wire_sq = MLX5_GET(cmd_hca_cap, hcattr, non_wire_sq);
712 attr->log_max_static_sq_wq = MLX5_GET(cmd_hca_cap, hcattr,
713 log_max_static_sq_wq);
714 attr->num_lag_ports = MLX5_GET(cmd_hca_cap, hcattr, num_lag_ports);
715 attr->dev_freq_khz = MLX5_GET(cmd_hca_cap, hcattr,
716 device_frequency_khz);
717 attr->scatter_fcs_w_decap_disable =
718 MLX5_GET(cmd_hca_cap, hcattr, scatter_fcs_w_decap_disable);
719 attr->roce = MLX5_GET(cmd_hca_cap, hcattr, roce);
720 attr->rq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, rq_ts_format);
721 attr->sq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, sq_ts_format);
722 attr->regex = MLX5_GET(cmd_hca_cap, hcattr, regexp);
723 attr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr,
724 regexp_num_of_engines);
725 attr->flow_hit_aso = !!(MLX5_GET64(cmd_hca_cap, hcattr,
727 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO);
728 attr->geneve_tlv_opt = !!(MLX5_GET64(cmd_hca_cap, hcattr,
730 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT);
731 attr->log_max_cq = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq);
732 attr->log_max_qp = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp);
733 attr->log_max_cq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq_sz);
734 attr->log_max_qp_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp_sz);
735 attr->log_max_mrw_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_mrw_sz);
736 attr->log_max_pd = MLX5_GET(cmd_hca_cap, hcattr, log_max_pd);
737 attr->log_max_srq = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq);
738 attr->log_max_srq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq_sz);
739 attr->reg_c_preserve =
740 MLX5_GET(cmd_hca_cap, hcattr, reg_c_preserve);
741 attr->mmo_dma_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo);
742 attr->mmo_compress_en = MLX5_GET(cmd_hca_cap, hcattr, compress);
743 attr->mmo_decompress_en = MLX5_GET(cmd_hca_cap, hcattr, decompress);
744 attr->compress_min_block_size = MLX5_GET(cmd_hca_cap, hcattr,
745 compress_min_block_size);
746 attr->log_max_mmo_dma = MLX5_GET(cmd_hca_cap, hcattr, log_dma_mmo_size);
747 attr->log_max_mmo_compress = MLX5_GET(cmd_hca_cap, hcattr,
748 log_compress_mmo_size);
749 attr->log_max_mmo_decompress = MLX5_GET(cmd_hca_cap, hcattr,
750 log_decompress_mmo_size);
751 attr->cqe_compression = MLX5_GET(cmd_hca_cap, hcattr, cqe_compression);
752 attr->mini_cqe_resp_flow_tag = MLX5_GET(cmd_hca_cap, hcattr,
753 mini_cqe_resp_flow_tag);
754 attr->mini_cqe_resp_l3_l4_tag = MLX5_GET(cmd_hca_cap, hcattr,
755 mini_cqe_resp_l3_l4_tag);
756 attr->umr_indirect_mkey_disabled =
757 MLX5_GET(cmd_hca_cap, hcattr, umr_indirect_mkey_disabled);
758 attr->umr_modify_entity_size_disabled =
759 MLX5_GET(cmd_hca_cap, hcattr, umr_modify_entity_size_disabled);
761 MLX5_SET(query_hca_cap_in, in, op_mod,
762 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP |
763 MLX5_HCA_CAP_OPMOD_GET_CUR);
764 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in),
769 DRV_LOG(DEBUG, "Failed to query devx QOS capabilities,"
770 " status %x, syndrome = %x", status, syndrome);
773 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
774 attr->qos.flow_meter_old =
775 MLX5_GET(qos_cap, hcattr, flow_meter_old);
776 attr->qos.log_max_flow_meter =
777 MLX5_GET(qos_cap, hcattr, log_max_flow_meter);
778 attr->qos.flow_meter_reg_c_ids =
779 MLX5_GET(qos_cap, hcattr, flow_meter_reg_id);
780 attr->qos.flow_meter =
781 MLX5_GET(qos_cap, hcattr, flow_meter);
782 attr->qos.packet_pacing =
783 MLX5_GET(qos_cap, hcattr, packet_pacing);
784 attr->qos.wqe_rate_pp =
785 MLX5_GET(qos_cap, hcattr, wqe_rate_pp);
787 if (attr->vdpa.valid)
788 mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa);
789 if (!attr->eth_net_offloads)
792 /* Query Flow Sampler Capability From FLow Table Properties Layout. */
793 memset(in, 0, sizeof(in));
794 memset(out, 0, sizeof(out));
795 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
796 MLX5_SET(query_hca_cap_in, in, op_mod,
797 MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE |
798 MLX5_HCA_CAP_OPMOD_GET_CUR);
800 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
803 status = MLX5_GET(query_hca_cap_out, out, status);
804 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
806 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, "
807 "status %x, syndrome = %x", status, syndrome);
808 attr->log_max_ft_sampler_num = 0;
811 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
812 attr->log_max_ft_sampler_num =
813 MLX5_GET(flow_table_nic_cap,
814 hcattr, flow_table_properties.log_max_ft_sampler_num);
816 /* Query HCA offloads for Ethernet protocol. */
817 memset(in, 0, sizeof(in));
818 memset(out, 0, sizeof(out));
819 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
820 MLX5_SET(query_hca_cap_in, in, op_mod,
821 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS |
822 MLX5_HCA_CAP_OPMOD_GET_CUR);
824 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
826 attr->eth_net_offloads = 0;
829 status = MLX5_GET(query_hca_cap_out, out, status);
830 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
832 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, "
833 "status %x, syndrome = %x", status, syndrome);
834 attr->eth_net_offloads = 0;
837 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
838 attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps,
839 hcattr, wqe_vlan_insert);
840 attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr,
842 attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps,
843 hcattr, tunnel_lro_gre);
844 attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps,
845 hcattr, tunnel_lro_vxlan);
846 attr->lro_max_msg_sz_mode = MLX5_GET
847 (per_protocol_networking_offload_caps,
848 hcattr, lro_max_msg_sz_mode);
849 for (i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) {
850 attr->lro_timer_supported_periods[i] =
851 MLX5_GET(per_protocol_networking_offload_caps, hcattr,
852 lro_timer_supported_periods[i]);
854 attr->lro_min_mss_size = MLX5_GET(per_protocol_networking_offload_caps,
855 hcattr, lro_min_mss_size);
856 attr->tunnel_stateless_geneve_rx =
857 MLX5_GET(per_protocol_networking_offload_caps,
858 hcattr, tunnel_stateless_geneve_rx);
859 attr->geneve_max_opt_len =
860 MLX5_GET(per_protocol_networking_offload_caps,
861 hcattr, max_geneve_opt_len);
862 attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps,
863 hcattr, wqe_inline_mode);
864 attr->tunnel_stateless_gtp = MLX5_GET
865 (per_protocol_networking_offload_caps,
866 hcattr, tunnel_stateless_gtp);
867 attr->rss_ind_tbl_cap = MLX5_GET
868 (per_protocol_networking_offload_caps,
869 hcattr, rss_ind_tbl_cap);
870 /* Query HCA attribute for ROCE. */
872 memset(in, 0, sizeof(in));
873 memset(out, 0, sizeof(out));
874 MLX5_SET(query_hca_cap_in, in, opcode,
875 MLX5_CMD_OP_QUERY_HCA_CAP);
876 MLX5_SET(query_hca_cap_in, in, op_mod,
877 MLX5_GET_HCA_CAP_OP_MOD_ROCE |
878 MLX5_HCA_CAP_OPMOD_GET_CUR);
879 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in),
883 status = MLX5_GET(query_hca_cap_out, out, status);
884 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
887 "Failed to query devx HCA ROCE capabilities, "
888 "status %x, syndrome = %x", status, syndrome);
891 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
892 attr->qp_ts_format = MLX5_GET(roce_caps, hcattr, qp_ts_format);
894 if (attr->eth_virt &&
895 attr->wqe_inline_mode == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT) {
896 rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr);
904 rc = (rc > 0) ? -rc : rc;
909 * Query TIS transport domain from QP verbs object using DevX API.
912 * Pointer to verbs QP returned by ibv_create_qp .
914 * TIS number of TIS to query.
916 * Pointer to TIS transport domain variable, to be set by the routine.
919 * 0 on success, a negative value otherwise.
922 mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num,
925 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
926 uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0};
927 uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0};
931 MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS);
932 MLX5_SET(query_tis_in, in, tisn, tis_num);
933 rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out));
935 DRV_LOG(ERR, "Failed to query QP using DevX");
938 tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context);
939 *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain);
950 * Fill WQ data for DevX API command.
951 * Utility function for use when creating DevX objects containing a WQ.
954 * Pointer to WQ context to fill with data.
955 * @param [in] wq_attr
956 * Pointer to WQ attributes structure to fill in WQ context.
959 devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr)
961 MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type);
962 MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature);
963 MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode);
964 MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave);
965 MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge);
966 MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size);
967 MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset);
968 MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm);
969 MLX5_SET(wq, wq_ctx, pd, wq_attr->pd);
970 MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page);
971 MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr);
972 MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter);
973 MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter);
974 MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride);
975 if (wq_attr->log_wq_pg_sz > MLX5_ADAPTER_PAGE_SHIFT)
976 MLX5_SET(wq, wq_ctx, log_wq_pg_sz,
977 wq_attr->log_wq_pg_sz - MLX5_ADAPTER_PAGE_SHIFT);
978 MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz);
979 MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid);
980 MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid);
981 MLX5_SET(wq, wq_ctx, log_hairpin_num_packets,
982 wq_attr->log_hairpin_num_packets);
983 MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz);
984 MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides,
985 wq_attr->single_wqe_log_num_of_strides);
986 MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en);
987 MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes,
988 wq_attr->single_stride_log_num_of_bytes);
989 MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id);
990 MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id);
991 MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset);
995 * Create RQ using DevX API.
998 * Context returned from mlx5 open_device() glue function.
999 * @param [in] rq_attr
1000 * Pointer to create RQ attributes structure.
1001 * @param [in] socket
1002 * CPU socket ID for allocations.
1005 * The DevX object created, NULL otherwise and rte_errno is set.
1007 struct mlx5_devx_obj *
1008 mlx5_devx_cmd_create_rq(void *ctx,
1009 struct mlx5_devx_create_rq_attr *rq_attr,
1012 uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0};
1013 uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0};
1014 void *rq_ctx, *wq_ctx;
1015 struct mlx5_devx_wq_attr *wq_attr;
1016 struct mlx5_devx_obj *rq = NULL;
1018 rq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rq), 0, socket);
1020 DRV_LOG(ERR, "Failed to allocate RQ data");
1024 MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ);
1025 rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx);
1026 MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky);
1027 MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en);
1028 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);
1029 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);
1030 MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type);
1031 MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
1032 MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en);
1033 MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin);
1034 MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index);
1035 MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn);
1036 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
1037 MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn);
1038 MLX5_SET(sqc, rq_ctx, ts_format, rq_attr->ts_format);
1039 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);
1040 wq_attr = &rq_attr->wq_attr;
1041 devx_cmd_fill_wq_data(wq_ctx, wq_attr);
1042 rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1045 DRV_LOG(ERR, "Failed to create RQ using DevX");
1050 rq->id = MLX5_GET(create_rq_out, out, rqn);
1055 * Modify RQ using DevX API.
1058 * Pointer to RQ object structure.
1059 * @param [in] rq_attr
1060 * Pointer to modify RQ attributes structure.
1063 * 0 on success, a negative errno value otherwise and rte_errno is set.
1066 mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,
1067 struct mlx5_devx_modify_rq_attr *rq_attr)
1069 uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0};
1070 uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0};
1071 void *rq_ctx, *wq_ctx;
1074 MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ);
1075 MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state);
1076 MLX5_SET(modify_rq_in, in, rqn, rq->id);
1077 MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask);
1078 rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1079 MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
1080 if (rq_attr->modify_bitmask &
1081 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS)
1082 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);
1083 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD)
1084 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);
1085 if (rq_attr->modify_bitmask &
1086 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID)
1087 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
1088 MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq);
1089 MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca);
1090 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) {
1091 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);
1092 MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm);
1094 ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in),
1097 DRV_LOG(ERR, "Failed to modify RQ using DevX");
1105 * Create TIR using DevX API.
1108 * Context returned from mlx5 open_device() glue function.
1109 * @param [in] tir_attr
1110 * Pointer to TIR attributes structure.
1113 * The DevX object created, NULL otherwise and rte_errno is set.
1115 struct mlx5_devx_obj *
1116 mlx5_devx_cmd_create_tir(void *ctx,
1117 struct mlx5_devx_tir_attr *tir_attr)
1119 uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
1120 uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0};
1121 void *tir_ctx, *outer, *inner, *rss_key;
1122 struct mlx5_devx_obj *tir = NULL;
1124 tir = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tir), 0, SOCKET_ID_ANY);
1126 DRV_LOG(ERR, "Failed to allocate TIR data");
1130 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR);
1131 tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx);
1132 MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type);
1133 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs,
1134 tir_attr->lro_timeout_period_usecs);
1135 MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask);
1136 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz);
1137 MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn);
1138 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric);
1139 MLX5_SET(tirc, tir_ctx, tunneled_offload_en,
1140 tir_attr->tunneled_offload_en);
1141 MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table);
1142 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn);
1143 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block);
1144 MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain);
1145 rss_key = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_toeplitz_key);
1146 memcpy(rss_key, tir_attr->rx_hash_toeplitz_key, MLX5_RSS_HASH_KEY_LEN);
1147 outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer);
1148 MLX5_SET(rx_hash_field_select, outer, l3_prot_type,
1149 tir_attr->rx_hash_field_selector_outer.l3_prot_type);
1150 MLX5_SET(rx_hash_field_select, outer, l4_prot_type,
1151 tir_attr->rx_hash_field_selector_outer.l4_prot_type);
1152 MLX5_SET(rx_hash_field_select, outer, selected_fields,
1153 tir_attr->rx_hash_field_selector_outer.selected_fields);
1154 inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner);
1155 MLX5_SET(rx_hash_field_select, inner, l3_prot_type,
1156 tir_attr->rx_hash_field_selector_inner.l3_prot_type);
1157 MLX5_SET(rx_hash_field_select, inner, l4_prot_type,
1158 tir_attr->rx_hash_field_selector_inner.l4_prot_type);
1159 MLX5_SET(rx_hash_field_select, inner, selected_fields,
1160 tir_attr->rx_hash_field_selector_inner.selected_fields);
1161 tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1164 DRV_LOG(ERR, "Failed to create TIR using DevX");
1169 tir->id = MLX5_GET(create_tir_out, out, tirn);
1174 * Modify TIR using DevX API.
1177 * Pointer to TIR DevX object structure.
1178 * @param [in] modify_tir_attr
1179 * Pointer to TIR modification attributes structure.
1182 * 0 on success, a negative errno value otherwise and rte_errno is set.
1185 mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir,
1186 struct mlx5_devx_modify_tir_attr *modify_tir_attr)
1188 struct mlx5_devx_tir_attr *tir_attr = &modify_tir_attr->tir;
1189 uint32_t in[MLX5_ST_SZ_DW(modify_tir_in)] = {0};
1190 uint32_t out[MLX5_ST_SZ_DW(modify_tir_out)] = {0};
1194 MLX5_SET(modify_tir_in, in, opcode, MLX5_CMD_OP_MODIFY_TIR);
1195 MLX5_SET(modify_tir_in, in, tirn, modify_tir_attr->tirn);
1196 MLX5_SET64(modify_tir_in, in, modify_bitmask,
1197 modify_tir_attr->modify_bitmask);
1198 tir_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1199 if (modify_tir_attr->modify_bitmask &
1200 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO) {
1201 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs,
1202 tir_attr->lro_timeout_period_usecs);
1203 MLX5_SET(tirc, tir_ctx, lro_enable_mask,
1204 tir_attr->lro_enable_mask);
1205 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz,
1206 tir_attr->lro_max_msg_sz);
1208 if (modify_tir_attr->modify_bitmask &
1209 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE)
1210 MLX5_SET(tirc, tir_ctx, indirect_table,
1211 tir_attr->indirect_table);
1212 if (modify_tir_attr->modify_bitmask &
1213 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH) {
1215 void *outer, *inner;
1217 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric,
1218 tir_attr->rx_hash_symmetric);
1219 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn);
1220 for (i = 0; i < 10; i++) {
1221 MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i],
1222 tir_attr->rx_hash_toeplitz_key[i]);
1224 outer = MLX5_ADDR_OF(tirc, tir_ctx,
1225 rx_hash_field_selector_outer);
1226 MLX5_SET(rx_hash_field_select, outer, l3_prot_type,
1227 tir_attr->rx_hash_field_selector_outer.l3_prot_type);
1228 MLX5_SET(rx_hash_field_select, outer, l4_prot_type,
1229 tir_attr->rx_hash_field_selector_outer.l4_prot_type);
1231 (rx_hash_field_select, outer, selected_fields,
1232 tir_attr->rx_hash_field_selector_outer.selected_fields);
1233 inner = MLX5_ADDR_OF(tirc, tir_ctx,
1234 rx_hash_field_selector_inner);
1235 MLX5_SET(rx_hash_field_select, inner, l3_prot_type,
1236 tir_attr->rx_hash_field_selector_inner.l3_prot_type);
1237 MLX5_SET(rx_hash_field_select, inner, l4_prot_type,
1238 tir_attr->rx_hash_field_selector_inner.l4_prot_type);
1240 (rx_hash_field_select, inner, selected_fields,
1241 tir_attr->rx_hash_field_selector_inner.selected_fields);
1243 if (modify_tir_attr->modify_bitmask &
1244 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN) {
1245 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block);
1247 ret = mlx5_glue->devx_obj_modify(tir->obj, in, sizeof(in),
1250 DRV_LOG(ERR, "Failed to modify TIR using DevX");
1258 * Create RQT using DevX API.
1261 * Context returned from mlx5 open_device() glue function.
1262 * @param [in] rqt_attr
1263 * Pointer to RQT attributes structure.
1266 * The DevX object created, NULL otherwise and rte_errno is set.
1268 struct mlx5_devx_obj *
1269 mlx5_devx_cmd_create_rqt(void *ctx,
1270 struct mlx5_devx_rqt_attr *rqt_attr)
1272 uint32_t *in = NULL;
1273 uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) +
1274 rqt_attr->rqt_actual_size * sizeof(uint32_t);
1275 uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0};
1277 struct mlx5_devx_obj *rqt = NULL;
1280 in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY);
1282 DRV_LOG(ERR, "Failed to allocate RQT IN data");
1286 rqt = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt), 0, SOCKET_ID_ANY);
1288 DRV_LOG(ERR, "Failed to allocate RQT data");
1293 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
1294 rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1295 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type);
1296 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size);
1297 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size);
1298 for (i = 0; i < rqt_attr->rqt_actual_size; i++)
1299 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]);
1300 rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out));
1303 DRV_LOG(ERR, "Failed to create RQT using DevX");
1308 rqt->id = MLX5_GET(create_rqt_out, out, rqtn);
1313 * Modify RQT using DevX API.
1316 * Pointer to RQT DevX object structure.
1317 * @param [in] rqt_attr
1318 * Pointer to RQT attributes structure.
1321 * 0 on success, a negative errno value otherwise and rte_errno is set.
1324 mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt,
1325 struct mlx5_devx_rqt_attr *rqt_attr)
1327 uint32_t inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) +
1328 rqt_attr->rqt_actual_size * sizeof(uint32_t);
1329 uint32_t out[MLX5_ST_SZ_DW(modify_rqt_out)] = {0};
1330 uint32_t *in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY);
1336 DRV_LOG(ERR, "Failed to allocate RQT modify IN data.");
1340 MLX5_SET(modify_rqt_in, in, opcode, MLX5_CMD_OP_MODIFY_RQT);
1341 MLX5_SET(modify_rqt_in, in, rqtn, rqt->id);
1342 MLX5_SET64(modify_rqt_in, in, modify_bitmask, 0x1);
1343 rqt_ctx = MLX5_ADDR_OF(modify_rqt_in, in, rqt_context);
1344 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type);
1345 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size);
1346 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size);
1347 for (i = 0; i < rqt_attr->rqt_actual_size; i++)
1348 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]);
1349 ret = mlx5_glue->devx_obj_modify(rqt->obj, in, inlen, out, sizeof(out));
1352 DRV_LOG(ERR, "Failed to modify RQT using DevX.");
1360 * Create SQ using DevX API.
1363 * Context returned from mlx5 open_device() glue function.
1364 * @param [in] sq_attr
1365 * Pointer to SQ attributes structure.
1366 * @param [in] socket
1367 * CPU socket ID for allocations.
1370 * The DevX object created, NULL otherwise and rte_errno is set.
1372 struct mlx5_devx_obj *
1373 mlx5_devx_cmd_create_sq(void *ctx,
1374 struct mlx5_devx_create_sq_attr *sq_attr)
1376 uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0};
1377 uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0};
1380 struct mlx5_devx_wq_attr *wq_attr;
1381 struct mlx5_devx_obj *sq = NULL;
1383 sq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sq), 0, SOCKET_ID_ANY);
1385 DRV_LOG(ERR, "Failed to allocate SQ data");
1389 MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ);
1390 sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx);
1391 MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky);
1392 MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master);
1393 MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre);
1394 MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en);
1395 MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe,
1396 sq_attr->allow_multi_pkt_send_wqe);
1397 MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode,
1398 sq_attr->min_wqe_inline_mode);
1399 MLX5_SET(sqc, sq_ctx, state, sq_attr->state);
1400 MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr);
1401 MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp);
1402 MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin);
1403 MLX5_SET(sqc, sq_ctx, non_wire, sq_attr->non_wire);
1404 MLX5_SET(sqc, sq_ctx, static_sq_wq, sq_attr->static_sq_wq);
1405 MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index);
1406 MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn);
1407 MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index,
1408 sq_attr->packet_pacing_rate_limit_index);
1409 MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz);
1410 MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num);
1411 MLX5_SET(sqc, sq_ctx, ts_format, sq_attr->ts_format);
1412 wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq);
1413 wq_attr = &sq_attr->wq_attr;
1414 devx_cmd_fill_wq_data(wq_ctx, wq_attr);
1415 sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1418 DRV_LOG(ERR, "Failed to create SQ using DevX");
1423 sq->id = MLX5_GET(create_sq_out, out, sqn);
1428 * Modify SQ using DevX API.
1431 * Pointer to SQ object structure.
1432 * @param [in] sq_attr
1433 * Pointer to SQ attributes structure.
1436 * 0 on success, a negative errno value otherwise and rte_errno is set.
1439 mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq,
1440 struct mlx5_devx_modify_sq_attr *sq_attr)
1442 uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0};
1443 uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0};
1447 MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ);
1448 MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state);
1449 MLX5_SET(modify_sq_in, in, sqn, sq->id);
1450 sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1451 MLX5_SET(sqc, sq_ctx, state, sq_attr->state);
1452 MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq);
1453 MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca);
1454 ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in),
1457 DRV_LOG(ERR, "Failed to modify SQ using DevX");
1465 * Create TIS using DevX API.
1468 * Context returned from mlx5 open_device() glue function.
1469 * @param [in] tis_attr
1470 * Pointer to TIS attributes structure.
1473 * The DevX object created, NULL otherwise and rte_errno is set.
1475 struct mlx5_devx_obj *
1476 mlx5_devx_cmd_create_tis(void *ctx,
1477 struct mlx5_devx_tis_attr *tis_attr)
1479 uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
1480 uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0};
1481 struct mlx5_devx_obj *tis = NULL;
1484 tis = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tis), 0, SOCKET_ID_ANY);
1486 DRV_LOG(ERR, "Failed to allocate TIS object");
1490 MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS);
1491 tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx);
1492 MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity,
1493 tis_attr->strict_lag_tx_port_affinity);
1494 MLX5_SET(tisc, tis_ctx, lag_tx_port_affinity,
1495 tis_attr->lag_tx_port_affinity);
1496 MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio);
1497 MLX5_SET(tisc, tis_ctx, transport_domain,
1498 tis_attr->transport_domain);
1499 tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1502 DRV_LOG(ERR, "Failed to create TIS using DevX");
1507 tis->id = MLX5_GET(create_tis_out, out, tisn);
1512 * Create transport domain using DevX API.
1515 * Context returned from mlx5 open_device() glue function.
1517 * The DevX object created, NULL otherwise and rte_errno is set.
1519 struct mlx5_devx_obj *
1520 mlx5_devx_cmd_create_td(void *ctx)
1522 uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0};
1523 uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0};
1524 struct mlx5_devx_obj *td = NULL;
1526 td = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*td), 0, SOCKET_ID_ANY);
1528 DRV_LOG(ERR, "Failed to allocate TD object");
1532 MLX5_SET(alloc_transport_domain_in, in, opcode,
1533 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN);
1534 td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1537 DRV_LOG(ERR, "Failed to create TIS using DevX");
1542 td->id = MLX5_GET(alloc_transport_domain_out, out,
1548 * Dump all flows to file.
1550 * @param[in] fdb_domain
1552 * @param[in] rx_domain
1554 * @param[in] tx_domain
1557 * Pointer to file stream.
1560 * 0 on success, a nagative value otherwise.
1563 mlx5_devx_cmd_flow_dump(void *fdb_domain __rte_unused,
1564 void *rx_domain __rte_unused,
1565 void *tx_domain __rte_unused, FILE *file __rte_unused)
1569 #ifdef HAVE_MLX5_DR_FLOW_DUMP
1571 ret = mlx5_glue->dr_dump_domain(file, fdb_domain);
1575 MLX5_ASSERT(rx_domain);
1576 ret = mlx5_glue->dr_dump_domain(file, rx_domain);
1579 MLX5_ASSERT(tx_domain);
1580 ret = mlx5_glue->dr_dump_domain(file, tx_domain);
1588 * Create CQ using DevX API.
1591 * Context returned from mlx5 open_device() glue function.
1593 * Pointer to CQ attributes structure.
1596 * The DevX object created, NULL otherwise and rte_errno is set.
1598 struct mlx5_devx_obj *
1599 mlx5_devx_cmd_create_cq(void *ctx, struct mlx5_devx_cq_attr *attr)
1601 uint32_t in[MLX5_ST_SZ_DW(create_cq_in)] = {0};
1602 uint32_t out[MLX5_ST_SZ_DW(create_cq_out)] = {0};
1603 struct mlx5_devx_obj *cq_obj = mlx5_malloc(MLX5_MEM_ZERO,
1606 void *cqctx = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1609 DRV_LOG(ERR, "Failed to allocate CQ object memory.");
1613 MLX5_SET(create_cq_in, in, opcode, MLX5_CMD_OP_CREATE_CQ);
1614 if (attr->db_umem_valid) {
1615 MLX5_SET(cqc, cqctx, dbr_umem_valid, attr->db_umem_valid);
1616 MLX5_SET(cqc, cqctx, dbr_umem_id, attr->db_umem_id);
1617 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_umem_offset);
1619 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_addr);
1621 MLX5_SET(cqc, cqctx, cqe_sz, (RTE_CACHE_LINE_SIZE == 128) ?
1622 MLX5_CQE_SIZE_128B : MLX5_CQE_SIZE_64B);
1623 MLX5_SET(cqc, cqctx, cc, attr->use_first_only);
1624 MLX5_SET(cqc, cqctx, oi, attr->overrun_ignore);
1625 MLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size);
1626 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT)
1627 MLX5_SET(cqc, cqctx, log_page_size,
1628 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT);
1629 MLX5_SET(cqc, cqctx, c_eqn, attr->eqn);
1630 MLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id);
1631 MLX5_SET(cqc, cqctx, cqe_comp_en, !!attr->cqe_comp_en);
1632 MLX5_SET(cqc, cqctx, mini_cqe_res_format, attr->mini_cqe_res_format);
1633 MLX5_SET(cqc, cqctx, mini_cqe_res_format_ext,
1634 attr->mini_cqe_res_format_ext);
1635 if (attr->q_umem_valid) {
1636 MLX5_SET(create_cq_in, in, cq_umem_valid, attr->q_umem_valid);
1637 MLX5_SET(create_cq_in, in, cq_umem_id, attr->q_umem_id);
1638 MLX5_SET64(create_cq_in, in, cq_umem_offset,
1639 attr->q_umem_offset);
1641 cq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
1645 DRV_LOG(ERR, "Failed to create CQ using DevX errno=%d.", errno);
1649 cq_obj->id = MLX5_GET(create_cq_out, out, cqn);
1654 * Create VIRTQ using DevX API.
1657 * Context returned from mlx5 open_device() glue function.
1659 * Pointer to VIRTQ attributes structure.
1662 * The DevX object created, NULL otherwise and rte_errno is set.
1664 struct mlx5_devx_obj *
1665 mlx5_devx_cmd_create_virtq(void *ctx,
1666 struct mlx5_devx_virtq_attr *attr)
1668 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0};
1669 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
1670 struct mlx5_devx_obj *virtq_obj = mlx5_malloc(MLX5_MEM_ZERO,
1673 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq);
1674 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr);
1675 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context);
1678 DRV_LOG(ERR, "Failed to allocate virtq data.");
1682 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
1683 MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
1684 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
1685 MLX5_GENERAL_OBJ_TYPE_VIRTQ);
1686 MLX5_SET16(virtio_net_q, virtq, hw_available_index,
1687 attr->hw_available_index);
1688 MLX5_SET16(virtio_net_q, virtq, hw_used_index, attr->hw_used_index);
1689 MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4);
1690 MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6);
1691 MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum);
1692 MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum);
1693 MLX5_SET16(virtio_q, virtctx, virtio_version_1_0,
1694 attr->virtio_version_1_0);
1695 MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode);
1696 MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id);
1697 MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr);
1698 MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr);
1699 MLX5_SET64(virtio_q, virtctx, available_addr, attr->available_addr);
1700 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index);
1701 MLX5_SET16(virtio_q, virtctx, queue_size, attr->q_size);
1702 MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey);
1703 MLX5_SET(virtio_q, virtctx, umem_1_id, attr->umems[0].id);
1704 MLX5_SET(virtio_q, virtctx, umem_1_size, attr->umems[0].size);
1705 MLX5_SET64(virtio_q, virtctx, umem_1_offset, attr->umems[0].offset);
1706 MLX5_SET(virtio_q, virtctx, umem_2_id, attr->umems[1].id);
1707 MLX5_SET(virtio_q, virtctx, umem_2_size, attr->umems[1].size);
1708 MLX5_SET64(virtio_q, virtctx, umem_2_offset, attr->umems[1].offset);
1709 MLX5_SET(virtio_q, virtctx, umem_3_id, attr->umems[2].id);
1710 MLX5_SET(virtio_q, virtctx, umem_3_size, attr->umems[2].size);
1711 MLX5_SET64(virtio_q, virtctx, umem_3_offset, attr->umems[2].offset);
1712 MLX5_SET(virtio_q, virtctx, counter_set_id, attr->counters_obj_id);
1713 MLX5_SET(virtio_q, virtctx, pd, attr->pd);
1714 MLX5_SET(virtio_q, virtctx, queue_period_mode, attr->hw_latency_mode);
1715 MLX5_SET(virtio_q, virtctx, queue_period_us, attr->hw_max_latency_us);
1716 MLX5_SET(virtio_q, virtctx, queue_max_count, attr->hw_max_pending_comp);
1717 MLX5_SET(virtio_net_q, virtq, tisn_or_qpn, attr->tis_id);
1718 virtq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
1720 if (!virtq_obj->obj) {
1722 DRV_LOG(ERR, "Failed to create VIRTQ Obj using DevX.");
1723 mlx5_free(virtq_obj);
1726 virtq_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
1731 * Modify VIRTQ using DevX API.
1733 * @param[in] virtq_obj
1734 * Pointer to virtq object structure.
1736 * Pointer to modify virtq attributes structure.
1739 * 0 on success, a negative errno value otherwise and rte_errno is set.
1742 mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj,
1743 struct mlx5_devx_virtq_attr *attr)
1745 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0};
1746 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
1747 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq);
1748 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr);
1749 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context);
1752 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
1753 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT);
1754 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
1755 MLX5_GENERAL_OBJ_TYPE_VIRTQ);
1756 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id);
1757 MLX5_SET64(virtio_net_q, virtq, modify_field_select, attr->type);
1758 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index);
1759 switch (attr->type) {
1760 case MLX5_VIRTQ_MODIFY_TYPE_STATE:
1761 MLX5_SET16(virtio_net_q, virtq, state, attr->state);
1763 case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS:
1764 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_mkey,
1765 attr->dirty_bitmap_mkey);
1766 MLX5_SET64(virtio_net_q, virtq, dirty_bitmap_addr,
1767 attr->dirty_bitmap_addr);
1768 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_size,
1769 attr->dirty_bitmap_size);
1771 case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE:
1772 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_dump_enable,
1773 attr->dirty_bitmap_dump_enable);
1779 ret = mlx5_glue->devx_obj_modify(virtq_obj->obj, in, sizeof(in),
1782 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX.");
1790 * Query VIRTQ using DevX API.
1792 * @param[in] virtq_obj
1793 * Pointer to virtq object structure.
1794 * @param [in/out] attr
1795 * Pointer to virtq attributes structure.
1798 * 0 on success, a negative errno value otherwise and rte_errno is set.
1801 mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj,
1802 struct mlx5_devx_virtq_attr *attr)
1804 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
1805 uint32_t out[MLX5_ST_SZ_DW(query_virtq_out)] = {0};
1806 void *hdr = MLX5_ADDR_OF(query_virtq_out, in, hdr);
1807 void *virtq = MLX5_ADDR_OF(query_virtq_out, out, virtq);
1810 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
1811 MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
1812 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
1813 MLX5_GENERAL_OBJ_TYPE_VIRTQ);
1814 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id);
1815 ret = mlx5_glue->devx_obj_query(virtq_obj->obj, in, sizeof(in),
1818 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX.");
1822 attr->hw_available_index = MLX5_GET16(virtio_net_q, virtq,
1823 hw_available_index);
1824 attr->hw_used_index = MLX5_GET16(virtio_net_q, virtq, hw_used_index);
1825 attr->state = MLX5_GET16(virtio_net_q, virtq, state);
1826 attr->error_type = MLX5_GET16(virtio_net_q, virtq,
1827 virtio_q_context.error_type);
1832 * Create QP using DevX API.
1835 * Context returned from mlx5 open_device() glue function.
1837 * Pointer to QP attributes structure.
1840 * The DevX object created, NULL otherwise and rte_errno is set.
1842 struct mlx5_devx_obj *
1843 mlx5_devx_cmd_create_qp(void *ctx,
1844 struct mlx5_devx_qp_attr *attr)
1846 uint32_t in[MLX5_ST_SZ_DW(create_qp_in)] = {0};
1847 uint32_t out[MLX5_ST_SZ_DW(create_qp_out)] = {0};
1848 struct mlx5_devx_obj *qp_obj = mlx5_malloc(MLX5_MEM_ZERO,
1851 void *qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1854 DRV_LOG(ERR, "Failed to allocate QP data.");
1858 MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP);
1859 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC);
1860 MLX5_SET(qpc, qpc, pd, attr->pd);
1861 MLX5_SET(qpc, qpc, ts_format, attr->ts_format);
1862 if (attr->uar_index) {
1863 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
1864 MLX5_SET(qpc, qpc, uar_page, attr->uar_index);
1865 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT)
1866 MLX5_SET(qpc, qpc, log_page_size,
1867 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT);
1868 if (attr->sq_size) {
1869 MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->sq_size));
1870 MLX5_SET(qpc, qpc, cqn_snd, attr->cqn);
1871 MLX5_SET(qpc, qpc, log_sq_size,
1872 rte_log2_u32(attr->sq_size));
1874 MLX5_SET(qpc, qpc, no_sq, 1);
1876 if (attr->rq_size) {
1877 MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->rq_size));
1878 MLX5_SET(qpc, qpc, cqn_rcv, attr->cqn);
1879 MLX5_SET(qpc, qpc, log_rq_stride, attr->log_rq_stride -
1880 MLX5_LOG_RQ_STRIDE_SHIFT);
1881 MLX5_SET(qpc, qpc, log_rq_size,
1882 rte_log2_u32(attr->rq_size));
1883 MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ);
1885 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ);
1887 if (attr->dbr_umem_valid) {
1888 MLX5_SET(qpc, qpc, dbr_umem_valid,
1889 attr->dbr_umem_valid);
1890 MLX5_SET(qpc, qpc, dbr_umem_id, attr->dbr_umem_id);
1892 MLX5_SET64(qpc, qpc, dbr_addr, attr->dbr_address);
1893 MLX5_SET64(create_qp_in, in, wq_umem_offset,
1894 attr->wq_umem_offset);
1895 MLX5_SET(create_qp_in, in, wq_umem_id, attr->wq_umem_id);
1896 MLX5_SET(create_qp_in, in, wq_umem_valid, 1);
1898 /* Special QP to be managed by FW - no SQ\RQ\CQ\UAR\DB rec. */
1899 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ);
1900 MLX5_SET(qpc, qpc, no_sq, 1);
1902 qp_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
1906 DRV_LOG(ERR, "Failed to create QP Obj using DevX.");
1910 qp_obj->id = MLX5_GET(create_qp_out, out, qpn);
1915 * Modify QP using DevX API.
1916 * Currently supports only force loop-back QP.
1919 * Pointer to QP object structure.
1920 * @param [in] qp_st_mod_op
1921 * The QP state modification operation.
1922 * @param [in] remote_qp_id
1923 * The remote QP ID for MLX5_CMD_OP_INIT2RTR_QP operation.
1926 * 0 on success, a negative errno value otherwise and rte_errno is set.
1929 mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op,
1930 uint32_t remote_qp_id)
1933 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)];
1934 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)];
1935 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)];
1938 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)];
1939 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)];
1940 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)];
1945 unsigned int outlen;
1947 memset(&in, 0, sizeof(in));
1948 memset(&out, 0, sizeof(out));
1949 MLX5_SET(rst2init_qp_in, &in, opcode, qp_st_mod_op);
1950 switch (qp_st_mod_op) {
1951 case MLX5_CMD_OP_RST2INIT_QP:
1952 MLX5_SET(rst2init_qp_in, &in, qpn, qp->id);
1953 qpc = MLX5_ADDR_OF(rst2init_qp_in, &in, qpc);
1954 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1);
1955 MLX5_SET(qpc, qpc, rre, 1);
1956 MLX5_SET(qpc, qpc, rwe, 1);
1957 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
1958 inlen = sizeof(in.rst2init);
1959 outlen = sizeof(out.rst2init);
1961 case MLX5_CMD_OP_INIT2RTR_QP:
1962 MLX5_SET(init2rtr_qp_in, &in, qpn, qp->id);
1963 qpc = MLX5_ADDR_OF(init2rtr_qp_in, &in, qpc);
1964 MLX5_SET(qpc, qpc, primary_address_path.fl, 1);
1965 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1);
1966 MLX5_SET(qpc, qpc, mtu, 1);
1967 MLX5_SET(qpc, qpc, log_msg_max, 30);
1968 MLX5_SET(qpc, qpc, remote_qpn, remote_qp_id);
1969 MLX5_SET(qpc, qpc, min_rnr_nak, 0);
1970 inlen = sizeof(in.init2rtr);
1971 outlen = sizeof(out.init2rtr);
1973 case MLX5_CMD_OP_RTR2RTS_QP:
1974 qpc = MLX5_ADDR_OF(rtr2rts_qp_in, &in, qpc);
1975 MLX5_SET(rtr2rts_qp_in, &in, qpn, qp->id);
1976 MLX5_SET(qpc, qpc, primary_address_path.ack_timeout, 14);
1977 MLX5_SET(qpc, qpc, log_ack_req_freq, 0);
1978 MLX5_SET(qpc, qpc, retry_count, 7);
1979 MLX5_SET(qpc, qpc, rnr_retry, 7);
1980 inlen = sizeof(in.rtr2rts);
1981 outlen = sizeof(out.rtr2rts);
1984 DRV_LOG(ERR, "Invalid or unsupported QP modify op %u.",
1989 ret = mlx5_glue->devx_obj_modify(qp->obj, &in, inlen, &out, outlen);
1991 DRV_LOG(ERR, "Failed to modify QP using DevX.");
1998 struct mlx5_devx_obj *
1999 mlx5_devx_cmd_create_virtio_q_counters(void *ctx)
2001 uint32_t in[MLX5_ST_SZ_DW(create_virtio_q_counters_in)] = {0};
2002 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2003 struct mlx5_devx_obj *couners_obj = mlx5_malloc(MLX5_MEM_ZERO,
2004 sizeof(*couners_obj), 0,
2006 void *hdr = MLX5_ADDR_OF(create_virtio_q_counters_in, in, hdr);
2009 DRV_LOG(ERR, "Failed to allocate virtio queue counters data.");
2013 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2014 MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2015 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2016 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS);
2017 couners_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
2019 if (!couners_obj->obj) {
2021 DRV_LOG(ERR, "Failed to create virtio queue counters Obj using"
2023 mlx5_free(couners_obj);
2026 couners_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2031 mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj,
2032 struct mlx5_devx_virtio_q_couners_attr *attr)
2034 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
2035 uint32_t out[MLX5_ST_SZ_DW(query_virtio_q_counters_out)] = {0};
2036 void *hdr = MLX5_ADDR_OF(query_virtio_q_counters_out, in, hdr);
2037 void *virtio_q_counters = MLX5_ADDR_OF(query_virtio_q_counters_out, out,
2041 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2042 MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
2043 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2044 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS);
2045 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, couners_obj->id);
2046 ret = mlx5_glue->devx_obj_query(couners_obj->obj, in, sizeof(in), out,
2049 DRV_LOG(ERR, "Failed to query virtio q counters using DevX.");
2053 attr->received_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters,
2055 attr->completed_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters,
2057 attr->error_cqes = MLX5_GET(virtio_q_counters, virtio_q_counters,
2059 attr->bad_desc_errors = MLX5_GET(virtio_q_counters, virtio_q_counters,
2061 attr->exceed_max_chain = MLX5_GET(virtio_q_counters, virtio_q_counters,
2063 attr->invalid_buffer = MLX5_GET(virtio_q_counters, virtio_q_counters,
2069 * Create general object of type FLOW_HIT_ASO using DevX API.
2072 * Context returned from mlx5 open_device() glue function.
2074 * PD value to associate the FLOW_HIT_ASO object with.
2077 * The DevX object created, NULL otherwise and rte_errno is set.
2079 struct mlx5_devx_obj *
2080 mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, uint32_t pd)
2082 uint32_t in[MLX5_ST_SZ_DW(create_flow_hit_aso_in)] = {0};
2083 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2084 struct mlx5_devx_obj *flow_hit_aso_obj = NULL;
2087 flow_hit_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*flow_hit_aso_obj),
2089 if (!flow_hit_aso_obj) {
2090 DRV_LOG(ERR, "Failed to allocate FLOW_HIT_ASO object data");
2094 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, hdr);
2095 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2096 MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2097 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2098 MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO);
2099 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, flow_hit_aso);
2100 MLX5_SET(flow_hit_aso, ptr, access_pd, pd);
2101 flow_hit_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2103 if (!flow_hit_aso_obj->obj) {
2105 DRV_LOG(ERR, "Failed to create FLOW_HIT_ASO obj using DevX.");
2106 mlx5_free(flow_hit_aso_obj);
2109 flow_hit_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2110 return flow_hit_aso_obj;
2114 * Create PD using DevX API.
2117 * Context returned from mlx5 open_device() glue function.
2120 * The DevX object created, NULL otherwise and rte_errno is set.
2122 struct mlx5_devx_obj *
2123 mlx5_devx_cmd_alloc_pd(void *ctx)
2125 struct mlx5_devx_obj *ppd =
2126 mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ppd), 0, SOCKET_ID_ANY);
2127 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {0};
2128 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {0};
2131 DRV_LOG(ERR, "Failed to allocate PD data.");
2135 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD);
2136 ppd->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2140 DRV_LOG(ERR, "Failed to allocate PD Obj using DevX.");
2144 ppd->id = MLX5_GET(alloc_pd_out, out, pd);
2149 * Create general object of type GENEVE TLV option using DevX API.
2152 * Context returned from mlx5 open_device() glue function.
2154 * TLV option variable value of class
2156 * TLV option variable value of type
2158 * TLV option variable value of len
2161 * The DevX object created, NULL otherwise and rte_errno is set.
2163 struct mlx5_devx_obj *
2164 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx,
2165 uint16_t class, uint8_t type, uint8_t len)
2167 uint32_t in[MLX5_ST_SZ_DW(create_geneve_tlv_option_in)] = {0};
2168 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2169 struct mlx5_devx_obj *geneve_tlv_opt_obj = mlx5_malloc(MLX5_MEM_ZERO,
2170 sizeof(*geneve_tlv_opt_obj),
2173 if (!geneve_tlv_opt_obj) {
2174 DRV_LOG(ERR, "Failed to allocate geneve tlv option object.");
2178 void *hdr = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, hdr);
2179 void *opt = MLX5_ADDR_OF(create_geneve_tlv_option_in, in,
2181 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2182 MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2183 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2184 MLX5_OBJ_TYPE_GENEVE_TLV_OPT);
2185 MLX5_SET(geneve_tlv_option, opt, option_class,
2186 rte_be_to_cpu_16(class));
2187 MLX5_SET(geneve_tlv_option, opt, option_type, type);
2188 MLX5_SET(geneve_tlv_option, opt, option_data_length, len);
2189 geneve_tlv_opt_obj->obj = mlx5_glue->devx_obj_create(ctx, in,
2190 sizeof(in), out, sizeof(out));
2191 if (!geneve_tlv_opt_obj->obj) {
2193 DRV_LOG(ERR, "Failed to create Geneve tlv option "
2195 mlx5_free(geneve_tlv_opt_obj);
2198 geneve_tlv_opt_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2199 return geneve_tlv_opt_obj;
2203 mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id)
2205 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2206 uint32_t in[MLX5_ST_SZ_DW(query_rq_in)] = {0};
2207 uint32_t out[MLX5_ST_SZ_DW(query_rq_out)] = {0};
2211 MLX5_SET(query_rq_in, in, opcode, MLX5_CMD_OP_QUERY_RQ);
2212 MLX5_SET(query_rq_in, in, rqn, ((struct ibv_wq *)wq)->wq_num);
2213 rc = mlx5_glue->devx_wq_query(wq, in, sizeof(in), out, sizeof(out));
2216 DRV_LOG(ERR, "Failed to query WQ counter set ID using DevX - "
2217 "rc = %d, errno = %d.", rc, errno);
2220 rq_ctx = MLX5_ADDR_OF(query_rq_out, out, rq_context);
2221 *counter_set_id = MLX5_GET(rqc, rq_ctx, counter_set_id);
2225 (void)counter_set_id;
2231 * Allocate queue counters via devx interface.
2234 * Context returned from mlx5 open_device() glue function.
2237 * Pointer to counter object on success, a NULL value otherwise and
2240 struct mlx5_devx_obj *
2241 mlx5_devx_cmd_queue_counter_alloc(void *ctx)
2243 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 0,
2245 uint32_t in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {0};
2246 uint32_t out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {0};
2252 MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER);
2253 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
2256 DRV_LOG(DEBUG, "Can't allocate q counter set by DevX - error "
2262 dcs->id = MLX5_GET(alloc_q_counter_out, out, counter_set_id);
2267 * Query queue counters values.
2270 * devx object of the queue counter set.
2272 * Whether hardware should clear the counters after the query or not.
2273 * @param[out] out_of_buffers
2274 * Number of dropped occurred due to lack of WQE for the associated QPs/RQs.
2277 * 0 on success, a negative value otherwise.
2280 mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear,
2281 uint32_t *out_of_buffers)
2283 uint32_t out[MLX5_ST_SZ_BYTES(query_q_counter_out)] = {0};
2284 uint32_t in[MLX5_ST_SZ_DW(query_q_counter_in)] = {0};
2287 MLX5_SET(query_q_counter_in, in, opcode,
2288 MLX5_CMD_OP_QUERY_Q_COUNTER);
2289 MLX5_SET(query_q_counter_in, in, op_mod, 0);
2290 MLX5_SET(query_q_counter_in, in, counter_set_id, dcs->id);
2291 MLX5_SET(query_q_counter_in, in, clear, !!clear);
2292 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out,
2295 DRV_LOG(ERR, "Failed to query devx q counter set - rc %d", rc);
2299 *out_of_buffers = MLX5_GET(query_q_counter_out, out, out_of_buffer);