drivers/common/mlx5/mlx5_devx_cmds.c

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /* Copyright 2018 Mellanox Technologies, Ltd */
   3
   4 #include <unistd.h>
   5
   6 #include <rte_errno.h>
   7 #include <rte_malloc.h>
   8 #include <rte_eal_paging.h>
   9
  10 #include "mlx5_prm.h"
  11 #include "mlx5_devx_cmds.h"
  12 #include "mlx5_common_log.h"
  13 #include "mlx5_malloc.h"
  14
  15
  16 /**
  17  * Perform read access to the registers. Reads data from register
  18  * and writes ones to the specified buffer.
  19  *
  20  * @param[in] ctx
  21  *   Context returned from mlx5 open_device() glue function.
  22  * @param[in] reg_id
  23  *   Register identifier according to the PRM.
  24  * @param[in] arg
  25  *   Register access auxiliary parameter according to the PRM.
  26  * @param[out] data
  27  *   Pointer to the buffer to store read data.
  28  * @param[in] dw_cnt
  29  *   Buffer size in double words.
  30  *
  31  * @return
  32  *   0 on success, a negative value otherwise.
  33  */
  34 int
  35 mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg,
  36                             uint32_t *data, uint32_t dw_cnt)
  37 {
  38         uint32_t in[MLX5_ST_SZ_DW(access_register_in)]   = {0};
  39         uint32_t out[MLX5_ST_SZ_DW(access_register_out) +
  40                      MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0};
  41         int status, rc;
  42
  43         MLX5_ASSERT(data && dw_cnt);
  44         MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX);
  45         if (dw_cnt  > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) {
  46                 DRV_LOG(ERR, "Not enough  buffer for register read data");
  47                 return -1;
  48         }
  49         MLX5_SET(access_register_in, in, opcode,
  50                  MLX5_CMD_OP_ACCESS_REGISTER_USER);
  51         MLX5_SET(access_register_in, in, op_mod,
  52                                         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ);
  53         MLX5_SET(access_register_in, in, register_id, reg_id);
  54         MLX5_SET(access_register_in, in, argument, arg);
  55         rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out,
  56                                          MLX5_ST_SZ_BYTES(access_register_out) +
  57                                          sizeof(uint32_t) * dw_cnt);
  58         if (rc)
  59                 goto error;
  60         status = MLX5_GET(access_register_out, out, status);
  61         if (status) {
  62                 int syndrome = MLX5_GET(access_register_out, out, syndrome);
  63
  64                 DRV_LOG(DEBUG, "Failed to access NIC register 0x%X, "
  65                                "status %x, syndrome = %x",
  66                                reg_id, status, syndrome);
  67                 return -1;
  68         }
  69         memcpy(data, &out[MLX5_ST_SZ_DW(access_register_out)],
  70                dw_cnt * sizeof(uint32_t));
  71         return 0;
  72 error:
  73         rc = (rc > 0) ? -rc : rc;
  74         return rc;
  75 }
  76
  77 /**
  78  * Allocate flow counters via devx interface.
  79  *
  80  * @param[in] ctx
  81  *   Context returned from mlx5 open_device() glue function.
  82  * @param dcs
  83  *   Pointer to counters properties structure to be filled by the routine.
  84  * @param bulk_n_128
  85  *   Bulk counter numbers in 128 counters units.
  86  *
  87  * @return
  88  *   Pointer to counter object on success, a negative value otherwise and
  89  *   rte_errno is set.
  90  */
  91 struct mlx5_devx_obj *
  92 mlx5_devx_cmd_flow_counter_alloc(void *ctx, uint32_t bulk_n_128)
  93 {
  94         struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs),
  95                                                 0, SOCKET_ID_ANY);
  96         uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)]   = {0};
  97         uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0};
  98
  99         if (!dcs) {
 100                 rte_errno = ENOMEM;
 101                 return NULL;
 102         }
 103         MLX5_SET(alloc_flow_counter_in, in, opcode,
 104                  MLX5_CMD_OP_ALLOC_FLOW_COUNTER);
 105         MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128);
 106         dcs->obj = mlx5_glue->devx_obj_create(ctx, in,
 107                                               sizeof(in), out, sizeof(out));
 108         if (!dcs->obj) {
 109                 DRV_LOG(ERR, "Can't allocate counters - error %d", errno);
 110                 rte_errno = errno;
 111                 mlx5_free(dcs);
 112                 return NULL;
 113         }
 114         dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id);
 115         return dcs;
 116 }
 117
 118 /**
 119  * Query flow counters values.
 120  *
 121  * @param[in] dcs
 122  *   devx object that was obtained from mlx5_devx_cmd_fc_alloc.
 123  * @param[in] clear
 124  *   Whether hardware should clear the counters after the query or not.
 125  * @param[in] n_counters
 126  *   0 in case of 1 counter to read, otherwise the counter number to read.
 127  *  @param pkts
 128  *   The number of packets that matched the flow.
 129  *  @param bytes
 130  *    The number of bytes that matched the flow.
 131  *  @param mkey
 132  *   The mkey key for batch query.
 133  *  @param addr
 134  *    The address in the mkey range for batch query.
 135  *  @param cmd_comp
 136  *   The completion object for asynchronous batch query.
 137  *  @param async_id
 138  *    The ID to be returned in the asynchronous batch query response.
 139  *
 140  * @return
 141  *   0 on success, a negative value otherwise.
 142  */
 143 int
 144 mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs,
 145                                  int clear, uint32_t n_counters,
 146                                  uint64_t *pkts, uint64_t *bytes,
 147                                  uint32_t mkey, void *addr,
 148                                  void *cmd_comp,
 149                                  uint64_t async_id)
 150 {
 151         int out_len = MLX5_ST_SZ_BYTES(query_flow_counter_out) +
 152                         MLX5_ST_SZ_BYTES(traffic_counter);
 153         uint32_t out[out_len];
 154         uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0};
 155         void *stats;
 156         int rc;
 157
 158         MLX5_SET(query_flow_counter_in, in, opcode,
 159                  MLX5_CMD_OP_QUERY_FLOW_COUNTER);
 160         MLX5_SET(query_flow_counter_in, in, op_mod, 0);
 161         MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id);
 162         MLX5_SET(query_flow_counter_in, in, clear, !!clear);
 163
 164         if (n_counters) {
 165                 MLX5_SET(query_flow_counter_in, in, num_of_counters,
 166                          n_counters);
 167                 MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1);
 168                 MLX5_SET(query_flow_counter_in, in, mkey, mkey);
 169                 MLX5_SET64(query_flow_counter_in, in, address,
 170                            (uint64_t)(uintptr_t)addr);
 171         }
 172         if (!cmd_comp)
 173                 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out,
 174                                                out_len);
 175         else
 176                 rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in),
 177                                                      out_len, async_id,
 178                                                      cmd_comp);
 179         if (rc) {
 180                 DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc);
 181                 rte_errno = rc;
 182                 return -rc;
 183         }
 184         if (!n_counters) {
 185                 stats = MLX5_ADDR_OF(query_flow_counter_out,
 186                                      out, flow_statistics);
 187                 *pkts = MLX5_GET64(traffic_counter, stats, packets);
 188                 *bytes = MLX5_GET64(traffic_counter, stats, octets);
 189         }
 190         return 0;
 191 }
 192
 193 /**
 194  * Create a new mkey.
 195  *
 196  * @param[in] ctx
 197  *   Context returned from mlx5 open_device() glue function.
 198  * @param[in] attr
 199  *   Attributes of the requested mkey.
 200  *
 201  * @return
 202  *   Pointer to Devx mkey on success, a negative value otherwise and rte_errno
 203  *   is set.
 204  */
 205 struct mlx5_devx_obj *
 206 mlx5_devx_cmd_mkey_create(void *ctx,
 207                           struct mlx5_devx_mkey_attr *attr)
 208 {
 209         struct mlx5_klm *klm_array = attr->klm_array;
 210         int klm_num = attr->klm_num;
 211         int in_size_dw = MLX5_ST_SZ_DW(create_mkey_in) +
 212                      (klm_num ? RTE_ALIGN(klm_num, 4) : 0) * MLX5_ST_SZ_DW(klm);
 213         uint32_t in[in_size_dw];
 214         uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0};
 215         void *mkc;
 216         struct mlx5_devx_obj *mkey = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mkey),
 217                                                  0, SOCKET_ID_ANY);
 218         size_t pgsize;
 219         uint32_t translation_size;
 220
 221         if (!mkey) {
 222                 rte_errno = ENOMEM;
 223                 return NULL;
 224         }
 225         memset(in, 0, in_size_dw * 4);
 226         pgsize = rte_mem_page_size();
 227         if (pgsize == (size_t)-1) {
 228                 mlx5_free(mkey);
 229                 DRV_LOG(ERR, "Failed to get page size");
 230                 rte_errno = ENOMEM;
 231                 return NULL;
 232         }
 233         MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY);
 234         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 235         if (klm_num > 0) {
 236                 int i;
 237                 uint8_t *klm = (uint8_t *)MLX5_ADDR_OF(create_mkey_in, in,
 238                                                        klm_pas_mtt);
 239                 translation_size = RTE_ALIGN(klm_num, 4);
 240                 for (i = 0; i < klm_num; i++) {
 241                         MLX5_SET(klm, klm, byte_count, klm_array[i].byte_count);
 242                         MLX5_SET(klm, klm, mkey, klm_array[i].mkey);
 243                         MLX5_SET64(klm, klm, address, klm_array[i].address);
 244                         klm += MLX5_ST_SZ_BYTES(klm);
 245                 }
 246                 for (; i < (int)translation_size; i++) {
 247                         MLX5_SET(klm, klm, mkey, 0x0);
 248                         MLX5_SET64(klm, klm, address, 0x0);
 249                         klm += MLX5_ST_SZ_BYTES(klm);
 250                 }
 251                 MLX5_SET(mkc, mkc, access_mode_1_0, attr->log_entity_size ?
 252                          MLX5_MKC_ACCESS_MODE_KLM_FBS :
 253                          MLX5_MKC_ACCESS_MODE_KLM);
 254                 MLX5_SET(mkc, mkc, log_page_size, attr->log_entity_size);
 255         } else {
 256                 translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16;
 257                 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
 258                 MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize));
 259         }
 260         MLX5_SET(create_mkey_in, in, translations_octword_actual_size,
 261                  translation_size);
 262         MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id);
 263         MLX5_SET(create_mkey_in, in, pg_access, attr->pg_access);
 264         MLX5_SET(mkc, mkc, lw, 0x1);
 265         MLX5_SET(mkc, mkc, lr, 0x1);
 266         if (attr->set_remote_rw) {
 267                 MLX5_SET(mkc, mkc, rw, 0x1);
 268                 MLX5_SET(mkc, mkc, rr, 0x1);
 269         }
 270         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 271         MLX5_SET(mkc, mkc, pd, attr->pd);
 272         MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF);
 273         MLX5_SET(mkc, mkc, umr_en, attr->umr_en);
 274         MLX5_SET(mkc, mkc, translations_octword_size, translation_size);
 275         MLX5_SET(mkc, mkc, relaxed_ordering_write,
 276                  attr->relaxed_ordering_write);
 277         MLX5_SET(mkc, mkc, relaxed_ordering_read, attr->relaxed_ordering_read);
 278         MLX5_SET64(mkc, mkc, start_addr, attr->addr);
 279         MLX5_SET64(mkc, mkc, len, attr->size);
 280         MLX5_SET(mkc, mkc, crypto_en, attr->crypto_en);
 281         if (attr->crypto_en) {
 282                 MLX5_SET(mkc, mkc, bsf_en, attr->crypto_en);
 283                 MLX5_SET(mkc, mkc, bsf_octword_size, 4);
 284         }
 285         mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out,
 286                                                sizeof(out));
 287         if (!mkey->obj) {
 288                 DRV_LOG(ERR, "Can't create %sdirect mkey - error %d",
 289                         klm_num ? "an in" : "a ", errno);
 290                 rte_errno = errno;
 291                 mlx5_free(mkey);
 292                 return NULL;
 293         }
 294         mkey->id = MLX5_GET(create_mkey_out, out, mkey_index);
 295         mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF);
 296         return mkey;
 297 }
 298
 299 /**
 300  * Get status of devx command response.
 301  * Mainly used for asynchronous commands.
 302  *
 303  * @param[in] out
 304  *   The out response buffer.
 305  *
 306  * @return
 307  *   0 on success, non-zero value otherwise.
 308  */
 309 int
 310 mlx5_devx_get_out_command_status(void *out)
 311 {
 312         int status;
 313
 314         if (!out)
 315                 return -EINVAL;
 316         status = MLX5_GET(query_flow_counter_out, out, status);
 317         if (status) {
 318                 int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome);
 319
 320                 DRV_LOG(ERR, "Bad DevX status %x, syndrome = %x", status,
 321                         syndrome);
 322         }
 323         return status;
 324 }
 325
 326 /**
 327  * Destroy any object allocated by a Devx API.
 328  *
 329  * @param[in] obj
 330  *   Pointer to a general object.
 331  *
 332  * @return
 333  *   0 on success, a negative value otherwise.
 334  */
 335 int
 336 mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj)
 337 {
 338         int ret;
 339
 340         if (!obj)
 341                 return 0;
 342         ret =  mlx5_glue->devx_obj_destroy(obj->obj);
 343         mlx5_free(obj);
 344         return ret;
 345 }
 346
 347 /**
 348  * Query NIC vport context.
 349  * Fills minimal inline attribute.
 350  *
 351  * @param[in] ctx
 352  *   ibv contexts returned from mlx5dv_open_device.
 353  * @param[in] vport
 354  *   vport index
 355  * @param[out] attr
 356  *   Attributes device values.
 357  *
 358  * @return
 359  *   0 on success, a negative value otherwise.
 360  */
 361 static int
 362 mlx5_devx_cmd_query_nic_vport_context(void *ctx,
 363                                       unsigned int vport,
 364                                       struct mlx5_hca_attr *attr)
 365 {
 366         uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0};
 367         uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0};
 368         void *vctx;
 369         int status, syndrome, rc;
 370
 371         /* Query NIC vport context to determine inline mode. */
 372         MLX5_SET(query_nic_vport_context_in, in, opcode,
 373                  MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT);
 374         MLX5_SET(query_nic_vport_context_in, in, vport_number, vport);
 375         if (vport)
 376                 MLX5_SET(query_nic_vport_context_in, in, other_vport, 1);
 377         rc = mlx5_glue->devx_general_cmd(ctx,
 378                                          in, sizeof(in),
 379                                          out, sizeof(out));
 380         if (rc)
 381                 goto error;
 382         status = MLX5_GET(query_nic_vport_context_out, out, status);
 383         syndrome = MLX5_GET(query_nic_vport_context_out, out, syndrome);
 384         if (status) {
 385                 DRV_LOG(DEBUG, "Failed to query NIC vport context, "
 386                         "status %x, syndrome = %x", status, syndrome);
 387                 return -1;
 388         }
 389         vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out,
 390                             nic_vport_context);
 391         attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx,
 392                                            min_wqe_inline_mode);
 393         return 0;
 394 error:
 395         rc = (rc > 0) ? -rc : rc;
 396         return rc;
 397 }
 398
 399 /**
 400  * Query NIC vDPA attributes.
 401  *
 402  * @param[in] ctx
 403  *   Context returned from mlx5 open_device() glue function.
 404  * @param[out] vdpa_attr
 405  *   vDPA Attributes structure to fill.
 406  */
 407 static void
 408 mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx,
 409                                   struct mlx5_hca_vdpa_attr *vdpa_attr)
 410 {
 411         uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0};
 412         uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0};
 413         void *hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 414         int status, syndrome, rc;
 415
 416         MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
 417         MLX5_SET(query_hca_cap_in, in, op_mod,
 418                  MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION |
 419                  MLX5_HCA_CAP_OPMOD_GET_CUR);
 420         rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
 421         status = MLX5_GET(query_hca_cap_out, out, status);
 422         syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
 423         if (rc || status) {
 424                 RTE_LOG(DEBUG, PMD, "Failed to query devx VDPA capabilities,"
 425                         " status %x, syndrome = %x", status, syndrome);
 426                 vdpa_attr->valid = 0;
 427         } else {
 428                 vdpa_attr->valid = 1;
 429                 vdpa_attr->desc_tunnel_offload_type =
 430                         MLX5_GET(virtio_emulation_cap, hcattr,
 431                                  desc_tunnel_offload_type);
 432                 vdpa_attr->eth_frame_offload_type =
 433                         MLX5_GET(virtio_emulation_cap, hcattr,
 434                                  eth_frame_offload_type);
 435                 vdpa_attr->virtio_version_1_0 =
 436                         MLX5_GET(virtio_emulation_cap, hcattr,
 437                                  virtio_version_1_0);
 438                 vdpa_attr->tso_ipv4 = MLX5_GET(virtio_emulation_cap, hcattr,
 439                                                tso_ipv4);
 440                 vdpa_attr->tso_ipv6 = MLX5_GET(virtio_emulation_cap, hcattr,
 441                                                tso_ipv6);
 442                 vdpa_attr->tx_csum = MLX5_GET(virtio_emulation_cap, hcattr,
 443                                               tx_csum);
 444                 vdpa_attr->rx_csum = MLX5_GET(virtio_emulation_cap, hcattr,
 445                                               rx_csum);
 446                 vdpa_attr->event_mode = MLX5_GET(virtio_emulation_cap, hcattr,
 447                                                  event_mode);
 448                 vdpa_attr->virtio_queue_type =
 449                         MLX5_GET(virtio_emulation_cap, hcattr,
 450                                  virtio_queue_type);
 451                 vdpa_attr->log_doorbell_stride =
 452                         MLX5_GET(virtio_emulation_cap, hcattr,
 453                                  log_doorbell_stride);
 454                 vdpa_attr->log_doorbell_bar_size =
 455                         MLX5_GET(virtio_emulation_cap, hcattr,
 456                                  log_doorbell_bar_size);
 457                 vdpa_attr->doorbell_bar_offset =
 458                         MLX5_GET64(virtio_emulation_cap, hcattr,
 459                                    doorbell_bar_offset);
 460                 vdpa_attr->max_num_virtio_queues =
 461                         MLX5_GET(virtio_emulation_cap, hcattr,
 462                                  max_num_virtio_queues);
 463                 vdpa_attr->umems[0].a = MLX5_GET(virtio_emulation_cap, hcattr,
 464                                                  umem_1_buffer_param_a);
 465                 vdpa_attr->umems[0].b = MLX5_GET(virtio_emulation_cap, hcattr,
 466                                                  umem_1_buffer_param_b);
 467                 vdpa_attr->umems[1].a = MLX5_GET(virtio_emulation_cap, hcattr,
 468                                                  umem_2_buffer_param_a);
 469                 vdpa_attr->umems[1].b = MLX5_GET(virtio_emulation_cap, hcattr,
 470                                                  umem_2_buffer_param_b);
 471                 vdpa_attr->umems[2].a = MLX5_GET(virtio_emulation_cap, hcattr,
 472                                                  umem_3_buffer_param_a);
 473                 vdpa_attr->umems[2].b = MLX5_GET(virtio_emulation_cap, hcattr,
 474                                                  umem_3_buffer_param_b);
 475         }
 476 }
 477
 478 int
 479 mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj,
 480                                   uint32_t ids[], uint32_t num)
 481 {
 482         uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
 483         uint32_t out[MLX5_ST_SZ_DW(create_flex_parser_out)] = {0};
 484         void *hdr = MLX5_ADDR_OF(create_flex_parser_out, in, hdr);
 485         void *flex = MLX5_ADDR_OF(create_flex_parser_out, out, flex);
 486         void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table);
 487         int ret;
 488         uint32_t idx = 0;
 489         uint32_t i;
 490
 491         if (num > MLX5_GRAPH_NODE_SAMPLE_NUM) {
 492                 rte_errno = EINVAL;
 493                 DRV_LOG(ERR, "Too many sample IDs to be fetched.");
 494                 return -rte_errno;
 495         }
 496         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
 497                  MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
 498         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
 499                  MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH);
 500         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, flex_obj->id);
 501         ret = mlx5_glue->devx_obj_query(flex_obj->obj, in, sizeof(in),
 502                                         out, sizeof(out));
 503         if (ret) {
 504                 rte_errno = ret;
 505                 DRV_LOG(ERR, "Failed to query sample IDs with object %p.",
 506                         (void *)flex_obj);
 507                 return -rte_errno;
 508         }
 509         for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) {
 510                 void *s_off = (void *)((char *)sample + i *
 511                               MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample));
 512                 uint32_t en;
 513
 514                 en = MLX5_GET(parse_graph_flow_match_sample, s_off,
 515                               flow_match_sample_en);
 516                 if (!en)
 517                         continue;
 518                 ids[idx++] = MLX5_GET(parse_graph_flow_match_sample, s_off,
 519                                   flow_match_sample_field_id);
 520         }
 521         if (num != idx) {
 522                 rte_errno = EINVAL;
 523                 DRV_LOG(ERR, "Number of sample IDs are not as expected.");
 524                 return -rte_errno;
 525         }
 526         return ret;
 527 }
 528
 529
 530 struct mlx5_devx_obj *
 531 mlx5_devx_cmd_create_flex_parser(void *ctx,
 532                               struct mlx5_devx_graph_node_attr *data)
 533 {
 534         uint32_t in[MLX5_ST_SZ_DW(create_flex_parser_in)] = {0};
 535         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
 536         void *hdr = MLX5_ADDR_OF(create_flex_parser_in, in, hdr);
 537         void *flex = MLX5_ADDR_OF(create_flex_parser_in, in, flex);
 538         void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table);
 539         void *in_arc = MLX5_ADDR_OF(parse_graph_flex, flex, input_arc);
 540         void *out_arc = MLX5_ADDR_OF(parse_graph_flex, flex, output_arc);
 541         struct mlx5_devx_obj *parse_flex_obj = mlx5_malloc
 542                      (MLX5_MEM_ZERO, sizeof(*parse_flex_obj), 0, SOCKET_ID_ANY);
 543         uint32_t i;
 544
 545         if (!parse_flex_obj) {
 546                 DRV_LOG(ERR, "Failed to allocate flex parser data.");
 547                 rte_errno = ENOMEM;
 548                 return NULL;
 549         }
 550         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
 551                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
 552         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
 553                  MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH);
 554         MLX5_SET(parse_graph_flex, flex, header_length_mode,
 555                  data->header_length_mode);
 556         MLX5_SET(parse_graph_flex, flex, header_length_base_value,
 557                  data->header_length_base_value);
 558         MLX5_SET(parse_graph_flex, flex, header_length_field_offset,
 559                  data->header_length_field_offset);
 560         MLX5_SET(parse_graph_flex, flex, header_length_field_shift,
 561                  data->header_length_field_shift);
 562         MLX5_SET(parse_graph_flex, flex, header_length_field_mask,
 563                  data->header_length_field_mask);
 564         for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) {
 565                 struct mlx5_devx_match_sample_attr *s = &data->sample[i];
 566                 void *s_off = (void *)((char *)sample + i *
 567                               MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample));
 568
 569                 if (!s->flow_match_sample_en)
 570                         continue;
 571                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 572                          flow_match_sample_en, !!s->flow_match_sample_en);
 573                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 574                          flow_match_sample_field_offset,
 575                          s->flow_match_sample_field_offset);
 576                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 577                          flow_match_sample_offset_mode,
 578                          s->flow_match_sample_offset_mode);
 579                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 580                          flow_match_sample_field_offset_mask,
 581                          s->flow_match_sample_field_offset_mask);
 582                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 583                          flow_match_sample_field_offset_shift,
 584                          s->flow_match_sample_field_offset_shift);
 585                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 586                          flow_match_sample_field_base_offset,
 587                          s->flow_match_sample_field_base_offset);
 588                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 589                          flow_match_sample_tunnel_mode,
 590                          s->flow_match_sample_tunnel_mode);
 591         }
 592         for (i = 0; i < MLX5_GRAPH_NODE_ARC_NUM; i++) {
 593                 struct mlx5_devx_graph_arc_attr *ia = &data->in[i];
 594                 struct mlx5_devx_graph_arc_attr *oa = &data->out[i];
 595                 void *in_off = (void *)((char *)in_arc + i *
 596                               MLX5_ST_SZ_BYTES(parse_graph_arc));
 597                 void *out_off = (void *)((char *)out_arc + i *
 598                               MLX5_ST_SZ_BYTES(parse_graph_arc));
 599
 600                 if (ia->arc_parse_graph_node != 0) {
 601                         MLX5_SET(parse_graph_arc, in_off,
 602                                  compare_condition_value,
 603                                  ia->compare_condition_value);
 604                         MLX5_SET(parse_graph_arc, in_off, start_inner_tunnel,
 605                                  ia->start_inner_tunnel);
 606                         MLX5_SET(parse_graph_arc, in_off, arc_parse_graph_node,
 607                                  ia->arc_parse_graph_node);
 608                         MLX5_SET(parse_graph_arc, in_off,
 609                                  parse_graph_node_handle,
 610                                  ia->parse_graph_node_handle);
 611                 }
 612                 if (oa->arc_parse_graph_node != 0) {
 613                         MLX5_SET(parse_graph_arc, out_off,
 614                                  compare_condition_value,
 615                                  oa->compare_condition_value);
 616                         MLX5_SET(parse_graph_arc, out_off, start_inner_tunnel,
 617                                  oa->start_inner_tunnel);
 618                         MLX5_SET(parse_graph_arc, out_off, arc_parse_graph_node,
 619                                  oa->arc_parse_graph_node);
 620                         MLX5_SET(parse_graph_arc, out_off,
 621                                  parse_graph_node_handle,
 622                                  oa->parse_graph_node_handle);
 623                 }
 624         }
 625         parse_flex_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
 626                                                          out, sizeof(out));
 627         if (!parse_flex_obj->obj) {
 628                 rte_errno = errno;
 629                 DRV_LOG(ERR, "Failed to create FLEX PARSE GRAPH object "
 630                         "by using DevX.");
 631                 mlx5_free(parse_flex_obj);
 632                 return NULL;
 633         }
 634         parse_flex_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
 635         return parse_flex_obj;
 636 }
 637
 638 /**
 639  * Query HCA attributes.
 640  * Using those attributes we can check on run time if the device
 641  * is having the required capabilities.
 642  *
 643  * @param[in] ctx
 644  *   Context returned from mlx5 open_device() glue function.
 645  * @param[out] attr
 646  *   Attributes device values.
 647  *
 648  * @return
 649  *   0 on success, a negative value otherwise.
 650  */
 651 int
 652 mlx5_devx_cmd_query_hca_attr(void *ctx,
 653                              struct mlx5_hca_attr *attr)
 654 {
 655         uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0};
 656         uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0};
 657         void *hcattr;
 658         int status, syndrome, rc, i;
 659         uint64_t general_obj_types_supported = 0;
 660
 661         MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
 662         MLX5_SET(query_hca_cap_in, in, op_mod,
 663                  MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE |
 664                  MLX5_HCA_CAP_OPMOD_GET_CUR);
 665
 666         rc = mlx5_glue->devx_general_cmd(ctx,
 667                                          in, sizeof(in), out, sizeof(out));
 668         if (rc)
 669                 goto error;
 670         status = MLX5_GET(query_hca_cap_out, out, status);
 671         syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
 672         if (status) {
 673                 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, "
 674                         "status %x, syndrome = %x", status, syndrome);
 675                 return -1;
 676         }
 677         hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 678         attr->flow_counter_bulk_alloc_bitmap =
 679                         MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc);
 680         attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr,
 681                                             flow_counters_dump);
 682         attr->log_max_rqt_size = MLX5_GET(cmd_hca_cap, hcattr,
 683                                           log_max_rqt_size);
 684         attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager);
 685         attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin);
 686         attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr,
 687                                                 log_max_hairpin_queues);
 688         attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr,
 689                                                     log_max_hairpin_wq_data_sz);
 690         attr->log_max_hairpin_num_packets = MLX5_GET
 691                 (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz);
 692         attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id);
 693         attr->relaxed_ordering_write = MLX5_GET(cmd_hca_cap, hcattr,
 694                                                 relaxed_ordering_write);
 695         attr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr,
 696                                                relaxed_ordering_read);
 697         attr->access_register_user = MLX5_GET(cmd_hca_cap, hcattr,
 698                                               access_register_user);
 699         attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr,
 700                                           eth_net_offloads);
 701         attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt);
 702         attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr,
 703                                                flex_parser_protocols);
 704         attr->max_geneve_tlv_options = MLX5_GET(cmd_hca_cap, hcattr,
 705                         max_geneve_tlv_options);
 706         attr->max_geneve_tlv_option_data_len = MLX5_GET(cmd_hca_cap, hcattr,
 707                         max_geneve_tlv_option_data_len);
 708         attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos);
 709         attr->qos.flow_meter_aso_sup = !!(MLX5_GET64(cmd_hca_cap, hcattr,
 710                                          general_obj_types) &
 711                               MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO);
 712         attr->vdpa.valid = !!(MLX5_GET64(cmd_hca_cap, hcattr,
 713                                          general_obj_types) &
 714                               MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q);
 715         attr->vdpa.queue_counters_valid = !!(MLX5_GET64(cmd_hca_cap, hcattr,
 716                                                         general_obj_types) &
 717                                   MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS);
 718         attr->parse_graph_flex_node = !!(MLX5_GET64(cmd_hca_cap, hcattr,
 719                                          general_obj_types) &
 720                               MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE);
 721         attr->wqe_index_ignore = MLX5_GET(cmd_hca_cap, hcattr,
 722                                           wqe_index_ignore_cap);
 723         attr->cross_channel = MLX5_GET(cmd_hca_cap, hcattr, cd);
 724         attr->non_wire_sq = MLX5_GET(cmd_hca_cap, hcattr, non_wire_sq);
 725         attr->log_max_static_sq_wq = MLX5_GET(cmd_hca_cap, hcattr,
 726                                               log_max_static_sq_wq);
 727         attr->num_lag_ports = MLX5_GET(cmd_hca_cap, hcattr, num_lag_ports);
 728         attr->dev_freq_khz = MLX5_GET(cmd_hca_cap, hcattr,
 729                                       device_frequency_khz);
 730         attr->scatter_fcs_w_decap_disable =
 731                 MLX5_GET(cmd_hca_cap, hcattr, scatter_fcs_w_decap_disable);
 732         attr->roce = MLX5_GET(cmd_hca_cap, hcattr, roce);
 733         attr->rq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, rq_ts_format);
 734         attr->sq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, sq_ts_format);
 735         attr->regex = MLX5_GET(cmd_hca_cap, hcattr, regexp);
 736         attr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr,
 737                                                regexp_num_of_engines);
 738         /* Read the general_obj_types bitmap and extract the relevant bits. */
 739         general_obj_types_supported = MLX5_GET64(cmd_hca_cap, hcattr,
 740                                                  general_obj_types);
 741         attr->vdpa.valid = !!(general_obj_types_supported &
 742                               MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q);
 743         attr->vdpa.queue_counters_valid =
 744                         !!(general_obj_types_supported &
 745                            MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS);
 746         attr->parse_graph_flex_node =
 747                         !!(general_obj_types_supported &
 748                            MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE);
 749         attr->flow_hit_aso = !!(general_obj_types_supported &
 750                                 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO);
 751         attr->geneve_tlv_opt = !!(general_obj_types_supported &
 752                                   MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT);
 753         attr->dek = !!(general_obj_types_supported &
 754                        MLX5_GENERAL_OBJ_TYPES_CAP_DEK);
 755         attr->import_kek = !!(general_obj_types_supported &
 756                               MLX5_GENERAL_OBJ_TYPES_CAP_IMPORT_KEK);
 757         attr->credential = !!(general_obj_types_supported &
 758                               MLX5_GENERAL_OBJ_TYPES_CAP_CREDENTIAL);
 759         attr->crypto_login = !!(general_obj_types_supported &
 760                                 MLX5_GENERAL_OBJ_TYPES_CAP_CRYPTO_LOGIN);
 761         /* Add reading of other GENERAL_OBJ_TYPES_CAP bits above this line. */
 762         attr->log_max_cq = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq);
 763         attr->log_max_qp = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp);
 764         attr->log_max_cq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq_sz);
 765         attr->log_max_qp_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp_sz);
 766         attr->log_max_mrw_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_mrw_sz);
 767         attr->log_max_pd = MLX5_GET(cmd_hca_cap, hcattr, log_max_pd);
 768         attr->log_max_srq = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq);
 769         attr->log_max_srq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq_sz);
 770         attr->reg_c_preserve =
 771                 MLX5_GET(cmd_hca_cap, hcattr, reg_c_preserve);
 772         attr->mmo_dma_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo);
 773         attr->mmo_compress_en = MLX5_GET(cmd_hca_cap, hcattr, compress);
 774         attr->mmo_decompress_en = MLX5_GET(cmd_hca_cap, hcattr, decompress);
 775         attr->compress_min_block_size = MLX5_GET(cmd_hca_cap, hcattr,
 776                                                  compress_min_block_size);
 777         attr->log_max_mmo_dma = MLX5_GET(cmd_hca_cap, hcattr, log_dma_mmo_size);
 778         attr->log_max_mmo_compress = MLX5_GET(cmd_hca_cap, hcattr,
 779                                               log_compress_mmo_size);
 780         attr->log_max_mmo_decompress = MLX5_GET(cmd_hca_cap, hcattr,
 781                                                 log_decompress_mmo_size);
 782         attr->cqe_compression = MLX5_GET(cmd_hca_cap, hcattr, cqe_compression);
 783         attr->mini_cqe_resp_flow_tag = MLX5_GET(cmd_hca_cap, hcattr,
 784                                                 mini_cqe_resp_flow_tag);
 785         attr->mini_cqe_resp_l3_l4_tag = MLX5_GET(cmd_hca_cap, hcattr,
 786                                                  mini_cqe_resp_l3_l4_tag);
 787         attr->umr_indirect_mkey_disabled =
 788                 MLX5_GET(cmd_hca_cap, hcattr, umr_indirect_mkey_disabled);
 789         attr->umr_modify_entity_size_disabled =
 790                 MLX5_GET(cmd_hca_cap, hcattr, umr_modify_entity_size_disabled);
 791         attr->crypto = MLX5_GET(cmd_hca_cap, hcattr, crypto);
 792         if (attr->crypto)
 793                 attr->aes_xts = MLX5_GET(cmd_hca_cap, hcattr, aes_xts);
 794         if (attr->qos.sup) {
 795                 MLX5_SET(query_hca_cap_in, in, op_mod,
 796                          MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP |
 797                          MLX5_HCA_CAP_OPMOD_GET_CUR);
 798                 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in),
 799                                                  out, sizeof(out));
 800                 if (rc)
 801                         goto error;
 802                 if (status) {
 803                         DRV_LOG(DEBUG, "Failed to query devx QOS capabilities,"
 804                                 " status %x, syndrome = %x", status, syndrome);
 805                         return -1;
 806                 }
 807                 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 808                 attr->qos.flow_meter_old =
 809                                 MLX5_GET(qos_cap, hcattr, flow_meter_old);
 810                 attr->qos.log_max_flow_meter =
 811                                 MLX5_GET(qos_cap, hcattr, log_max_flow_meter);
 812                 attr->qos.flow_meter_reg_c_ids =
 813                                 MLX5_GET(qos_cap, hcattr, flow_meter_reg_id);
 814                 attr->qos.flow_meter =
 815                                 MLX5_GET(qos_cap, hcattr, flow_meter);
 816                 attr->qos.packet_pacing =
 817                                 MLX5_GET(qos_cap, hcattr, packet_pacing);
 818                 attr->qos.wqe_rate_pp =
 819                                 MLX5_GET(qos_cap, hcattr, wqe_rate_pp);
 820                 if (attr->qos.flow_meter_aso_sup) {
 821                         attr->qos.log_meter_aso_granularity =
 822                                 MLX5_GET(qos_cap, hcattr,
 823                                         log_meter_aso_granularity);
 824                         attr->qos.log_meter_aso_max_alloc =
 825                                 MLX5_GET(qos_cap, hcattr,
 826                                         log_meter_aso_max_alloc);
 827                         attr->qos.log_max_num_meter_aso =
 828                                 MLX5_GET(qos_cap, hcattr,
 829                                         log_max_num_meter_aso);
 830                 }
 831         }
 832         if (attr->vdpa.valid)
 833                 mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa);
 834         if (!attr->eth_net_offloads)
 835                 return 0;
 836
 837         /* Query Flow Sampler Capability From FLow Table Properties Layout. */
 838         memset(in, 0, sizeof(in));
 839         memset(out, 0, sizeof(out));
 840         MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
 841         MLX5_SET(query_hca_cap_in, in, op_mod,
 842                  MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE |
 843                  MLX5_HCA_CAP_OPMOD_GET_CUR);
 844
 845         rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
 846         if (rc)
 847                 goto error;
 848         status = MLX5_GET(query_hca_cap_out, out, status);
 849         syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
 850         if (status) {
 851                 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, "
 852                         "status %x, syndrome = %x", status, syndrome);
 853                 attr->log_max_ft_sampler_num = 0;
 854                 return -1;
 855         }
 856         hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 857         attr->log_max_ft_sampler_num =
 858                         MLX5_GET(flow_table_nic_cap,
 859                         hcattr, flow_table_properties.log_max_ft_sampler_num);
 860
 861         /* Query HCA offloads for Ethernet protocol. */
 862         memset(in, 0, sizeof(in));
 863         memset(out, 0, sizeof(out));
 864         MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
 865         MLX5_SET(query_hca_cap_in, in, op_mod,
 866                  MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS |
 867                  MLX5_HCA_CAP_OPMOD_GET_CUR);
 868
 869         rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
 870         if (rc) {
 871                 attr->eth_net_offloads = 0;
 872                 goto error;
 873         }
 874         status = MLX5_GET(query_hca_cap_out, out, status);
 875         syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
 876         if (status) {
 877                 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, "
 878                         "status %x, syndrome = %x", status, syndrome);
 879                 attr->eth_net_offloads = 0;
 880                 return -1;
 881         }
 882         hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 883         attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps,
 884                                          hcattr, wqe_vlan_insert);
 885         attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr,
 886                                  lro_cap);
 887         attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps,
 888                                         hcattr, tunnel_lro_gre);
 889         attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps,
 890                                           hcattr, tunnel_lro_vxlan);
 891         attr->lro_max_msg_sz_mode = MLX5_GET
 892                                         (per_protocol_networking_offload_caps,
 893                                          hcattr, lro_max_msg_sz_mode);
 894         for (i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) {
 895                 attr->lro_timer_supported_periods[i] =
 896                         MLX5_GET(per_protocol_networking_offload_caps, hcattr,
 897                                  lro_timer_supported_periods[i]);
 898         }
 899         attr->lro_min_mss_size = MLX5_GET(per_protocol_networking_offload_caps,
 900                                           hcattr, lro_min_mss_size);
 901         attr->tunnel_stateless_geneve_rx =
 902                             MLX5_GET(per_protocol_networking_offload_caps,
 903                                      hcattr, tunnel_stateless_geneve_rx);
 904         attr->geneve_max_opt_len =
 905                     MLX5_GET(per_protocol_networking_offload_caps,
 906                              hcattr, max_geneve_opt_len);
 907         attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps,
 908                                          hcattr, wqe_inline_mode);
 909         attr->tunnel_stateless_gtp = MLX5_GET
 910                                         (per_protocol_networking_offload_caps,
 911                                          hcattr, tunnel_stateless_gtp);
 912         attr->rss_ind_tbl_cap = MLX5_GET
 913                                         (per_protocol_networking_offload_caps,
 914                                          hcattr, rss_ind_tbl_cap);
 915         /* Query HCA attribute for ROCE. */
 916         if (attr->roce) {
 917                 memset(in, 0, sizeof(in));
 918                 memset(out, 0, sizeof(out));
 919                 MLX5_SET(query_hca_cap_in, in, opcode,
 920                          MLX5_CMD_OP_QUERY_HCA_CAP);
 921                 MLX5_SET(query_hca_cap_in, in, op_mod,
 922                          MLX5_GET_HCA_CAP_OP_MOD_ROCE |
 923                          MLX5_HCA_CAP_OPMOD_GET_CUR);
 924                 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in),
 925                                                  out, sizeof(out));
 926                 if (rc)
 927                         goto error;
 928                 status = MLX5_GET(query_hca_cap_out, out, status);
 929                 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
 930                 if (status) {
 931                         DRV_LOG(DEBUG,
 932                                 "Failed to query devx HCA ROCE capabilities, "
 933                                 "status %x, syndrome = %x", status, syndrome);
 934                         return -1;
 935                 }
 936                 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 937                 attr->qp_ts_format = MLX5_GET(roce_caps, hcattr, qp_ts_format);
 938         }
 939         if (attr->eth_virt &&
 940             attr->wqe_inline_mode == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT) {
 941                 rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr);
 942                 if (rc) {
 943                         attr->eth_virt = 0;
 944                         goto error;
 945                 }
 946         }
 947         return 0;
 948 error:
 949         rc = (rc > 0) ? -rc : rc;
 950         return rc;
 951 }
 952
 953 /**
 954  * Query TIS transport domain from QP verbs object using DevX API.
 955  *
 956  * @param[in] qp
 957  *   Pointer to verbs QP returned by ibv_create_qp .
 958  * @param[in] tis_num
 959  *   TIS number of TIS to query.
 960  * @param[out] tis_td
 961  *   Pointer to TIS transport domain variable, to be set by the routine.
 962  *
 963  * @return
 964  *   0 on success, a negative value otherwise.
 965  */
 966 int
 967 mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num,
 968                               uint32_t *tis_td)
 969 {
 970 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 971         uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0};
 972         uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0};
 973         int rc;
 974         void *tis_ctx;
 975
 976         MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS);
 977         MLX5_SET(query_tis_in, in, tisn, tis_num);
 978         rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out));
 979         if (rc) {
 980                 DRV_LOG(ERR, "Failed to query QP using DevX");
 981                 return -rc;
 982         };
 983         tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context);
 984         *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain);
 985         return 0;
 986 #else
 987         (void)qp;
 988         (void)tis_num;
 989         (void)tis_td;
 990         return -ENOTSUP;
 991 #endif
 992 }
 993
 994 /**
 995  * Fill WQ data for DevX API command.
 996  * Utility function for use when creating DevX objects containing a WQ.
 997  *
 998  * @param[in] wq_ctx
 999  *   Pointer to WQ context to fill with data.
1000  * @param [in] wq_attr
1001  *   Pointer to WQ attributes structure to fill in WQ context.
1002  */
1003 static void
1004 devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr)
1005 {
1006         MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type);
1007         MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature);
1008         MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode);
1009         MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave);
1010         MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge);
1011         MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size);
1012         MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset);
1013         MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm);
1014         MLX5_SET(wq, wq_ctx, pd, wq_attr->pd);
1015         MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page);
1016         MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr);
1017         MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter);
1018         MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter);
1019         MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride);
1020         if (wq_attr->log_wq_pg_sz > MLX5_ADAPTER_PAGE_SHIFT)
1021                 MLX5_SET(wq, wq_ctx, log_wq_pg_sz,
1022                          wq_attr->log_wq_pg_sz - MLX5_ADAPTER_PAGE_SHIFT);
1023         MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz);
1024         MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid);
1025         MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid);
1026         MLX5_SET(wq, wq_ctx, log_hairpin_num_packets,
1027                  wq_attr->log_hairpin_num_packets);
1028         MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz);
1029         MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides,
1030                  wq_attr->single_wqe_log_num_of_strides);
1031         MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en);
1032         MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes,
1033                  wq_attr->single_stride_log_num_of_bytes);
1034         MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id);
1035         MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id);
1036         MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset);
1037 }
1038
1039 /**
1040  * Create RQ using DevX API.
1041  *
1042  * @param[in] ctx
1043  *   Context returned from mlx5 open_device() glue function.
1044  * @param [in] rq_attr
1045  *   Pointer to create RQ attributes structure.
1046  * @param [in] socket
1047  *   CPU socket ID for allocations.
1048  *
1049  * @return
1050  *   The DevX object created, NULL otherwise and rte_errno is set.
1051  */
1052 struct mlx5_devx_obj *
1053 mlx5_devx_cmd_create_rq(void *ctx,
1054                         struct mlx5_devx_create_rq_attr *rq_attr,
1055                         int socket)
1056 {
1057         uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0};
1058         uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0};
1059         void *rq_ctx, *wq_ctx;
1060         struct mlx5_devx_wq_attr *wq_attr;
1061         struct mlx5_devx_obj *rq = NULL;
1062
1063         rq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rq), 0, socket);
1064         if (!rq) {
1065                 DRV_LOG(ERR, "Failed to allocate RQ data");
1066                 rte_errno = ENOMEM;
1067                 return NULL;
1068         }
1069         MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ);
1070         rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx);
1071         MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky);
1072         MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en);
1073         MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);
1074         MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);
1075         MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type);
1076         MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
1077         MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en);
1078         MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin);
1079         MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index);
1080         MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn);
1081         MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
1082         MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn);
1083         MLX5_SET(sqc, rq_ctx, ts_format, rq_attr->ts_format);
1084         wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);
1085         wq_attr = &rq_attr->wq_attr;
1086         devx_cmd_fill_wq_data(wq_ctx, wq_attr);
1087         rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1088                                                   out, sizeof(out));
1089         if (!rq->obj) {
1090                 DRV_LOG(ERR, "Failed to create RQ using DevX");
1091                 rte_errno = errno;
1092                 mlx5_free(rq);
1093                 return NULL;
1094         }
1095         rq->id = MLX5_GET(create_rq_out, out, rqn);
1096         return rq;
1097 }
1098
1099 /**
1100  * Modify RQ using DevX API.
1101  *
1102  * @param[in] rq
1103  *   Pointer to RQ object structure.
1104  * @param [in] rq_attr
1105  *   Pointer to modify RQ attributes structure.
1106  *
1107  * @return
1108  *   0 on success, a negative errno value otherwise and rte_errno is set.
1109  */
1110 int
1111 mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,
1112                         struct mlx5_devx_modify_rq_attr *rq_attr)
1113 {
1114         uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0};
1115         uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0};
1116         void *rq_ctx, *wq_ctx;
1117         int ret;
1118
1119         MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ);
1120         MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state);
1121         MLX5_SET(modify_rq_in, in, rqn, rq->id);
1122         MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask);
1123         rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1124         MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
1125         if (rq_attr->modify_bitmask &
1126                         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS)
1127                 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);
1128         if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD)
1129                 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);
1130         if (rq_attr->modify_bitmask &
1131                         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID)
1132                 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
1133         MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq);
1134         MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca);
1135         if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) {
1136                 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);
1137                 MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm);
1138         }
1139         ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in),
1140                                          out, sizeof(out));
1141         if (ret) {
1142                 DRV_LOG(ERR, "Failed to modify RQ using DevX");
1143                 rte_errno = errno;
1144                 return -errno;
1145         }
1146         return ret;
1147 }
1148
1149 /**
1150  * Create TIR using DevX API.
1151  *
1152  * @param[in] ctx
1153  *  Context returned from mlx5 open_device() glue function.
1154  * @param [in] tir_attr
1155  *   Pointer to TIR attributes structure.
1156  *
1157  * @return
1158  *   The DevX object created, NULL otherwise and rte_errno is set.
1159  */
1160 struct mlx5_devx_obj *
1161 mlx5_devx_cmd_create_tir(void *ctx,
1162                          struct mlx5_devx_tir_attr *tir_attr)
1163 {
1164         uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
1165         uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0};
1166         void *tir_ctx, *outer, *inner, *rss_key;
1167         struct mlx5_devx_obj *tir = NULL;
1168
1169         tir = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tir), 0, SOCKET_ID_ANY);
1170         if (!tir) {
1171                 DRV_LOG(ERR, "Failed to allocate TIR data");
1172                 rte_errno = ENOMEM;
1173                 return NULL;
1174         }
1175         MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR);
1176         tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx);
1177         MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type);
1178         MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs,
1179                  tir_attr->lro_timeout_period_usecs);
1180         MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask);
1181         MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz);
1182         MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn);
1183         MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric);
1184         MLX5_SET(tirc, tir_ctx, tunneled_offload_en,
1185                  tir_attr->tunneled_offload_en);
1186         MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table);
1187         MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn);
1188         MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block);
1189         MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain);
1190         rss_key = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_toeplitz_key);
1191         memcpy(rss_key, tir_attr->rx_hash_toeplitz_key, MLX5_RSS_HASH_KEY_LEN);
1192         outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer);
1193         MLX5_SET(rx_hash_field_select, outer, l3_prot_type,
1194                  tir_attr->rx_hash_field_selector_outer.l3_prot_type);
1195         MLX5_SET(rx_hash_field_select, outer, l4_prot_type,
1196                  tir_attr->rx_hash_field_selector_outer.l4_prot_type);
1197         MLX5_SET(rx_hash_field_select, outer, selected_fields,
1198                  tir_attr->rx_hash_field_selector_outer.selected_fields);
1199         inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner);
1200         MLX5_SET(rx_hash_field_select, inner, l3_prot_type,
1201                  tir_attr->rx_hash_field_selector_inner.l3_prot_type);
1202         MLX5_SET(rx_hash_field_select, inner, l4_prot_type,
1203                  tir_attr->rx_hash_field_selector_inner.l4_prot_type);
1204         MLX5_SET(rx_hash_field_select, inner, selected_fields,
1205                  tir_attr->rx_hash_field_selector_inner.selected_fields);
1206         tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1207                                                    out, sizeof(out));
1208         if (!tir->obj) {
1209                 DRV_LOG(ERR, "Failed to create TIR using DevX");
1210                 rte_errno = errno;
1211                 mlx5_free(tir);
1212                 return NULL;
1213         }
1214         tir->id = MLX5_GET(create_tir_out, out, tirn);
1215         return tir;
1216 }
1217
1218 /**
1219  * Modify TIR using DevX API.
1220  *
1221  * @param[in] tir
1222  *   Pointer to TIR DevX object structure.
1223  * @param [in] modify_tir_attr
1224  *   Pointer to TIR modification attributes structure.
1225  *
1226  * @return
1227  *   0 on success, a negative errno value otherwise and rte_errno is set.
1228  */
1229 int
1230 mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir,
1231                          struct mlx5_devx_modify_tir_attr *modify_tir_attr)
1232 {
1233         struct mlx5_devx_tir_attr *tir_attr = &modify_tir_attr->tir;
1234         uint32_t in[MLX5_ST_SZ_DW(modify_tir_in)] = {0};
1235         uint32_t out[MLX5_ST_SZ_DW(modify_tir_out)] = {0};
1236         void *tir_ctx;
1237         int ret;
1238
1239         MLX5_SET(modify_tir_in, in, opcode, MLX5_CMD_OP_MODIFY_TIR);
1240         MLX5_SET(modify_tir_in, in, tirn, modify_tir_attr->tirn);
1241         MLX5_SET64(modify_tir_in, in, modify_bitmask,
1242                    modify_tir_attr->modify_bitmask);
1243         tir_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1244         if (modify_tir_attr->modify_bitmask &
1245                         MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO) {
1246                 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs,
1247                          tir_attr->lro_timeout_period_usecs);
1248                 MLX5_SET(tirc, tir_ctx, lro_enable_mask,
1249                          tir_attr->lro_enable_mask);
1250                 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz,
1251                          tir_attr->lro_max_msg_sz);
1252         }
1253         if (modify_tir_attr->modify_bitmask &
1254                         MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE)
1255                 MLX5_SET(tirc, tir_ctx, indirect_table,
1256                          tir_attr->indirect_table);
1257         if (modify_tir_attr->modify_bitmask &
1258                         MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH) {
1259                 int i;
1260                 void *outer, *inner;
1261
1262                 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric,
1263                          tir_attr->rx_hash_symmetric);
1264                 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn);
1265                 for (i = 0; i < 10; i++) {
1266                         MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i],
1267                                  tir_attr->rx_hash_toeplitz_key[i]);
1268                 }
1269                 outer = MLX5_ADDR_OF(tirc, tir_ctx,
1270                                      rx_hash_field_selector_outer);
1271                 MLX5_SET(rx_hash_field_select, outer, l3_prot_type,
1272                          tir_attr->rx_hash_field_selector_outer.l3_prot_type);
1273                 MLX5_SET(rx_hash_field_select, outer, l4_prot_type,
1274                          tir_attr->rx_hash_field_selector_outer.l4_prot_type);
1275                 MLX5_SET
1276                 (rx_hash_field_select, outer, selected_fields,
1277                  tir_attr->rx_hash_field_selector_outer.selected_fields);
1278                 inner = MLX5_ADDR_OF(tirc, tir_ctx,
1279                                      rx_hash_field_selector_inner);
1280                 MLX5_SET(rx_hash_field_select, inner, l3_prot_type,
1281                          tir_attr->rx_hash_field_selector_inner.l3_prot_type);
1282                 MLX5_SET(rx_hash_field_select, inner, l4_prot_type,
1283                          tir_attr->rx_hash_field_selector_inner.l4_prot_type);
1284                 MLX5_SET
1285                 (rx_hash_field_select, inner, selected_fields,
1286                  tir_attr->rx_hash_field_selector_inner.selected_fields);
1287         }
1288         if (modify_tir_attr->modify_bitmask &
1289             MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN) {
1290                 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block);
1291         }
1292         ret = mlx5_glue->devx_obj_modify(tir->obj, in, sizeof(in),
1293                                          out, sizeof(out));
1294         if (ret) {
1295                 DRV_LOG(ERR, "Failed to modify TIR using DevX");
1296                 rte_errno = errno;
1297                 return -errno;
1298         }
1299         return ret;
1300 }
1301
1302 /**
1303  * Create RQT using DevX API.
1304  *
1305  * @param[in] ctx
1306  *   Context returned from mlx5 open_device() glue function.
1307  * @param [in] rqt_attr
1308  *   Pointer to RQT attributes structure.
1309  *
1310  * @return
1311  *   The DevX object created, NULL otherwise and rte_errno is set.
1312  */
1313 struct mlx5_devx_obj *
1314 mlx5_devx_cmd_create_rqt(void *ctx,
1315                          struct mlx5_devx_rqt_attr *rqt_attr)
1316 {
1317         uint32_t *in = NULL;
1318         uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) +
1319                          rqt_attr->rqt_actual_size * sizeof(uint32_t);
1320         uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0};
1321         void *rqt_ctx;
1322         struct mlx5_devx_obj *rqt = NULL;
1323         int i;
1324
1325         in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY);
1326         if (!in) {
1327                 DRV_LOG(ERR, "Failed to allocate RQT IN data");
1328                 rte_errno = ENOMEM;
1329                 return NULL;
1330         }
1331         rqt = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt), 0, SOCKET_ID_ANY);
1332         if (!rqt) {
1333                 DRV_LOG(ERR, "Failed to allocate RQT data");
1334                 rte_errno = ENOMEM;
1335                 mlx5_free(in);
1336                 return NULL;
1337         }
1338         MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
1339         rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1340         MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type);
1341         MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size);
1342         MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size);
1343         for (i = 0; i < rqt_attr->rqt_actual_size; i++)
1344                 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]);
1345         rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out));
1346         mlx5_free(in);
1347         if (!rqt->obj) {
1348                 DRV_LOG(ERR, "Failed to create RQT using DevX");
1349                 rte_errno = errno;
1350                 mlx5_free(rqt);
1351                 return NULL;
1352         }
1353         rqt->id = MLX5_GET(create_rqt_out, out, rqtn);
1354         return rqt;
1355 }
1356
1357 /**
1358  * Modify RQT using DevX API.
1359  *
1360  * @param[in] rqt
1361  *   Pointer to RQT DevX object structure.
1362  * @param [in] rqt_attr
1363  *   Pointer to RQT attributes structure.
1364  *
1365  * @return
1366  *   0 on success, a negative errno value otherwise and rte_errno is set.
1367  */
1368 int
1369 mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt,
1370                          struct mlx5_devx_rqt_attr *rqt_attr)
1371 {
1372         uint32_t inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) +
1373                          rqt_attr->rqt_actual_size * sizeof(uint32_t);
1374         uint32_t out[MLX5_ST_SZ_DW(modify_rqt_out)] = {0};
1375         uint32_t *in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY);
1376         void *rqt_ctx;
1377         int i;
1378         int ret;
1379
1380         if (!in) {
1381                 DRV_LOG(ERR, "Failed to allocate RQT modify IN data.");
1382                 rte_errno = ENOMEM;
1383                 return -ENOMEM;
1384         }
1385         MLX5_SET(modify_rqt_in, in, opcode, MLX5_CMD_OP_MODIFY_RQT);
1386         MLX5_SET(modify_rqt_in, in, rqtn, rqt->id);
1387         MLX5_SET64(modify_rqt_in, in, modify_bitmask, 0x1);
1388         rqt_ctx = MLX5_ADDR_OF(modify_rqt_in, in, rqt_context);
1389         MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type);
1390         MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size);
1391         MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size);
1392         for (i = 0; i < rqt_attr->rqt_actual_size; i++)
1393                 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]);
1394         ret = mlx5_glue->devx_obj_modify(rqt->obj, in, inlen, out, sizeof(out));
1395         mlx5_free(in);
1396         if (ret) {
1397                 DRV_LOG(ERR, "Failed to modify RQT using DevX.");
1398                 rte_errno = errno;
1399                 return -rte_errno;
1400         }
1401         return ret;
1402 }
1403
1404 /**
1405  * Create SQ using DevX API.
1406  *
1407  * @param[in] ctx
1408  *   Context returned from mlx5 open_device() glue function.
1409  * @param [in] sq_attr
1410  *   Pointer to SQ attributes structure.
1411  * @param [in] socket
1412  *   CPU socket ID for allocations.
1413  *
1414  * @return
1415  *   The DevX object created, NULL otherwise and rte_errno is set.
1416  **/
1417 struct mlx5_devx_obj *
1418 mlx5_devx_cmd_create_sq(void *ctx,
1419                         struct mlx5_devx_create_sq_attr *sq_attr)
1420 {
1421         uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0};
1422         uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0};
1423         void *sq_ctx;
1424         void *wq_ctx;
1425         struct mlx5_devx_wq_attr *wq_attr;
1426         struct mlx5_devx_obj *sq = NULL;
1427
1428         sq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sq), 0, SOCKET_ID_ANY);
1429         if (!sq) {
1430                 DRV_LOG(ERR, "Failed to allocate SQ data");
1431                 rte_errno = ENOMEM;
1432                 return NULL;
1433         }
1434         MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ);
1435         sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx);
1436         MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky);
1437         MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master);
1438         MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre);
1439         MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en);
1440         MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe,
1441                  sq_attr->allow_multi_pkt_send_wqe);
1442         MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode,
1443                  sq_attr->min_wqe_inline_mode);
1444         MLX5_SET(sqc, sq_ctx, state, sq_attr->state);
1445         MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr);
1446         MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp);
1447         MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin);
1448         MLX5_SET(sqc, sq_ctx, non_wire, sq_attr->non_wire);
1449         MLX5_SET(sqc, sq_ctx, static_sq_wq, sq_attr->static_sq_wq);
1450         MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index);
1451         MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn);
1452         MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index,
1453                  sq_attr->packet_pacing_rate_limit_index);
1454         MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz);
1455         MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num);
1456         MLX5_SET(sqc, sq_ctx, ts_format, sq_attr->ts_format);
1457         wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq);
1458         wq_attr = &sq_attr->wq_attr;
1459         devx_cmd_fill_wq_data(wq_ctx, wq_attr);
1460         sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1461                                              out, sizeof(out));
1462         if (!sq->obj) {
1463                 DRV_LOG(ERR, "Failed to create SQ using DevX");
1464                 rte_errno = errno;
1465                 mlx5_free(sq);
1466                 return NULL;
1467         }
1468         sq->id = MLX5_GET(create_sq_out, out, sqn);
1469         return sq;
1470 }
1471
1472 /**
1473  * Modify SQ using DevX API.
1474  *
1475  * @param[in] sq
1476  *   Pointer to SQ object structure.
1477  * @param [in] sq_attr
1478  *   Pointer to SQ attributes structure.
1479  *
1480  * @return
1481  *   0 on success, a negative errno value otherwise and rte_errno is set.
1482  */
1483 int
1484 mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq,
1485                         struct mlx5_devx_modify_sq_attr *sq_attr)
1486 {
1487         uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0};
1488         uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0};
1489         void *sq_ctx;
1490         int ret;
1491
1492         MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ);
1493         MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state);
1494         MLX5_SET(modify_sq_in, in, sqn, sq->id);
1495         sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1496         MLX5_SET(sqc, sq_ctx, state, sq_attr->state);
1497         MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq);
1498         MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca);
1499         ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in),
1500                                          out, sizeof(out));
1501         if (ret) {
1502                 DRV_LOG(ERR, "Failed to modify SQ using DevX");
1503                 rte_errno = errno;
1504                 return -rte_errno;
1505         }
1506         return ret;
1507 }
1508
1509 /**
1510  * Create TIS using DevX API.
1511  *
1512  * @param[in] ctx
1513  *   Context returned from mlx5 open_device() glue function.
1514  * @param [in] tis_attr
1515  *   Pointer to TIS attributes structure.
1516  *
1517  * @return
1518  *   The DevX object created, NULL otherwise and rte_errno is set.
1519  */
1520 struct mlx5_devx_obj *
1521 mlx5_devx_cmd_create_tis(void *ctx,
1522                          struct mlx5_devx_tis_attr *tis_attr)
1523 {
1524         uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
1525         uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0};
1526         struct mlx5_devx_obj *tis = NULL;
1527         void *tis_ctx;
1528
1529         tis = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tis), 0, SOCKET_ID_ANY);
1530         if (!tis) {
1531                 DRV_LOG(ERR, "Failed to allocate TIS object");
1532                 rte_errno = ENOMEM;
1533                 return NULL;
1534         }
1535         MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS);
1536         tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx);
1537         MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity,
1538                  tis_attr->strict_lag_tx_port_affinity);
1539         MLX5_SET(tisc, tis_ctx, lag_tx_port_affinity,
1540                  tis_attr->lag_tx_port_affinity);
1541         MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio);
1542         MLX5_SET(tisc, tis_ctx, transport_domain,
1543                  tis_attr->transport_domain);
1544         tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1545                                               out, sizeof(out));
1546         if (!tis->obj) {
1547                 DRV_LOG(ERR, "Failed to create TIS using DevX");
1548                 rte_errno = errno;
1549                 mlx5_free(tis);
1550                 return NULL;
1551         }
1552         tis->id = MLX5_GET(create_tis_out, out, tisn);
1553         return tis;
1554 }
1555
1556 /**
1557  * Create transport domain using DevX API.
1558  *
1559  * @param[in] ctx
1560  *   Context returned from mlx5 open_device() glue function.
1561  * @return
1562  *   The DevX object created, NULL otherwise and rte_errno is set.
1563  */
1564 struct mlx5_devx_obj *
1565 mlx5_devx_cmd_create_td(void *ctx)
1566 {
1567         uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0};
1568         uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0};
1569         struct mlx5_devx_obj *td = NULL;
1570
1571         td = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*td), 0, SOCKET_ID_ANY);
1572         if (!td) {
1573                 DRV_LOG(ERR, "Failed to allocate TD object");
1574                 rte_errno = ENOMEM;
1575                 return NULL;
1576         }
1577         MLX5_SET(alloc_transport_domain_in, in, opcode,
1578                  MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN);
1579         td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1580                                              out, sizeof(out));
1581         if (!td->obj) {
1582                 DRV_LOG(ERR, "Failed to create TIS using DevX");
1583                 rte_errno = errno;
1584                 mlx5_free(td);
1585                 return NULL;
1586         }
1587         td->id = MLX5_GET(alloc_transport_domain_out, out,
1588                            transport_domain);
1589         return td;
1590 }
1591
1592 /**
1593  * Dump all flows to file.
1594  *
1595  * @param[in] fdb_domain
1596  *   FDB domain.
1597  * @param[in] rx_domain
1598  *   RX domain.
1599  * @param[in] tx_domain
1600  *   TX domain.
1601  * @param[out] file
1602  *   Pointer to file stream.
1603  *
1604  * @return
1605  *   0 on success, a nagative value otherwise.
1606  */
1607 int
1608 mlx5_devx_cmd_flow_dump(void *fdb_domain __rte_unused,
1609                         void *rx_domain __rte_unused,
1610                         void *tx_domain __rte_unused, FILE *file __rte_unused)
1611 {
1612         int ret = 0;
1613
1614 #ifdef HAVE_MLX5_DR_FLOW_DUMP
1615         if (fdb_domain) {
1616                 ret = mlx5_glue->dr_dump_domain(file, fdb_domain);
1617                 if (ret)
1618                         return ret;
1619         }
1620         MLX5_ASSERT(rx_domain);
1621         ret = mlx5_glue->dr_dump_domain(file, rx_domain);
1622         if (ret)
1623                 return ret;
1624         MLX5_ASSERT(tx_domain);
1625         ret = mlx5_glue->dr_dump_domain(file, tx_domain);
1626 #else
1627         ret = ENOTSUP;
1628 #endif
1629         return -ret;
1630 }
1631
1632 int
1633 mlx5_devx_cmd_flow_single_dump(void *rule_info __rte_unused,
1634                         FILE *file __rte_unused)
1635 {
1636         int ret = 0;
1637 #ifdef HAVE_MLX5_DR_FLOW_DUMP_RULE
1638         if (rule_info)
1639                 ret = mlx5_glue->dr_dump_rule(file, rule_info);
1640 #else
1641         ret = ENOTSUP;
1642 #endif
1643         return -ret;
1644 }
1645
1646 /*
1647  * Create CQ using DevX API.
1648  *
1649  * @param[in] ctx
1650  *   Context returned from mlx5 open_device() glue function.
1651  * @param [in] attr
1652  *   Pointer to CQ attributes structure.
1653  *
1654  * @return
1655  *   The DevX object created, NULL otherwise and rte_errno is set.
1656  */
1657 struct mlx5_devx_obj *
1658 mlx5_devx_cmd_create_cq(void *ctx, struct mlx5_devx_cq_attr *attr)
1659 {
1660         uint32_t in[MLX5_ST_SZ_DW(create_cq_in)] = {0};
1661         uint32_t out[MLX5_ST_SZ_DW(create_cq_out)] = {0};
1662         struct mlx5_devx_obj *cq_obj = mlx5_malloc(MLX5_MEM_ZERO,
1663                                                    sizeof(*cq_obj),
1664                                                    0, SOCKET_ID_ANY);
1665         void *cqctx = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1666
1667         if (!cq_obj) {
1668                 DRV_LOG(ERR, "Failed to allocate CQ object memory.");
1669                 rte_errno = ENOMEM;
1670                 return NULL;
1671         }
1672         MLX5_SET(create_cq_in, in, opcode, MLX5_CMD_OP_CREATE_CQ);
1673         if (attr->db_umem_valid) {
1674                 MLX5_SET(cqc, cqctx, dbr_umem_valid, attr->db_umem_valid);
1675                 MLX5_SET(cqc, cqctx, dbr_umem_id, attr->db_umem_id);
1676                 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_umem_offset);
1677         } else {
1678                 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_addr);
1679         }
1680         MLX5_SET(cqc, cqctx, cqe_sz, (RTE_CACHE_LINE_SIZE == 128) ?
1681                                      MLX5_CQE_SIZE_128B : MLX5_CQE_SIZE_64B);
1682         MLX5_SET(cqc, cqctx, cc, attr->use_first_only);
1683         MLX5_SET(cqc, cqctx, oi, attr->overrun_ignore);
1684         MLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size);
1685         if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT)
1686                 MLX5_SET(cqc, cqctx, log_page_size,
1687                          attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT);
1688         MLX5_SET(cqc, cqctx, c_eqn, attr->eqn);
1689         MLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id);
1690         MLX5_SET(cqc, cqctx, cqe_comp_en, !!attr->cqe_comp_en);
1691         MLX5_SET(cqc, cqctx, mini_cqe_res_format, attr->mini_cqe_res_format);
1692         MLX5_SET(cqc, cqctx, mini_cqe_res_format_ext,
1693                  attr->mini_cqe_res_format_ext);
1694         if (attr->q_umem_valid) {
1695                 MLX5_SET(create_cq_in, in, cq_umem_valid, attr->q_umem_valid);
1696                 MLX5_SET(create_cq_in, in, cq_umem_id, attr->q_umem_id);
1697                 MLX5_SET64(create_cq_in, in, cq_umem_offset,
1698                            attr->q_umem_offset);
1699         }
1700         cq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
1701                                                  sizeof(out));
1702         if (!cq_obj->obj) {
1703                 rte_errno = errno;
1704                 DRV_LOG(ERR, "Failed to create CQ using DevX errno=%d.", errno);
1705                 mlx5_free(cq_obj);
1706                 return NULL;
1707         }
1708         cq_obj->id = MLX5_GET(create_cq_out, out, cqn);
1709         return cq_obj;
1710 }
1711
1712 /**
1713  * Create VIRTQ using DevX API.
1714  *
1715  * @param[in] ctx
1716  *   Context returned from mlx5 open_device() glue function.
1717  * @param [in] attr
1718  *   Pointer to VIRTQ attributes structure.
1719  *
1720  * @return
1721  *   The DevX object created, NULL otherwise and rte_errno is set.
1722  */
1723 struct mlx5_devx_obj *
1724 mlx5_devx_cmd_create_virtq(void *ctx,
1725                            struct mlx5_devx_virtq_attr *attr)
1726 {
1727         uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0};
1728         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
1729         struct mlx5_devx_obj *virtq_obj = mlx5_malloc(MLX5_MEM_ZERO,
1730                                                      sizeof(*virtq_obj),
1731                                                      0, SOCKET_ID_ANY);
1732         void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq);
1733         void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr);
1734         void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context);
1735
1736         if (!virtq_obj) {
1737                 DRV_LOG(ERR, "Failed to allocate virtq data.");
1738                 rte_errno = ENOMEM;
1739                 return NULL;
1740         }
1741         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
1742                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
1743         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
1744                  MLX5_GENERAL_OBJ_TYPE_VIRTQ);
1745         MLX5_SET16(virtio_net_q, virtq, hw_available_index,
1746                    attr->hw_available_index);
1747         MLX5_SET16(virtio_net_q, virtq, hw_used_index, attr->hw_used_index);
1748         MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4);
1749         MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6);
1750         MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum);
1751         MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum);
1752         MLX5_SET16(virtio_q, virtctx, virtio_version_1_0,
1753                    attr->virtio_version_1_0);
1754         MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode);
1755         MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id);
1756         MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr);
1757         MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr);
1758         MLX5_SET64(virtio_q, virtctx, available_addr, attr->available_addr);
1759         MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index);
1760         MLX5_SET16(virtio_q, virtctx, queue_size, attr->q_size);
1761         MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey);
1762         MLX5_SET(virtio_q, virtctx, umem_1_id, attr->umems[0].id);
1763         MLX5_SET(virtio_q, virtctx, umem_1_size, attr->umems[0].size);
1764         MLX5_SET64(virtio_q, virtctx, umem_1_offset, attr->umems[0].offset);
1765         MLX5_SET(virtio_q, virtctx, umem_2_id, attr->umems[1].id);
1766         MLX5_SET(virtio_q, virtctx, umem_2_size, attr->umems[1].size);
1767         MLX5_SET64(virtio_q, virtctx, umem_2_offset, attr->umems[1].offset);
1768         MLX5_SET(virtio_q, virtctx, umem_3_id, attr->umems[2].id);
1769         MLX5_SET(virtio_q, virtctx, umem_3_size, attr->umems[2].size);
1770         MLX5_SET64(virtio_q, virtctx, umem_3_offset, attr->umems[2].offset);
1771         MLX5_SET(virtio_q, virtctx, counter_set_id, attr->counters_obj_id);
1772         MLX5_SET(virtio_q, virtctx, pd, attr->pd);
1773         MLX5_SET(virtio_q, virtctx, queue_period_mode, attr->hw_latency_mode);
1774         MLX5_SET(virtio_q, virtctx, queue_period_us, attr->hw_max_latency_us);
1775         MLX5_SET(virtio_q, virtctx, queue_max_count, attr->hw_max_pending_comp);
1776         MLX5_SET(virtio_net_q, virtq, tisn_or_qpn, attr->tis_id);
1777         virtq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
1778                                                     sizeof(out));
1779         if (!virtq_obj->obj) {
1780                 rte_errno = errno;
1781                 DRV_LOG(ERR, "Failed to create VIRTQ Obj using DevX.");
1782                 mlx5_free(virtq_obj);
1783                 return NULL;
1784         }
1785         virtq_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
1786         return virtq_obj;
1787 }
1788
1789 /**
1790  * Modify VIRTQ using DevX API.
1791  *
1792  * @param[in] virtq_obj
1793  *   Pointer to virtq object structure.
1794  * @param [in] attr
1795  *   Pointer to modify virtq attributes structure.
1796  *
1797  * @return
1798  *   0 on success, a negative errno value otherwise and rte_errno is set.
1799  */
1800 int
1801 mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj,
1802                            struct mlx5_devx_virtq_attr *attr)
1803 {
1804         uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0};
1805         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
1806         void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq);
1807         void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr);
1808         void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context);
1809         int ret;
1810
1811         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
1812                  MLX5_CMD_OP_MODIFY_GENERAL_OBJECT);
1813         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
1814                  MLX5_GENERAL_OBJ_TYPE_VIRTQ);
1815         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id);
1816         MLX5_SET64(virtio_net_q, virtq, modify_field_select, attr->type);
1817         MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index);
1818         switch (attr->type) {
1819         case MLX5_VIRTQ_MODIFY_TYPE_STATE:
1820                 MLX5_SET16(virtio_net_q, virtq, state, attr->state);
1821                 break;
1822         case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS:
1823                 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_mkey,
1824                          attr->dirty_bitmap_mkey);
1825                 MLX5_SET64(virtio_net_q, virtq, dirty_bitmap_addr,
1826                          attr->dirty_bitmap_addr);
1827                 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_size,
1828                          attr->dirty_bitmap_size);
1829                 break;
1830         case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE:
1831                 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_dump_enable,
1832                          attr->dirty_bitmap_dump_enable);
1833                 break;
1834         default:
1835                 rte_errno = EINVAL;
1836                 return -rte_errno;
1837         }
1838         ret = mlx5_glue->devx_obj_modify(virtq_obj->obj, in, sizeof(in),
1839                                          out, sizeof(out));
1840         if (ret) {
1841                 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX.");
1842                 rte_errno = errno;
1843                 return -rte_errno;
1844         }
1845         return ret;
1846 }
1847
1848 /**
1849  * Query VIRTQ using DevX API.
1850  *
1851  * @param[in] virtq_obj
1852  *   Pointer to virtq object structure.
1853  * @param [in/out] attr
1854  *   Pointer to virtq attributes structure.
1855  *
1856  * @return
1857  *   0 on success, a negative errno value otherwise and rte_errno is set.
1858  */
1859 int
1860 mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj,
1861                            struct mlx5_devx_virtq_attr *attr)
1862 {
1863         uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
1864         uint32_t out[MLX5_ST_SZ_DW(query_virtq_out)] = {0};
1865         void *hdr = MLX5_ADDR_OF(query_virtq_out, in, hdr);
1866         void *virtq = MLX5_ADDR_OF(query_virtq_out, out, virtq);
1867         int ret;
1868
1869         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
1870                  MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
1871         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
1872                  MLX5_GENERAL_OBJ_TYPE_VIRTQ);
1873         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id);
1874         ret = mlx5_glue->devx_obj_query(virtq_obj->obj, in, sizeof(in),
1875                                          out, sizeof(out));
1876         if (ret) {
1877                 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX.");
1878                 rte_errno = errno;
1879                 return -errno;
1880         }
1881         attr->hw_available_index = MLX5_GET16(virtio_net_q, virtq,
1882                                               hw_available_index);
1883         attr->hw_used_index = MLX5_GET16(virtio_net_q, virtq, hw_used_index);
1884         attr->state = MLX5_GET16(virtio_net_q, virtq, state);
1885         attr->error_type = MLX5_GET16(virtio_net_q, virtq,
1886                                       virtio_q_context.error_type);
1887         return ret;
1888 }
1889
1890 /**
1891  * Create QP using DevX API.
1892  *
1893  * @param[in] ctx
1894  *   Context returned from mlx5 open_device() glue function.
1895  * @param [in] attr
1896  *   Pointer to QP attributes structure.
1897  *
1898  * @return
1899  *   The DevX object created, NULL otherwise and rte_errno is set.
1900  */
1901 struct mlx5_devx_obj *
1902 mlx5_devx_cmd_create_qp(void *ctx,
1903                         struct mlx5_devx_qp_attr *attr)
1904 {
1905         uint32_t in[MLX5_ST_SZ_DW(create_qp_in)] = {0};
1906         uint32_t out[MLX5_ST_SZ_DW(create_qp_out)] = {0};
1907         struct mlx5_devx_obj *qp_obj = mlx5_malloc(MLX5_MEM_ZERO,
1908                                                    sizeof(*qp_obj),
1909                                                    0, SOCKET_ID_ANY);
1910         void *qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1911
1912         if (!qp_obj) {
1913                 DRV_LOG(ERR, "Failed to allocate QP data.");
1914                 rte_errno = ENOMEM;
1915                 return NULL;
1916         }
1917         MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP);
1918         MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC);
1919         MLX5_SET(qpc, qpc, pd, attr->pd);
1920         MLX5_SET(qpc, qpc, ts_format, attr->ts_format);
1921         if (attr->uar_index) {
1922                 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
1923                 MLX5_SET(qpc, qpc, uar_page, attr->uar_index);
1924                 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT)
1925                         MLX5_SET(qpc, qpc, log_page_size,
1926                                  attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT);
1927                 if (attr->sq_size) {
1928                         MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->sq_size));
1929                         MLX5_SET(qpc, qpc, cqn_snd, attr->cqn);
1930                         MLX5_SET(qpc, qpc, log_sq_size,
1931                                  rte_log2_u32(attr->sq_size));
1932                 } else {
1933                         MLX5_SET(qpc, qpc, no_sq, 1);
1934                 }
1935                 if (attr->rq_size) {
1936                         MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->rq_size));
1937                         MLX5_SET(qpc, qpc, cqn_rcv, attr->cqn);
1938                         MLX5_SET(qpc, qpc, log_rq_stride, attr->log_rq_stride -
1939                                  MLX5_LOG_RQ_STRIDE_SHIFT);
1940                         MLX5_SET(qpc, qpc, log_rq_size,
1941                                  rte_log2_u32(attr->rq_size));
1942                         MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ);
1943                 } else {
1944                         MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ);
1945                 }
1946                 if (attr->dbr_umem_valid) {
1947                         MLX5_SET(qpc, qpc, dbr_umem_valid,
1948                                  attr->dbr_umem_valid);
1949                         MLX5_SET(qpc, qpc, dbr_umem_id, attr->dbr_umem_id);
1950                 }
1951                 MLX5_SET64(qpc, qpc, dbr_addr, attr->dbr_address);
1952                 MLX5_SET64(create_qp_in, in, wq_umem_offset,
1953                            attr->wq_umem_offset);
1954                 MLX5_SET(create_qp_in, in, wq_umem_id, attr->wq_umem_id);
1955                 MLX5_SET(create_qp_in, in, wq_umem_valid, 1);
1956         } else {
1957                 /* Special QP to be managed by FW - no SQ\RQ\CQ\UAR\DB rec. */
1958                 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ);
1959                 MLX5_SET(qpc, qpc, no_sq, 1);
1960         }
1961         qp_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
1962                                                  sizeof(out));
1963         if (!qp_obj->obj) {
1964                 rte_errno = errno;
1965                 DRV_LOG(ERR, "Failed to create QP Obj using DevX.");
1966                 mlx5_free(qp_obj);
1967                 return NULL;
1968         }
1969         qp_obj->id = MLX5_GET(create_qp_out, out, qpn);
1970         return qp_obj;
1971 }
1972
1973 /**
1974  * Modify QP using DevX API.
1975  * Currently supports only force loop-back QP.
1976  *
1977  * @param[in] qp
1978  *   Pointer to QP object structure.
1979  * @param [in] qp_st_mod_op
1980  *   The QP state modification operation.
1981  * @param [in] remote_qp_id
1982  *   The remote QP ID for MLX5_CMD_OP_INIT2RTR_QP operation.
1983  *
1984  * @return
1985  *   0 on success, a negative errno value otherwise and rte_errno is set.
1986  */
1987 int
1988 mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op,
1989                               uint32_t remote_qp_id)
1990 {
1991         union {
1992                 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)];
1993                 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)];
1994                 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)];
1995         } in;
1996         union {
1997                 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)];
1998                 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)];
1999                 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)];
2000         } out;
2001         void *qpc;
2002         int ret;
2003         unsigned int inlen;
2004         unsigned int outlen;
2005
2006         memset(&in, 0, sizeof(in));
2007         memset(&out, 0, sizeof(out));
2008         MLX5_SET(rst2init_qp_in, &in, opcode, qp_st_mod_op);
2009         switch (qp_st_mod_op) {
2010         case MLX5_CMD_OP_RST2INIT_QP:
2011                 MLX5_SET(rst2init_qp_in, &in, qpn, qp->id);
2012                 qpc = MLX5_ADDR_OF(rst2init_qp_in, &in, qpc);
2013                 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1);
2014                 MLX5_SET(qpc, qpc, rre, 1);
2015                 MLX5_SET(qpc, qpc, rwe, 1);
2016                 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
2017                 inlen = sizeof(in.rst2init);
2018                 outlen = sizeof(out.rst2init);
2019                 break;
2020         case MLX5_CMD_OP_INIT2RTR_QP:
2021                 MLX5_SET(init2rtr_qp_in, &in, qpn, qp->id);
2022                 qpc = MLX5_ADDR_OF(init2rtr_qp_in, &in, qpc);
2023                 MLX5_SET(qpc, qpc, primary_address_path.fl, 1);
2024                 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1);
2025                 MLX5_SET(qpc, qpc, mtu, 1);
2026                 MLX5_SET(qpc, qpc, log_msg_max, 30);
2027                 MLX5_SET(qpc, qpc, remote_qpn, remote_qp_id);
2028                 MLX5_SET(qpc, qpc, min_rnr_nak, 0);
2029                 inlen = sizeof(in.init2rtr);
2030                 outlen = sizeof(out.init2rtr);
2031                 break;
2032         case MLX5_CMD_OP_RTR2RTS_QP:
2033                 qpc = MLX5_ADDR_OF(rtr2rts_qp_in, &in, qpc);
2034                 MLX5_SET(rtr2rts_qp_in, &in, qpn, qp->id);
2035                 MLX5_SET(qpc, qpc, primary_address_path.ack_timeout, 14);
2036                 MLX5_SET(qpc, qpc, log_ack_req_freq, 0);
2037                 MLX5_SET(qpc, qpc, retry_count, 7);
2038                 MLX5_SET(qpc, qpc, rnr_retry, 7);
2039                 inlen = sizeof(in.rtr2rts);
2040                 outlen = sizeof(out.rtr2rts);
2041                 break;
2042         default:
2043                 DRV_LOG(ERR, "Invalid or unsupported QP modify op %u.",
2044                         qp_st_mod_op);
2045                 rte_errno = EINVAL;
2046                 return -rte_errno;
2047         }
2048         ret = mlx5_glue->devx_obj_modify(qp->obj, &in, inlen, &out, outlen);
2049         if (ret) {
2050                 DRV_LOG(ERR, "Failed to modify QP using DevX.");
2051                 rte_errno = errno;
2052                 return -rte_errno;
2053         }
2054         return ret;
2055 }
2056
2057 struct mlx5_devx_obj *
2058 mlx5_devx_cmd_create_virtio_q_counters(void *ctx)
2059 {
2060         uint32_t in[MLX5_ST_SZ_DW(create_virtio_q_counters_in)] = {0};
2061         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2062         struct mlx5_devx_obj *couners_obj = mlx5_malloc(MLX5_MEM_ZERO,
2063                                                        sizeof(*couners_obj), 0,
2064                                                        SOCKET_ID_ANY);
2065         void *hdr = MLX5_ADDR_OF(create_virtio_q_counters_in, in, hdr);
2066
2067         if (!couners_obj) {
2068                 DRV_LOG(ERR, "Failed to allocate virtio queue counters data.");
2069                 rte_errno = ENOMEM;
2070                 return NULL;
2071         }
2072         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2073                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2074         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2075                  MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS);
2076         couners_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
2077                                                       sizeof(out));
2078         if (!couners_obj->obj) {
2079                 rte_errno = errno;
2080                 DRV_LOG(ERR, "Failed to create virtio queue counters Obj using"
2081                         " DevX.");
2082                 mlx5_free(couners_obj);
2083                 return NULL;
2084         }
2085         couners_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2086         return couners_obj;
2087 }
2088
2089 int
2090 mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj,
2091                                    struct mlx5_devx_virtio_q_couners_attr *attr)
2092 {
2093         uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
2094         uint32_t out[MLX5_ST_SZ_DW(query_virtio_q_counters_out)] = {0};
2095         void *hdr = MLX5_ADDR_OF(query_virtio_q_counters_out, in, hdr);
2096         void *virtio_q_counters = MLX5_ADDR_OF(query_virtio_q_counters_out, out,
2097                                                virtio_q_counters);
2098         int ret;
2099
2100         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2101                  MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
2102         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2103                  MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS);
2104         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, couners_obj->id);
2105         ret = mlx5_glue->devx_obj_query(couners_obj->obj, in, sizeof(in), out,
2106                                         sizeof(out));
2107         if (ret) {
2108                 DRV_LOG(ERR, "Failed to query virtio q counters using DevX.");
2109                 rte_errno = errno;
2110                 return -errno;
2111         }
2112         attr->received_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters,
2113                                          received_desc);
2114         attr->completed_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters,
2115                                           completed_desc);
2116         attr->error_cqes = MLX5_GET(virtio_q_counters, virtio_q_counters,
2117                                     error_cqes);
2118         attr->bad_desc_errors = MLX5_GET(virtio_q_counters, virtio_q_counters,
2119                                          bad_desc_errors);
2120         attr->exceed_max_chain = MLX5_GET(virtio_q_counters, virtio_q_counters,
2121                                           exceed_max_chain);
2122         attr->invalid_buffer = MLX5_GET(virtio_q_counters, virtio_q_counters,
2123                                         invalid_buffer);
2124         return ret;
2125 }
2126
2127 /**
2128  * Create general object of type FLOW_HIT_ASO using DevX API.
2129  *
2130  * @param[in] ctx
2131  *   Context returned from mlx5 open_device() glue function.
2132  * @param [in] pd
2133  *   PD value to associate the FLOW_HIT_ASO object with.
2134  *
2135  * @return
2136  *   The DevX object created, NULL otherwise and rte_errno is set.
2137  */
2138 struct mlx5_devx_obj *
2139 mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, uint32_t pd)
2140 {
2141         uint32_t in[MLX5_ST_SZ_DW(create_flow_hit_aso_in)] = {0};
2142         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2143         struct mlx5_devx_obj *flow_hit_aso_obj = NULL;
2144         void *ptr = NULL;
2145
2146         flow_hit_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*flow_hit_aso_obj),
2147                                        0, SOCKET_ID_ANY);
2148         if (!flow_hit_aso_obj) {
2149                 DRV_LOG(ERR, "Failed to allocate FLOW_HIT_ASO object data");
2150                 rte_errno = ENOMEM;
2151                 return NULL;
2152         }
2153         ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, hdr);
2154         MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2155                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2156         MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2157                  MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO);
2158         ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, flow_hit_aso);
2159         MLX5_SET(flow_hit_aso, ptr, access_pd, pd);
2160         flow_hit_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2161                                                            out, sizeof(out));
2162         if (!flow_hit_aso_obj->obj) {
2163                 rte_errno = errno;
2164                 DRV_LOG(ERR, "Failed to create FLOW_HIT_ASO obj using DevX.");
2165                 mlx5_free(flow_hit_aso_obj);
2166                 return NULL;
2167         }
2168         flow_hit_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2169         return flow_hit_aso_obj;
2170 }
2171
2172 /*
2173  * Create PD using DevX API.
2174  *
2175  * @param[in] ctx
2176  *   Context returned from mlx5 open_device() glue function.
2177  *
2178  * @return
2179  *   The DevX object created, NULL otherwise and rte_errno is set.
2180  */
2181 struct mlx5_devx_obj *
2182 mlx5_devx_cmd_alloc_pd(void *ctx)
2183 {
2184         struct mlx5_devx_obj *ppd =
2185                 mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ppd), 0, SOCKET_ID_ANY);
2186         u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {0};
2187         u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {0};
2188
2189         if (!ppd) {
2190                 DRV_LOG(ERR, "Failed to allocate PD data.");
2191                 rte_errno = ENOMEM;
2192                 return NULL;
2193         }
2194         MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD);
2195         ppd->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2196                                 out, sizeof(out));
2197         if (!ppd->obj) {
2198                 mlx5_free(ppd);
2199                 DRV_LOG(ERR, "Failed to allocate PD Obj using DevX.");
2200                 rte_errno = errno;
2201                 return NULL;
2202         }
2203         ppd->id = MLX5_GET(alloc_pd_out, out, pd);
2204         return ppd;
2205 }
2206
2207 /**
2208  * Create general object of type FLOW_METER_ASO using DevX API.
2209  *
2210  * @param[in] ctx
2211  *   Context returned from mlx5 open_device() glue function.
2212  * @param [in] pd
2213  *   PD value to associate the FLOW_METER_ASO object with.
2214  * @param [in] log_obj_size
2215  *   log_obj_size define to allocate number of 2 * meters
2216  *   in one FLOW_METER_ASO object.
2217  *
2218  * @return
2219  *   The DevX object created, NULL otherwise and rte_errno is set.
2220  */
2221 struct mlx5_devx_obj *
2222 mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx, uint32_t pd,
2223                                                 uint32_t log_obj_size)
2224 {
2225         uint32_t in[MLX5_ST_SZ_DW(create_flow_meter_aso_in)] = {0};
2226         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)];
2227         struct mlx5_devx_obj *flow_meter_aso_obj;
2228         void *ptr;
2229
2230         flow_meter_aso_obj = mlx5_malloc(MLX5_MEM_ZERO,
2231                                                 sizeof(*flow_meter_aso_obj),
2232                                                 0, SOCKET_ID_ANY);
2233         if (!flow_meter_aso_obj) {
2234                 DRV_LOG(ERR, "Failed to allocate FLOW_METER_ASO object data");
2235                 rte_errno = ENOMEM;
2236                 return NULL;
2237         }
2238         ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, hdr);
2239         MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2240                 MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2241         MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2242                 MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO);
2243         MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range,
2244                 log_obj_size);
2245         ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, flow_meter_aso);
2246         MLX5_SET(flow_meter_aso, ptr, access_pd, pd);
2247         flow_meter_aso_obj->obj = mlx5_glue->devx_obj_create(
2248                                                         ctx, in, sizeof(in),
2249                                                         out, sizeof(out));
2250         if (!flow_meter_aso_obj->obj) {
2251                 rte_errno = errno;
2252                 DRV_LOG(ERR, "Failed to create FLOW_METER_ASO obj using DevX.");
2253                 mlx5_free(flow_meter_aso_obj);
2254                 return NULL;
2255         }
2256         flow_meter_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr,
2257                                                                 out, obj_id);
2258         return flow_meter_aso_obj;
2259 }
2260
2261 /**
2262  * Create general object of type GENEVE TLV option using DevX API.
2263  *
2264  * @param[in] ctx
2265  *   Context returned from mlx5 open_device() glue function.
2266  * @param [in] class
2267  *   TLV option variable value of class
2268  * @param [in] type
2269  *   TLV option variable value of type
2270  * @param [in] len
2271  *   TLV option variable value of len
2272  *
2273  * @return
2274  *   The DevX object created, NULL otherwise and rte_errno is set.
2275  */
2276 struct mlx5_devx_obj *
2277 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx,
2278                 uint16_t class, uint8_t type, uint8_t len)
2279 {
2280         uint32_t in[MLX5_ST_SZ_DW(create_geneve_tlv_option_in)] = {0};
2281         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2282         struct mlx5_devx_obj *geneve_tlv_opt_obj = mlx5_malloc(MLX5_MEM_ZERO,
2283                                                    sizeof(*geneve_tlv_opt_obj),
2284                                                    0, SOCKET_ID_ANY);
2285
2286         if (!geneve_tlv_opt_obj) {
2287                 DRV_LOG(ERR, "Failed to allocate geneve tlv option object.");
2288                 rte_errno = ENOMEM;
2289                 return NULL;
2290         }
2291         void *hdr = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, hdr);
2292         void *opt = MLX5_ADDR_OF(create_geneve_tlv_option_in, in,
2293                         geneve_tlv_opt);
2294         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2295                         MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2296         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2297                  MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT);
2298         MLX5_SET(geneve_tlv_option, opt, option_class,
2299                         rte_be_to_cpu_16(class));
2300         MLX5_SET(geneve_tlv_option, opt, option_type, type);
2301         MLX5_SET(geneve_tlv_option, opt, option_data_length, len);
2302         geneve_tlv_opt_obj->obj = mlx5_glue->devx_obj_create(ctx, in,
2303                                         sizeof(in), out, sizeof(out));
2304         if (!geneve_tlv_opt_obj->obj) {
2305                 rte_errno = errno;
2306                 DRV_LOG(ERR, "Failed to create Geneve tlv option "
2307                                 "Obj using DevX.");
2308                 mlx5_free(geneve_tlv_opt_obj);
2309                 return NULL;
2310         }
2311         geneve_tlv_opt_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2312         return geneve_tlv_opt_obj;
2313 }
2314
2315 int
2316 mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id)
2317 {
2318 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2319         uint32_t in[MLX5_ST_SZ_DW(query_rq_in)] = {0};
2320         uint32_t out[MLX5_ST_SZ_DW(query_rq_out)] = {0};
2321         int rc;
2322         void *rq_ctx;
2323
2324         MLX5_SET(query_rq_in, in, opcode, MLX5_CMD_OP_QUERY_RQ);
2325         MLX5_SET(query_rq_in, in, rqn, ((struct ibv_wq *)wq)->wq_num);
2326         rc = mlx5_glue->devx_wq_query(wq, in, sizeof(in), out, sizeof(out));
2327         if (rc) {
2328                 rte_errno = errno;
2329                 DRV_LOG(ERR, "Failed to query WQ counter set ID using DevX - "
2330                         "rc = %d, errno = %d.", rc, errno);
2331                 return -rc;
2332         };
2333         rq_ctx = MLX5_ADDR_OF(query_rq_out, out, rq_context);
2334         *counter_set_id = MLX5_GET(rqc, rq_ctx, counter_set_id);
2335         return 0;
2336 #else
2337         (void)wq;
2338         (void)counter_set_id;
2339         return -ENOTSUP;
2340 #endif
2341 }
2342
2343 /*
2344  * Allocate queue counters via devx interface.
2345  *
2346  * @param[in] ctx
2347  *   Context returned from mlx5 open_device() glue function.
2348  *
2349  * @return
2350  *   Pointer to counter object on success, a NULL value otherwise and
2351  *   rte_errno is set.
2352  */
2353 struct mlx5_devx_obj *
2354 mlx5_devx_cmd_queue_counter_alloc(void *ctx)
2355 {
2356         struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 0,
2357                                                 SOCKET_ID_ANY);
2358         uint32_t in[MLX5_ST_SZ_DW(alloc_q_counter_in)]   = {0};
2359         uint32_t out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {0};
2360
2361         if (!dcs) {
2362                 rte_errno = ENOMEM;
2363                 return NULL;
2364         }
2365         MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER);
2366         dcs->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
2367                                               sizeof(out));
2368         if (!dcs->obj) {
2369                 DRV_LOG(DEBUG, "Can't allocate q counter set by DevX - error "
2370                         "%d.", errno);
2371                 rte_errno = errno;
2372                 mlx5_free(dcs);
2373                 return NULL;
2374         }
2375         dcs->id = MLX5_GET(alloc_q_counter_out, out, counter_set_id);
2376         return dcs;
2377 }
2378
2379 /**
2380  * Query queue counters values.
2381  *
2382  * @param[in] dcs
2383  *   devx object of the queue counter set.
2384  * @param[in] clear
2385  *   Whether hardware should clear the counters after the query or not.
2386  *  @param[out] out_of_buffers
2387  *   Number of dropped occurred due to lack of WQE for the associated QPs/RQs.
2388  *
2389  * @return
2390  *   0 on success, a negative value otherwise.
2391  */
2392 int
2393 mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear,
2394                                   uint32_t *out_of_buffers)
2395 {
2396         uint32_t out[MLX5_ST_SZ_BYTES(query_q_counter_out)] = {0};
2397         uint32_t in[MLX5_ST_SZ_DW(query_q_counter_in)] = {0};
2398         int rc;
2399
2400         MLX5_SET(query_q_counter_in, in, opcode,
2401                  MLX5_CMD_OP_QUERY_Q_COUNTER);
2402         MLX5_SET(query_q_counter_in, in, op_mod, 0);
2403         MLX5_SET(query_q_counter_in, in, counter_set_id, dcs->id);
2404         MLX5_SET(query_q_counter_in, in, clear, !!clear);
2405         rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out,
2406                                        sizeof(out));
2407         if (rc) {
2408                 DRV_LOG(ERR, "Failed to query devx q counter set - rc %d", rc);
2409                 rte_errno = rc;
2410                 return -rc;
2411         }
2412         *out_of_buffers = MLX5_GET(query_q_counter_out, out, out_of_buffer);
2413         return 0;
2414 }
2415
2416 /**
2417  * Create general object of type DEK using DevX API.
2418  *
2419  * @param[in] ctx
2420  *   Context returned from mlx5 open_device() glue function.
2421  * @param [in] attr
2422  *   Pointer to DEK attributes structure.
2423  *
2424  * @return
2425  *   The DevX object created, NULL otherwise and rte_errno is set.
2426  */
2427 struct mlx5_devx_obj *
2428 mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr)
2429 {
2430         uint32_t in[MLX5_ST_SZ_DW(create_dek_in)] = {0};
2431         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2432         struct mlx5_devx_obj *dek_obj = NULL;
2433         void *ptr = NULL, *key_addr = NULL;
2434
2435         dek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dek_obj),
2436                               0, SOCKET_ID_ANY);
2437         if (dek_obj == NULL) {
2438                 DRV_LOG(ERR, "Failed to allocate DEK object data");
2439                 rte_errno = ENOMEM;
2440                 return NULL;
2441         }
2442         ptr = MLX5_ADDR_OF(create_dek_in, in, hdr);
2443         MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2444                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2445         MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2446                  MLX5_GENERAL_OBJ_TYPE_DEK);
2447         ptr = MLX5_ADDR_OF(create_dek_in, in, dek);
2448         MLX5_SET(dek, ptr, key_size, attr->key_size);
2449         MLX5_SET(dek, ptr, has_keytag, attr->has_keytag);
2450         MLX5_SET(dek, ptr, key_purpose, attr->key_purpose);
2451         MLX5_SET(dek, ptr, pd, attr->pd);
2452         MLX5_SET64(dek, ptr, opaque, attr->opaque);
2453         key_addr = MLX5_ADDR_OF(dek, ptr, key);
2454         memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE);
2455         dek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2456                                                   out, sizeof(out));
2457         if (dek_obj->obj == NULL) {
2458                 rte_errno = errno;
2459                 DRV_LOG(ERR, "Failed to create DEK obj using DevX.");
2460                 mlx5_free(dek_obj);
2461                 return NULL;
2462         }
2463         dek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2464         return dek_obj;
2465 }
2466
2467 /**
2468  * Create general object of type IMPORT_KEK using DevX API.
2469  *
2470  * @param[in] ctx
2471  *   Context returned from mlx5 open_device() glue function.
2472  * @param [in] attr
2473  *   Pointer to IMPORT_KEK attributes structure.
2474  *
2475  * @return
2476  *   The DevX object created, NULL otherwise and rte_errno is set.
2477  */
2478 struct mlx5_devx_obj *
2479 mlx5_devx_cmd_create_import_kek_obj(void *ctx,
2480                                     struct mlx5_devx_import_kek_attr *attr)
2481 {
2482         uint32_t in[MLX5_ST_SZ_DW(create_import_kek_in)] = {0};
2483         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2484         struct mlx5_devx_obj *import_kek_obj = NULL;
2485         void *ptr = NULL, *key_addr = NULL;
2486
2487         import_kek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*import_kek_obj),
2488                                      0, SOCKET_ID_ANY);
2489         if (import_kek_obj == NULL) {
2490                 DRV_LOG(ERR, "Failed to allocate IMPORT_KEK object data");
2491                 rte_errno = ENOMEM;
2492                 return NULL;
2493         }
2494         ptr = MLX5_ADDR_OF(create_import_kek_in, in, hdr);
2495         MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2496                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2497         MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2498                  MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK);
2499         ptr = MLX5_ADDR_OF(create_import_kek_in, in, import_kek);
2500         MLX5_SET(import_kek, ptr, key_size, attr->key_size);
2501         key_addr = MLX5_ADDR_OF(import_kek, ptr, key);
2502         memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE);
2503         import_kek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2504                                                          out, sizeof(out));
2505         if (import_kek_obj->obj == NULL) {
2506                 rte_errno = errno;
2507                 DRV_LOG(ERR, "Failed to create IMPORT_KEK object using DevX.");
2508                 mlx5_free(import_kek_obj);
2509                 return NULL;
2510         }
2511         import_kek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2512         return import_kek_obj;
2513 }
2514
2515 /**
2516  * Create general object of type CREDENTIAL using DevX API.
2517  *
2518  * @param[in] ctx
2519  *   Context returned from mlx5 open_device() glue function.
2520  * @param [in] attr
2521  *   Pointer to CREDENTIAL attributes structure.
2522  *
2523  * @return
2524  *   The DevX object created, NULL otherwise and rte_errno is set.
2525  */
2526 struct mlx5_devx_obj *
2527 mlx5_devx_cmd_create_credential_obj(void *ctx,
2528                                     struct mlx5_devx_credential_attr *attr)
2529 {
2530         uint32_t in[MLX5_ST_SZ_DW(create_credential_in)] = {0};
2531         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2532         struct mlx5_devx_obj *credential_obj = NULL;
2533         void *ptr = NULL, *credential_addr = NULL;
2534
2535         credential_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*credential_obj),
2536                                      0, SOCKET_ID_ANY);
2537         if (credential_obj == NULL) {
2538                 DRV_LOG(ERR, "Failed to allocate CREDENTIAL object data");
2539                 rte_errno = ENOMEM;
2540                 return NULL;
2541         }
2542         ptr = MLX5_ADDR_OF(create_credential_in, in, hdr);
2543         MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2544                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2545         MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2546                  MLX5_GENERAL_OBJ_TYPE_CREDENTIAL);
2547         ptr = MLX5_ADDR_OF(create_credential_in, in, credential);
2548         MLX5_SET(credential, ptr, credential_role, attr->credential_role);
2549         credential_addr = MLX5_ADDR_OF(credential, ptr, credential);
2550         memcpy(credential_addr, (void *)(attr->credential),
2551                MLX5_CRYPTO_CREDENTIAL_SIZE);
2552         credential_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2553                                                          out, sizeof(out));
2554         if (credential_obj->obj == NULL) {
2555                 rte_errno = errno;
2556                 DRV_LOG(ERR, "Failed to create CREDENTIAL object using DevX.");
2557                 mlx5_free(credential_obj);
2558                 return NULL;
2559         }
2560         credential_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2561         return credential_obj;
2562 }
2563
2564 /**
2565  * Create general object of type CRYPTO_LOGIN using DevX API.
2566  *
2567  * @param[in] ctx
2568  *   Context returned from mlx5 open_device() glue function.
2569  * @param [in] attr
2570  *   Pointer to CRYPTO_LOGIN attributes structure.
2571  *
2572  * @return
2573  *   The DevX object created, NULL otherwise and rte_errno is set.
2574  */
2575 struct mlx5_devx_obj *
2576 mlx5_devx_cmd_create_crypto_login_obj(void *ctx,
2577                                       struct mlx5_devx_crypto_login_attr *attr)
2578 {
2579         uint32_t in[MLX5_ST_SZ_DW(create_crypto_login_in)] = {0};
2580         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2581         struct mlx5_devx_obj *crypto_login_obj = NULL;
2582         void *ptr = NULL, *credential_addr = NULL;
2583
2584         crypto_login_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*crypto_login_obj),
2585                                        0, SOCKET_ID_ANY);
2586         if (crypto_login_obj == NULL) {
2587                 DRV_LOG(ERR, "Failed to allocate CRYPTO_LOGIN object data");
2588                 rte_errno = ENOMEM;
2589                 return NULL;
2590         }
2591         ptr = MLX5_ADDR_OF(create_crypto_login_in, in, hdr);
2592         MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2593                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2594         MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2595                  MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN);
2596         ptr = MLX5_ADDR_OF(create_crypto_login_in, in, crypto_login);
2597         MLX5_SET(crypto_login, ptr, credential_pointer,
2598                  attr->credential_pointer);
2599         MLX5_SET(crypto_login, ptr, session_import_kek_ptr,
2600                  attr->session_import_kek_ptr);
2601         credential_addr = MLX5_ADDR_OF(crypto_login, ptr, credential);
2602         memcpy(credential_addr, (void *)(attr->credential),
2603                MLX5_CRYPTO_CREDENTIAL_SIZE);
2604         crypto_login_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2605                                                            out, sizeof(out));
2606         if (crypto_login_obj->obj == NULL) {
2607                 rte_errno = errno;
2608                 DRV_LOG(ERR, "Failed to create CRYPTO_LOGIN obj using DevX.");
2609                 mlx5_free(crypto_login_obj);
2610                 return NULL;
2611         }
2612         crypto_login_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2613         return crypto_login_obj;
2614 }