1 // SPDX-License-Identifier: BSD-3-Clause
2 /* Copyright 2018 Mellanox Technologies, Ltd */
7 #include <rte_malloc.h>
10 #include "mlx5_devx_cmds.h"
11 #include "mlx5_common_utils.h"
15 * Allocate flow counters via devx interface.
18 * ibv contexts returned from mlx5dv_open_device.
20 * Pointer to counters properties structure to be filled by the routine.
22 * Bulk counter numbers in 128 counters units.
25 * Pointer to counter object on success, a negative value otherwise and
28 struct mlx5_devx_obj *
29 mlx5_devx_cmd_flow_counter_alloc(struct ibv_context *ctx, uint32_t bulk_n_128)
31 struct mlx5_devx_obj *dcs = rte_zmalloc("dcs", sizeof(*dcs), 0);
32 uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0};
33 uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0};
39 MLX5_SET(alloc_flow_counter_in, in, opcode,
40 MLX5_CMD_OP_ALLOC_FLOW_COUNTER);
41 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128);
42 dcs->obj = mlx5_glue->devx_obj_create(ctx, in,
43 sizeof(in), out, sizeof(out));
45 DRV_LOG(ERR, "Can't allocate counters - error %d", errno);
50 dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id);
55 * Query flow counters values.
58 * devx object that was obtained from mlx5_devx_cmd_fc_alloc.
60 * Whether hardware should clear the counters after the query or not.
61 * @param[in] n_counters
62 * 0 in case of 1 counter to read, otherwise the counter number to read.
64 * The number of packets that matched the flow.
66 * The number of bytes that matched the flow.
68 * The mkey key for batch query.
70 * The address in the mkey range for batch query.
72 * The completion object for asynchronous batch query.
74 * The ID to be returned in the asynchronous batch query response.
77 * 0 on success, a negative value otherwise.
80 mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs,
81 int clear, uint32_t n_counters,
82 uint64_t *pkts, uint64_t *bytes,
83 uint32_t mkey, void *addr,
84 struct mlx5dv_devx_cmd_comp *cmd_comp,
87 int out_len = MLX5_ST_SZ_BYTES(query_flow_counter_out) +
88 MLX5_ST_SZ_BYTES(traffic_counter);
89 uint32_t out[out_len];
90 uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0};
94 MLX5_SET(query_flow_counter_in, in, opcode,
95 MLX5_CMD_OP_QUERY_FLOW_COUNTER);
96 MLX5_SET(query_flow_counter_in, in, op_mod, 0);
97 MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id);
98 MLX5_SET(query_flow_counter_in, in, clear, !!clear);
101 MLX5_SET(query_flow_counter_in, in, num_of_counters,
103 MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1);
104 MLX5_SET(query_flow_counter_in, in, mkey, mkey);
105 MLX5_SET64(query_flow_counter_in, in, address,
106 (uint64_t)(uintptr_t)addr);
109 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out,
112 rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in),
116 DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc);
121 stats = MLX5_ADDR_OF(query_flow_counter_out,
122 out, flow_statistics);
123 *pkts = MLX5_GET64(traffic_counter, stats, packets);
124 *bytes = MLX5_GET64(traffic_counter, stats, octets);
133 * ibv contexts returned from mlx5dv_open_device.
135 * Attributes of the requested mkey.
138 * Pointer to Devx mkey on success, a negative value otherwise and rte_errno
141 struct mlx5_devx_obj *
142 mlx5_devx_cmd_mkey_create(struct ibv_context *ctx,
143 struct mlx5_devx_mkey_attr *attr)
145 uint32_t in[MLX5_ST_SZ_DW(create_mkey_in)] = {0};
146 uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0};
148 struct mlx5_devx_obj *mkey = rte_zmalloc("mkey", sizeof(*mkey), 0);
150 uint32_t translation_size;
156 pgsize = sysconf(_SC_PAGESIZE);
157 translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16;
158 MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY);
159 MLX5_SET(create_mkey_in, in, translations_octword_actual_size,
161 MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id);
162 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
163 MLX5_SET(mkc, mkc, lw, 0x1);
164 MLX5_SET(mkc, mkc, lr, 0x1);
165 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
166 MLX5_SET(mkc, mkc, qpn, 0xffffff);
167 MLX5_SET(mkc, mkc, pd, attr->pd);
168 MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF);
169 MLX5_SET(mkc, mkc, translations_octword_size, translation_size);
170 MLX5_SET64(mkc, mkc, start_addr, attr->addr);
171 MLX5_SET64(mkc, mkc, len, attr->size);
172 MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize));
173 mkey->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
176 DRV_LOG(ERR, "Can't create mkey - error %d", errno);
181 mkey->id = MLX5_GET(create_mkey_out, out, mkey_index);
182 mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF);
187 * Get status of devx command response.
188 * Mainly used for asynchronous commands.
191 * The out response buffer.
194 * 0 on success, non-zero value otherwise.
197 mlx5_devx_get_out_command_status(void *out)
203 status = MLX5_GET(query_flow_counter_out, out, status);
205 int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome);
207 DRV_LOG(ERR, "Bad devX status %x, syndrome = %x", status,
214 * Destroy any object allocated by a Devx API.
217 * Pointer to a general object.
220 * 0 on success, a negative value otherwise.
223 mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj)
229 ret = mlx5_glue->devx_obj_destroy(obj->obj);
235 * Query NIC vport context.
236 * Fills minimal inline attribute.
239 * ibv contexts returned from mlx5dv_open_device.
243 * Attributes device values.
246 * 0 on success, a negative value otherwise.
249 mlx5_devx_cmd_query_nic_vport_context(struct ibv_context *ctx,
251 struct mlx5_hca_attr *attr)
253 uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0};
254 uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0};
256 int status, syndrome, rc;
258 /* Query NIC vport context to determine inline mode. */
259 MLX5_SET(query_nic_vport_context_in, in, opcode,
260 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT);
261 MLX5_SET(query_nic_vport_context_in, in, vport_number, vport);
263 MLX5_SET(query_nic_vport_context_in, in, other_vport, 1);
264 rc = mlx5_glue->devx_general_cmd(ctx,
269 status = MLX5_GET(query_nic_vport_context_out, out, status);
270 syndrome = MLX5_GET(query_nic_vport_context_out, out, syndrome);
272 DRV_LOG(DEBUG, "Failed to query NIC vport context, "
273 "status %x, syndrome = %x",
277 vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out,
279 attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx,
280 min_wqe_inline_mode);
283 rc = (rc > 0) ? -rc : rc;
288 * Query HCA attributes.
289 * Using those attributes we can check on run time if the device
290 * is having the required capabilities.
293 * ibv contexts returned from mlx5dv_open_device.
295 * Attributes device values.
298 * 0 on success, a negative value otherwise.
301 mlx5_devx_cmd_query_hca_attr(struct ibv_context *ctx,
302 struct mlx5_hca_attr *attr)
304 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0};
305 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0};
307 int status, syndrome, rc;
309 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
310 MLX5_SET(query_hca_cap_in, in, op_mod,
311 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE |
312 MLX5_HCA_CAP_OPMOD_GET_CUR);
314 rc = mlx5_glue->devx_general_cmd(ctx,
315 in, sizeof(in), out, sizeof(out));
318 status = MLX5_GET(query_hca_cap_out, out, status);
319 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
321 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, "
322 "status %x, syndrome = %x",
326 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
327 attr->flow_counter_bulk_alloc_bitmap =
328 MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc);
329 attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr,
331 attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager);
332 attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin);
333 attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr,
334 log_max_hairpin_queues);
335 attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr,
336 log_max_hairpin_wq_data_sz);
337 attr->log_max_hairpin_num_packets = MLX5_GET
338 (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz);
339 attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id);
340 attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr,
342 attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt);
343 attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr,
344 flex_parser_protocols);
345 attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos);
347 MLX5_SET(query_hca_cap_in, in, op_mod,
348 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP |
349 MLX5_HCA_CAP_OPMOD_GET_CUR);
350 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in),
355 DRV_LOG(DEBUG, "Failed to query devx QOS capabilities,"
356 " status %x, syndrome = %x",
360 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
361 attr->qos.srtcm_sup =
362 MLX5_GET(qos_cap, hcattr, flow_meter_srtcm);
363 attr->qos.log_max_flow_meter =
364 MLX5_GET(qos_cap, hcattr, log_max_flow_meter);
365 attr->qos.flow_meter_reg_c_ids =
366 MLX5_GET(qos_cap, hcattr, flow_meter_reg_id);
367 attr->qos.flow_meter_reg_share =
368 MLX5_GET(qos_cap, hcattr, flow_meter_reg_share);
370 if (!attr->eth_net_offloads)
373 /* Query HCA offloads for Ethernet protocol. */
374 memset(in, 0, sizeof(in));
375 memset(out, 0, sizeof(out));
376 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
377 MLX5_SET(query_hca_cap_in, in, op_mod,
378 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS |
379 MLX5_HCA_CAP_OPMOD_GET_CUR);
381 rc = mlx5_glue->devx_general_cmd(ctx,
385 attr->eth_net_offloads = 0;
388 status = MLX5_GET(query_hca_cap_out, out, status);
389 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
391 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, "
392 "status %x, syndrome = %x",
394 attr->eth_net_offloads = 0;
397 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
398 attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps,
399 hcattr, wqe_vlan_insert);
400 attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr,
402 attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps,
403 hcattr, tunnel_lro_gre);
404 attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps,
405 hcattr, tunnel_lro_vxlan);
406 attr->lro_max_msg_sz_mode = MLX5_GET
407 (per_protocol_networking_offload_caps,
408 hcattr, lro_max_msg_sz_mode);
409 for (int i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) {
410 attr->lro_timer_supported_periods[i] =
411 MLX5_GET(per_protocol_networking_offload_caps, hcattr,
412 lro_timer_supported_periods[i]);
414 attr->tunnel_stateless_geneve_rx =
415 MLX5_GET(per_protocol_networking_offload_caps,
416 hcattr, tunnel_stateless_geneve_rx);
417 attr->geneve_max_opt_len =
418 MLX5_GET(per_protocol_networking_offload_caps,
419 hcattr, max_geneve_opt_len);
420 attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps,
421 hcattr, wqe_inline_mode);
422 attr->tunnel_stateless_gtp = MLX5_GET
423 (per_protocol_networking_offload_caps,
424 hcattr, tunnel_stateless_gtp);
425 if (attr->wqe_inline_mode != MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
427 if (attr->eth_virt) {
428 rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr);
436 rc = (rc > 0) ? -rc : rc;
441 * Query TIS transport domain from QP verbs object using DevX API.
444 * Pointer to verbs QP returned by ibv_create_qp .
446 * TIS number of TIS to query.
448 * Pointer to TIS transport domain variable, to be set by the routine.
451 * 0 on success, a negative value otherwise.
454 mlx5_devx_cmd_qp_query_tis_td(struct ibv_qp *qp, uint32_t tis_num,
457 uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0};
458 uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0};
462 MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS);
463 MLX5_SET(query_tis_in, in, tisn, tis_num);
464 rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out));
466 DRV_LOG(ERR, "Failed to query QP using DevX");
469 tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context);
470 *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain);
475 * Fill WQ data for DevX API command.
476 * Utility function for use when creating DevX objects containing a WQ.
479 * Pointer to WQ context to fill with data.
480 * @param [in] wq_attr
481 * Pointer to WQ attributes structure to fill in WQ context.
484 devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr)
486 MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type);
487 MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature);
488 MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode);
489 MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave);
490 MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge);
491 MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size);
492 MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset);
493 MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm);
494 MLX5_SET(wq, wq_ctx, pd, wq_attr->pd);
495 MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page);
496 MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr);
497 MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter);
498 MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter);
499 MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride);
500 MLX5_SET(wq, wq_ctx, log_wq_pg_sz, wq_attr->log_wq_pg_sz);
501 MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz);
502 MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid);
503 MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid);
504 MLX5_SET(wq, wq_ctx, log_hairpin_num_packets,
505 wq_attr->log_hairpin_num_packets);
506 MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz);
507 MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides,
508 wq_attr->single_wqe_log_num_of_strides);
509 MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en);
510 MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes,
511 wq_attr->single_stride_log_num_of_bytes);
512 MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id);
513 MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id);
514 MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset);
518 * Create RQ using DevX API.
521 * ibv_context returned from mlx5dv_open_device.
522 * @param [in] rq_attr
523 * Pointer to create RQ attributes structure.
525 * CPU socket ID for allocations.
528 * The DevX object created, NULL otherwise and rte_errno is set.
530 struct mlx5_devx_obj *
531 mlx5_devx_cmd_create_rq(struct ibv_context *ctx,
532 struct mlx5_devx_create_rq_attr *rq_attr,
535 uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0};
536 uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0};
537 void *rq_ctx, *wq_ctx;
538 struct mlx5_devx_wq_attr *wq_attr;
539 struct mlx5_devx_obj *rq = NULL;
541 rq = rte_calloc_socket(__func__, 1, sizeof(*rq), 0, socket);
543 DRV_LOG(ERR, "Failed to allocate RQ data");
547 MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ);
548 rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx);
549 MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky);
550 MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en);
551 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);
552 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);
553 MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type);
554 MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
555 MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en);
556 MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin);
557 MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index);
558 MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn);
559 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
560 MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn);
561 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);
562 wq_attr = &rq_attr->wq_attr;
563 devx_cmd_fill_wq_data(wq_ctx, wq_attr);
564 rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
567 DRV_LOG(ERR, "Failed to create RQ using DevX");
572 rq->id = MLX5_GET(create_rq_out, out, rqn);
577 * Modify RQ using DevX API.
580 * Pointer to RQ object structure.
581 * @param [in] rq_attr
582 * Pointer to modify RQ attributes structure.
585 * 0 on success, a negative errno value otherwise and rte_errno is set.
588 mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,
589 struct mlx5_devx_modify_rq_attr *rq_attr)
591 uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0};
592 uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0};
593 void *rq_ctx, *wq_ctx;
596 MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ);
597 MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state);
598 MLX5_SET(modify_rq_in, in, rqn, rq->id);
599 MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask);
600 rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx);
601 MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
602 if (rq_attr->modify_bitmask &
603 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS)
604 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);
605 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD)
606 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);
607 if (rq_attr->modify_bitmask &
608 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID)
609 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
610 MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq);
611 MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca);
612 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) {
613 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);
614 MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm);
616 ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in),
619 DRV_LOG(ERR, "Failed to modify RQ using DevX");
627 * Create TIR using DevX API.
630 * ibv_context returned from mlx5dv_open_device.
631 * @param [in] tir_attr
632 * Pointer to TIR attributes structure.
635 * The DevX object created, NULL otherwise and rte_errno is set.
637 struct mlx5_devx_obj *
638 mlx5_devx_cmd_create_tir(struct ibv_context *ctx,
639 struct mlx5_devx_tir_attr *tir_attr)
641 uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
642 uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0};
643 void *tir_ctx, *outer, *inner;
644 struct mlx5_devx_obj *tir = NULL;
647 tir = rte_calloc(__func__, 1, sizeof(*tir), 0);
649 DRV_LOG(ERR, "Failed to allocate TIR data");
653 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR);
654 tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx);
655 MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type);
656 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs,
657 tir_attr->lro_timeout_period_usecs);
658 MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask);
659 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz);
660 MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn);
661 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric);
662 MLX5_SET(tirc, tir_ctx, tunneled_offload_en,
663 tir_attr->tunneled_offload_en);
664 MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table);
665 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn);
666 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block);
667 MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain);
668 for (i = 0; i < 10; i++) {
669 MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i],
670 tir_attr->rx_hash_toeplitz_key[i]);
672 outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer);
673 MLX5_SET(rx_hash_field_select, outer, l3_prot_type,
674 tir_attr->rx_hash_field_selector_outer.l3_prot_type);
675 MLX5_SET(rx_hash_field_select, outer, l4_prot_type,
676 tir_attr->rx_hash_field_selector_outer.l4_prot_type);
677 MLX5_SET(rx_hash_field_select, outer, selected_fields,
678 tir_attr->rx_hash_field_selector_outer.selected_fields);
679 inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner);
680 MLX5_SET(rx_hash_field_select, inner, l3_prot_type,
681 tir_attr->rx_hash_field_selector_inner.l3_prot_type);
682 MLX5_SET(rx_hash_field_select, inner, l4_prot_type,
683 tir_attr->rx_hash_field_selector_inner.l4_prot_type);
684 MLX5_SET(rx_hash_field_select, inner, selected_fields,
685 tir_attr->rx_hash_field_selector_inner.selected_fields);
686 tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
689 DRV_LOG(ERR, "Failed to create TIR using DevX");
694 tir->id = MLX5_GET(create_tir_out, out, tirn);
699 * Create RQT using DevX API.
702 * ibv_context returned from mlx5dv_open_device.
703 * @param [in] rqt_attr
704 * Pointer to RQT attributes structure.
707 * The DevX object created, NULL otherwise and rte_errno is set.
709 struct mlx5_devx_obj *
710 mlx5_devx_cmd_create_rqt(struct ibv_context *ctx,
711 struct mlx5_devx_rqt_attr *rqt_attr)
714 uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) +
715 rqt_attr->rqt_actual_size * sizeof(uint32_t);
716 uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0};
718 struct mlx5_devx_obj *rqt = NULL;
721 in = rte_calloc(__func__, 1, inlen, 0);
723 DRV_LOG(ERR, "Failed to allocate RQT IN data");
727 rqt = rte_calloc(__func__, 1, sizeof(*rqt), 0);
729 DRV_LOG(ERR, "Failed to allocate RQT data");
734 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
735 rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
736 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size);
737 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size);
738 for (i = 0; i < rqt_attr->rqt_actual_size; i++)
739 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]);
740 rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out));
743 DRV_LOG(ERR, "Failed to create RQT using DevX");
748 rqt->id = MLX5_GET(create_rqt_out, out, rqtn);
753 * Create SQ using DevX API.
756 * ibv_context returned from mlx5dv_open_device.
757 * @param [in] sq_attr
758 * Pointer to SQ attributes structure.
760 * CPU socket ID for allocations.
763 * The DevX object created, NULL otherwise and rte_errno is set.
765 struct mlx5_devx_obj *
766 mlx5_devx_cmd_create_sq(struct ibv_context *ctx,
767 struct mlx5_devx_create_sq_attr *sq_attr)
769 uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0};
770 uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0};
773 struct mlx5_devx_wq_attr *wq_attr;
774 struct mlx5_devx_obj *sq = NULL;
776 sq = rte_calloc(__func__, 1, sizeof(*sq), 0);
778 DRV_LOG(ERR, "Failed to allocate SQ data");
782 MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ);
783 sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx);
784 MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky);
785 MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master);
786 MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre);
787 MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en);
788 MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe,
789 sq_attr->flush_in_error_en);
790 MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode,
791 sq_attr->min_wqe_inline_mode);
792 MLX5_SET(sqc, sq_ctx, state, sq_attr->state);
793 MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr);
794 MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp);
795 MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin);
796 MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index);
797 MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn);
798 MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index,
799 sq_attr->packet_pacing_rate_limit_index);
800 MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz);
801 MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num);
802 wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq);
803 wq_attr = &sq_attr->wq_attr;
804 devx_cmd_fill_wq_data(wq_ctx, wq_attr);
805 sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
808 DRV_LOG(ERR, "Failed to create SQ using DevX");
813 sq->id = MLX5_GET(create_sq_out, out, sqn);
818 * Modify SQ using DevX API.
821 * Pointer to SQ object structure.
822 * @param [in] sq_attr
823 * Pointer to SQ attributes structure.
826 * 0 on success, a negative errno value otherwise and rte_errno is set.
829 mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq,
830 struct mlx5_devx_modify_sq_attr *sq_attr)
832 uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0};
833 uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0};
837 MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ);
838 MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state);
839 MLX5_SET(modify_sq_in, in, sqn, sq->id);
840 sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx);
841 MLX5_SET(sqc, sq_ctx, state, sq_attr->state);
842 MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq);
843 MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca);
844 ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in),
847 DRV_LOG(ERR, "Failed to modify SQ using DevX");
855 * Create TIS using DevX API.
858 * ibv_context returned from mlx5dv_open_device.
859 * @param [in] tis_attr
860 * Pointer to TIS attributes structure.
863 * The DevX object created, NULL otherwise and rte_errno is set.
865 struct mlx5_devx_obj *
866 mlx5_devx_cmd_create_tis(struct ibv_context *ctx,
867 struct mlx5_devx_tis_attr *tis_attr)
869 uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
870 uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0};
871 struct mlx5_devx_obj *tis = NULL;
874 tis = rte_calloc(__func__, 1, sizeof(*tis), 0);
876 DRV_LOG(ERR, "Failed to allocate TIS object");
880 MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS);
881 tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx);
882 MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity,
883 tis_attr->strict_lag_tx_port_affinity);
884 MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity,
885 tis_attr->strict_lag_tx_port_affinity);
886 MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio);
887 MLX5_SET(tisc, tis_ctx, transport_domain,
888 tis_attr->transport_domain);
889 tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
892 DRV_LOG(ERR, "Failed to create TIS using DevX");
897 tis->id = MLX5_GET(create_tis_out, out, tisn);
902 * Create transport domain using DevX API.
905 * ibv_context returned from mlx5dv_open_device.
908 * The DevX object created, NULL otherwise and rte_errno is set.
910 struct mlx5_devx_obj *
911 mlx5_devx_cmd_create_td(struct ibv_context *ctx)
913 uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0};
914 uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0};
915 struct mlx5_devx_obj *td = NULL;
917 td = rte_calloc(__func__, 1, sizeof(*td), 0);
919 DRV_LOG(ERR, "Failed to allocate TD object");
923 MLX5_SET(alloc_transport_domain_in, in, opcode,
924 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN);
925 td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
928 DRV_LOG(ERR, "Failed to create TIS using DevX");
933 td->id = MLX5_GET(alloc_transport_domain_out, out,
939 * Dump all flows to file.
941 * @param[in] fdb_domain
943 * @param[in] rx_domain
945 * @param[in] tx_domain
948 * Pointer to file stream.
951 * 0 on success, a nagative value otherwise.
954 mlx5_devx_cmd_flow_dump(void *fdb_domain __rte_unused,
955 void *rx_domain __rte_unused,
956 void *tx_domain __rte_unused, FILE *file __rte_unused)
960 #ifdef HAVE_MLX5_DR_FLOW_DUMP
962 ret = mlx5_glue->dr_dump_domain(file, fdb_domain);
967 ret = mlx5_glue->dr_dump_domain(file, rx_domain);
971 ret = mlx5_glue->dr_dump_domain(file, tx_domain);