drivers/common/mlx5/mlx5_devx_cmds.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2018 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <unistd.h>
   6
   7 #include <rte_errno.h>
   8 #include <rte_malloc.h>
   9 #include <rte_eal_paging.h>
  10
  11 #include "mlx5_prm.h"
  12 #include "mlx5_devx_cmds.h"
  13 #include "mlx5_common_log.h"
  14 #include "mlx5_malloc.h"
  15
  16 /**
  17  * Perform read access to the registers. Reads data from register
  18  * and writes ones to the specified buffer.
  19  *
  20  * @param[in] ctx
  21  *   Context returned from mlx5 open_device() glue function.
  22  * @param[in] reg_id
  23  *   Register identifier according to the PRM.
  24  * @param[in] arg
  25  *   Register access auxiliary parameter according to the PRM.
  26  * @param[out] data
  27  *   Pointer to the buffer to store read data.
  28  * @param[in] dw_cnt
  29  *   Buffer size in double words.
  30  *
  31  * @return
  32  *   0 on success, a negative value otherwise.
  33  */
  34 int
  35 mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg,
  36                             uint32_t *data, uint32_t dw_cnt)
  37 {
  38         uint32_t in[MLX5_ST_SZ_DW(access_register_in)]   = {0};
  39         uint32_t out[MLX5_ST_SZ_DW(access_register_out) +
  40                      MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0};
  41         int status, rc;
  42
  43         MLX5_ASSERT(data && dw_cnt);
  44         MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX);
  45         if (dw_cnt  > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) {
  46                 DRV_LOG(ERR, "Not enough  buffer for register read data");
  47                 return -1;
  48         }
  49         MLX5_SET(access_register_in, in, opcode,
  50                  MLX5_CMD_OP_ACCESS_REGISTER_USER);
  51         MLX5_SET(access_register_in, in, op_mod,
  52                                         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ);
  53         MLX5_SET(access_register_in, in, register_id, reg_id);
  54         MLX5_SET(access_register_in, in, argument, arg);
  55         rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out,
  56                                          MLX5_ST_SZ_BYTES(access_register_out) +
  57                                          sizeof(uint32_t) * dw_cnt);
  58         if (rc)
  59                 goto error;
  60         status = MLX5_GET(access_register_out, out, status);
  61         if (status) {
  62                 int syndrome = MLX5_GET(access_register_out, out, syndrome);
  63
  64                 DRV_LOG(DEBUG, "Failed to read access NIC register 0x%X, "
  65                                "status %x, syndrome = %x",
  66                                reg_id, status, syndrome);
  67                 return -1;
  68         }
  69         memcpy(data, &out[MLX5_ST_SZ_DW(access_register_out)],
  70                dw_cnt * sizeof(uint32_t));
  71         return 0;
  72 error:
  73         rc = (rc > 0) ? -rc : rc;
  74         return rc;
  75 }
  76
  77 /**
  78  * Perform write access to the registers.
  79  *
  80  * @param[in] ctx
  81  *   Context returned from mlx5 open_device() glue function.
  82  * @param[in] reg_id
  83  *   Register identifier according to the PRM.
  84  * @param[in] arg
  85  *   Register access auxiliary parameter according to the PRM.
  86  * @param[out] data
  87  *   Pointer to the buffer containing data to write.
  88  * @param[in] dw_cnt
  89  *   Buffer size in double words (32bit units).
  90  *
  91  * @return
  92  *   0 on success, a negative value otherwise.
  93  */
  94 int
  95 mlx5_devx_cmd_register_write(void *ctx, uint16_t reg_id, uint32_t arg,
  96                              uint32_t *data, uint32_t dw_cnt)
  97 {
  98         uint32_t in[MLX5_ST_SZ_DW(access_register_in) +
  99                     MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0};
 100         uint32_t out[MLX5_ST_SZ_DW(access_register_out)] = {0};
 101         int status, rc;
 102         void *ptr;
 103
 104         MLX5_ASSERT(data && dw_cnt);
 105         MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX);
 106         if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) {
 107                 DRV_LOG(ERR, "Data to write exceeds max size");
 108                 return -1;
 109         }
 110         MLX5_SET(access_register_in, in, opcode,
 111                  MLX5_CMD_OP_ACCESS_REGISTER_USER);
 112         MLX5_SET(access_register_in, in, op_mod,
 113                  MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE);
 114         MLX5_SET(access_register_in, in, register_id, reg_id);
 115         MLX5_SET(access_register_in, in, argument, arg);
 116         ptr = MLX5_ADDR_OF(access_register_in, in, register_data);
 117         memcpy(ptr, data, dw_cnt * sizeof(uint32_t));
 118         rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
 119
 120         rc = mlx5_glue->devx_general_cmd(ctx, in,
 121                                          MLX5_ST_SZ_BYTES(access_register_in) +
 122                                          dw_cnt * sizeof(uint32_t),
 123                                          out, sizeof(out));
 124         if (rc)
 125                 goto error;
 126         status = MLX5_GET(access_register_out, out, status);
 127         if (status) {
 128                 int syndrome = MLX5_GET(access_register_out, out, syndrome);
 129
 130                 DRV_LOG(DEBUG, "Failed to write access NIC register 0x%X, "
 131                                "status %x, syndrome = %x",
 132                                reg_id, status, syndrome);
 133                 return -1;
 134         }
 135         return 0;
 136 error:
 137         rc = (rc > 0) ? -rc : rc;
 138         return rc;
 139 }
 140
 141 /**
 142  * Allocate flow counters via devx interface.
 143  *
 144  * @param[in] ctx
 145  *   Context returned from mlx5 open_device() glue function.
 146  * @param dcs
 147  *   Pointer to counters properties structure to be filled by the routine.
 148  * @param bulk_n_128
 149  *   Bulk counter numbers in 128 counters units.
 150  *
 151  * @return
 152  *   Pointer to counter object on success, a negative value otherwise and
 153  *   rte_errno is set.
 154  */
 155 struct mlx5_devx_obj *
 156 mlx5_devx_cmd_flow_counter_alloc(void *ctx, uint32_t bulk_n_128)
 157 {
 158         struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs),
 159                                                 0, SOCKET_ID_ANY);
 160         uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)]   = {0};
 161         uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0};
 162
 163         if (!dcs) {
 164                 rte_errno = ENOMEM;
 165                 return NULL;
 166         }
 167         MLX5_SET(alloc_flow_counter_in, in, opcode,
 168                  MLX5_CMD_OP_ALLOC_FLOW_COUNTER);
 169         MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128);
 170         dcs->obj = mlx5_glue->devx_obj_create(ctx, in,
 171                                               sizeof(in), out, sizeof(out));
 172         if (!dcs->obj) {
 173                 DRV_LOG(ERR, "Can't allocate counters - error %d", errno);
 174                 rte_errno = errno;
 175                 mlx5_free(dcs);
 176                 return NULL;
 177         }
 178         dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id);
 179         return dcs;
 180 }
 181
 182 /**
 183  * Query flow counters values.
 184  *
 185  * @param[in] dcs
 186  *   devx object that was obtained from mlx5_devx_cmd_fc_alloc.
 187  * @param[in] clear
 188  *   Whether hardware should clear the counters after the query or not.
 189  * @param[in] n_counters
 190  *   0 in case of 1 counter to read, otherwise the counter number to read.
 191  *  @param pkts
 192  *   The number of packets that matched the flow.
 193  *  @param bytes
 194  *    The number of bytes that matched the flow.
 195  *  @param mkey
 196  *   The mkey key for batch query.
 197  *  @param addr
 198  *    The address in the mkey range for batch query.
 199  *  @param cmd_comp
 200  *   The completion object for asynchronous batch query.
 201  *  @param async_id
 202  *    The ID to be returned in the asynchronous batch query response.
 203  *
 204  * @return
 205  *   0 on success, a negative value otherwise.
 206  */
 207 int
 208 mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs,
 209                                  int clear, uint32_t n_counters,
 210                                  uint64_t *pkts, uint64_t *bytes,
 211                                  uint32_t mkey, void *addr,
 212                                  void *cmd_comp,
 213                                  uint64_t async_id)
 214 {
 215         int out_len = MLX5_ST_SZ_BYTES(query_flow_counter_out) +
 216                         MLX5_ST_SZ_BYTES(traffic_counter);
 217         uint32_t out[out_len];
 218         uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0};
 219         void *stats;
 220         int rc;
 221
 222         MLX5_SET(query_flow_counter_in, in, opcode,
 223                  MLX5_CMD_OP_QUERY_FLOW_COUNTER);
 224         MLX5_SET(query_flow_counter_in, in, op_mod, 0);
 225         MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id);
 226         MLX5_SET(query_flow_counter_in, in, clear, !!clear);
 227
 228         if (n_counters) {
 229                 MLX5_SET(query_flow_counter_in, in, num_of_counters,
 230                          n_counters);
 231                 MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1);
 232                 MLX5_SET(query_flow_counter_in, in, mkey, mkey);
 233                 MLX5_SET64(query_flow_counter_in, in, address,
 234                            (uint64_t)(uintptr_t)addr);
 235         }
 236         if (!cmd_comp)
 237                 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out,
 238                                                out_len);
 239         else
 240                 rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in),
 241                                                      out_len, async_id,
 242                                                      cmd_comp);
 243         if (rc) {
 244                 DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc);
 245                 rte_errno = rc;
 246                 return -rc;
 247         }
 248         if (!n_counters) {
 249                 stats = MLX5_ADDR_OF(query_flow_counter_out,
 250                                      out, flow_statistics);
 251                 *pkts = MLX5_GET64(traffic_counter, stats, packets);
 252                 *bytes = MLX5_GET64(traffic_counter, stats, octets);
 253         }
 254         return 0;
 255 }
 256
 257 /**
 258  * Create a new mkey.
 259  *
 260  * @param[in] ctx
 261  *   Context returned from mlx5 open_device() glue function.
 262  * @param[in] attr
 263  *   Attributes of the requested mkey.
 264  *
 265  * @return
 266  *   Pointer to Devx mkey on success, a negative value otherwise and rte_errno
 267  *   is set.
 268  */
 269 struct mlx5_devx_obj *
 270 mlx5_devx_cmd_mkey_create(void *ctx,
 271                           struct mlx5_devx_mkey_attr *attr)
 272 {
 273         struct mlx5_klm *klm_array = attr->klm_array;
 274         int klm_num = attr->klm_num;
 275         int in_size_dw = MLX5_ST_SZ_DW(create_mkey_in) +
 276                      (klm_num ? RTE_ALIGN(klm_num, 4) : 0) * MLX5_ST_SZ_DW(klm);
 277         uint32_t in[in_size_dw];
 278         uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0};
 279         void *mkc;
 280         struct mlx5_devx_obj *mkey = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mkey),
 281                                                  0, SOCKET_ID_ANY);
 282         size_t pgsize;
 283         uint32_t translation_size;
 284
 285         if (!mkey) {
 286                 rte_errno = ENOMEM;
 287                 return NULL;
 288         }
 289         memset(in, 0, in_size_dw * 4);
 290         pgsize = rte_mem_page_size();
 291         if (pgsize == (size_t)-1) {
 292                 mlx5_free(mkey);
 293                 DRV_LOG(ERR, "Failed to get page size");
 294                 rte_errno = ENOMEM;
 295                 return NULL;
 296         }
 297         MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY);
 298         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 299         if (klm_num > 0) {
 300                 int i;
 301                 uint8_t *klm = (uint8_t *)MLX5_ADDR_OF(create_mkey_in, in,
 302                                                        klm_pas_mtt);
 303                 translation_size = RTE_ALIGN(klm_num, 4);
 304                 for (i = 0; i < klm_num; i++) {
 305                         MLX5_SET(klm, klm, byte_count, klm_array[i].byte_count);
 306                         MLX5_SET(klm, klm, mkey, klm_array[i].mkey);
 307                         MLX5_SET64(klm, klm, address, klm_array[i].address);
 308                         klm += MLX5_ST_SZ_BYTES(klm);
 309                 }
 310                 for (; i < (int)translation_size; i++) {
 311                         MLX5_SET(klm, klm, mkey, 0x0);
 312                         MLX5_SET64(klm, klm, address, 0x0);
 313                         klm += MLX5_ST_SZ_BYTES(klm);
 314                 }
 315                 MLX5_SET(mkc, mkc, access_mode_1_0, attr->log_entity_size ?
 316                          MLX5_MKC_ACCESS_MODE_KLM_FBS :
 317                          MLX5_MKC_ACCESS_MODE_KLM);
 318                 MLX5_SET(mkc, mkc, log_page_size, attr->log_entity_size);
 319         } else {
 320                 translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16;
 321                 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
 322                 MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize));
 323         }
 324         MLX5_SET(create_mkey_in, in, translations_octword_actual_size,
 325                  translation_size);
 326         MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id);
 327         MLX5_SET(create_mkey_in, in, pg_access, attr->pg_access);
 328         MLX5_SET(mkc, mkc, lw, 0x1);
 329         MLX5_SET(mkc, mkc, lr, 0x1);
 330         if (attr->set_remote_rw) {
 331                 MLX5_SET(mkc, mkc, rw, 0x1);
 332                 MLX5_SET(mkc, mkc, rr, 0x1);
 333         }
 334         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 335         MLX5_SET(mkc, mkc, pd, attr->pd);
 336         MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF);
 337         MLX5_SET(mkc, mkc, umr_en, attr->umr_en);
 338         MLX5_SET(mkc, mkc, translations_octword_size, translation_size);
 339         MLX5_SET(mkc, mkc, relaxed_ordering_write,
 340                  attr->relaxed_ordering_write);
 341         MLX5_SET(mkc, mkc, relaxed_ordering_read, attr->relaxed_ordering_read);
 342         MLX5_SET64(mkc, mkc, start_addr, attr->addr);
 343         MLX5_SET64(mkc, mkc, len, attr->size);
 344         MLX5_SET(mkc, mkc, crypto_en, attr->crypto_en);
 345         if (attr->crypto_en) {
 346                 MLX5_SET(mkc, mkc, bsf_en, attr->crypto_en);
 347                 MLX5_SET(mkc, mkc, bsf_octword_size, 4);
 348         }
 349         mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out,
 350                                                sizeof(out));
 351         if (!mkey->obj) {
 352                 DRV_LOG(ERR, "Can't create %sdirect mkey - error %d",
 353                         klm_num ? "an in" : "a ", errno);
 354                 rte_errno = errno;
 355                 mlx5_free(mkey);
 356                 return NULL;
 357         }
 358         mkey->id = MLX5_GET(create_mkey_out, out, mkey_index);
 359         mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF);
 360         return mkey;
 361 }
 362
 363 /**
 364  * Get status of devx command response.
 365  * Mainly used for asynchronous commands.
 366  *
 367  * @param[in] out
 368  *   The out response buffer.
 369  *
 370  * @return
 371  *   0 on success, non-zero value otherwise.
 372  */
 373 int
 374 mlx5_devx_get_out_command_status(void *out)
 375 {
 376         int status;
 377
 378         if (!out)
 379                 return -EINVAL;
 380         status = MLX5_GET(query_flow_counter_out, out, status);
 381         if (status) {
 382                 int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome);
 383
 384                 DRV_LOG(ERR, "Bad DevX status %x, syndrome = %x", status,
 385                         syndrome);
 386         }
 387         return status;
 388 }
 389
 390 /**
 391  * Destroy any object allocated by a Devx API.
 392  *
 393  * @param[in] obj
 394  *   Pointer to a general object.
 395  *
 396  * @return
 397  *   0 on success, a negative value otherwise.
 398  */
 399 int
 400 mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj)
 401 {
 402         int ret;
 403
 404         if (!obj)
 405                 return 0;
 406         ret =  mlx5_glue->devx_obj_destroy(obj->obj);
 407         mlx5_free(obj);
 408         return ret;
 409 }
 410
 411 /**
 412  * Query NIC vport context.
 413  * Fills minimal inline attribute.
 414  *
 415  * @param[in] ctx
 416  *   ibv contexts returned from mlx5dv_open_device.
 417  * @param[in] vport
 418  *   vport index
 419  * @param[out] attr
 420  *   Attributes device values.
 421  *
 422  * @return
 423  *   0 on success, a negative value otherwise.
 424  */
 425 static int
 426 mlx5_devx_cmd_query_nic_vport_context(void *ctx,
 427                                       unsigned int vport,
 428                                       struct mlx5_hca_attr *attr)
 429 {
 430         uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0};
 431         uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0};
 432         void *vctx;
 433         int status, syndrome, rc;
 434
 435         /* Query NIC vport context to determine inline mode. */
 436         MLX5_SET(query_nic_vport_context_in, in, opcode,
 437                  MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT);
 438         MLX5_SET(query_nic_vport_context_in, in, vport_number, vport);
 439         if (vport)
 440                 MLX5_SET(query_nic_vport_context_in, in, other_vport, 1);
 441         rc = mlx5_glue->devx_general_cmd(ctx,
 442                                          in, sizeof(in),
 443                                          out, sizeof(out));
 444         if (rc)
 445                 goto error;
 446         status = MLX5_GET(query_nic_vport_context_out, out, status);
 447         syndrome = MLX5_GET(query_nic_vport_context_out, out, syndrome);
 448         if (status) {
 449                 DRV_LOG(DEBUG, "Failed to query NIC vport context, "
 450                         "status %x, syndrome = %x", status, syndrome);
 451                 return -1;
 452         }
 453         vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out,
 454                             nic_vport_context);
 455         attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx,
 456                                            min_wqe_inline_mode);
 457         return 0;
 458 error:
 459         rc = (rc > 0) ? -rc : rc;
 460         return rc;
 461 }
 462
 463 /**
 464  * Query NIC vDPA attributes.
 465  *
 466  * @param[in] ctx
 467  *   Context returned from mlx5 open_device() glue function.
 468  * @param[out] vdpa_attr
 469  *   vDPA Attributes structure to fill.
 470  */
 471 static void
 472 mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx,
 473                                   struct mlx5_hca_vdpa_attr *vdpa_attr)
 474 {
 475         uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0};
 476         uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0};
 477         void *hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 478         int status, syndrome, rc;
 479
 480         MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
 481         MLX5_SET(query_hca_cap_in, in, op_mod,
 482                  MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION |
 483                  MLX5_HCA_CAP_OPMOD_GET_CUR);
 484         rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
 485         status = MLX5_GET(query_hca_cap_out, out, status);
 486         syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
 487         if (rc || status) {
 488                 RTE_LOG(DEBUG, PMD, "Failed to query devx VDPA capabilities,"
 489                         " status %x, syndrome = %x", status, syndrome);
 490                 vdpa_attr->valid = 0;
 491         } else {
 492                 vdpa_attr->valid = 1;
 493                 vdpa_attr->desc_tunnel_offload_type =
 494                         MLX5_GET(virtio_emulation_cap, hcattr,
 495                                  desc_tunnel_offload_type);
 496                 vdpa_attr->eth_frame_offload_type =
 497                         MLX5_GET(virtio_emulation_cap, hcattr,
 498                                  eth_frame_offload_type);
 499                 vdpa_attr->virtio_version_1_0 =
 500                         MLX5_GET(virtio_emulation_cap, hcattr,
 501                                  virtio_version_1_0);
 502                 vdpa_attr->tso_ipv4 = MLX5_GET(virtio_emulation_cap, hcattr,
 503                                                tso_ipv4);
 504                 vdpa_attr->tso_ipv6 = MLX5_GET(virtio_emulation_cap, hcattr,
 505                                                tso_ipv6);
 506                 vdpa_attr->tx_csum = MLX5_GET(virtio_emulation_cap, hcattr,
 507                                               tx_csum);
 508                 vdpa_attr->rx_csum = MLX5_GET(virtio_emulation_cap, hcattr,
 509                                               rx_csum);
 510                 vdpa_attr->event_mode = MLX5_GET(virtio_emulation_cap, hcattr,
 511                                                  event_mode);
 512                 vdpa_attr->virtio_queue_type =
 513                         MLX5_GET(virtio_emulation_cap, hcattr,
 514                                  virtio_queue_type);
 515                 vdpa_attr->log_doorbell_stride =
 516                         MLX5_GET(virtio_emulation_cap, hcattr,
 517                                  log_doorbell_stride);
 518                 vdpa_attr->log_doorbell_bar_size =
 519                         MLX5_GET(virtio_emulation_cap, hcattr,
 520                                  log_doorbell_bar_size);
 521                 vdpa_attr->doorbell_bar_offset =
 522                         MLX5_GET64(virtio_emulation_cap, hcattr,
 523                                    doorbell_bar_offset);
 524                 vdpa_attr->max_num_virtio_queues =
 525                         MLX5_GET(virtio_emulation_cap, hcattr,
 526                                  max_num_virtio_queues);
 527                 vdpa_attr->umems[0].a = MLX5_GET(virtio_emulation_cap, hcattr,
 528                                                  umem_1_buffer_param_a);
 529                 vdpa_attr->umems[0].b = MLX5_GET(virtio_emulation_cap, hcattr,
 530                                                  umem_1_buffer_param_b);
 531                 vdpa_attr->umems[1].a = MLX5_GET(virtio_emulation_cap, hcattr,
 532                                                  umem_2_buffer_param_a);
 533                 vdpa_attr->umems[1].b = MLX5_GET(virtio_emulation_cap, hcattr,
 534                                                  umem_2_buffer_param_b);
 535                 vdpa_attr->umems[2].a = MLX5_GET(virtio_emulation_cap, hcattr,
 536                                                  umem_3_buffer_param_a);
 537                 vdpa_attr->umems[2].b = MLX5_GET(virtio_emulation_cap, hcattr,
 538                                                  umem_3_buffer_param_b);
 539         }
 540 }
 541
 542 int
 543 mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj,
 544                                   uint32_t ids[], uint32_t num)
 545 {
 546         uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
 547         uint32_t out[MLX5_ST_SZ_DW(create_flex_parser_out)] = {0};
 548         void *hdr = MLX5_ADDR_OF(create_flex_parser_out, in, hdr);
 549         void *flex = MLX5_ADDR_OF(create_flex_parser_out, out, flex);
 550         void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table);
 551         int ret;
 552         uint32_t idx = 0;
 553         uint32_t i;
 554
 555         if (num > MLX5_GRAPH_NODE_SAMPLE_NUM) {
 556                 rte_errno = EINVAL;
 557                 DRV_LOG(ERR, "Too many sample IDs to be fetched.");
 558                 return -rte_errno;
 559         }
 560         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
 561                  MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
 562         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
 563                  MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH);
 564         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, flex_obj->id);
 565         ret = mlx5_glue->devx_obj_query(flex_obj->obj, in, sizeof(in),
 566                                         out, sizeof(out));
 567         if (ret) {
 568                 rte_errno = ret;
 569                 DRV_LOG(ERR, "Failed to query sample IDs with object %p.",
 570                         (void *)flex_obj);
 571                 return -rte_errno;
 572         }
 573         for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) {
 574                 void *s_off = (void *)((char *)sample + i *
 575                               MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample));
 576                 uint32_t en;
 577
 578                 en = MLX5_GET(parse_graph_flow_match_sample, s_off,
 579                               flow_match_sample_en);
 580                 if (!en)
 581                         continue;
 582                 ids[idx++] = MLX5_GET(parse_graph_flow_match_sample, s_off,
 583                                   flow_match_sample_field_id);
 584         }
 585         if (num != idx) {
 586                 rte_errno = EINVAL;
 587                 DRV_LOG(ERR, "Number of sample IDs are not as expected.");
 588                 return -rte_errno;
 589         }
 590         return ret;
 591 }
 592
 593
 594 struct mlx5_devx_obj *
 595 mlx5_devx_cmd_create_flex_parser(void *ctx,
 596                               struct mlx5_devx_graph_node_attr *data)
 597 {
 598         uint32_t in[MLX5_ST_SZ_DW(create_flex_parser_in)] = {0};
 599         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
 600         void *hdr = MLX5_ADDR_OF(create_flex_parser_in, in, hdr);
 601         void *flex = MLX5_ADDR_OF(create_flex_parser_in, in, flex);
 602         void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table);
 603         void *in_arc = MLX5_ADDR_OF(parse_graph_flex, flex, input_arc);
 604         void *out_arc = MLX5_ADDR_OF(parse_graph_flex, flex, output_arc);
 605         struct mlx5_devx_obj *parse_flex_obj = mlx5_malloc
 606                      (MLX5_MEM_ZERO, sizeof(*parse_flex_obj), 0, SOCKET_ID_ANY);
 607         uint32_t i;
 608
 609         if (!parse_flex_obj) {
 610                 DRV_LOG(ERR, "Failed to allocate flex parser data.");
 611                 rte_errno = ENOMEM;
 612                 return NULL;
 613         }
 614         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
 615                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
 616         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
 617                  MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH);
 618         MLX5_SET(parse_graph_flex, flex, header_length_mode,
 619                  data->header_length_mode);
 620         MLX5_SET(parse_graph_flex, flex, header_length_base_value,
 621                  data->header_length_base_value);
 622         MLX5_SET(parse_graph_flex, flex, header_length_field_offset,
 623                  data->header_length_field_offset);
 624         MLX5_SET(parse_graph_flex, flex, header_length_field_shift,
 625                  data->header_length_field_shift);
 626         MLX5_SET(parse_graph_flex, flex, header_length_field_mask,
 627                  data->header_length_field_mask);
 628         for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) {
 629                 struct mlx5_devx_match_sample_attr *s = &data->sample[i];
 630                 void *s_off = (void *)((char *)sample + i *
 631                               MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample));
 632
 633                 if (!s->flow_match_sample_en)
 634                         continue;
 635                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 636                          flow_match_sample_en, !!s->flow_match_sample_en);
 637                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 638                          flow_match_sample_field_offset,
 639                          s->flow_match_sample_field_offset);
 640                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 641                          flow_match_sample_offset_mode,
 642                          s->flow_match_sample_offset_mode);
 643                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 644                          flow_match_sample_field_offset_mask,
 645                          s->flow_match_sample_field_offset_mask);
 646                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 647                          flow_match_sample_field_offset_shift,
 648                          s->flow_match_sample_field_offset_shift);
 649                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 650                          flow_match_sample_field_base_offset,
 651                          s->flow_match_sample_field_base_offset);
 652                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 653                          flow_match_sample_tunnel_mode,
 654                          s->flow_match_sample_tunnel_mode);
 655         }
 656         for (i = 0; i < MLX5_GRAPH_NODE_ARC_NUM; i++) {
 657                 struct mlx5_devx_graph_arc_attr *ia = &data->in[i];
 658                 struct mlx5_devx_graph_arc_attr *oa = &data->out[i];
 659                 void *in_off = (void *)((char *)in_arc + i *
 660                               MLX5_ST_SZ_BYTES(parse_graph_arc));
 661                 void *out_off = (void *)((char *)out_arc + i *
 662                               MLX5_ST_SZ_BYTES(parse_graph_arc));
 663
 664                 if (ia->arc_parse_graph_node != 0) {
 665                         MLX5_SET(parse_graph_arc, in_off,
 666                                  compare_condition_value,
 667                                  ia->compare_condition_value);
 668                         MLX5_SET(parse_graph_arc, in_off, start_inner_tunnel,
 669                                  ia->start_inner_tunnel);
 670                         MLX5_SET(parse_graph_arc, in_off, arc_parse_graph_node,
 671                                  ia->arc_parse_graph_node);
 672                         MLX5_SET(parse_graph_arc, in_off,
 673                                  parse_graph_node_handle,
 674                                  ia->parse_graph_node_handle);
 675                 }
 676                 if (oa->arc_parse_graph_node != 0) {
 677                         MLX5_SET(parse_graph_arc, out_off,
 678                                  compare_condition_value,
 679                                  oa->compare_condition_value);
 680                         MLX5_SET(parse_graph_arc, out_off, start_inner_tunnel,
 681                                  oa->start_inner_tunnel);
 682                         MLX5_SET(parse_graph_arc, out_off, arc_parse_graph_node,
 683                                  oa->arc_parse_graph_node);
 684                         MLX5_SET(parse_graph_arc, out_off,
 685                                  parse_graph_node_handle,
 686                                  oa->parse_graph_node_handle);
 687                 }
 688         }
 689         parse_flex_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
 690                                                          out, sizeof(out));
 691         if (!parse_flex_obj->obj) {
 692                 rte_errno = errno;
 693                 DRV_LOG(ERR, "Failed to create FLEX PARSE GRAPH object "
 694                         "by using DevX.");
 695                 mlx5_free(parse_flex_obj);
 696                 return NULL;
 697         }
 698         parse_flex_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
 699         return parse_flex_obj;
 700 }
 701
 702 static int
 703 mlx5_devx_query_pkt_integrity_match(void *hcattr)
 704 {
 705         return MLX5_GET(flow_table_nic_cap, hcattr,
 706                         ft_field_support_2_nic_receive.inner_l3_ok) &&
 707                MLX5_GET(flow_table_nic_cap, hcattr,
 708                         ft_field_support_2_nic_receive.inner_l4_ok) &&
 709                MLX5_GET(flow_table_nic_cap, hcattr,
 710                         ft_field_support_2_nic_receive.outer_l3_ok) &&
 711                MLX5_GET(flow_table_nic_cap, hcattr,
 712                         ft_field_support_2_nic_receive.outer_l4_ok) &&
 713                MLX5_GET(flow_table_nic_cap, hcattr,
 714                         ft_field_support_2_nic_receive
 715                                 .inner_ipv4_checksum_ok) &&
 716                MLX5_GET(flow_table_nic_cap, hcattr,
 717                         ft_field_support_2_nic_receive.inner_l4_checksum_ok) &&
 718                MLX5_GET(flow_table_nic_cap, hcattr,
 719                         ft_field_support_2_nic_receive
 720                                 .outer_ipv4_checksum_ok) &&
 721                MLX5_GET(flow_table_nic_cap, hcattr,
 722                         ft_field_support_2_nic_receive.outer_l4_checksum_ok);
 723 }
 724
 725 /**
 726  * Query HCA attributes.
 727  * Using those attributes we can check on run time if the device
 728  * is having the required capabilities.
 729  *
 730  * @param[in] ctx
 731  *   Context returned from mlx5 open_device() glue function.
 732  * @param[out] attr
 733  *   Attributes device values.
 734  *
 735  * @return
 736  *   0 on success, a negative value otherwise.
 737  */
 738 int
 739 mlx5_devx_cmd_query_hca_attr(void *ctx,
 740                              struct mlx5_hca_attr *attr)
 741 {
 742         uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0};
 743         uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0};
 744         void *hcattr;
 745         int status, syndrome, rc, i;
 746         uint64_t general_obj_types_supported = 0;
 747
 748         MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
 749         MLX5_SET(query_hca_cap_in, in, op_mod,
 750                  MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE |
 751                  MLX5_HCA_CAP_OPMOD_GET_CUR);
 752
 753         rc = mlx5_glue->devx_general_cmd(ctx,
 754                                          in, sizeof(in), out, sizeof(out));
 755         if (rc)
 756                 goto error;
 757         status = MLX5_GET(query_hca_cap_out, out, status);
 758         syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
 759         if (status) {
 760                 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, "
 761                         "status %x, syndrome = %x", status, syndrome);
 762                 return -1;
 763         }
 764         hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 765         attr->flow_counter_bulk_alloc_bitmap =
 766                         MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc);
 767         attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr,
 768                                             flow_counters_dump);
 769         attr->log_max_rqt_size = MLX5_GET(cmd_hca_cap, hcattr,
 770                                           log_max_rqt_size);
 771         attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager);
 772         attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin);
 773         attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr,
 774                                                 log_max_hairpin_queues);
 775         attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr,
 776                                                     log_max_hairpin_wq_data_sz);
 777         attr->log_max_hairpin_num_packets = MLX5_GET
 778                 (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz);
 779         attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id);
 780         attr->relaxed_ordering_write = MLX5_GET(cmd_hca_cap, hcattr,
 781                                                 relaxed_ordering_write);
 782         attr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr,
 783                                                relaxed_ordering_read);
 784         attr->access_register_user = MLX5_GET(cmd_hca_cap, hcattr,
 785                                               access_register_user);
 786         attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr,
 787                                           eth_net_offloads);
 788         attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt);
 789         attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr,
 790                                                flex_parser_protocols);
 791         attr->max_geneve_tlv_options = MLX5_GET(cmd_hca_cap, hcattr,
 792                         max_geneve_tlv_options);
 793         attr->max_geneve_tlv_option_data_len = MLX5_GET(cmd_hca_cap, hcattr,
 794                         max_geneve_tlv_option_data_len);
 795         attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos);
 796         attr->qos.flow_meter_aso_sup = !!(MLX5_GET64(cmd_hca_cap, hcattr,
 797                                          general_obj_types) &
 798                               MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO);
 799         attr->vdpa.valid = !!(MLX5_GET64(cmd_hca_cap, hcattr,
 800                                          general_obj_types) &
 801                               MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q);
 802         attr->vdpa.queue_counters_valid = !!(MLX5_GET64(cmd_hca_cap, hcattr,
 803                                                         general_obj_types) &
 804                                   MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS);
 805         attr->parse_graph_flex_node = !!(MLX5_GET64(cmd_hca_cap, hcattr,
 806                                          general_obj_types) &
 807                               MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE);
 808         attr->wqe_index_ignore = MLX5_GET(cmd_hca_cap, hcattr,
 809                                           wqe_index_ignore_cap);
 810         attr->cross_channel = MLX5_GET(cmd_hca_cap, hcattr, cd);
 811         attr->non_wire_sq = MLX5_GET(cmd_hca_cap, hcattr, non_wire_sq);
 812         attr->log_max_static_sq_wq = MLX5_GET(cmd_hca_cap, hcattr,
 813                                               log_max_static_sq_wq);
 814         attr->num_lag_ports = MLX5_GET(cmd_hca_cap, hcattr, num_lag_ports);
 815         attr->dev_freq_khz = MLX5_GET(cmd_hca_cap, hcattr,
 816                                       device_frequency_khz);
 817         attr->scatter_fcs_w_decap_disable =
 818                 MLX5_GET(cmd_hca_cap, hcattr, scatter_fcs_w_decap_disable);
 819         attr->roce = MLX5_GET(cmd_hca_cap, hcattr, roce);
 820         attr->rq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, rq_ts_format);
 821         attr->sq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, sq_ts_format);
 822         attr->steering_format_version =
 823                 MLX5_GET(cmd_hca_cap, hcattr, steering_format_version);
 824         attr->regex = MLX5_GET(cmd_hca_cap, hcattr, regexp);
 825         attr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr,
 826                                                regexp_num_of_engines);
 827         /* Read the general_obj_types bitmap and extract the relevant bits. */
 828         general_obj_types_supported = MLX5_GET64(cmd_hca_cap, hcattr,
 829                                                  general_obj_types);
 830         attr->vdpa.valid = !!(general_obj_types_supported &
 831                               MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q);
 832         attr->vdpa.queue_counters_valid =
 833                         !!(general_obj_types_supported &
 834                            MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS);
 835         attr->parse_graph_flex_node =
 836                         !!(general_obj_types_supported &
 837                            MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE);
 838         attr->flow_hit_aso = !!(general_obj_types_supported &
 839                                 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO);
 840         attr->geneve_tlv_opt = !!(general_obj_types_supported &
 841                                   MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT);
 842         attr->dek = !!(general_obj_types_supported &
 843                        MLX5_GENERAL_OBJ_TYPES_CAP_DEK);
 844         attr->import_kek = !!(general_obj_types_supported &
 845                               MLX5_GENERAL_OBJ_TYPES_CAP_IMPORT_KEK);
 846         attr->credential = !!(general_obj_types_supported &
 847                               MLX5_GENERAL_OBJ_TYPES_CAP_CREDENTIAL);
 848         attr->crypto_login = !!(general_obj_types_supported &
 849                                 MLX5_GENERAL_OBJ_TYPES_CAP_CRYPTO_LOGIN);
 850         /* Add reading of other GENERAL_OBJ_TYPES_CAP bits above this line. */
 851         attr->log_max_cq = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq);
 852         attr->log_max_qp = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp);
 853         attr->log_max_cq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq_sz);
 854         attr->log_max_qp_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp_sz);
 855         attr->log_max_mrw_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_mrw_sz);
 856         attr->log_max_pd = MLX5_GET(cmd_hca_cap, hcattr, log_max_pd);
 857         attr->log_max_srq = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq);
 858         attr->log_max_srq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq_sz);
 859         attr->reg_c_preserve =
 860                 MLX5_GET(cmd_hca_cap, hcattr, reg_c_preserve);
 861         attr->mmo_regex_qp_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_qp);
 862         attr->mmo_regex_sq_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_sq);
 863         attr->mmo_dma_sq_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_sq);
 864         attr->mmo_compress_sq_en = MLX5_GET(cmd_hca_cap, hcattr,
 865                         compress_mmo_sq);
 866         attr->mmo_decompress_sq_en = MLX5_GET(cmd_hca_cap, hcattr,
 867                         decompress_mmo_sq);
 868         attr->mmo_dma_qp_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_qp);
 869         attr->mmo_compress_qp_en = MLX5_GET(cmd_hca_cap, hcattr,
 870                         compress_mmo_qp);
 871         attr->mmo_decompress_qp_en = MLX5_GET(cmd_hca_cap, hcattr,
 872                         decompress_mmo_qp);
 873         attr->compress_min_block_size = MLX5_GET(cmd_hca_cap, hcattr,
 874                                                  compress_min_block_size);
 875         attr->log_max_mmo_dma = MLX5_GET(cmd_hca_cap, hcattr, log_dma_mmo_size);
 876         attr->log_max_mmo_compress = MLX5_GET(cmd_hca_cap, hcattr,
 877                                               log_compress_mmo_size);
 878         attr->log_max_mmo_decompress = MLX5_GET(cmd_hca_cap, hcattr,
 879                                                 log_decompress_mmo_size);
 880         attr->cqe_compression = MLX5_GET(cmd_hca_cap, hcattr, cqe_compression);
 881         attr->mini_cqe_resp_flow_tag = MLX5_GET(cmd_hca_cap, hcattr,
 882                                                 mini_cqe_resp_flow_tag);
 883         attr->mini_cqe_resp_l3_l4_tag = MLX5_GET(cmd_hca_cap, hcattr,
 884                                                  mini_cqe_resp_l3_l4_tag);
 885         attr->umr_indirect_mkey_disabled =
 886                 MLX5_GET(cmd_hca_cap, hcattr, umr_indirect_mkey_disabled);
 887         attr->umr_modify_entity_size_disabled =
 888                 MLX5_GET(cmd_hca_cap, hcattr, umr_modify_entity_size_disabled);
 889         attr->crypto = MLX5_GET(cmd_hca_cap, hcattr, crypto);
 890         if (attr->crypto)
 891                 attr->aes_xts = MLX5_GET(cmd_hca_cap, hcattr, aes_xts);
 892         attr->ct_offload = !!(MLX5_GET64(cmd_hca_cap, hcattr,
 893                                          general_obj_types) &
 894                               MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD);
 895         if (attr->qos.sup) {
 896                 MLX5_SET(query_hca_cap_in, in, op_mod,
 897                          MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP |
 898                          MLX5_HCA_CAP_OPMOD_GET_CUR);
 899                 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in),
 900                                                  out, sizeof(out));
 901                 if (rc)
 902                         goto error;
 903                 if (status) {
 904                         DRV_LOG(DEBUG, "Failed to query devx QOS capabilities,"
 905                                 " status %x, syndrome = %x", status, syndrome);
 906                         return -1;
 907                 }
 908                 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 909                 attr->qos.flow_meter_old =
 910                                 MLX5_GET(qos_cap, hcattr, flow_meter_old);
 911                 attr->qos.log_max_flow_meter =
 912                                 MLX5_GET(qos_cap, hcattr, log_max_flow_meter);
 913                 attr->qos.flow_meter_reg_c_ids =
 914                                 MLX5_GET(qos_cap, hcattr, flow_meter_reg_id);
 915                 attr->qos.flow_meter =
 916                                 MLX5_GET(qos_cap, hcattr, flow_meter);
 917                 attr->qos.packet_pacing =
 918                                 MLX5_GET(qos_cap, hcattr, packet_pacing);
 919                 attr->qos.wqe_rate_pp =
 920                                 MLX5_GET(qos_cap, hcattr, wqe_rate_pp);
 921                 if (attr->qos.flow_meter_aso_sup) {
 922                         attr->qos.log_meter_aso_granularity =
 923                                 MLX5_GET(qos_cap, hcattr,
 924                                         log_meter_aso_granularity);
 925                         attr->qos.log_meter_aso_max_alloc =
 926                                 MLX5_GET(qos_cap, hcattr,
 927                                         log_meter_aso_max_alloc);
 928                         attr->qos.log_max_num_meter_aso =
 929                                 MLX5_GET(qos_cap, hcattr,
 930                                         log_max_num_meter_aso);
 931                 }
 932         }
 933         if (attr->vdpa.valid)
 934                 mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa);
 935         if (!attr->eth_net_offloads)
 936                 return 0;
 937
 938         /* Query Flow Sampler Capability From FLow Table Properties Layout. */
 939         memset(in, 0, sizeof(in));
 940         memset(out, 0, sizeof(out));
 941         MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
 942         MLX5_SET(query_hca_cap_in, in, op_mod,
 943                  MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE |
 944                  MLX5_HCA_CAP_OPMOD_GET_CUR);
 945
 946         rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
 947         if (rc)
 948                 goto error;
 949         status = MLX5_GET(query_hca_cap_out, out, status);
 950         syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
 951         if (status) {
 952                 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, "
 953                         "status %x, syndrome = %x", status, syndrome);
 954                 attr->log_max_ft_sampler_num = 0;
 955                 return -1;
 956         }
 957         hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 958         attr->log_max_ft_sampler_num = MLX5_GET
 959                 (flow_table_nic_cap, hcattr,
 960                  flow_table_properties_nic_receive.log_max_ft_sampler_num);
 961         attr->flow.tunnel_header_0_1 = MLX5_GET
 962                 (flow_table_nic_cap, hcattr,
 963                  ft_field_support_2_nic_receive.tunnel_header_0_1);
 964         attr->pkt_integrity_match = mlx5_devx_query_pkt_integrity_match(hcattr);
 965         attr->inner_ipv4_ihl = MLX5_GET
 966                 (flow_table_nic_cap, hcattr,
 967                  ft_field_support_2_nic_receive.inner_ipv4_ihl);
 968         attr->outer_ipv4_ihl = MLX5_GET
 969                 (flow_table_nic_cap, hcattr,
 970                  ft_field_support_2_nic_receive.outer_ipv4_ihl);
 971         /* Query HCA offloads for Ethernet protocol. */
 972         memset(in, 0, sizeof(in));
 973         memset(out, 0, sizeof(out));
 974         MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
 975         MLX5_SET(query_hca_cap_in, in, op_mod,
 976                  MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS |
 977                  MLX5_HCA_CAP_OPMOD_GET_CUR);
 978
 979         rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
 980         if (rc) {
 981                 attr->eth_net_offloads = 0;
 982                 goto error;
 983         }
 984         status = MLX5_GET(query_hca_cap_out, out, status);
 985         syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
 986         if (status) {
 987                 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, "
 988                         "status %x, syndrome = %x", status, syndrome);
 989                 attr->eth_net_offloads = 0;
 990                 return -1;
 991         }
 992         hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 993         attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps,
 994                                          hcattr, wqe_vlan_insert);
 995         attr->csum_cap = MLX5_GET(per_protocol_networking_offload_caps,
 996                                          hcattr, csum_cap);
 997         attr->vlan_cap = MLX5_GET(per_protocol_networking_offload_caps,
 998                                          hcattr, vlan_cap);
 999         attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr,
1000                                  lro_cap);
1001         attr->max_lso_cap = MLX5_GET(per_protocol_networking_offload_caps,
1002                                  hcattr, max_lso_cap);
1003         attr->scatter_fcs = MLX5_GET(per_protocol_networking_offload_caps,
1004                                  hcattr, scatter_fcs);
1005         attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps,
1006                                         hcattr, tunnel_lro_gre);
1007         attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps,
1008                                           hcattr, tunnel_lro_vxlan);
1009         attr->swp = MLX5_GET(per_protocol_networking_offload_caps,
1010                                           hcattr, swp);
1011         attr->tunnel_stateless_gre =
1012                                 MLX5_GET(per_protocol_networking_offload_caps,
1013                                           hcattr, tunnel_stateless_gre);
1014         attr->tunnel_stateless_vxlan =
1015                                 MLX5_GET(per_protocol_networking_offload_caps,
1016                                           hcattr, tunnel_stateless_vxlan);
1017         attr->swp_csum = MLX5_GET(per_protocol_networking_offload_caps,
1018                                           hcattr, swp_csum);
1019         attr->swp_lso = MLX5_GET(per_protocol_networking_offload_caps,
1020                                           hcattr, swp_lso);
1021         attr->lro_max_msg_sz_mode = MLX5_GET
1022                                         (per_protocol_networking_offload_caps,
1023                                          hcattr, lro_max_msg_sz_mode);
1024         for (i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) {
1025                 attr->lro_timer_supported_periods[i] =
1026                         MLX5_GET(per_protocol_networking_offload_caps, hcattr,
1027                                  lro_timer_supported_periods[i]);
1028         }
1029         attr->lro_min_mss_size = MLX5_GET(per_protocol_networking_offload_caps,
1030                                           hcattr, lro_min_mss_size);
1031         attr->tunnel_stateless_geneve_rx =
1032                             MLX5_GET(per_protocol_networking_offload_caps,
1033                                      hcattr, tunnel_stateless_geneve_rx);
1034         attr->geneve_max_opt_len =
1035                     MLX5_GET(per_protocol_networking_offload_caps,
1036                              hcattr, max_geneve_opt_len);
1037         attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps,
1038                                          hcattr, wqe_inline_mode);
1039         attr->tunnel_stateless_gtp = MLX5_GET
1040                                         (per_protocol_networking_offload_caps,
1041                                          hcattr, tunnel_stateless_gtp);
1042         attr->rss_ind_tbl_cap = MLX5_GET
1043                                         (per_protocol_networking_offload_caps,
1044                                          hcattr, rss_ind_tbl_cap);
1045         /* Query HCA attribute for ROCE. */
1046         if (attr->roce) {
1047                 memset(in, 0, sizeof(in));
1048                 memset(out, 0, sizeof(out));
1049                 MLX5_SET(query_hca_cap_in, in, opcode,
1050                          MLX5_CMD_OP_QUERY_HCA_CAP);
1051                 MLX5_SET(query_hca_cap_in, in, op_mod,
1052                          MLX5_GET_HCA_CAP_OP_MOD_ROCE |
1053                          MLX5_HCA_CAP_OPMOD_GET_CUR);
1054                 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in),
1055                                                  out, sizeof(out));
1056                 if (rc)
1057                         goto error;
1058                 status = MLX5_GET(query_hca_cap_out, out, status);
1059                 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
1060                 if (status) {
1061                         DRV_LOG(DEBUG,
1062                                 "Failed to query devx HCA ROCE capabilities, "
1063                                 "status %x, syndrome = %x", status, syndrome);
1064                         return -1;
1065                 }
1066                 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
1067                 attr->qp_ts_format = MLX5_GET(roce_caps, hcattr, qp_ts_format);
1068         }
1069         if (attr->eth_virt &&
1070             attr->wqe_inline_mode == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT) {
1071                 rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr);
1072                 if (rc) {
1073                         attr->eth_virt = 0;
1074                         goto error;
1075                 }
1076         }
1077         return 0;
1078 error:
1079         rc = (rc > 0) ? -rc : rc;
1080         return rc;
1081 }
1082
1083 /**
1084  * Query TIS transport domain from QP verbs object using DevX API.
1085  *
1086  * @param[in] qp
1087  *   Pointer to verbs QP returned by ibv_create_qp .
1088  * @param[in] tis_num
1089  *   TIS number of TIS to query.
1090  * @param[out] tis_td
1091  *   Pointer to TIS transport domain variable, to be set by the routine.
1092  *
1093  * @return
1094  *   0 on success, a negative value otherwise.
1095  */
1096 int
1097 mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num,
1098                               uint32_t *tis_td)
1099 {
1100 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
1101         uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0};
1102         uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0};
1103         int rc;
1104         void *tis_ctx;
1105
1106         MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS);
1107         MLX5_SET(query_tis_in, in, tisn, tis_num);
1108         rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out));
1109         if (rc) {
1110                 DRV_LOG(ERR, "Failed to query QP using DevX");
1111                 return -rc;
1112         };
1113         tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context);
1114         *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain);
1115         return 0;
1116 #else
1117         (void)qp;
1118         (void)tis_num;
1119         (void)tis_td;
1120         return -ENOTSUP;
1121 #endif
1122 }
1123
1124 /**
1125  * Fill WQ data for DevX API command.
1126  * Utility function for use when creating DevX objects containing a WQ.
1127  *
1128  * @param[in] wq_ctx
1129  *   Pointer to WQ context to fill with data.
1130  * @param [in] wq_attr
1131  *   Pointer to WQ attributes structure to fill in WQ context.
1132  */
1133 static void
1134 devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr)
1135 {
1136         MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type);
1137         MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature);
1138         MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode);
1139         MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave);
1140         MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge);
1141         MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size);
1142         MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset);
1143         MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm);
1144         MLX5_SET(wq, wq_ctx, pd, wq_attr->pd);
1145         MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page);
1146         MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr);
1147         MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter);
1148         MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter);
1149         MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride);
1150         if (wq_attr->log_wq_pg_sz > MLX5_ADAPTER_PAGE_SHIFT)
1151                 MLX5_SET(wq, wq_ctx, log_wq_pg_sz,
1152                          wq_attr->log_wq_pg_sz - MLX5_ADAPTER_PAGE_SHIFT);
1153         MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz);
1154         MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid);
1155         MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid);
1156         MLX5_SET(wq, wq_ctx, log_hairpin_num_packets,
1157                  wq_attr->log_hairpin_num_packets);
1158         MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz);
1159         MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides,
1160                  wq_attr->single_wqe_log_num_of_strides);
1161         MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en);
1162         MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes,
1163                  wq_attr->single_stride_log_num_of_bytes);
1164         MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id);
1165         MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id);
1166         MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset);
1167 }
1168
1169 /**
1170  * Create RQ using DevX API.
1171  *
1172  * @param[in] ctx
1173  *   Context returned from mlx5 open_device() glue function.
1174  * @param [in] rq_attr
1175  *   Pointer to create RQ attributes structure.
1176  * @param [in] socket
1177  *   CPU socket ID for allocations.
1178  *
1179  * @return
1180  *   The DevX object created, NULL otherwise and rte_errno is set.
1181  */
1182 struct mlx5_devx_obj *
1183 mlx5_devx_cmd_create_rq(void *ctx,
1184                         struct mlx5_devx_create_rq_attr *rq_attr,
1185                         int socket)
1186 {
1187         uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0};
1188         uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0};
1189         void *rq_ctx, *wq_ctx;
1190         struct mlx5_devx_wq_attr *wq_attr;
1191         struct mlx5_devx_obj *rq = NULL;
1192
1193         rq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rq), 0, socket);
1194         if (!rq) {
1195                 DRV_LOG(ERR, "Failed to allocate RQ data");
1196                 rte_errno = ENOMEM;
1197                 return NULL;
1198         }
1199         MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ);
1200         rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx);
1201         MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky);
1202         MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en);
1203         MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);
1204         MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);
1205         MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type);
1206         MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
1207         MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en);
1208         MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin);
1209         MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index);
1210         MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn);
1211         MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
1212         MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn);
1213         MLX5_SET(sqc, rq_ctx, ts_format, rq_attr->ts_format);
1214         wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);
1215         wq_attr = &rq_attr->wq_attr;
1216         devx_cmd_fill_wq_data(wq_ctx, wq_attr);
1217         rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1218                                                   out, sizeof(out));
1219         if (!rq->obj) {
1220                 DRV_LOG(ERR, "Failed to create RQ using DevX");
1221                 rte_errno = errno;
1222                 mlx5_free(rq);
1223                 return NULL;
1224         }
1225         rq->id = MLX5_GET(create_rq_out, out, rqn);
1226         return rq;
1227 }
1228
1229 /**
1230  * Modify RQ using DevX API.
1231  *
1232  * @param[in] rq
1233  *   Pointer to RQ object structure.
1234  * @param [in] rq_attr
1235  *   Pointer to modify RQ attributes structure.
1236  *
1237  * @return
1238  *   0 on success, a negative errno value otherwise and rte_errno is set.
1239  */
1240 int
1241 mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,
1242                         struct mlx5_devx_modify_rq_attr *rq_attr)
1243 {
1244         uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0};
1245         uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0};
1246         void *rq_ctx, *wq_ctx;
1247         int ret;
1248
1249         MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ);
1250         MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state);
1251         MLX5_SET(modify_rq_in, in, rqn, rq->id);
1252         MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask);
1253         rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1254         MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
1255         if (rq_attr->modify_bitmask &
1256                         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS)
1257                 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);
1258         if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD)
1259                 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);
1260         if (rq_attr->modify_bitmask &
1261                         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID)
1262                 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
1263         MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq);
1264         MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca);
1265         if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) {
1266                 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);
1267                 MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm);
1268         }
1269         ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in),
1270                                          out, sizeof(out));
1271         if (ret) {
1272                 DRV_LOG(ERR, "Failed to modify RQ using DevX");
1273                 rte_errno = errno;
1274                 return -errno;
1275         }
1276         return ret;
1277 }
1278
1279 /**
1280  * Create TIR using DevX API.
1281  *
1282  * @param[in] ctx
1283  *  Context returned from mlx5 open_device() glue function.
1284  * @param [in] tir_attr
1285  *   Pointer to TIR attributes structure.
1286  *
1287  * @return
1288  *   The DevX object created, NULL otherwise and rte_errno is set.
1289  */
1290 struct mlx5_devx_obj *
1291 mlx5_devx_cmd_create_tir(void *ctx,
1292                          struct mlx5_devx_tir_attr *tir_attr)
1293 {
1294         uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
1295         uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0};
1296         void *tir_ctx, *outer, *inner, *rss_key;
1297         struct mlx5_devx_obj *tir = NULL;
1298
1299         tir = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tir), 0, SOCKET_ID_ANY);
1300         if (!tir) {
1301                 DRV_LOG(ERR, "Failed to allocate TIR data");
1302                 rte_errno = ENOMEM;
1303                 return NULL;
1304         }
1305         MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR);
1306         tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx);
1307         MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type);
1308         MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs,
1309                  tir_attr->lro_timeout_period_usecs);
1310         MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask);
1311         MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz);
1312         MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn);
1313         MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric);
1314         MLX5_SET(tirc, tir_ctx, tunneled_offload_en,
1315                  tir_attr->tunneled_offload_en);
1316         MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table);
1317         MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn);
1318         MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block);
1319         MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain);
1320         rss_key = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_toeplitz_key);
1321         memcpy(rss_key, tir_attr->rx_hash_toeplitz_key, MLX5_RSS_HASH_KEY_LEN);
1322         outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer);
1323         MLX5_SET(rx_hash_field_select, outer, l3_prot_type,
1324                  tir_attr->rx_hash_field_selector_outer.l3_prot_type);
1325         MLX5_SET(rx_hash_field_select, outer, l4_prot_type,
1326                  tir_attr->rx_hash_field_selector_outer.l4_prot_type);
1327         MLX5_SET(rx_hash_field_select, outer, selected_fields,
1328                  tir_attr->rx_hash_field_selector_outer.selected_fields);
1329         inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner);
1330         MLX5_SET(rx_hash_field_select, inner, l3_prot_type,
1331                  tir_attr->rx_hash_field_selector_inner.l3_prot_type);
1332         MLX5_SET(rx_hash_field_select, inner, l4_prot_type,
1333                  tir_attr->rx_hash_field_selector_inner.l4_prot_type);
1334         MLX5_SET(rx_hash_field_select, inner, selected_fields,
1335                  tir_attr->rx_hash_field_selector_inner.selected_fields);
1336         tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1337                                                    out, sizeof(out));
1338         if (!tir->obj) {
1339                 DRV_LOG(ERR, "Failed to create TIR using DevX");
1340                 rte_errno = errno;
1341                 mlx5_free(tir);
1342                 return NULL;
1343         }
1344         tir->id = MLX5_GET(create_tir_out, out, tirn);
1345         return tir;
1346 }
1347
1348 /**
1349  * Modify TIR using DevX API.
1350  *
1351  * @param[in] tir
1352  *   Pointer to TIR DevX object structure.
1353  * @param [in] modify_tir_attr
1354  *   Pointer to TIR modification attributes structure.
1355  *
1356  * @return
1357  *   0 on success, a negative errno value otherwise and rte_errno is set.
1358  */
1359 int
1360 mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir,
1361                          struct mlx5_devx_modify_tir_attr *modify_tir_attr)
1362 {
1363         struct mlx5_devx_tir_attr *tir_attr = &modify_tir_attr->tir;
1364         uint32_t in[MLX5_ST_SZ_DW(modify_tir_in)] = {0};
1365         uint32_t out[MLX5_ST_SZ_DW(modify_tir_out)] = {0};
1366         void *tir_ctx;
1367         int ret;
1368
1369         MLX5_SET(modify_tir_in, in, opcode, MLX5_CMD_OP_MODIFY_TIR);
1370         MLX5_SET(modify_tir_in, in, tirn, modify_tir_attr->tirn);
1371         MLX5_SET64(modify_tir_in, in, modify_bitmask,
1372                    modify_tir_attr->modify_bitmask);
1373         tir_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1374         if (modify_tir_attr->modify_bitmask &
1375                         MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO) {
1376                 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs,
1377                          tir_attr->lro_timeout_period_usecs);
1378                 MLX5_SET(tirc, tir_ctx, lro_enable_mask,
1379                          tir_attr->lro_enable_mask);
1380                 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz,
1381                          tir_attr->lro_max_msg_sz);
1382         }
1383         if (modify_tir_attr->modify_bitmask &
1384                         MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE)
1385                 MLX5_SET(tirc, tir_ctx, indirect_table,
1386                          tir_attr->indirect_table);
1387         if (modify_tir_attr->modify_bitmask &
1388                         MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH) {
1389                 int i;
1390                 void *outer, *inner;
1391
1392                 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric,
1393                          tir_attr->rx_hash_symmetric);
1394                 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn);
1395                 for (i = 0; i < 10; i++) {
1396                         MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i],
1397                                  tir_attr->rx_hash_toeplitz_key[i]);
1398                 }
1399                 outer = MLX5_ADDR_OF(tirc, tir_ctx,
1400                                      rx_hash_field_selector_outer);
1401                 MLX5_SET(rx_hash_field_select, outer, l3_prot_type,
1402                          tir_attr->rx_hash_field_selector_outer.l3_prot_type);
1403                 MLX5_SET(rx_hash_field_select, outer, l4_prot_type,
1404                          tir_attr->rx_hash_field_selector_outer.l4_prot_type);
1405                 MLX5_SET
1406                 (rx_hash_field_select, outer, selected_fields,
1407                  tir_attr->rx_hash_field_selector_outer.selected_fields);
1408                 inner = MLX5_ADDR_OF(tirc, tir_ctx,
1409                                      rx_hash_field_selector_inner);
1410                 MLX5_SET(rx_hash_field_select, inner, l3_prot_type,
1411                          tir_attr->rx_hash_field_selector_inner.l3_prot_type);
1412                 MLX5_SET(rx_hash_field_select, inner, l4_prot_type,
1413                          tir_attr->rx_hash_field_selector_inner.l4_prot_type);
1414                 MLX5_SET
1415                 (rx_hash_field_select, inner, selected_fields,
1416                  tir_attr->rx_hash_field_selector_inner.selected_fields);
1417         }
1418         if (modify_tir_attr->modify_bitmask &
1419             MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN) {
1420                 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block);
1421         }
1422         ret = mlx5_glue->devx_obj_modify(tir->obj, in, sizeof(in),
1423                                          out, sizeof(out));
1424         if (ret) {
1425                 DRV_LOG(ERR, "Failed to modify TIR using DevX");
1426                 rte_errno = errno;
1427                 return -errno;
1428         }
1429         return ret;
1430 }
1431
1432 /**
1433  * Create RQT using DevX API.
1434  *
1435  * @param[in] ctx
1436  *   Context returned from mlx5 open_device() glue function.
1437  * @param [in] rqt_attr
1438  *   Pointer to RQT attributes structure.
1439  *
1440  * @return
1441  *   The DevX object created, NULL otherwise and rte_errno is set.
1442  */
1443 struct mlx5_devx_obj *
1444 mlx5_devx_cmd_create_rqt(void *ctx,
1445                          struct mlx5_devx_rqt_attr *rqt_attr)
1446 {
1447         uint32_t *in = NULL;
1448         uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) +
1449                          rqt_attr->rqt_actual_size * sizeof(uint32_t);
1450         uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0};
1451         void *rqt_ctx;
1452         struct mlx5_devx_obj *rqt = NULL;
1453         int i;
1454
1455         in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY);
1456         if (!in) {
1457                 DRV_LOG(ERR, "Failed to allocate RQT IN data");
1458                 rte_errno = ENOMEM;
1459                 return NULL;
1460         }
1461         rqt = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt), 0, SOCKET_ID_ANY);
1462         if (!rqt) {
1463                 DRV_LOG(ERR, "Failed to allocate RQT data");
1464                 rte_errno = ENOMEM;
1465                 mlx5_free(in);
1466                 return NULL;
1467         }
1468         MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
1469         rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1470         MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type);
1471         MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size);
1472         MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size);
1473         for (i = 0; i < rqt_attr->rqt_actual_size; i++)
1474                 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]);
1475         rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out));
1476         mlx5_free(in);
1477         if (!rqt->obj) {
1478                 DRV_LOG(ERR, "Failed to create RQT using DevX");
1479                 rte_errno = errno;
1480                 mlx5_free(rqt);
1481                 return NULL;
1482         }
1483         rqt->id = MLX5_GET(create_rqt_out, out, rqtn);
1484         return rqt;
1485 }
1486
1487 /**
1488  * Modify RQT using DevX API.
1489  *
1490  * @param[in] rqt
1491  *   Pointer to RQT DevX object structure.
1492  * @param [in] rqt_attr
1493  *   Pointer to RQT attributes structure.
1494  *
1495  * @return
1496  *   0 on success, a negative errno value otherwise and rte_errno is set.
1497  */
1498 int
1499 mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt,
1500                          struct mlx5_devx_rqt_attr *rqt_attr)
1501 {
1502         uint32_t inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) +
1503                          rqt_attr->rqt_actual_size * sizeof(uint32_t);
1504         uint32_t out[MLX5_ST_SZ_DW(modify_rqt_out)] = {0};
1505         uint32_t *in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY);
1506         void *rqt_ctx;
1507         int i;
1508         int ret;
1509
1510         if (!in) {
1511                 DRV_LOG(ERR, "Failed to allocate RQT modify IN data.");
1512                 rte_errno = ENOMEM;
1513                 return -ENOMEM;
1514         }
1515         MLX5_SET(modify_rqt_in, in, opcode, MLX5_CMD_OP_MODIFY_RQT);
1516         MLX5_SET(modify_rqt_in, in, rqtn, rqt->id);
1517         MLX5_SET64(modify_rqt_in, in, modify_bitmask, 0x1);
1518         rqt_ctx = MLX5_ADDR_OF(modify_rqt_in, in, rqt_context);
1519         MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type);
1520         MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size);
1521         MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size);
1522         for (i = 0; i < rqt_attr->rqt_actual_size; i++)
1523                 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]);
1524         ret = mlx5_glue->devx_obj_modify(rqt->obj, in, inlen, out, sizeof(out));
1525         mlx5_free(in);
1526         if (ret) {
1527                 DRV_LOG(ERR, "Failed to modify RQT using DevX.");
1528                 rte_errno = errno;
1529                 return -rte_errno;
1530         }
1531         return ret;
1532 }
1533
1534 /**
1535  * Create SQ using DevX API.
1536  *
1537  * @param[in] ctx
1538  *   Context returned from mlx5 open_device() glue function.
1539  * @param [in] sq_attr
1540  *   Pointer to SQ attributes structure.
1541  * @param [in] socket
1542  *   CPU socket ID for allocations.
1543  *
1544  * @return
1545  *   The DevX object created, NULL otherwise and rte_errno is set.
1546  **/
1547 struct mlx5_devx_obj *
1548 mlx5_devx_cmd_create_sq(void *ctx,
1549                         struct mlx5_devx_create_sq_attr *sq_attr)
1550 {
1551         uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0};
1552         uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0};
1553         void *sq_ctx;
1554         void *wq_ctx;
1555         struct mlx5_devx_wq_attr *wq_attr;
1556         struct mlx5_devx_obj *sq = NULL;
1557
1558         sq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sq), 0, SOCKET_ID_ANY);
1559         if (!sq) {
1560                 DRV_LOG(ERR, "Failed to allocate SQ data");
1561                 rte_errno = ENOMEM;
1562                 return NULL;
1563         }
1564         MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ);
1565         sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx);
1566         MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky);
1567         MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master);
1568         MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre);
1569         MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en);
1570         MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe,
1571                  sq_attr->allow_multi_pkt_send_wqe);
1572         MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode,
1573                  sq_attr->min_wqe_inline_mode);
1574         MLX5_SET(sqc, sq_ctx, state, sq_attr->state);
1575         MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr);
1576         MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp);
1577         MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin);
1578         MLX5_SET(sqc, sq_ctx, non_wire, sq_attr->non_wire);
1579         MLX5_SET(sqc, sq_ctx, static_sq_wq, sq_attr->static_sq_wq);
1580         MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index);
1581         MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn);
1582         MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index,
1583                  sq_attr->packet_pacing_rate_limit_index);
1584         MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz);
1585         MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num);
1586         MLX5_SET(sqc, sq_ctx, ts_format, sq_attr->ts_format);
1587         wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq);
1588         wq_attr = &sq_attr->wq_attr;
1589         devx_cmd_fill_wq_data(wq_ctx, wq_attr);
1590         sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1591                                              out, sizeof(out));
1592         if (!sq->obj) {
1593                 DRV_LOG(ERR, "Failed to create SQ using DevX");
1594                 rte_errno = errno;
1595                 mlx5_free(sq);
1596                 return NULL;
1597         }
1598         sq->id = MLX5_GET(create_sq_out, out, sqn);
1599         return sq;
1600 }
1601
1602 /**
1603  * Modify SQ using DevX API.
1604  *
1605  * @param[in] sq
1606  *   Pointer to SQ object structure.
1607  * @param [in] sq_attr
1608  *   Pointer to SQ attributes structure.
1609  *
1610  * @return
1611  *   0 on success, a negative errno value otherwise and rte_errno is set.
1612  */
1613 int
1614 mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq,
1615                         struct mlx5_devx_modify_sq_attr *sq_attr)
1616 {
1617         uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0};
1618         uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0};
1619         void *sq_ctx;
1620         int ret;
1621
1622         MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ);
1623         MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state);
1624         MLX5_SET(modify_sq_in, in, sqn, sq->id);
1625         sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1626         MLX5_SET(sqc, sq_ctx, state, sq_attr->state);
1627         MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq);
1628         MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca);
1629         ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in),
1630                                          out, sizeof(out));
1631         if (ret) {
1632                 DRV_LOG(ERR, "Failed to modify SQ using DevX");
1633                 rte_errno = errno;
1634                 return -rte_errno;
1635         }
1636         return ret;
1637 }
1638
1639 /**
1640  * Create TIS using DevX API.
1641  *
1642  * @param[in] ctx
1643  *   Context returned from mlx5 open_device() glue function.
1644  * @param [in] tis_attr
1645  *   Pointer to TIS attributes structure.
1646  *
1647  * @return
1648  *   The DevX object created, NULL otherwise and rte_errno is set.
1649  */
1650 struct mlx5_devx_obj *
1651 mlx5_devx_cmd_create_tis(void *ctx,
1652                          struct mlx5_devx_tis_attr *tis_attr)
1653 {
1654         uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
1655         uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0};
1656         struct mlx5_devx_obj *tis = NULL;
1657         void *tis_ctx;
1658
1659         tis = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tis), 0, SOCKET_ID_ANY);
1660         if (!tis) {
1661                 DRV_LOG(ERR, "Failed to allocate TIS object");
1662                 rte_errno = ENOMEM;
1663                 return NULL;
1664         }
1665         MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS);
1666         tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx);
1667         MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity,
1668                  tis_attr->strict_lag_tx_port_affinity);
1669         MLX5_SET(tisc, tis_ctx, lag_tx_port_affinity,
1670                  tis_attr->lag_tx_port_affinity);
1671         MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio);
1672         MLX5_SET(tisc, tis_ctx, transport_domain,
1673                  tis_attr->transport_domain);
1674         tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1675                                               out, sizeof(out));
1676         if (!tis->obj) {
1677                 DRV_LOG(ERR, "Failed to create TIS using DevX");
1678                 rte_errno = errno;
1679                 mlx5_free(tis);
1680                 return NULL;
1681         }
1682         tis->id = MLX5_GET(create_tis_out, out, tisn);
1683         return tis;
1684 }
1685
1686 /**
1687  * Create transport domain using DevX API.
1688  *
1689  * @param[in] ctx
1690  *   Context returned from mlx5 open_device() glue function.
1691  * @return
1692  *   The DevX object created, NULL otherwise and rte_errno is set.
1693  */
1694 struct mlx5_devx_obj *
1695 mlx5_devx_cmd_create_td(void *ctx)
1696 {
1697         uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0};
1698         uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0};
1699         struct mlx5_devx_obj *td = NULL;
1700
1701         td = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*td), 0, SOCKET_ID_ANY);
1702         if (!td) {
1703                 DRV_LOG(ERR, "Failed to allocate TD object");
1704                 rte_errno = ENOMEM;
1705                 return NULL;
1706         }
1707         MLX5_SET(alloc_transport_domain_in, in, opcode,
1708                  MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN);
1709         td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1710                                              out, sizeof(out));
1711         if (!td->obj) {
1712                 DRV_LOG(ERR, "Failed to create TIS using DevX");
1713                 rte_errno = errno;
1714                 mlx5_free(td);
1715                 return NULL;
1716         }
1717         td->id = MLX5_GET(alloc_transport_domain_out, out,
1718                            transport_domain);
1719         return td;
1720 }
1721
1722 /**
1723  * Dump all flows to file.
1724  *
1725  * @param[in] fdb_domain
1726  *   FDB domain.
1727  * @param[in] rx_domain
1728  *   RX domain.
1729  * @param[in] tx_domain
1730  *   TX domain.
1731  * @param[out] file
1732  *   Pointer to file stream.
1733  *
1734  * @return
1735  *   0 on success, a nagative value otherwise.
1736  */
1737 int
1738 mlx5_devx_cmd_flow_dump(void *fdb_domain __rte_unused,
1739                         void *rx_domain __rte_unused,
1740                         void *tx_domain __rte_unused, FILE *file __rte_unused)
1741 {
1742         int ret = 0;
1743
1744 #ifdef HAVE_MLX5_DR_FLOW_DUMP
1745         if (fdb_domain) {
1746                 ret = mlx5_glue->dr_dump_domain(file, fdb_domain);
1747                 if (ret)
1748                         return ret;
1749         }
1750         MLX5_ASSERT(rx_domain);
1751         ret = mlx5_glue->dr_dump_domain(file, rx_domain);
1752         if (ret)
1753                 return ret;
1754         MLX5_ASSERT(tx_domain);
1755         ret = mlx5_glue->dr_dump_domain(file, tx_domain);
1756 #else
1757         ret = ENOTSUP;
1758 #endif
1759         return -ret;
1760 }
1761
1762 int
1763 mlx5_devx_cmd_flow_single_dump(void *rule_info __rte_unused,
1764                         FILE *file __rte_unused)
1765 {
1766         int ret = 0;
1767 #ifdef HAVE_MLX5_DR_FLOW_DUMP_RULE
1768         if (rule_info)
1769                 ret = mlx5_glue->dr_dump_rule(file, rule_info);
1770 #else
1771         ret = ENOTSUP;
1772 #endif
1773         return -ret;
1774 }
1775
1776 /*
1777  * Create CQ using DevX API.
1778  *
1779  * @param[in] ctx
1780  *   Context returned from mlx5 open_device() glue function.
1781  * @param [in] attr
1782  *   Pointer to CQ attributes structure.
1783  *
1784  * @return
1785  *   The DevX object created, NULL otherwise and rte_errno is set.
1786  */
1787 struct mlx5_devx_obj *
1788 mlx5_devx_cmd_create_cq(void *ctx, struct mlx5_devx_cq_attr *attr)
1789 {
1790         uint32_t in[MLX5_ST_SZ_DW(create_cq_in)] = {0};
1791         uint32_t out[MLX5_ST_SZ_DW(create_cq_out)] = {0};
1792         struct mlx5_devx_obj *cq_obj = mlx5_malloc(MLX5_MEM_ZERO,
1793                                                    sizeof(*cq_obj),
1794                                                    0, SOCKET_ID_ANY);
1795         void *cqctx = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1796
1797         if (!cq_obj) {
1798                 DRV_LOG(ERR, "Failed to allocate CQ object memory.");
1799                 rte_errno = ENOMEM;
1800                 return NULL;
1801         }
1802         MLX5_SET(create_cq_in, in, opcode, MLX5_CMD_OP_CREATE_CQ);
1803         if (attr->db_umem_valid) {
1804                 MLX5_SET(cqc, cqctx, dbr_umem_valid, attr->db_umem_valid);
1805                 MLX5_SET(cqc, cqctx, dbr_umem_id, attr->db_umem_id);
1806                 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_umem_offset);
1807         } else {
1808                 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_addr);
1809         }
1810         MLX5_SET(cqc, cqctx, cqe_sz, (RTE_CACHE_LINE_SIZE == 128) ?
1811                                      MLX5_CQE_SIZE_128B : MLX5_CQE_SIZE_64B);
1812         MLX5_SET(cqc, cqctx, cc, attr->use_first_only);
1813         MLX5_SET(cqc, cqctx, oi, attr->overrun_ignore);
1814         MLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size);
1815         if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT)
1816                 MLX5_SET(cqc, cqctx, log_page_size,
1817                          attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT);
1818         MLX5_SET(cqc, cqctx, c_eqn, attr->eqn);
1819         MLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id);
1820         MLX5_SET(cqc, cqctx, cqe_comp_en, !!attr->cqe_comp_en);
1821         MLX5_SET(cqc, cqctx, mini_cqe_res_format, attr->mini_cqe_res_format);
1822         MLX5_SET(cqc, cqctx, mini_cqe_res_format_ext,
1823                  attr->mini_cqe_res_format_ext);
1824         if (attr->q_umem_valid) {
1825                 MLX5_SET(create_cq_in, in, cq_umem_valid, attr->q_umem_valid);
1826                 MLX5_SET(create_cq_in, in, cq_umem_id, attr->q_umem_id);
1827                 MLX5_SET64(create_cq_in, in, cq_umem_offset,
1828                            attr->q_umem_offset);
1829         }
1830         cq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
1831                                                  sizeof(out));
1832         if (!cq_obj->obj) {
1833                 rte_errno = errno;
1834                 DRV_LOG(ERR, "Failed to create CQ using DevX errno=%d.", errno);
1835                 mlx5_free(cq_obj);
1836                 return NULL;
1837         }
1838         cq_obj->id = MLX5_GET(create_cq_out, out, cqn);
1839         return cq_obj;
1840 }
1841
1842 /**
1843  * Create VIRTQ using DevX API.
1844  *
1845  * @param[in] ctx
1846  *   Context returned from mlx5 open_device() glue function.
1847  * @param [in] attr
1848  *   Pointer to VIRTQ attributes structure.
1849  *
1850  * @return
1851  *   The DevX object created, NULL otherwise and rte_errno is set.
1852  */
1853 struct mlx5_devx_obj *
1854 mlx5_devx_cmd_create_virtq(void *ctx,
1855                            struct mlx5_devx_virtq_attr *attr)
1856 {
1857         uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0};
1858         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
1859         struct mlx5_devx_obj *virtq_obj = mlx5_malloc(MLX5_MEM_ZERO,
1860                                                      sizeof(*virtq_obj),
1861                                                      0, SOCKET_ID_ANY);
1862         void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq);
1863         void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr);
1864         void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context);
1865
1866         if (!virtq_obj) {
1867                 DRV_LOG(ERR, "Failed to allocate virtq data.");
1868                 rte_errno = ENOMEM;
1869                 return NULL;
1870         }
1871         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
1872                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
1873         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
1874                  MLX5_GENERAL_OBJ_TYPE_VIRTQ);
1875         MLX5_SET16(virtio_net_q, virtq, hw_available_index,
1876                    attr->hw_available_index);
1877         MLX5_SET16(virtio_net_q, virtq, hw_used_index, attr->hw_used_index);
1878         MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4);
1879         MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6);
1880         MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum);
1881         MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum);
1882         MLX5_SET16(virtio_q, virtctx, virtio_version_1_0,
1883                    attr->virtio_version_1_0);
1884         MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode);
1885         MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id);
1886         MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr);
1887         MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr);
1888         MLX5_SET64(virtio_q, virtctx, available_addr, attr->available_addr);
1889         MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index);
1890         MLX5_SET16(virtio_q, virtctx, queue_size, attr->q_size);
1891         MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey);
1892         MLX5_SET(virtio_q, virtctx, umem_1_id, attr->umems[0].id);
1893         MLX5_SET(virtio_q, virtctx, umem_1_size, attr->umems[0].size);
1894         MLX5_SET64(virtio_q, virtctx, umem_1_offset, attr->umems[0].offset);
1895         MLX5_SET(virtio_q, virtctx, umem_2_id, attr->umems[1].id);
1896         MLX5_SET(virtio_q, virtctx, umem_2_size, attr->umems[1].size);
1897         MLX5_SET64(virtio_q, virtctx, umem_2_offset, attr->umems[1].offset);
1898         MLX5_SET(virtio_q, virtctx, umem_3_id, attr->umems[2].id);
1899         MLX5_SET(virtio_q, virtctx, umem_3_size, attr->umems[2].size);
1900         MLX5_SET64(virtio_q, virtctx, umem_3_offset, attr->umems[2].offset);
1901         MLX5_SET(virtio_q, virtctx, counter_set_id, attr->counters_obj_id);
1902         MLX5_SET(virtio_q, virtctx, pd, attr->pd);
1903         MLX5_SET(virtio_q, virtctx, queue_period_mode, attr->hw_latency_mode);
1904         MLX5_SET(virtio_q, virtctx, queue_period_us, attr->hw_max_latency_us);
1905         MLX5_SET(virtio_q, virtctx, queue_max_count, attr->hw_max_pending_comp);
1906         MLX5_SET(virtio_net_q, virtq, tisn_or_qpn, attr->tis_id);
1907         virtq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
1908                                                     sizeof(out));
1909         if (!virtq_obj->obj) {
1910                 rte_errno = errno;
1911                 DRV_LOG(ERR, "Failed to create VIRTQ Obj using DevX.");
1912                 mlx5_free(virtq_obj);
1913                 return NULL;
1914         }
1915         virtq_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
1916         return virtq_obj;
1917 }
1918
1919 /**
1920  * Modify VIRTQ using DevX API.
1921  *
1922  * @param[in] virtq_obj
1923  *   Pointer to virtq object structure.
1924  * @param [in] attr
1925  *   Pointer to modify virtq attributes structure.
1926  *
1927  * @return
1928  *   0 on success, a negative errno value otherwise and rte_errno is set.
1929  */
1930 int
1931 mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj,
1932                            struct mlx5_devx_virtq_attr *attr)
1933 {
1934         uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0};
1935         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
1936         void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq);
1937         void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr);
1938         void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context);
1939         int ret;
1940
1941         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
1942                  MLX5_CMD_OP_MODIFY_GENERAL_OBJECT);
1943         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
1944                  MLX5_GENERAL_OBJ_TYPE_VIRTQ);
1945         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id);
1946         MLX5_SET64(virtio_net_q, virtq, modify_field_select, attr->type);
1947         MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index);
1948         switch (attr->type) {
1949         case MLX5_VIRTQ_MODIFY_TYPE_STATE:
1950                 MLX5_SET16(virtio_net_q, virtq, state, attr->state);
1951                 break;
1952         case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS:
1953                 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_mkey,
1954                          attr->dirty_bitmap_mkey);
1955                 MLX5_SET64(virtio_net_q, virtq, dirty_bitmap_addr,
1956                          attr->dirty_bitmap_addr);
1957                 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_size,
1958                          attr->dirty_bitmap_size);
1959                 break;
1960         case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE:
1961                 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_dump_enable,
1962                          attr->dirty_bitmap_dump_enable);
1963                 break;
1964         default:
1965                 rte_errno = EINVAL;
1966                 return -rte_errno;
1967         }
1968         ret = mlx5_glue->devx_obj_modify(virtq_obj->obj, in, sizeof(in),
1969                                          out, sizeof(out));
1970         if (ret) {
1971                 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX.");
1972                 rte_errno = errno;
1973                 return -rte_errno;
1974         }
1975         return ret;
1976 }
1977
1978 /**
1979  * Query VIRTQ using DevX API.
1980  *
1981  * @param[in] virtq_obj
1982  *   Pointer to virtq object structure.
1983  * @param [in/out] attr
1984  *   Pointer to virtq attributes structure.
1985  *
1986  * @return
1987  *   0 on success, a negative errno value otherwise and rte_errno is set.
1988  */
1989 int
1990 mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj,
1991                            struct mlx5_devx_virtq_attr *attr)
1992 {
1993         uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
1994         uint32_t out[MLX5_ST_SZ_DW(query_virtq_out)] = {0};
1995         void *hdr = MLX5_ADDR_OF(query_virtq_out, in, hdr);
1996         void *virtq = MLX5_ADDR_OF(query_virtq_out, out, virtq);
1997         int ret;
1998
1999         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2000                  MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
2001         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2002                  MLX5_GENERAL_OBJ_TYPE_VIRTQ);
2003         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id);
2004         ret = mlx5_glue->devx_obj_query(virtq_obj->obj, in, sizeof(in),
2005                                          out, sizeof(out));
2006         if (ret) {
2007                 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX.");
2008                 rte_errno = errno;
2009                 return -errno;
2010         }
2011         attr->hw_available_index = MLX5_GET16(virtio_net_q, virtq,
2012                                               hw_available_index);
2013         attr->hw_used_index = MLX5_GET16(virtio_net_q, virtq, hw_used_index);
2014         attr->state = MLX5_GET16(virtio_net_q, virtq, state);
2015         attr->error_type = MLX5_GET16(virtio_net_q, virtq,
2016                                       virtio_q_context.error_type);
2017         return ret;
2018 }
2019
2020 /**
2021  * Create QP using DevX API.
2022  *
2023  * @param[in] ctx
2024  *   Context returned from mlx5 open_device() glue function.
2025  * @param [in] attr
2026  *   Pointer to QP attributes structure.
2027  *
2028  * @return
2029  *   The DevX object created, NULL otherwise and rte_errno is set.
2030  */
2031 struct mlx5_devx_obj *
2032 mlx5_devx_cmd_create_qp(void *ctx,
2033                         struct mlx5_devx_qp_attr *attr)
2034 {
2035         uint32_t in[MLX5_ST_SZ_DW(create_qp_in)] = {0};
2036         uint32_t out[MLX5_ST_SZ_DW(create_qp_out)] = {0};
2037         struct mlx5_devx_obj *qp_obj = mlx5_malloc(MLX5_MEM_ZERO,
2038                                                    sizeof(*qp_obj),
2039                                                    0, SOCKET_ID_ANY);
2040         void *qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
2041
2042         if (!qp_obj) {
2043                 DRV_LOG(ERR, "Failed to allocate QP data.");
2044                 rte_errno = ENOMEM;
2045                 return NULL;
2046         }
2047         MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP);
2048         MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC);
2049         MLX5_SET(qpc, qpc, pd, attr->pd);
2050         MLX5_SET(qpc, qpc, ts_format, attr->ts_format);
2051         MLX5_SET(qpc, qpc, user_index, attr->user_index);
2052         if (attr->uar_index) {
2053                 if (attr->mmo) {
2054                         void *qpc_ext_and_pas_list = MLX5_ADDR_OF(create_qp_in,
2055                                 in, qpc_extension_and_pas_list);
2056                         void *qpc_ext = MLX5_ADDR_OF(qpc_extension_and_pas_list,
2057                                 qpc_ext_and_pas_list, qpc_data_extension);
2058                         MLX5_SET(qpc_extension, qpc_ext, mmo, 1);
2059                 }
2060                 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
2061                 MLX5_SET(qpc, qpc, uar_page, attr->uar_index);
2062                 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT)
2063                         MLX5_SET(qpc, qpc, log_page_size,
2064                                  attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT);
2065                 if (attr->sq_size) {
2066                         MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->sq_size));
2067                         MLX5_SET(qpc, qpc, cqn_snd, attr->cqn);
2068                         MLX5_SET(qpc, qpc, log_sq_size,
2069                                  rte_log2_u32(attr->sq_size));
2070                 } else {
2071                         MLX5_SET(qpc, qpc, no_sq, 1);
2072                 }
2073                 if (attr->rq_size) {
2074                         MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->rq_size));
2075                         MLX5_SET(qpc, qpc, cqn_rcv, attr->cqn);
2076                         MLX5_SET(qpc, qpc, log_rq_stride, attr->log_rq_stride -
2077                                  MLX5_LOG_RQ_STRIDE_SHIFT);
2078                         MLX5_SET(qpc, qpc, log_rq_size,
2079                                  rte_log2_u32(attr->rq_size));
2080                         MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ);
2081                 } else {
2082                         MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ);
2083                 }
2084                 if (attr->dbr_umem_valid) {
2085                         MLX5_SET(qpc, qpc, dbr_umem_valid,
2086                                  attr->dbr_umem_valid);
2087                         MLX5_SET(qpc, qpc, dbr_umem_id, attr->dbr_umem_id);
2088                 }
2089                 MLX5_SET64(qpc, qpc, dbr_addr, attr->dbr_address);
2090                 MLX5_SET64(create_qp_in, in, wq_umem_offset,
2091                            attr->wq_umem_offset);
2092                 MLX5_SET(create_qp_in, in, wq_umem_id, attr->wq_umem_id);
2093                 MLX5_SET(create_qp_in, in, wq_umem_valid, 1);
2094         } else {
2095                 /* Special QP to be managed by FW - no SQ\RQ\CQ\UAR\DB rec. */
2096                 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ);
2097                 MLX5_SET(qpc, qpc, no_sq, 1);
2098         }
2099         qp_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
2100                                                  sizeof(out));
2101         if (!qp_obj->obj) {
2102                 rte_errno = errno;
2103                 DRV_LOG(ERR, "Failed to create QP Obj using DevX.");
2104                 mlx5_free(qp_obj);
2105                 return NULL;
2106         }
2107         qp_obj->id = MLX5_GET(create_qp_out, out, qpn);
2108         return qp_obj;
2109 }
2110
2111 /**
2112  * Modify QP using DevX API.
2113  * Currently supports only force loop-back QP.
2114  *
2115  * @param[in] qp
2116  *   Pointer to QP object structure.
2117  * @param [in] qp_st_mod_op
2118  *   The QP state modification operation.
2119  * @param [in] remote_qp_id
2120  *   The remote QP ID for MLX5_CMD_OP_INIT2RTR_QP operation.
2121  *
2122  * @return
2123  *   0 on success, a negative errno value otherwise and rte_errno is set.
2124  */
2125 int
2126 mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op,
2127                               uint32_t remote_qp_id)
2128 {
2129         union {
2130                 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)];
2131                 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)];
2132                 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)];
2133         } in;
2134         union {
2135                 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)];
2136                 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)];
2137                 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)];
2138         } out;
2139         void *qpc;
2140         int ret;
2141         unsigned int inlen;
2142         unsigned int outlen;
2143
2144         memset(&in, 0, sizeof(in));
2145         memset(&out, 0, sizeof(out));
2146         MLX5_SET(rst2init_qp_in, &in, opcode, qp_st_mod_op);
2147         switch (qp_st_mod_op) {
2148         case MLX5_CMD_OP_RST2INIT_QP:
2149                 MLX5_SET(rst2init_qp_in, &in, qpn, qp->id);
2150                 qpc = MLX5_ADDR_OF(rst2init_qp_in, &in, qpc);
2151                 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1);
2152                 MLX5_SET(qpc, qpc, rre, 1);
2153                 MLX5_SET(qpc, qpc, rwe, 1);
2154                 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
2155                 inlen = sizeof(in.rst2init);
2156                 outlen = sizeof(out.rst2init);
2157                 break;
2158         case MLX5_CMD_OP_INIT2RTR_QP:
2159                 MLX5_SET(init2rtr_qp_in, &in, qpn, qp->id);
2160                 qpc = MLX5_ADDR_OF(init2rtr_qp_in, &in, qpc);
2161                 MLX5_SET(qpc, qpc, primary_address_path.fl, 1);
2162                 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1);
2163                 MLX5_SET(qpc, qpc, mtu, 1);
2164                 MLX5_SET(qpc, qpc, log_msg_max, 30);
2165                 MLX5_SET(qpc, qpc, remote_qpn, remote_qp_id);
2166                 MLX5_SET(qpc, qpc, min_rnr_nak, 0);
2167                 inlen = sizeof(in.init2rtr);
2168                 outlen = sizeof(out.init2rtr);
2169                 break;
2170         case MLX5_CMD_OP_RTR2RTS_QP:
2171                 qpc = MLX5_ADDR_OF(rtr2rts_qp_in, &in, qpc);
2172                 MLX5_SET(rtr2rts_qp_in, &in, qpn, qp->id);
2173                 MLX5_SET(qpc, qpc, primary_address_path.ack_timeout, 14);
2174                 MLX5_SET(qpc, qpc, log_ack_req_freq, 0);
2175                 MLX5_SET(qpc, qpc, retry_count, 7);
2176                 MLX5_SET(qpc, qpc, rnr_retry, 7);
2177                 inlen = sizeof(in.rtr2rts);
2178                 outlen = sizeof(out.rtr2rts);
2179                 break;
2180         default:
2181                 DRV_LOG(ERR, "Invalid or unsupported QP modify op %u.",
2182                         qp_st_mod_op);
2183                 rte_errno = EINVAL;
2184                 return -rte_errno;
2185         }
2186         ret = mlx5_glue->devx_obj_modify(qp->obj, &in, inlen, &out, outlen);
2187         if (ret) {
2188                 DRV_LOG(ERR, "Failed to modify QP using DevX.");
2189                 rte_errno = errno;
2190                 return -rte_errno;
2191         }
2192         return ret;
2193 }
2194
2195 struct mlx5_devx_obj *
2196 mlx5_devx_cmd_create_virtio_q_counters(void *ctx)
2197 {
2198         uint32_t in[MLX5_ST_SZ_DW(create_virtio_q_counters_in)] = {0};
2199         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2200         struct mlx5_devx_obj *couners_obj = mlx5_malloc(MLX5_MEM_ZERO,
2201                                                        sizeof(*couners_obj), 0,
2202                                                        SOCKET_ID_ANY);
2203         void *hdr = MLX5_ADDR_OF(create_virtio_q_counters_in, in, hdr);
2204
2205         if (!couners_obj) {
2206                 DRV_LOG(ERR, "Failed to allocate virtio queue counters data.");
2207                 rte_errno = ENOMEM;
2208                 return NULL;
2209         }
2210         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2211                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2212         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2213                  MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS);
2214         couners_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
2215                                                       sizeof(out));
2216         if (!couners_obj->obj) {
2217                 rte_errno = errno;
2218                 DRV_LOG(ERR, "Failed to create virtio queue counters Obj using"
2219                         " DevX.");
2220                 mlx5_free(couners_obj);
2221                 return NULL;
2222         }
2223         couners_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2224         return couners_obj;
2225 }
2226
2227 int
2228 mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj,
2229                                    struct mlx5_devx_virtio_q_couners_attr *attr)
2230 {
2231         uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
2232         uint32_t out[MLX5_ST_SZ_DW(query_virtio_q_counters_out)] = {0};
2233         void *hdr = MLX5_ADDR_OF(query_virtio_q_counters_out, in, hdr);
2234         void *virtio_q_counters = MLX5_ADDR_OF(query_virtio_q_counters_out, out,
2235                                                virtio_q_counters);
2236         int ret;
2237
2238         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2239                  MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
2240         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2241                  MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS);
2242         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, couners_obj->id);
2243         ret = mlx5_glue->devx_obj_query(couners_obj->obj, in, sizeof(in), out,
2244                                         sizeof(out));
2245         if (ret) {
2246                 DRV_LOG(ERR, "Failed to query virtio q counters using DevX.");
2247                 rte_errno = errno;
2248                 return -errno;
2249         }
2250         attr->received_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters,
2251                                          received_desc);
2252         attr->completed_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters,
2253                                           completed_desc);
2254         attr->error_cqes = MLX5_GET(virtio_q_counters, virtio_q_counters,
2255                                     error_cqes);
2256         attr->bad_desc_errors = MLX5_GET(virtio_q_counters, virtio_q_counters,
2257                                          bad_desc_errors);
2258         attr->exceed_max_chain = MLX5_GET(virtio_q_counters, virtio_q_counters,
2259                                           exceed_max_chain);
2260         attr->invalid_buffer = MLX5_GET(virtio_q_counters, virtio_q_counters,
2261                                         invalid_buffer);
2262         return ret;
2263 }
2264
2265 /**
2266  * Create general object of type FLOW_HIT_ASO using DevX API.
2267  *
2268  * @param[in] ctx
2269  *   Context returned from mlx5 open_device() glue function.
2270  * @param [in] pd
2271  *   PD value to associate the FLOW_HIT_ASO object with.
2272  *
2273  * @return
2274  *   The DevX object created, NULL otherwise and rte_errno is set.
2275  */
2276 struct mlx5_devx_obj *
2277 mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, uint32_t pd)
2278 {
2279         uint32_t in[MLX5_ST_SZ_DW(create_flow_hit_aso_in)] = {0};
2280         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2281         struct mlx5_devx_obj *flow_hit_aso_obj = NULL;
2282         void *ptr = NULL;
2283
2284         flow_hit_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*flow_hit_aso_obj),
2285                                        0, SOCKET_ID_ANY);
2286         if (!flow_hit_aso_obj) {
2287                 DRV_LOG(ERR, "Failed to allocate FLOW_HIT_ASO object data");
2288                 rte_errno = ENOMEM;
2289                 return NULL;
2290         }
2291         ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, hdr);
2292         MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2293                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2294         MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2295                  MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO);
2296         ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, flow_hit_aso);
2297         MLX5_SET(flow_hit_aso, ptr, access_pd, pd);
2298         flow_hit_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2299                                                            out, sizeof(out));
2300         if (!flow_hit_aso_obj->obj) {
2301                 rte_errno = errno;
2302                 DRV_LOG(ERR, "Failed to create FLOW_HIT_ASO obj using DevX.");
2303                 mlx5_free(flow_hit_aso_obj);
2304                 return NULL;
2305         }
2306         flow_hit_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2307         return flow_hit_aso_obj;
2308 }
2309
2310 /*
2311  * Create PD using DevX API.
2312  *
2313  * @param[in] ctx
2314  *   Context returned from mlx5 open_device() glue function.
2315  *
2316  * @return
2317  *   The DevX object created, NULL otherwise and rte_errno is set.
2318  */
2319 struct mlx5_devx_obj *
2320 mlx5_devx_cmd_alloc_pd(void *ctx)
2321 {
2322         struct mlx5_devx_obj *ppd =
2323                 mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ppd), 0, SOCKET_ID_ANY);
2324         u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {0};
2325         u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {0};
2326
2327         if (!ppd) {
2328                 DRV_LOG(ERR, "Failed to allocate PD data.");
2329                 rte_errno = ENOMEM;
2330                 return NULL;
2331         }
2332         MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD);
2333         ppd->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2334                                 out, sizeof(out));
2335         if (!ppd->obj) {
2336                 mlx5_free(ppd);
2337                 DRV_LOG(ERR, "Failed to allocate PD Obj using DevX.");
2338                 rte_errno = errno;
2339                 return NULL;
2340         }
2341         ppd->id = MLX5_GET(alloc_pd_out, out, pd);
2342         return ppd;
2343 }
2344
2345 /**
2346  * Create general object of type FLOW_METER_ASO using DevX API.
2347  *
2348  * @param[in] ctx
2349  *   Context returned from mlx5 open_device() glue function.
2350  * @param [in] pd
2351  *   PD value to associate the FLOW_METER_ASO object with.
2352  * @param [in] log_obj_size
2353  *   log_obj_size define to allocate number of 2 * meters
2354  *   in one FLOW_METER_ASO object.
2355  *
2356  * @return
2357  *   The DevX object created, NULL otherwise and rte_errno is set.
2358  */
2359 struct mlx5_devx_obj *
2360 mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx, uint32_t pd,
2361                                                 uint32_t log_obj_size)
2362 {
2363         uint32_t in[MLX5_ST_SZ_DW(create_flow_meter_aso_in)] = {0};
2364         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)];
2365         struct mlx5_devx_obj *flow_meter_aso_obj;
2366         void *ptr;
2367
2368         flow_meter_aso_obj = mlx5_malloc(MLX5_MEM_ZERO,
2369                                                 sizeof(*flow_meter_aso_obj),
2370                                                 0, SOCKET_ID_ANY);
2371         if (!flow_meter_aso_obj) {
2372                 DRV_LOG(ERR, "Failed to allocate FLOW_METER_ASO object data");
2373                 rte_errno = ENOMEM;
2374                 return NULL;
2375         }
2376         ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, hdr);
2377         MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2378                 MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2379         MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2380                 MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO);
2381         MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range,
2382                 log_obj_size);
2383         ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, flow_meter_aso);
2384         MLX5_SET(flow_meter_aso, ptr, access_pd, pd);
2385         flow_meter_aso_obj->obj = mlx5_glue->devx_obj_create(
2386                                                         ctx, in, sizeof(in),
2387                                                         out, sizeof(out));
2388         if (!flow_meter_aso_obj->obj) {
2389                 rte_errno = errno;
2390                 DRV_LOG(ERR, "Failed to create FLOW_METER_ASO obj using DevX.");
2391                 mlx5_free(flow_meter_aso_obj);
2392                 return NULL;
2393         }
2394         flow_meter_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr,
2395                                                                 out, obj_id);
2396         return flow_meter_aso_obj;
2397 }
2398
2399 /*
2400  * Create general object of type CONN_TRACK_OFFLOAD using DevX API.
2401  *
2402  * @param[in] ctx
2403  *   Context returned from mlx5 open_device() glue function.
2404  * @param [in] pd
2405  *   PD value to associate the CONN_TRACK_OFFLOAD ASO object with.
2406  * @param [in] log_obj_size
2407  *   log_obj_size to allocate its power of 2 * objects
2408  *   in one CONN_TRACK_OFFLOAD bulk allocation.
2409  *
2410  * @return
2411  *   The DevX object created, NULL otherwise and rte_errno is set.
2412  */
2413 struct mlx5_devx_obj *
2414 mlx5_devx_cmd_create_conn_track_offload_obj(void *ctx, uint32_t pd,
2415                                             uint32_t log_obj_size)
2416 {
2417         uint32_t in[MLX5_ST_SZ_DW(create_conn_track_aso_in)] = {0};
2418         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)];
2419         struct mlx5_devx_obj *ct_aso_obj;
2420         void *ptr;
2421
2422         ct_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ct_aso_obj),
2423                                  0, SOCKET_ID_ANY);
2424         if (!ct_aso_obj) {
2425                 DRV_LOG(ERR, "Failed to allocate CONN_TRACK_OFFLOAD object.");
2426                 rte_errno = ENOMEM;
2427                 return NULL;
2428         }
2429         ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, hdr);
2430         MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2431                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2432         MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2433                  MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD);
2434         MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range, log_obj_size);
2435         ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, conn_track_offload);
2436         MLX5_SET(conn_track_offload, ptr, conn_track_aso_access_pd, pd);
2437         ct_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2438                                                      out, sizeof(out));
2439         if (!ct_aso_obj->obj) {
2440                 rte_errno = errno;
2441                 DRV_LOG(ERR, "Failed to create CONN_TRACK_OFFLOAD obj by using DevX.");
2442                 mlx5_free(ct_aso_obj);
2443                 return NULL;
2444         }
2445         ct_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2446         return ct_aso_obj;
2447 }
2448
2449 /**
2450  * Create general object of type GENEVE TLV option using DevX API.
2451  *
2452  * @param[in] ctx
2453  *   Context returned from mlx5 open_device() glue function.
2454  * @param [in] class
2455  *   TLV option variable value of class
2456  * @param [in] type
2457  *   TLV option variable value of type
2458  * @param [in] len
2459  *   TLV option variable value of len
2460  *
2461  * @return
2462  *   The DevX object created, NULL otherwise and rte_errno is set.
2463  */
2464 struct mlx5_devx_obj *
2465 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx,
2466                 uint16_t class, uint8_t type, uint8_t len)
2467 {
2468         uint32_t in[MLX5_ST_SZ_DW(create_geneve_tlv_option_in)] = {0};
2469         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2470         struct mlx5_devx_obj *geneve_tlv_opt_obj = mlx5_malloc(MLX5_MEM_ZERO,
2471                                                    sizeof(*geneve_tlv_opt_obj),
2472                                                    0, SOCKET_ID_ANY);
2473
2474         if (!geneve_tlv_opt_obj) {
2475                 DRV_LOG(ERR, "Failed to allocate geneve tlv option object.");
2476                 rte_errno = ENOMEM;
2477                 return NULL;
2478         }
2479         void *hdr = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, hdr);
2480         void *opt = MLX5_ADDR_OF(create_geneve_tlv_option_in, in,
2481                         geneve_tlv_opt);
2482         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2483                         MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2484         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2485                  MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT);
2486         MLX5_SET(geneve_tlv_option, opt, option_class,
2487                         rte_be_to_cpu_16(class));
2488         MLX5_SET(geneve_tlv_option, opt, option_type, type);
2489         MLX5_SET(geneve_tlv_option, opt, option_data_length, len);
2490         geneve_tlv_opt_obj->obj = mlx5_glue->devx_obj_create(ctx, in,
2491                                         sizeof(in), out, sizeof(out));
2492         if (!geneve_tlv_opt_obj->obj) {
2493                 rte_errno = errno;
2494                 DRV_LOG(ERR, "Failed to create Geneve tlv option "
2495                                 "Obj using DevX.");
2496                 mlx5_free(geneve_tlv_opt_obj);
2497                 return NULL;
2498         }
2499         geneve_tlv_opt_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2500         return geneve_tlv_opt_obj;
2501 }
2502
2503 int
2504 mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id)
2505 {
2506 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2507         uint32_t in[MLX5_ST_SZ_DW(query_rq_in)] = {0};
2508         uint32_t out[MLX5_ST_SZ_DW(query_rq_out)] = {0};
2509         int rc;
2510         void *rq_ctx;
2511
2512         MLX5_SET(query_rq_in, in, opcode, MLX5_CMD_OP_QUERY_RQ);
2513         MLX5_SET(query_rq_in, in, rqn, ((struct ibv_wq *)wq)->wq_num);
2514         rc = mlx5_glue->devx_wq_query(wq, in, sizeof(in), out, sizeof(out));
2515         if (rc) {
2516                 rte_errno = errno;
2517                 DRV_LOG(ERR, "Failed to query WQ counter set ID using DevX - "
2518                         "rc = %d, errno = %d.", rc, errno);
2519                 return -rc;
2520         };
2521         rq_ctx = MLX5_ADDR_OF(query_rq_out, out, rq_context);
2522         *counter_set_id = MLX5_GET(rqc, rq_ctx, counter_set_id);
2523         return 0;
2524 #else
2525         (void)wq;
2526         (void)counter_set_id;
2527         return -ENOTSUP;
2528 #endif
2529 }
2530
2531 /*
2532  * Allocate queue counters via devx interface.
2533  *
2534  * @param[in] ctx
2535  *   Context returned from mlx5 open_device() glue function.
2536  *
2537  * @return
2538  *   Pointer to counter object on success, a NULL value otherwise and
2539  *   rte_errno is set.
2540  */
2541 struct mlx5_devx_obj *
2542 mlx5_devx_cmd_queue_counter_alloc(void *ctx)
2543 {
2544         struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 0,
2545                                                 SOCKET_ID_ANY);
2546         uint32_t in[MLX5_ST_SZ_DW(alloc_q_counter_in)]   = {0};
2547         uint32_t out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {0};
2548
2549         if (!dcs) {
2550                 rte_errno = ENOMEM;
2551                 return NULL;
2552         }
2553         MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER);
2554         dcs->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
2555                                               sizeof(out));
2556         if (!dcs->obj) {
2557                 DRV_LOG(DEBUG, "Can't allocate q counter set by DevX - error "
2558                         "%d.", errno);
2559                 rte_errno = errno;
2560                 mlx5_free(dcs);
2561                 return NULL;
2562         }
2563         dcs->id = MLX5_GET(alloc_q_counter_out, out, counter_set_id);
2564         return dcs;
2565 }
2566
2567 /**
2568  * Query queue counters values.
2569  *
2570  * @param[in] dcs
2571  *   devx object of the queue counter set.
2572  * @param[in] clear
2573  *   Whether hardware should clear the counters after the query or not.
2574  *  @param[out] out_of_buffers
2575  *   Number of dropped occurred due to lack of WQE for the associated QPs/RQs.
2576  *
2577  * @return
2578  *   0 on success, a negative value otherwise.
2579  */
2580 int
2581 mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear,
2582                                   uint32_t *out_of_buffers)
2583 {
2584         uint32_t out[MLX5_ST_SZ_BYTES(query_q_counter_out)] = {0};
2585         uint32_t in[MLX5_ST_SZ_DW(query_q_counter_in)] = {0};
2586         int rc;
2587
2588         MLX5_SET(query_q_counter_in, in, opcode,
2589                  MLX5_CMD_OP_QUERY_Q_COUNTER);
2590         MLX5_SET(query_q_counter_in, in, op_mod, 0);
2591         MLX5_SET(query_q_counter_in, in, counter_set_id, dcs->id);
2592         MLX5_SET(query_q_counter_in, in, clear, !!clear);
2593         rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out,
2594                                        sizeof(out));
2595         if (rc) {
2596                 DRV_LOG(ERR, "Failed to query devx q counter set - rc %d", rc);
2597                 rte_errno = rc;
2598                 return -rc;
2599         }
2600         *out_of_buffers = MLX5_GET(query_q_counter_out, out, out_of_buffer);
2601         return 0;
2602 }
2603
2604 /**
2605  * Create general object of type DEK using DevX API.
2606  *
2607  * @param[in] ctx
2608  *   Context returned from mlx5 open_device() glue function.
2609  * @param [in] attr
2610  *   Pointer to DEK attributes structure.
2611  *
2612  * @return
2613  *   The DevX object created, NULL otherwise and rte_errno is set.
2614  */
2615 struct mlx5_devx_obj *
2616 mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr)
2617 {
2618         uint32_t in[MLX5_ST_SZ_DW(create_dek_in)] = {0};
2619         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2620         struct mlx5_devx_obj *dek_obj = NULL;
2621         void *ptr = NULL, *key_addr = NULL;
2622
2623         dek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dek_obj),
2624                               0, SOCKET_ID_ANY);
2625         if (dek_obj == NULL) {
2626                 DRV_LOG(ERR, "Failed to allocate DEK object data");
2627                 rte_errno = ENOMEM;
2628                 return NULL;
2629         }
2630         ptr = MLX5_ADDR_OF(create_dek_in, in, hdr);
2631         MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2632                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2633         MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2634                  MLX5_GENERAL_OBJ_TYPE_DEK);
2635         ptr = MLX5_ADDR_OF(create_dek_in, in, dek);
2636         MLX5_SET(dek, ptr, key_size, attr->key_size);
2637         MLX5_SET(dek, ptr, has_keytag, attr->has_keytag);
2638         MLX5_SET(dek, ptr, key_purpose, attr->key_purpose);
2639         MLX5_SET(dek, ptr, pd, attr->pd);
2640         MLX5_SET64(dek, ptr, opaque, attr->opaque);
2641         key_addr = MLX5_ADDR_OF(dek, ptr, key);
2642         memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE);
2643         dek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2644                                                   out, sizeof(out));
2645         if (dek_obj->obj == NULL) {
2646                 rte_errno = errno;
2647                 DRV_LOG(ERR, "Failed to create DEK obj using DevX.");
2648                 mlx5_free(dek_obj);
2649                 return NULL;
2650         }
2651         dek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2652         return dek_obj;
2653 }
2654
2655 /**
2656  * Create general object of type IMPORT_KEK using DevX API.
2657  *
2658  * @param[in] ctx
2659  *   Context returned from mlx5 open_device() glue function.
2660  * @param [in] attr
2661  *   Pointer to IMPORT_KEK attributes structure.
2662  *
2663  * @return
2664  *   The DevX object created, NULL otherwise and rte_errno is set.
2665  */
2666 struct mlx5_devx_obj *
2667 mlx5_devx_cmd_create_import_kek_obj(void *ctx,
2668                                     struct mlx5_devx_import_kek_attr *attr)
2669 {
2670         uint32_t in[MLX5_ST_SZ_DW(create_import_kek_in)] = {0};
2671         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2672         struct mlx5_devx_obj *import_kek_obj = NULL;
2673         void *ptr = NULL, *key_addr = NULL;
2674
2675         import_kek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*import_kek_obj),
2676                                      0, SOCKET_ID_ANY);
2677         if (import_kek_obj == NULL) {
2678                 DRV_LOG(ERR, "Failed to allocate IMPORT_KEK object data");
2679                 rte_errno = ENOMEM;
2680                 return NULL;
2681         }
2682         ptr = MLX5_ADDR_OF(create_import_kek_in, in, hdr);
2683         MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2684                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2685         MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2686                  MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK);
2687         ptr = MLX5_ADDR_OF(create_import_kek_in, in, import_kek);
2688         MLX5_SET(import_kek, ptr, key_size, attr->key_size);
2689         key_addr = MLX5_ADDR_OF(import_kek, ptr, key);
2690         memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE);
2691         import_kek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2692                                                          out, sizeof(out));
2693         if (import_kek_obj->obj == NULL) {
2694                 rte_errno = errno;
2695                 DRV_LOG(ERR, "Failed to create IMPORT_KEK object using DevX.");
2696                 mlx5_free(import_kek_obj);
2697                 return NULL;
2698         }
2699         import_kek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2700         return import_kek_obj;
2701 }
2702
2703 /**
2704  * Create general object of type CREDENTIAL using DevX API.
2705  *
2706  * @param[in] ctx
2707  *   Context returned from mlx5 open_device() glue function.
2708  * @param [in] attr
2709  *   Pointer to CREDENTIAL attributes structure.
2710  *
2711  * @return
2712  *   The DevX object created, NULL otherwise and rte_errno is set.
2713  */
2714 struct mlx5_devx_obj *
2715 mlx5_devx_cmd_create_credential_obj(void *ctx,
2716                                     struct mlx5_devx_credential_attr *attr)
2717 {
2718         uint32_t in[MLX5_ST_SZ_DW(create_credential_in)] = {0};
2719         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2720         struct mlx5_devx_obj *credential_obj = NULL;
2721         void *ptr = NULL, *credential_addr = NULL;
2722
2723         credential_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*credential_obj),
2724                                      0, SOCKET_ID_ANY);
2725         if (credential_obj == NULL) {
2726                 DRV_LOG(ERR, "Failed to allocate CREDENTIAL object data");
2727                 rte_errno = ENOMEM;
2728                 return NULL;
2729         }
2730         ptr = MLX5_ADDR_OF(create_credential_in, in, hdr);
2731         MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2732                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2733         MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2734                  MLX5_GENERAL_OBJ_TYPE_CREDENTIAL);
2735         ptr = MLX5_ADDR_OF(create_credential_in, in, credential);
2736         MLX5_SET(credential, ptr, credential_role, attr->credential_role);
2737         credential_addr = MLX5_ADDR_OF(credential, ptr, credential);
2738         memcpy(credential_addr, (void *)(attr->credential),
2739                MLX5_CRYPTO_CREDENTIAL_SIZE);
2740         credential_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2741                                                          out, sizeof(out));
2742         if (credential_obj->obj == NULL) {
2743                 rte_errno = errno;
2744                 DRV_LOG(ERR, "Failed to create CREDENTIAL object using DevX.");
2745                 mlx5_free(credential_obj);
2746                 return NULL;
2747         }
2748         credential_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2749         return credential_obj;
2750 }
2751
2752 /**
2753  * Create general object of type CRYPTO_LOGIN using DevX API.
2754  *
2755  * @param[in] ctx
2756  *   Context returned from mlx5 open_device() glue function.
2757  * @param [in] attr
2758  *   Pointer to CRYPTO_LOGIN attributes structure.
2759  *
2760  * @return
2761  *   The DevX object created, NULL otherwise and rte_errno is set.
2762  */
2763 struct mlx5_devx_obj *
2764 mlx5_devx_cmd_create_crypto_login_obj(void *ctx,
2765                                       struct mlx5_devx_crypto_login_attr *attr)
2766 {
2767         uint32_t in[MLX5_ST_SZ_DW(create_crypto_login_in)] = {0};
2768         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2769         struct mlx5_devx_obj *crypto_login_obj = NULL;
2770         void *ptr = NULL, *credential_addr = NULL;
2771
2772         crypto_login_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*crypto_login_obj),
2773                                        0, SOCKET_ID_ANY);
2774         if (crypto_login_obj == NULL) {
2775                 DRV_LOG(ERR, "Failed to allocate CRYPTO_LOGIN object data");
2776                 rte_errno = ENOMEM;
2777                 return NULL;
2778         }
2779         ptr = MLX5_ADDR_OF(create_crypto_login_in, in, hdr);
2780         MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2781                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2782         MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2783                  MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN);
2784         ptr = MLX5_ADDR_OF(create_crypto_login_in, in, crypto_login);
2785         MLX5_SET(crypto_login, ptr, credential_pointer,
2786                  attr->credential_pointer);
2787         MLX5_SET(crypto_login, ptr, session_import_kek_ptr,
2788                  attr->session_import_kek_ptr);
2789         credential_addr = MLX5_ADDR_OF(crypto_login, ptr, credential);
2790         memcpy(credential_addr, (void *)(attr->credential),
2791                MLX5_CRYPTO_CREDENTIAL_SIZE);
2792         crypto_login_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2793                                                            out, sizeof(out));
2794         if (crypto_login_obj->obj == NULL) {
2795                 rte_errno = errno;
2796                 DRV_LOG(ERR, "Failed to create CRYPTO_LOGIN obj using DevX.");
2797                 mlx5_free(crypto_login_obj);
2798                 return NULL;
2799         }
2800         crypto_login_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2801         return crypto_login_obj;
2802 }