drivers/common/mlx5/mlx5_devx_cmds.c

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /* Copyright 2018 Mellanox Technologies, Ltd */
   3
   4 #include <unistd.h>
   5
   6 #include <rte_errno.h>
   7 #include <rte_malloc.h>
   8 #include <rte_eal_paging.h>
   9
  10 #include "mlx5_prm.h"
  11 #include "mlx5_devx_cmds.h"
  12 #include "mlx5_common_utils.h"
  13 #include "mlx5_malloc.h"
  14
  15
  16 /**
  17  * Perform read access to the registers. Reads data from register
  18  * and writes ones to the specified buffer.
  19  *
  20  * @param[in] ctx
  21  *   Context returned from mlx5 open_device() glue function.
  22  * @param[in] reg_id
  23  *   Register identifier according to the PRM.
  24  * @param[in] arg
  25  *   Register access auxiliary parameter according to the PRM.
  26  * @param[out] data
  27  *   Pointer to the buffer to store read data.
  28  * @param[in] dw_cnt
  29  *   Buffer size in double words.
  30  *
  31  * @return
  32  *   0 on success, a negative value otherwise.
  33  */
  34 int
  35 mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg,
  36                             uint32_t *data, uint32_t dw_cnt)
  37 {
  38         uint32_t in[MLX5_ST_SZ_DW(access_register_in)]   = {0};
  39         uint32_t out[MLX5_ST_SZ_DW(access_register_out) +
  40                      MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0};
  41         int status, rc;
  42
  43         MLX5_ASSERT(data && dw_cnt);
  44         MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX);
  45         if (dw_cnt  > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) {
  46                 DRV_LOG(ERR, "Not enough  buffer for register read data");
  47                 return -1;
  48         }
  49         MLX5_SET(access_register_in, in, opcode,
  50                  MLX5_CMD_OP_ACCESS_REGISTER_USER);
  51         MLX5_SET(access_register_in, in, op_mod,
  52                                         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ);
  53         MLX5_SET(access_register_in, in, register_id, reg_id);
  54         MLX5_SET(access_register_in, in, argument, arg);
  55         rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out,
  56                                          MLX5_ST_SZ_BYTES(access_register_out) +
  57                                          sizeof(uint32_t) * dw_cnt);
  58         if (rc)
  59                 goto error;
  60         status = MLX5_GET(access_register_out, out, status);
  61         if (status) {
  62                 int syndrome = MLX5_GET(access_register_out, out, syndrome);
  63
  64                 DRV_LOG(DEBUG, "Failed to access NIC register 0x%X, "
  65                                "status %x, syndrome = %x",
  66                                reg_id, status, syndrome);
  67                 return -1;
  68         }
  69         memcpy(data, &out[MLX5_ST_SZ_DW(access_register_out)],
  70                dw_cnt * sizeof(uint32_t));
  71         return 0;
  72 error:
  73         rc = (rc > 0) ? -rc : rc;
  74         return rc;
  75 }
  76
  77 /**
  78  * Allocate flow counters via devx interface.
  79  *
  80  * @param[in] ctx
  81  *   Context returned from mlx5 open_device() glue function.
  82  * @param dcs
  83  *   Pointer to counters properties structure to be filled by the routine.
  84  * @param bulk_n_128
  85  *   Bulk counter numbers in 128 counters units.
  86  *
  87  * @return
  88  *   Pointer to counter object on success, a negative value otherwise and
  89  *   rte_errno is set.
  90  */
  91 struct mlx5_devx_obj *
  92 mlx5_devx_cmd_flow_counter_alloc(void *ctx, uint32_t bulk_n_128)
  93 {
  94         struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs),
  95                                                 0, SOCKET_ID_ANY);
  96         uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)]   = {0};
  97         uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0};
  98
  99         if (!dcs) {
 100                 rte_errno = ENOMEM;
 101                 return NULL;
 102         }
 103         MLX5_SET(alloc_flow_counter_in, in, opcode,
 104                  MLX5_CMD_OP_ALLOC_FLOW_COUNTER);
 105         MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128);
 106         dcs->obj = mlx5_glue->devx_obj_create(ctx, in,
 107                                               sizeof(in), out, sizeof(out));
 108         if (!dcs->obj) {
 109                 DRV_LOG(ERR, "Can't allocate counters - error %d", errno);
 110                 rte_errno = errno;
 111                 mlx5_free(dcs);
 112                 return NULL;
 113         }
 114         dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id);
 115         return dcs;
 116 }
 117
 118 /**
 119  * Query flow counters values.
 120  *
 121  * @param[in] dcs
 122  *   devx object that was obtained from mlx5_devx_cmd_fc_alloc.
 123  * @param[in] clear
 124  *   Whether hardware should clear the counters after the query or not.
 125  * @param[in] n_counters
 126  *   0 in case of 1 counter to read, otherwise the counter number to read.
 127  *  @param pkts
 128  *   The number of packets that matched the flow.
 129  *  @param bytes
 130  *    The number of bytes that matched the flow.
 131  *  @param mkey
 132  *   The mkey key for batch query.
 133  *  @param addr
 134  *    The address in the mkey range for batch query.
 135  *  @param cmd_comp
 136  *   The completion object for asynchronous batch query.
 137  *  @param async_id
 138  *    The ID to be returned in the asynchronous batch query response.
 139  *
 140  * @return
 141  *   0 on success, a negative value otherwise.
 142  */
 143 int
 144 mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs,
 145                                  int clear, uint32_t n_counters,
 146                                  uint64_t *pkts, uint64_t *bytes,
 147                                  uint32_t mkey, void *addr,
 148                                  void *cmd_comp,
 149                                  uint64_t async_id)
 150 {
 151         int out_len = MLX5_ST_SZ_BYTES(query_flow_counter_out) +
 152                         MLX5_ST_SZ_BYTES(traffic_counter);
 153         uint32_t out[out_len];
 154         uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0};
 155         void *stats;
 156         int rc;
 157
 158         MLX5_SET(query_flow_counter_in, in, opcode,
 159                  MLX5_CMD_OP_QUERY_FLOW_COUNTER);
 160         MLX5_SET(query_flow_counter_in, in, op_mod, 0);
 161         MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id);
 162         MLX5_SET(query_flow_counter_in, in, clear, !!clear);
 163
 164         if (n_counters) {
 165                 MLX5_SET(query_flow_counter_in, in, num_of_counters,
 166                          n_counters);
 167                 MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1);
 168                 MLX5_SET(query_flow_counter_in, in, mkey, mkey);
 169                 MLX5_SET64(query_flow_counter_in, in, address,
 170                            (uint64_t)(uintptr_t)addr);
 171         }
 172         if (!cmd_comp)
 173                 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out,
 174                                                out_len);
 175         else
 176                 rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in),
 177                                                      out_len, async_id,
 178                                                      cmd_comp);
 179         if (rc) {
 180                 DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc);
 181                 rte_errno = rc;
 182                 return -rc;
 183         }
 184         if (!n_counters) {
 185                 stats = MLX5_ADDR_OF(query_flow_counter_out,
 186                                      out, flow_statistics);
 187                 *pkts = MLX5_GET64(traffic_counter, stats, packets);
 188                 *bytes = MLX5_GET64(traffic_counter, stats, octets);
 189         }
 190         return 0;
 191 }
 192
 193 /**
 194  * Create a new mkey.
 195  *
 196  * @param[in] ctx
 197  *   Context returned from mlx5 open_device() glue function.
 198  * @param[in] attr
 199  *   Attributes of the requested mkey.
 200  *
 201  * @return
 202  *   Pointer to Devx mkey on success, a negative value otherwise and rte_errno
 203  *   is set.
 204  */
 205 struct mlx5_devx_obj *
 206 mlx5_devx_cmd_mkey_create(void *ctx,
 207                           struct mlx5_devx_mkey_attr *attr)
 208 {
 209         struct mlx5_klm *klm_array = attr->klm_array;
 210         int klm_num = attr->klm_num;
 211         int in_size_dw = MLX5_ST_SZ_DW(create_mkey_in) +
 212                      (klm_num ? RTE_ALIGN(klm_num, 4) : 0) * MLX5_ST_SZ_DW(klm);
 213         uint32_t in[in_size_dw];
 214         uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0};
 215         void *mkc;
 216         struct mlx5_devx_obj *mkey = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mkey),
 217                                                  0, SOCKET_ID_ANY);
 218         size_t pgsize;
 219         uint32_t translation_size;
 220
 221         if (!mkey) {
 222                 rte_errno = ENOMEM;
 223                 return NULL;
 224         }
 225         memset(in, 0, in_size_dw * 4);
 226         pgsize = rte_mem_page_size();
 227         if (pgsize == (size_t)-1) {
 228                 mlx5_free(mkey);
 229                 DRV_LOG(ERR, "Failed to get page size");
 230                 rte_errno = ENOMEM;
 231                 return NULL;
 232         }
 233         MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY);
 234         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 235         if (klm_num > 0) {
 236                 int i;
 237                 uint8_t *klm = (uint8_t *)MLX5_ADDR_OF(create_mkey_in, in,
 238                                                        klm_pas_mtt);
 239                 translation_size = RTE_ALIGN(klm_num, 4);
 240                 for (i = 0; i < klm_num; i++) {
 241                         MLX5_SET(klm, klm, byte_count, klm_array[i].byte_count);
 242                         MLX5_SET(klm, klm, mkey, klm_array[i].mkey);
 243                         MLX5_SET64(klm, klm, address, klm_array[i].address);
 244                         klm += MLX5_ST_SZ_BYTES(klm);
 245                 }
 246                 for (; i < (int)translation_size; i++) {
 247                         MLX5_SET(klm, klm, mkey, 0x0);
 248                         MLX5_SET64(klm, klm, address, 0x0);
 249                         klm += MLX5_ST_SZ_BYTES(klm);
 250                 }
 251                 MLX5_SET(mkc, mkc, access_mode_1_0, attr->log_entity_size ?
 252                          MLX5_MKC_ACCESS_MODE_KLM_FBS :
 253                          MLX5_MKC_ACCESS_MODE_KLM);
 254                 MLX5_SET(mkc, mkc, log_page_size, attr->log_entity_size);
 255         } else {
 256                 translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16;
 257                 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
 258                 MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize));
 259         }
 260         MLX5_SET(create_mkey_in, in, translations_octword_actual_size,
 261                  translation_size);
 262         MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id);
 263         MLX5_SET(create_mkey_in, in, pg_access, attr->pg_access);
 264         MLX5_SET(mkc, mkc, lw, 0x1);
 265         MLX5_SET(mkc, mkc, lr, 0x1);
 266         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 267         MLX5_SET(mkc, mkc, pd, attr->pd);
 268         MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF);
 269         MLX5_SET(mkc, mkc, umr_en, attr->umr_en);
 270         MLX5_SET(mkc, mkc, translations_octword_size, translation_size);
 271         MLX5_SET(mkc, mkc, relaxed_ordering_write,
 272                  attr->relaxed_ordering_write);
 273         MLX5_SET(mkc, mkc, relaxed_ordering_read, attr->relaxed_ordering_read);
 274         MLX5_SET64(mkc, mkc, start_addr, attr->addr);
 275         MLX5_SET64(mkc, mkc, len, attr->size);
 276         mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out,
 277                                                sizeof(out));
 278         if (!mkey->obj) {
 279                 DRV_LOG(ERR, "Can't create %sdirect mkey - error %d",
 280                         klm_num ? "an in" : "a ", errno);
 281                 rte_errno = errno;
 282                 mlx5_free(mkey);
 283                 return NULL;
 284         }
 285         mkey->id = MLX5_GET(create_mkey_out, out, mkey_index);
 286         mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF);
 287         return mkey;
 288 }
 289
 290 /**
 291  * Get status of devx command response.
 292  * Mainly used for asynchronous commands.
 293  *
 294  * @param[in] out
 295  *   The out response buffer.
 296  *
 297  * @return
 298  *   0 on success, non-zero value otherwise.
 299  */
 300 int
 301 mlx5_devx_get_out_command_status(void *out)
 302 {
 303         int status;
 304
 305         if (!out)
 306                 return -EINVAL;
 307         status = MLX5_GET(query_flow_counter_out, out, status);
 308         if (status) {
 309                 int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome);
 310
 311                 DRV_LOG(ERR, "Bad DevX status %x, syndrome = %x", status,
 312                         syndrome);
 313         }
 314         return status;
 315 }
 316
 317 /**
 318  * Destroy any object allocated by a Devx API.
 319  *
 320  * @param[in] obj
 321  *   Pointer to a general object.
 322  *
 323  * @return
 324  *   0 on success, a negative value otherwise.
 325  */
 326 int
 327 mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj)
 328 {
 329         int ret;
 330
 331         if (!obj)
 332                 return 0;
 333         ret =  mlx5_glue->devx_obj_destroy(obj->obj);
 334         mlx5_free(obj);
 335         return ret;
 336 }
 337
 338 /**
 339  * Query NIC vport context.
 340  * Fills minimal inline attribute.
 341  *
 342  * @param[in] ctx
 343  *   ibv contexts returned from mlx5dv_open_device.
 344  * @param[in] vport
 345  *   vport index
 346  * @param[out] attr
 347  *   Attributes device values.
 348  *
 349  * @return
 350  *   0 on success, a negative value otherwise.
 351  */
 352 static int
 353 mlx5_devx_cmd_query_nic_vport_context(void *ctx,
 354                                       unsigned int vport,
 355                                       struct mlx5_hca_attr *attr)
 356 {
 357         uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0};
 358         uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0};
 359         void *vctx;
 360         int status, syndrome, rc;
 361
 362         /* Query NIC vport context to determine inline mode. */
 363         MLX5_SET(query_nic_vport_context_in, in, opcode,
 364                  MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT);
 365         MLX5_SET(query_nic_vport_context_in, in, vport_number, vport);
 366         if (vport)
 367                 MLX5_SET(query_nic_vport_context_in, in, other_vport, 1);
 368         rc = mlx5_glue->devx_general_cmd(ctx,
 369                                          in, sizeof(in),
 370                                          out, sizeof(out));
 371         if (rc)
 372                 goto error;
 373         status = MLX5_GET(query_nic_vport_context_out, out, status);
 374         syndrome = MLX5_GET(query_nic_vport_context_out, out, syndrome);
 375         if (status) {
 376                 DRV_LOG(DEBUG, "Failed to query NIC vport context, "
 377                         "status %x, syndrome = %x", status, syndrome);
 378                 return -1;
 379         }
 380         vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out,
 381                             nic_vport_context);
 382         attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx,
 383                                            min_wqe_inline_mode);
 384         return 0;
 385 error:
 386         rc = (rc > 0) ? -rc : rc;
 387         return rc;
 388 }
 389
 390 /**
 391  * Query NIC vDPA attributes.
 392  *
 393  * @param[in] ctx
 394  *   Context returned from mlx5 open_device() glue function.
 395  * @param[out] vdpa_attr
 396  *   vDPA Attributes structure to fill.
 397  */
 398 static void
 399 mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx,
 400                                   struct mlx5_hca_vdpa_attr *vdpa_attr)
 401 {
 402         uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0};
 403         uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0};
 404         void *hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 405         int status, syndrome, rc;
 406
 407         MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
 408         MLX5_SET(query_hca_cap_in, in, op_mod,
 409                  MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION |
 410                  MLX5_HCA_CAP_OPMOD_GET_CUR);
 411         rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
 412         status = MLX5_GET(query_hca_cap_out, out, status);
 413         syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
 414         if (rc || status) {
 415                 RTE_LOG(DEBUG, PMD, "Failed to query devx VDPA capabilities,"
 416                         " status %x, syndrome = %x", status, syndrome);
 417                 vdpa_attr->valid = 0;
 418         } else {
 419                 vdpa_attr->valid = 1;
 420                 vdpa_attr->desc_tunnel_offload_type =
 421                         MLX5_GET(virtio_emulation_cap, hcattr,
 422                                  desc_tunnel_offload_type);
 423                 vdpa_attr->eth_frame_offload_type =
 424                         MLX5_GET(virtio_emulation_cap, hcattr,
 425                                  eth_frame_offload_type);
 426                 vdpa_attr->virtio_version_1_0 =
 427                         MLX5_GET(virtio_emulation_cap, hcattr,
 428                                  virtio_version_1_0);
 429                 vdpa_attr->tso_ipv4 = MLX5_GET(virtio_emulation_cap, hcattr,
 430                                                tso_ipv4);
 431                 vdpa_attr->tso_ipv6 = MLX5_GET(virtio_emulation_cap, hcattr,
 432                                                tso_ipv6);
 433                 vdpa_attr->tx_csum = MLX5_GET(virtio_emulation_cap, hcattr,
 434                                               tx_csum);
 435                 vdpa_attr->rx_csum = MLX5_GET(virtio_emulation_cap, hcattr,
 436                                               rx_csum);
 437                 vdpa_attr->event_mode = MLX5_GET(virtio_emulation_cap, hcattr,
 438                                                  event_mode);
 439                 vdpa_attr->virtio_queue_type =
 440                         MLX5_GET(virtio_emulation_cap, hcattr,
 441                                  virtio_queue_type);
 442                 vdpa_attr->log_doorbell_stride =
 443                         MLX5_GET(virtio_emulation_cap, hcattr,
 444                                  log_doorbell_stride);
 445                 vdpa_attr->log_doorbell_bar_size =
 446                         MLX5_GET(virtio_emulation_cap, hcattr,
 447                                  log_doorbell_bar_size);
 448                 vdpa_attr->doorbell_bar_offset =
 449                         MLX5_GET64(virtio_emulation_cap, hcattr,
 450                                    doorbell_bar_offset);
 451                 vdpa_attr->max_num_virtio_queues =
 452                         MLX5_GET(virtio_emulation_cap, hcattr,
 453                                  max_num_virtio_queues);
 454                 vdpa_attr->umems[0].a = MLX5_GET(virtio_emulation_cap, hcattr,
 455                                                  umem_1_buffer_param_a);
 456                 vdpa_attr->umems[0].b = MLX5_GET(virtio_emulation_cap, hcattr,
 457                                                  umem_1_buffer_param_b);
 458                 vdpa_attr->umems[1].a = MLX5_GET(virtio_emulation_cap, hcattr,
 459                                                  umem_2_buffer_param_a);
 460                 vdpa_attr->umems[1].b = MLX5_GET(virtio_emulation_cap, hcattr,
 461                                                  umem_2_buffer_param_b);
 462                 vdpa_attr->umems[2].a = MLX5_GET(virtio_emulation_cap, hcattr,
 463                                                  umem_3_buffer_param_a);
 464                 vdpa_attr->umems[2].b = MLX5_GET(virtio_emulation_cap, hcattr,
 465                                                  umem_3_buffer_param_b);
 466         }
 467 }
 468
 469 int
 470 mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj,
 471                                   uint32_t ids[], uint32_t num)
 472 {
 473         uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
 474         uint32_t out[MLX5_ST_SZ_DW(create_flex_parser_out)] = {0};
 475         void *hdr = MLX5_ADDR_OF(create_flex_parser_out, in, hdr);
 476         void *flex = MLX5_ADDR_OF(create_flex_parser_out, out, flex);
 477         void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table);
 478         int ret;
 479         uint32_t idx = 0;
 480         uint32_t i;
 481
 482         if (num > MLX5_GRAPH_NODE_SAMPLE_NUM) {
 483                 rte_errno = EINVAL;
 484                 DRV_LOG(ERR, "Too many sample IDs to be fetched.");
 485                 return -rte_errno;
 486         }
 487         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
 488                  MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
 489         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
 490                  MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH);
 491         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, flex_obj->id);
 492         ret = mlx5_glue->devx_obj_query(flex_obj->obj, in, sizeof(in),
 493                                         out, sizeof(out));
 494         if (ret) {
 495                 rte_errno = ret;
 496                 DRV_LOG(ERR, "Failed to query sample IDs with object %p.",
 497                         (void *)flex_obj);
 498                 return -rte_errno;
 499         }
 500         for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) {
 501                 void *s_off = (void *)((char *)sample + i *
 502                               MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample));
 503                 uint32_t en;
 504
 505                 en = MLX5_GET(parse_graph_flow_match_sample, s_off,
 506                               flow_match_sample_en);
 507                 if (!en)
 508                         continue;
 509                 ids[idx++] = MLX5_GET(parse_graph_flow_match_sample, s_off,
 510                                   flow_match_sample_field_id);
 511         }
 512         if (num != idx) {
 513                 rte_errno = EINVAL;
 514                 DRV_LOG(ERR, "Number of sample IDs are not as expected.");
 515                 return -rte_errno;
 516         }
 517         return ret;
 518 }
 519
 520
 521 struct mlx5_devx_obj *
 522 mlx5_devx_cmd_create_flex_parser(void *ctx,
 523                               struct mlx5_devx_graph_node_attr *data)
 524 {
 525         uint32_t in[MLX5_ST_SZ_DW(create_flex_parser_in)] = {0};
 526         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
 527         void *hdr = MLX5_ADDR_OF(create_flex_parser_in, in, hdr);
 528         void *flex = MLX5_ADDR_OF(create_flex_parser_in, in, flex);
 529         void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table);
 530         void *in_arc = MLX5_ADDR_OF(parse_graph_flex, flex, input_arc);
 531         void *out_arc = MLX5_ADDR_OF(parse_graph_flex, flex, output_arc);
 532         struct mlx5_devx_obj *parse_flex_obj = mlx5_malloc
 533                      (MLX5_MEM_ZERO, sizeof(*parse_flex_obj), 0, SOCKET_ID_ANY);
 534         uint32_t i;
 535
 536         if (!parse_flex_obj) {
 537                 DRV_LOG(ERR, "Failed to allocate flex parser data.");
 538                 rte_errno = ENOMEM;
 539                 return NULL;
 540         }
 541         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
 542                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
 543         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
 544                  MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH);
 545         MLX5_SET(parse_graph_flex, flex, header_length_mode,
 546                  data->header_length_mode);
 547         MLX5_SET(parse_graph_flex, flex, header_length_base_value,
 548                  data->header_length_base_value);
 549         MLX5_SET(parse_graph_flex, flex, header_length_field_offset,
 550                  data->header_length_field_offset);
 551         MLX5_SET(parse_graph_flex, flex, header_length_field_shift,
 552                  data->header_length_field_shift);
 553         MLX5_SET(parse_graph_flex, flex, header_length_field_mask,
 554                  data->header_length_field_mask);
 555         for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) {
 556                 struct mlx5_devx_match_sample_attr *s = &data->sample[i];
 557                 void *s_off = (void *)((char *)sample + i *
 558                               MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample));
 559
 560                 if (!s->flow_match_sample_en)
 561                         continue;
 562                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 563                          flow_match_sample_en, !!s->flow_match_sample_en);
 564                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 565                          flow_match_sample_field_offset,
 566                          s->flow_match_sample_field_offset);
 567                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 568                          flow_match_sample_offset_mode,
 569                          s->flow_match_sample_offset_mode);
 570                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 571                          flow_match_sample_field_offset_mask,
 572                          s->flow_match_sample_field_offset_mask);
 573                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 574                          flow_match_sample_field_offset_shift,
 575                          s->flow_match_sample_field_offset_shift);
 576                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 577                          flow_match_sample_field_base_offset,
 578                          s->flow_match_sample_field_base_offset);
 579                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 580                          flow_match_sample_tunnel_mode,
 581                          s->flow_match_sample_tunnel_mode);
 582         }
 583         for (i = 0; i < MLX5_GRAPH_NODE_ARC_NUM; i++) {
 584                 struct mlx5_devx_graph_arc_attr *ia = &data->in[i];
 585                 struct mlx5_devx_graph_arc_attr *oa = &data->out[i];
 586                 void *in_off = (void *)((char *)in_arc + i *
 587                               MLX5_ST_SZ_BYTES(parse_graph_arc));
 588                 void *out_off = (void *)((char *)out_arc + i *
 589                               MLX5_ST_SZ_BYTES(parse_graph_arc));
 590
 591                 if (ia->arc_parse_graph_node != 0) {
 592                         MLX5_SET(parse_graph_arc, in_off,
 593                                  compare_condition_value,
 594                                  ia->compare_condition_value);
 595                         MLX5_SET(parse_graph_arc, in_off, start_inner_tunnel,
 596                                  ia->start_inner_tunnel);
 597                         MLX5_SET(parse_graph_arc, in_off, arc_parse_graph_node,
 598                                  ia->arc_parse_graph_node);
 599                         MLX5_SET(parse_graph_arc, in_off,
 600                                  parse_graph_node_handle,
 601                                  ia->parse_graph_node_handle);
 602                 }
 603                 if (oa->arc_parse_graph_node != 0) {
 604                         MLX5_SET(parse_graph_arc, out_off,
 605                                  compare_condition_value,
 606                                  oa->compare_condition_value);
 607                         MLX5_SET(parse_graph_arc, out_off, start_inner_tunnel,
 608                                  oa->start_inner_tunnel);
 609                         MLX5_SET(parse_graph_arc, out_off, arc_parse_graph_node,
 610                                  oa->arc_parse_graph_node);
 611                         MLX5_SET(parse_graph_arc, out_off,
 612                                  parse_graph_node_handle,
 613                                  oa->parse_graph_node_handle);
 614                 }
 615         }
 616         parse_flex_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
 617                                                          out, sizeof(out));
 618         if (!parse_flex_obj->obj) {
 619                 rte_errno = errno;
 620                 DRV_LOG(ERR, "Failed to create FLEX PARSE GRAPH object "
 621                         "by using DevX.");
 622                 mlx5_free(parse_flex_obj);
 623                 return NULL;
 624         }
 625         parse_flex_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
 626         return parse_flex_obj;
 627 }
 628
 629 /**
 630  * Query HCA attributes.
 631  * Using those attributes we can check on run time if the device
 632  * is having the required capabilities.
 633  *
 634  * @param[in] ctx
 635  *   Context returned from mlx5 open_device() glue function.
 636  * @param[out] attr
 637  *   Attributes device values.
 638  *
 639  * @return
 640  *   0 on success, a negative value otherwise.
 641  */
 642 int
 643 mlx5_devx_cmd_query_hca_attr(void *ctx,
 644                              struct mlx5_hca_attr *attr)
 645 {
 646         uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0};
 647         uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0};
 648         void *hcattr;
 649         int status, syndrome, rc, i;
 650         uint64_t general_obj_types_supported = 0;
 651
 652         MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
 653         MLX5_SET(query_hca_cap_in, in, op_mod,
 654                  MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE |
 655                  MLX5_HCA_CAP_OPMOD_GET_CUR);
 656
 657         rc = mlx5_glue->devx_general_cmd(ctx,
 658                                          in, sizeof(in), out, sizeof(out));
 659         if (rc)
 660                 goto error;
 661         status = MLX5_GET(query_hca_cap_out, out, status);
 662         syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
 663         if (status) {
 664                 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, "
 665                         "status %x, syndrome = %x", status, syndrome);
 666                 return -1;
 667         }
 668         hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 669         attr->flow_counter_bulk_alloc_bitmap =
 670                         MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc);
 671         attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr,
 672                                             flow_counters_dump);
 673         attr->log_max_rqt_size = MLX5_GET(cmd_hca_cap, hcattr,
 674                                           log_max_rqt_size);
 675         attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager);
 676         attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin);
 677         attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr,
 678                                                 log_max_hairpin_queues);
 679         attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr,
 680                                                     log_max_hairpin_wq_data_sz);
 681         attr->log_max_hairpin_num_packets = MLX5_GET
 682                 (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz);
 683         attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id);
 684         attr->relaxed_ordering_write = MLX5_GET(cmd_hca_cap, hcattr,
 685                                                 relaxed_ordering_write);
 686         attr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr,
 687                                                relaxed_ordering_read);
 688         attr->access_register_user = MLX5_GET(cmd_hca_cap, hcattr,
 689                                               access_register_user);
 690         attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr,
 691                                           eth_net_offloads);
 692         attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt);
 693         attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr,
 694                                                flex_parser_protocols);
 695         attr->max_geneve_tlv_options = MLX5_GET(cmd_hca_cap, hcattr,
 696                         max_geneve_tlv_options);
 697         attr->max_geneve_tlv_option_data_len = MLX5_GET(cmd_hca_cap, hcattr,
 698                         max_geneve_tlv_option_data_len);
 699         attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos);
 700         attr->qos.flow_meter_aso_sup = !!(MLX5_GET64(cmd_hca_cap, hcattr,
 701                                          general_obj_types) &
 702                               MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO);
 703         attr->vdpa.valid = !!(MLX5_GET64(cmd_hca_cap, hcattr,
 704                                          general_obj_types) &
 705                               MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q);
 706         attr->vdpa.queue_counters_valid = !!(MLX5_GET64(cmd_hca_cap, hcattr,
 707                                                         general_obj_types) &
 708                                   MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS);
 709         attr->parse_graph_flex_node = !!(MLX5_GET64(cmd_hca_cap, hcattr,
 710                                          general_obj_types) &
 711                               MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE);
 712         attr->wqe_index_ignore = MLX5_GET(cmd_hca_cap, hcattr,
 713                                           wqe_index_ignore_cap);
 714         attr->cross_channel = MLX5_GET(cmd_hca_cap, hcattr, cd);
 715         attr->non_wire_sq = MLX5_GET(cmd_hca_cap, hcattr, non_wire_sq);
 716         attr->log_max_static_sq_wq = MLX5_GET(cmd_hca_cap, hcattr,
 717                                               log_max_static_sq_wq);
 718         attr->num_lag_ports = MLX5_GET(cmd_hca_cap, hcattr, num_lag_ports);
 719         attr->dev_freq_khz = MLX5_GET(cmd_hca_cap, hcattr,
 720                                       device_frequency_khz);
 721         attr->scatter_fcs_w_decap_disable =
 722                 MLX5_GET(cmd_hca_cap, hcattr, scatter_fcs_w_decap_disable);
 723         attr->roce = MLX5_GET(cmd_hca_cap, hcattr, roce);
 724         attr->rq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, rq_ts_format);
 725         attr->sq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, sq_ts_format);
 726         attr->regex = MLX5_GET(cmd_hca_cap, hcattr, regexp);
 727         attr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr,
 728                                                regexp_num_of_engines);
 729         /* Read the general_obj_types bitmap and extract the relevant bits. */
 730         general_obj_types_supported = MLX5_GET64(cmd_hca_cap, hcattr,
 731                                                  general_obj_types);
 732         attr->vdpa.valid = !!(general_obj_types_supported &
 733                               MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q);
 734         attr->vdpa.queue_counters_valid =
 735                         !!(general_obj_types_supported &
 736                            MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS);
 737         attr->parse_graph_flex_node =
 738                         !!(general_obj_types_supported &
 739                            MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE);
 740         attr->flow_hit_aso = !!(general_obj_types_supported &
 741                                 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO);
 742         attr->geneve_tlv_opt = !!(general_obj_types_supported &
 743                                   MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT);
 744         /* Add reading of other GENERAL_OBJ_TYPES_CAP bits above this line. */
 745         attr->log_max_cq = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq);
 746         attr->log_max_qp = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp);
 747         attr->log_max_cq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq_sz);
 748         attr->log_max_qp_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp_sz);
 749         attr->log_max_mrw_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_mrw_sz);
 750         attr->log_max_pd = MLX5_GET(cmd_hca_cap, hcattr, log_max_pd);
 751         attr->log_max_srq = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq);
 752         attr->log_max_srq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq_sz);
 753         attr->reg_c_preserve =
 754                 MLX5_GET(cmd_hca_cap, hcattr, reg_c_preserve);
 755         attr->mmo_dma_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo);
 756         attr->mmo_compress_en = MLX5_GET(cmd_hca_cap, hcattr, compress);
 757         attr->mmo_decompress_en = MLX5_GET(cmd_hca_cap, hcattr, decompress);
 758         attr->compress_min_block_size = MLX5_GET(cmd_hca_cap, hcattr,
 759                                                  compress_min_block_size);
 760         attr->log_max_mmo_dma = MLX5_GET(cmd_hca_cap, hcattr, log_dma_mmo_size);
 761         attr->log_max_mmo_compress = MLX5_GET(cmd_hca_cap, hcattr,
 762                                               log_compress_mmo_size);
 763         attr->log_max_mmo_decompress = MLX5_GET(cmd_hca_cap, hcattr,
 764                                                 log_decompress_mmo_size);
 765         attr->cqe_compression = MLX5_GET(cmd_hca_cap, hcattr, cqe_compression);
 766         attr->mini_cqe_resp_flow_tag = MLX5_GET(cmd_hca_cap, hcattr,
 767                                                 mini_cqe_resp_flow_tag);
 768         attr->mini_cqe_resp_l3_l4_tag = MLX5_GET(cmd_hca_cap, hcattr,
 769                                                  mini_cqe_resp_l3_l4_tag);
 770         attr->umr_indirect_mkey_disabled =
 771                 MLX5_GET(cmd_hca_cap, hcattr, umr_indirect_mkey_disabled);
 772         attr->umr_modify_entity_size_disabled =
 773                 MLX5_GET(cmd_hca_cap, hcattr, umr_modify_entity_size_disabled);
 774         attr->crypto = MLX5_GET(cmd_hca_cap, hcattr, crypto);
 775         if (attr->crypto)
 776                 attr->aes_xts = MLX5_GET(cmd_hca_cap, hcattr, aes_xts);
 777         if (attr->qos.sup) {
 778                 MLX5_SET(query_hca_cap_in, in, op_mod,
 779                          MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP |
 780                          MLX5_HCA_CAP_OPMOD_GET_CUR);
 781                 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in),
 782                                                  out, sizeof(out));
 783                 if (rc)
 784                         goto error;
 785                 if (status) {
 786                         DRV_LOG(DEBUG, "Failed to query devx QOS capabilities,"
 787                                 " status %x, syndrome = %x", status, syndrome);
 788                         return -1;
 789                 }
 790                 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 791                 attr->qos.flow_meter_old =
 792                                 MLX5_GET(qos_cap, hcattr, flow_meter_old);
 793                 attr->qos.log_max_flow_meter =
 794                                 MLX5_GET(qos_cap, hcattr, log_max_flow_meter);
 795                 attr->qos.flow_meter_reg_c_ids =
 796                                 MLX5_GET(qos_cap, hcattr, flow_meter_reg_id);
 797                 attr->qos.flow_meter =
 798                                 MLX5_GET(qos_cap, hcattr, flow_meter);
 799                 attr->qos.packet_pacing =
 800                                 MLX5_GET(qos_cap, hcattr, packet_pacing);
 801                 attr->qos.wqe_rate_pp =
 802                                 MLX5_GET(qos_cap, hcattr, wqe_rate_pp);
 803                 if (attr->qos.flow_meter_aso_sup) {
 804                         attr->qos.log_meter_aso_granularity =
 805                                 MLX5_GET(qos_cap, hcattr,
 806                                         log_meter_aso_granularity);
 807                         attr->qos.log_meter_aso_max_alloc =
 808                                 MLX5_GET(qos_cap, hcattr,
 809                                         log_meter_aso_max_alloc);
 810                         attr->qos.log_max_num_meter_aso =
 811                                 MLX5_GET(qos_cap, hcattr,
 812                                         log_max_num_meter_aso);
 813                 }
 814         }
 815         if (attr->vdpa.valid)
 816                 mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa);
 817         if (!attr->eth_net_offloads)
 818                 return 0;
 819
 820         /* Query Flow Sampler Capability From FLow Table Properties Layout. */
 821         memset(in, 0, sizeof(in));
 822         memset(out, 0, sizeof(out));
 823         MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
 824         MLX5_SET(query_hca_cap_in, in, op_mod,
 825                  MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE |
 826                  MLX5_HCA_CAP_OPMOD_GET_CUR);
 827
 828         rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
 829         if (rc)
 830                 goto error;
 831         status = MLX5_GET(query_hca_cap_out, out, status);
 832         syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
 833         if (status) {
 834                 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, "
 835                         "status %x, syndrome = %x", status, syndrome);
 836                 attr->log_max_ft_sampler_num = 0;
 837                 return -1;
 838         }
 839         hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 840         attr->log_max_ft_sampler_num =
 841                         MLX5_GET(flow_table_nic_cap,
 842                         hcattr, flow_table_properties.log_max_ft_sampler_num);
 843
 844         /* Query HCA offloads for Ethernet protocol. */
 845         memset(in, 0, sizeof(in));
 846         memset(out, 0, sizeof(out));
 847         MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
 848         MLX5_SET(query_hca_cap_in, in, op_mod,
 849                  MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS |
 850                  MLX5_HCA_CAP_OPMOD_GET_CUR);
 851
 852         rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
 853         if (rc) {
 854                 attr->eth_net_offloads = 0;
 855                 goto error;
 856         }
 857         status = MLX5_GET(query_hca_cap_out, out, status);
 858         syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
 859         if (status) {
 860                 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, "
 861                         "status %x, syndrome = %x", status, syndrome);
 862                 attr->eth_net_offloads = 0;
 863                 return -1;
 864         }
 865         hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 866         attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps,
 867                                          hcattr, wqe_vlan_insert);
 868         attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr,
 869                                  lro_cap);
 870         attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps,
 871                                         hcattr, tunnel_lro_gre);
 872         attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps,
 873                                           hcattr, tunnel_lro_vxlan);
 874         attr->lro_max_msg_sz_mode = MLX5_GET
 875                                         (per_protocol_networking_offload_caps,
 876                                          hcattr, lro_max_msg_sz_mode);
 877         for (i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) {
 878                 attr->lro_timer_supported_periods[i] =
 879                         MLX5_GET(per_protocol_networking_offload_caps, hcattr,
 880                                  lro_timer_supported_periods[i]);
 881         }
 882         attr->lro_min_mss_size = MLX5_GET(per_protocol_networking_offload_caps,
 883                                           hcattr, lro_min_mss_size);
 884         attr->tunnel_stateless_geneve_rx =
 885                             MLX5_GET(per_protocol_networking_offload_caps,
 886                                      hcattr, tunnel_stateless_geneve_rx);
 887         attr->geneve_max_opt_len =
 888                     MLX5_GET(per_protocol_networking_offload_caps,
 889                              hcattr, max_geneve_opt_len);
 890         attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps,
 891                                          hcattr, wqe_inline_mode);
 892         attr->tunnel_stateless_gtp = MLX5_GET
 893                                         (per_protocol_networking_offload_caps,
 894                                          hcattr, tunnel_stateless_gtp);
 895         attr->rss_ind_tbl_cap = MLX5_GET
 896                                         (per_protocol_networking_offload_caps,
 897                                          hcattr, rss_ind_tbl_cap);
 898         /* Query HCA attribute for ROCE. */
 899         if (attr->roce) {
 900                 memset(in, 0, sizeof(in));
 901                 memset(out, 0, sizeof(out));
 902                 MLX5_SET(query_hca_cap_in, in, opcode,
 903                          MLX5_CMD_OP_QUERY_HCA_CAP);
 904                 MLX5_SET(query_hca_cap_in, in, op_mod,
 905                          MLX5_GET_HCA_CAP_OP_MOD_ROCE |
 906                          MLX5_HCA_CAP_OPMOD_GET_CUR);
 907                 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in),
 908                                                  out, sizeof(out));
 909                 if (rc)
 910                         goto error;
 911                 status = MLX5_GET(query_hca_cap_out, out, status);
 912                 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
 913                 if (status) {
 914                         DRV_LOG(DEBUG,
 915                                 "Failed to query devx HCA ROCE capabilities, "
 916                                 "status %x, syndrome = %x", status, syndrome);
 917                         return -1;
 918                 }
 919                 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 920                 attr->qp_ts_format = MLX5_GET(roce_caps, hcattr, qp_ts_format);
 921         }
 922         if (attr->eth_virt &&
 923             attr->wqe_inline_mode == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT) {
 924                 rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr);
 925                 if (rc) {
 926                         attr->eth_virt = 0;
 927                         goto error;
 928                 }
 929         }
 930         return 0;
 931 error:
 932         rc = (rc > 0) ? -rc : rc;
 933         return rc;
 934 }
 935
 936 /**
 937  * Query TIS transport domain from QP verbs object using DevX API.
 938  *
 939  * @param[in] qp
 940  *   Pointer to verbs QP returned by ibv_create_qp .
 941  * @param[in] tis_num
 942  *   TIS number of TIS to query.
 943  * @param[out] tis_td
 944  *   Pointer to TIS transport domain variable, to be set by the routine.
 945  *
 946  * @return
 947  *   0 on success, a negative value otherwise.
 948  */
 949 int
 950 mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num,
 951                               uint32_t *tis_td)
 952 {
 953 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 954         uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0};
 955         uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0};
 956         int rc;
 957         void *tis_ctx;
 958
 959         MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS);
 960         MLX5_SET(query_tis_in, in, tisn, tis_num);
 961         rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out));
 962         if (rc) {
 963                 DRV_LOG(ERR, "Failed to query QP using DevX");
 964                 return -rc;
 965         };
 966         tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context);
 967         *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain);
 968         return 0;
 969 #else
 970         (void)qp;
 971         (void)tis_num;
 972         (void)tis_td;
 973         return -ENOTSUP;
 974 #endif
 975 }
 976
 977 /**
 978  * Fill WQ data for DevX API command.
 979  * Utility function for use when creating DevX objects containing a WQ.
 980  *
 981  * @param[in] wq_ctx
 982  *   Pointer to WQ context to fill with data.
 983  * @param [in] wq_attr
 984  *   Pointer to WQ attributes structure to fill in WQ context.
 985  */
 986 static void
 987 devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr)
 988 {
 989         MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type);
 990         MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature);
 991         MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode);
 992         MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave);
 993         MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge);
 994         MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size);
 995         MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset);
 996         MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm);
 997         MLX5_SET(wq, wq_ctx, pd, wq_attr->pd);
 998         MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page);
 999         MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr);
1000         MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter);
1001         MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter);
1002         MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride);
1003         if (wq_attr->log_wq_pg_sz > MLX5_ADAPTER_PAGE_SHIFT)
1004                 MLX5_SET(wq, wq_ctx, log_wq_pg_sz,
1005                          wq_attr->log_wq_pg_sz - MLX5_ADAPTER_PAGE_SHIFT);
1006         MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz);
1007         MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid);
1008         MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid);
1009         MLX5_SET(wq, wq_ctx, log_hairpin_num_packets,
1010                  wq_attr->log_hairpin_num_packets);
1011         MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz);
1012         MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides,
1013                  wq_attr->single_wqe_log_num_of_strides);
1014         MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en);
1015         MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes,
1016                  wq_attr->single_stride_log_num_of_bytes);
1017         MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id);
1018         MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id);
1019         MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset);
1020 }
1021
1022 /**
1023  * Create RQ using DevX API.
1024  *
1025  * @param[in] ctx
1026  *   Context returned from mlx5 open_device() glue function.
1027  * @param [in] rq_attr
1028  *   Pointer to create RQ attributes structure.
1029  * @param [in] socket
1030  *   CPU socket ID for allocations.
1031  *
1032  * @return
1033  *   The DevX object created, NULL otherwise and rte_errno is set.
1034  */
1035 struct mlx5_devx_obj *
1036 mlx5_devx_cmd_create_rq(void *ctx,
1037                         struct mlx5_devx_create_rq_attr *rq_attr,
1038                         int socket)
1039 {
1040         uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0};
1041         uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0};
1042         void *rq_ctx, *wq_ctx;
1043         struct mlx5_devx_wq_attr *wq_attr;
1044         struct mlx5_devx_obj *rq = NULL;
1045
1046         rq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rq), 0, socket);
1047         if (!rq) {
1048                 DRV_LOG(ERR, "Failed to allocate RQ data");
1049                 rte_errno = ENOMEM;
1050                 return NULL;
1051         }
1052         MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ);
1053         rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx);
1054         MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky);
1055         MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en);
1056         MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);
1057         MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);
1058         MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type);
1059         MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
1060         MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en);
1061         MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin);
1062         MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index);
1063         MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn);
1064         MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
1065         MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn);
1066         MLX5_SET(sqc, rq_ctx, ts_format, rq_attr->ts_format);
1067         wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);
1068         wq_attr = &rq_attr->wq_attr;
1069         devx_cmd_fill_wq_data(wq_ctx, wq_attr);
1070         rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1071                                                   out, sizeof(out));
1072         if (!rq->obj) {
1073                 DRV_LOG(ERR, "Failed to create RQ using DevX");
1074                 rte_errno = errno;
1075                 mlx5_free(rq);
1076                 return NULL;
1077         }
1078         rq->id = MLX5_GET(create_rq_out, out, rqn);
1079         return rq;
1080 }
1081
1082 /**
1083  * Modify RQ using DevX API.
1084  *
1085  * @param[in] rq
1086  *   Pointer to RQ object structure.
1087  * @param [in] rq_attr
1088  *   Pointer to modify RQ attributes structure.
1089  *
1090  * @return
1091  *   0 on success, a negative errno value otherwise and rte_errno is set.
1092  */
1093 int
1094 mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,
1095                         struct mlx5_devx_modify_rq_attr *rq_attr)
1096 {
1097         uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0};
1098         uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0};
1099         void *rq_ctx, *wq_ctx;
1100         int ret;
1101
1102         MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ);
1103         MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state);
1104         MLX5_SET(modify_rq_in, in, rqn, rq->id);
1105         MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask);
1106         rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1107         MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
1108         if (rq_attr->modify_bitmask &
1109                         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS)
1110                 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);
1111         if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD)
1112                 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);
1113         if (rq_attr->modify_bitmask &
1114                         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID)
1115                 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
1116         MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq);
1117         MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca);
1118         if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) {
1119                 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);
1120                 MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm);
1121         }
1122         ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in),
1123                                          out, sizeof(out));
1124         if (ret) {
1125                 DRV_LOG(ERR, "Failed to modify RQ using DevX");
1126                 rte_errno = errno;
1127                 return -errno;
1128         }
1129         return ret;
1130 }
1131
1132 /**
1133  * Create TIR using DevX API.
1134  *
1135  * @param[in] ctx
1136  *  Context returned from mlx5 open_device() glue function.
1137  * @param [in] tir_attr
1138  *   Pointer to TIR attributes structure.
1139  *
1140  * @return
1141  *   The DevX object created, NULL otherwise and rte_errno is set.
1142  */
1143 struct mlx5_devx_obj *
1144 mlx5_devx_cmd_create_tir(void *ctx,
1145                          struct mlx5_devx_tir_attr *tir_attr)
1146 {
1147         uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
1148         uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0};
1149         void *tir_ctx, *outer, *inner, *rss_key;
1150         struct mlx5_devx_obj *tir = NULL;
1151
1152         tir = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tir), 0, SOCKET_ID_ANY);
1153         if (!tir) {
1154                 DRV_LOG(ERR, "Failed to allocate TIR data");
1155                 rte_errno = ENOMEM;
1156                 return NULL;
1157         }
1158         MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR);
1159         tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx);
1160         MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type);
1161         MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs,
1162                  tir_attr->lro_timeout_period_usecs);
1163         MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask);
1164         MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz);
1165         MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn);
1166         MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric);
1167         MLX5_SET(tirc, tir_ctx, tunneled_offload_en,
1168                  tir_attr->tunneled_offload_en);
1169         MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table);
1170         MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn);
1171         MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block);
1172         MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain);
1173         rss_key = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_toeplitz_key);
1174         memcpy(rss_key, tir_attr->rx_hash_toeplitz_key, MLX5_RSS_HASH_KEY_LEN);
1175         outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer);
1176         MLX5_SET(rx_hash_field_select, outer, l3_prot_type,
1177                  tir_attr->rx_hash_field_selector_outer.l3_prot_type);
1178         MLX5_SET(rx_hash_field_select, outer, l4_prot_type,
1179                  tir_attr->rx_hash_field_selector_outer.l4_prot_type);
1180         MLX5_SET(rx_hash_field_select, outer, selected_fields,
1181                  tir_attr->rx_hash_field_selector_outer.selected_fields);
1182         inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner);
1183         MLX5_SET(rx_hash_field_select, inner, l3_prot_type,
1184                  tir_attr->rx_hash_field_selector_inner.l3_prot_type);
1185         MLX5_SET(rx_hash_field_select, inner, l4_prot_type,
1186                  tir_attr->rx_hash_field_selector_inner.l4_prot_type);
1187         MLX5_SET(rx_hash_field_select, inner, selected_fields,
1188                  tir_attr->rx_hash_field_selector_inner.selected_fields);
1189         tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1190                                                    out, sizeof(out));
1191         if (!tir->obj) {
1192                 DRV_LOG(ERR, "Failed to create TIR using DevX");
1193                 rte_errno = errno;
1194                 mlx5_free(tir);
1195                 return NULL;
1196         }
1197         tir->id = MLX5_GET(create_tir_out, out, tirn);
1198         return tir;
1199 }
1200
1201 /**
1202  * Modify TIR using DevX API.
1203  *
1204  * @param[in] tir
1205  *   Pointer to TIR DevX object structure.
1206  * @param [in] modify_tir_attr
1207  *   Pointer to TIR modification attributes structure.
1208  *
1209  * @return
1210  *   0 on success, a negative errno value otherwise and rte_errno is set.
1211  */
1212 int
1213 mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir,
1214                          struct mlx5_devx_modify_tir_attr *modify_tir_attr)
1215 {
1216         struct mlx5_devx_tir_attr *tir_attr = &modify_tir_attr->tir;
1217         uint32_t in[MLX5_ST_SZ_DW(modify_tir_in)] = {0};
1218         uint32_t out[MLX5_ST_SZ_DW(modify_tir_out)] = {0};
1219         void *tir_ctx;
1220         int ret;
1221
1222         MLX5_SET(modify_tir_in, in, opcode, MLX5_CMD_OP_MODIFY_TIR);
1223         MLX5_SET(modify_tir_in, in, tirn, modify_tir_attr->tirn);
1224         MLX5_SET64(modify_tir_in, in, modify_bitmask,
1225                    modify_tir_attr->modify_bitmask);
1226         tir_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1227         if (modify_tir_attr->modify_bitmask &
1228                         MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO) {
1229                 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs,
1230                          tir_attr->lro_timeout_period_usecs);
1231                 MLX5_SET(tirc, tir_ctx, lro_enable_mask,
1232                          tir_attr->lro_enable_mask);
1233                 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz,
1234                          tir_attr->lro_max_msg_sz);
1235         }
1236         if (modify_tir_attr->modify_bitmask &
1237                         MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE)
1238                 MLX5_SET(tirc, tir_ctx, indirect_table,
1239                          tir_attr->indirect_table);
1240         if (modify_tir_attr->modify_bitmask &
1241                         MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH) {
1242                 int i;
1243                 void *outer, *inner;
1244
1245                 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric,
1246                          tir_attr->rx_hash_symmetric);
1247                 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn);
1248                 for (i = 0; i < 10; i++) {
1249                         MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i],
1250                                  tir_attr->rx_hash_toeplitz_key[i]);
1251                 }
1252                 outer = MLX5_ADDR_OF(tirc, tir_ctx,
1253                                      rx_hash_field_selector_outer);
1254                 MLX5_SET(rx_hash_field_select, outer, l3_prot_type,
1255                          tir_attr->rx_hash_field_selector_outer.l3_prot_type);
1256                 MLX5_SET(rx_hash_field_select, outer, l4_prot_type,
1257                          tir_attr->rx_hash_field_selector_outer.l4_prot_type);
1258                 MLX5_SET
1259                 (rx_hash_field_select, outer, selected_fields,
1260                  tir_attr->rx_hash_field_selector_outer.selected_fields);
1261                 inner = MLX5_ADDR_OF(tirc, tir_ctx,
1262                                      rx_hash_field_selector_inner);
1263                 MLX5_SET(rx_hash_field_select, inner, l3_prot_type,
1264                          tir_attr->rx_hash_field_selector_inner.l3_prot_type);
1265                 MLX5_SET(rx_hash_field_select, inner, l4_prot_type,
1266                          tir_attr->rx_hash_field_selector_inner.l4_prot_type);
1267                 MLX5_SET
1268                 (rx_hash_field_select, inner, selected_fields,
1269                  tir_attr->rx_hash_field_selector_inner.selected_fields);
1270         }
1271         if (modify_tir_attr->modify_bitmask &
1272             MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN) {
1273                 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block);
1274         }
1275         ret = mlx5_glue->devx_obj_modify(tir->obj, in, sizeof(in),
1276                                          out, sizeof(out));
1277         if (ret) {
1278                 DRV_LOG(ERR, "Failed to modify TIR using DevX");
1279                 rte_errno = errno;
1280                 return -errno;
1281         }
1282         return ret;
1283 }
1284
1285 /**
1286  * Create RQT using DevX API.
1287  *
1288  * @param[in] ctx
1289  *   Context returned from mlx5 open_device() glue function.
1290  * @param [in] rqt_attr
1291  *   Pointer to RQT attributes structure.
1292  *
1293  * @return
1294  *   The DevX object created, NULL otherwise and rte_errno is set.
1295  */
1296 struct mlx5_devx_obj *
1297 mlx5_devx_cmd_create_rqt(void *ctx,
1298                          struct mlx5_devx_rqt_attr *rqt_attr)
1299 {
1300         uint32_t *in = NULL;
1301         uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) +
1302                          rqt_attr->rqt_actual_size * sizeof(uint32_t);
1303         uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0};
1304         void *rqt_ctx;
1305         struct mlx5_devx_obj *rqt = NULL;
1306         int i;
1307
1308         in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY);
1309         if (!in) {
1310                 DRV_LOG(ERR, "Failed to allocate RQT IN data");
1311                 rte_errno = ENOMEM;
1312                 return NULL;
1313         }
1314         rqt = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt), 0, SOCKET_ID_ANY);
1315         if (!rqt) {
1316                 DRV_LOG(ERR, "Failed to allocate RQT data");
1317                 rte_errno = ENOMEM;
1318                 mlx5_free(in);
1319                 return NULL;
1320         }
1321         MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
1322         rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1323         MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type);
1324         MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size);
1325         MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size);
1326         for (i = 0; i < rqt_attr->rqt_actual_size; i++)
1327                 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]);
1328         rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out));
1329         mlx5_free(in);
1330         if (!rqt->obj) {
1331                 DRV_LOG(ERR, "Failed to create RQT using DevX");
1332                 rte_errno = errno;
1333                 mlx5_free(rqt);
1334                 return NULL;
1335         }
1336         rqt->id = MLX5_GET(create_rqt_out, out, rqtn);
1337         return rqt;
1338 }
1339
1340 /**
1341  * Modify RQT using DevX API.
1342  *
1343  * @param[in] rqt
1344  *   Pointer to RQT DevX object structure.
1345  * @param [in] rqt_attr
1346  *   Pointer to RQT attributes structure.
1347  *
1348  * @return
1349  *   0 on success, a negative errno value otherwise and rte_errno is set.
1350  */
1351 int
1352 mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt,
1353                          struct mlx5_devx_rqt_attr *rqt_attr)
1354 {
1355         uint32_t inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) +
1356                          rqt_attr->rqt_actual_size * sizeof(uint32_t);
1357         uint32_t out[MLX5_ST_SZ_DW(modify_rqt_out)] = {0};
1358         uint32_t *in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY);
1359         void *rqt_ctx;
1360         int i;
1361         int ret;
1362
1363         if (!in) {
1364                 DRV_LOG(ERR, "Failed to allocate RQT modify IN data.");
1365                 rte_errno = ENOMEM;
1366                 return -ENOMEM;
1367         }
1368         MLX5_SET(modify_rqt_in, in, opcode, MLX5_CMD_OP_MODIFY_RQT);
1369         MLX5_SET(modify_rqt_in, in, rqtn, rqt->id);
1370         MLX5_SET64(modify_rqt_in, in, modify_bitmask, 0x1);
1371         rqt_ctx = MLX5_ADDR_OF(modify_rqt_in, in, rqt_context);
1372         MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type);
1373         MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size);
1374         MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size);
1375         for (i = 0; i < rqt_attr->rqt_actual_size; i++)
1376                 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]);
1377         ret = mlx5_glue->devx_obj_modify(rqt->obj, in, inlen, out, sizeof(out));
1378         mlx5_free(in);
1379         if (ret) {
1380                 DRV_LOG(ERR, "Failed to modify RQT using DevX.");
1381                 rte_errno = errno;
1382                 return -rte_errno;
1383         }
1384         return ret;
1385 }
1386
1387 /**
1388  * Create SQ using DevX API.
1389  *
1390  * @param[in] ctx
1391  *   Context returned from mlx5 open_device() glue function.
1392  * @param [in] sq_attr
1393  *   Pointer to SQ attributes structure.
1394  * @param [in] socket
1395  *   CPU socket ID for allocations.
1396  *
1397  * @return
1398  *   The DevX object created, NULL otherwise and rte_errno is set.
1399  **/
1400 struct mlx5_devx_obj *
1401 mlx5_devx_cmd_create_sq(void *ctx,
1402                         struct mlx5_devx_create_sq_attr *sq_attr)
1403 {
1404         uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0};
1405         uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0};
1406         void *sq_ctx;
1407         void *wq_ctx;
1408         struct mlx5_devx_wq_attr *wq_attr;
1409         struct mlx5_devx_obj *sq = NULL;
1410
1411         sq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sq), 0, SOCKET_ID_ANY);
1412         if (!sq) {
1413                 DRV_LOG(ERR, "Failed to allocate SQ data");
1414                 rte_errno = ENOMEM;
1415                 return NULL;
1416         }
1417         MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ);
1418         sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx);
1419         MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky);
1420         MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master);
1421         MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre);
1422         MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en);
1423         MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe,
1424                  sq_attr->allow_multi_pkt_send_wqe);
1425         MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode,
1426                  sq_attr->min_wqe_inline_mode);
1427         MLX5_SET(sqc, sq_ctx, state, sq_attr->state);
1428         MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr);
1429         MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp);
1430         MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin);
1431         MLX5_SET(sqc, sq_ctx, non_wire, sq_attr->non_wire);
1432         MLX5_SET(sqc, sq_ctx, static_sq_wq, sq_attr->static_sq_wq);
1433         MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index);
1434         MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn);
1435         MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index,
1436                  sq_attr->packet_pacing_rate_limit_index);
1437         MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz);
1438         MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num);
1439         MLX5_SET(sqc, sq_ctx, ts_format, sq_attr->ts_format);
1440         wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq);
1441         wq_attr = &sq_attr->wq_attr;
1442         devx_cmd_fill_wq_data(wq_ctx, wq_attr);
1443         sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1444                                              out, sizeof(out));
1445         if (!sq->obj) {
1446                 DRV_LOG(ERR, "Failed to create SQ using DevX");
1447                 rte_errno = errno;
1448                 mlx5_free(sq);
1449                 return NULL;
1450         }
1451         sq->id = MLX5_GET(create_sq_out, out, sqn);
1452         return sq;
1453 }
1454
1455 /**
1456  * Modify SQ using DevX API.
1457  *
1458  * @param[in] sq
1459  *   Pointer to SQ object structure.
1460  * @param [in] sq_attr
1461  *   Pointer to SQ attributes structure.
1462  *
1463  * @return
1464  *   0 on success, a negative errno value otherwise and rte_errno is set.
1465  */
1466 int
1467 mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq,
1468                         struct mlx5_devx_modify_sq_attr *sq_attr)
1469 {
1470         uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0};
1471         uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0};
1472         void *sq_ctx;
1473         int ret;
1474
1475         MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ);
1476         MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state);
1477         MLX5_SET(modify_sq_in, in, sqn, sq->id);
1478         sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1479         MLX5_SET(sqc, sq_ctx, state, sq_attr->state);
1480         MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq);
1481         MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca);
1482         ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in),
1483                                          out, sizeof(out));
1484         if (ret) {
1485                 DRV_LOG(ERR, "Failed to modify SQ using DevX");
1486                 rte_errno = errno;
1487                 return -rte_errno;
1488         }
1489         return ret;
1490 }
1491
1492 /**
1493  * Create TIS using DevX API.
1494  *
1495  * @param[in] ctx
1496  *   Context returned from mlx5 open_device() glue function.
1497  * @param [in] tis_attr
1498  *   Pointer to TIS attributes structure.
1499  *
1500  * @return
1501  *   The DevX object created, NULL otherwise and rte_errno is set.
1502  */
1503 struct mlx5_devx_obj *
1504 mlx5_devx_cmd_create_tis(void *ctx,
1505                          struct mlx5_devx_tis_attr *tis_attr)
1506 {
1507         uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
1508         uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0};
1509         struct mlx5_devx_obj *tis = NULL;
1510         void *tis_ctx;
1511
1512         tis = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tis), 0, SOCKET_ID_ANY);
1513         if (!tis) {
1514                 DRV_LOG(ERR, "Failed to allocate TIS object");
1515                 rte_errno = ENOMEM;
1516                 return NULL;
1517         }
1518         MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS);
1519         tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx);
1520         MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity,
1521                  tis_attr->strict_lag_tx_port_affinity);
1522         MLX5_SET(tisc, tis_ctx, lag_tx_port_affinity,
1523                  tis_attr->lag_tx_port_affinity);
1524         MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio);
1525         MLX5_SET(tisc, tis_ctx, transport_domain,
1526                  tis_attr->transport_domain);
1527         tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1528                                               out, sizeof(out));
1529         if (!tis->obj) {
1530                 DRV_LOG(ERR, "Failed to create TIS using DevX");
1531                 rte_errno = errno;
1532                 mlx5_free(tis);
1533                 return NULL;
1534         }
1535         tis->id = MLX5_GET(create_tis_out, out, tisn);
1536         return tis;
1537 }
1538
1539 /**
1540  * Create transport domain using DevX API.
1541  *
1542  * @param[in] ctx
1543  *   Context returned from mlx5 open_device() glue function.
1544  * @return
1545  *   The DevX object created, NULL otherwise and rte_errno is set.
1546  */
1547 struct mlx5_devx_obj *
1548 mlx5_devx_cmd_create_td(void *ctx)
1549 {
1550         uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0};
1551         uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0};
1552         struct mlx5_devx_obj *td = NULL;
1553
1554         td = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*td), 0, SOCKET_ID_ANY);
1555         if (!td) {
1556                 DRV_LOG(ERR, "Failed to allocate TD object");
1557                 rte_errno = ENOMEM;
1558                 return NULL;
1559         }
1560         MLX5_SET(alloc_transport_domain_in, in, opcode,
1561                  MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN);
1562         td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1563                                              out, sizeof(out));
1564         if (!td->obj) {
1565                 DRV_LOG(ERR, "Failed to create TIS using DevX");
1566                 rte_errno = errno;
1567                 mlx5_free(td);
1568                 return NULL;
1569         }
1570         td->id = MLX5_GET(alloc_transport_domain_out, out,
1571                            transport_domain);
1572         return td;
1573 }
1574
1575 /**
1576  * Dump all flows to file.
1577  *
1578  * @param[in] fdb_domain
1579  *   FDB domain.
1580  * @param[in] rx_domain
1581  *   RX domain.
1582  * @param[in] tx_domain
1583  *   TX domain.
1584  * @param[out] file
1585  *   Pointer to file stream.
1586  *
1587  * @return
1588  *   0 on success, a nagative value otherwise.
1589  */
1590 int
1591 mlx5_devx_cmd_flow_dump(void *fdb_domain __rte_unused,
1592                         void *rx_domain __rte_unused,
1593                         void *tx_domain __rte_unused, FILE *file __rte_unused)
1594 {
1595         int ret = 0;
1596
1597 #ifdef HAVE_MLX5_DR_FLOW_DUMP
1598         if (fdb_domain) {
1599                 ret = mlx5_glue->dr_dump_domain(file, fdb_domain);
1600                 if (ret)
1601                         return ret;
1602         }
1603         MLX5_ASSERT(rx_domain);
1604         ret = mlx5_glue->dr_dump_domain(file, rx_domain);
1605         if (ret)
1606                 return ret;
1607         MLX5_ASSERT(tx_domain);
1608         ret = mlx5_glue->dr_dump_domain(file, tx_domain);
1609 #else
1610         ret = ENOTSUP;
1611 #endif
1612         return -ret;
1613 }
1614
1615 int
1616 mlx5_devx_cmd_flow_single_dump(void *rule_info __rte_unused,
1617                         FILE *file __rte_unused)
1618 {
1619         int ret = 0;
1620 #ifdef HAVE_MLX5_DR_FLOW_DUMP_RULE
1621         if (rule_info)
1622                 ret = mlx5_glue->dr_dump_rule(file, rule_info);
1623 #else
1624         ret = ENOTSUP;
1625 #endif
1626         return -ret;
1627 }
1628
1629 /*
1630  * Create CQ using DevX API.
1631  *
1632  * @param[in] ctx
1633  *   Context returned from mlx5 open_device() glue function.
1634  * @param [in] attr
1635  *   Pointer to CQ attributes structure.
1636  *
1637  * @return
1638  *   The DevX object created, NULL otherwise and rte_errno is set.
1639  */
1640 struct mlx5_devx_obj *
1641 mlx5_devx_cmd_create_cq(void *ctx, struct mlx5_devx_cq_attr *attr)
1642 {
1643         uint32_t in[MLX5_ST_SZ_DW(create_cq_in)] = {0};
1644         uint32_t out[MLX5_ST_SZ_DW(create_cq_out)] = {0};
1645         struct mlx5_devx_obj *cq_obj = mlx5_malloc(MLX5_MEM_ZERO,
1646                                                    sizeof(*cq_obj),
1647                                                    0, SOCKET_ID_ANY);
1648         void *cqctx = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1649
1650         if (!cq_obj) {
1651                 DRV_LOG(ERR, "Failed to allocate CQ object memory.");
1652                 rte_errno = ENOMEM;
1653                 return NULL;
1654         }
1655         MLX5_SET(create_cq_in, in, opcode, MLX5_CMD_OP_CREATE_CQ);
1656         if (attr->db_umem_valid) {
1657                 MLX5_SET(cqc, cqctx, dbr_umem_valid, attr->db_umem_valid);
1658                 MLX5_SET(cqc, cqctx, dbr_umem_id, attr->db_umem_id);
1659                 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_umem_offset);
1660         } else {
1661                 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_addr);
1662         }
1663         MLX5_SET(cqc, cqctx, cqe_sz, (RTE_CACHE_LINE_SIZE == 128) ?
1664                                      MLX5_CQE_SIZE_128B : MLX5_CQE_SIZE_64B);
1665         MLX5_SET(cqc, cqctx, cc, attr->use_first_only);
1666         MLX5_SET(cqc, cqctx, oi, attr->overrun_ignore);
1667         MLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size);
1668         if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT)
1669                 MLX5_SET(cqc, cqctx, log_page_size,
1670                          attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT);
1671         MLX5_SET(cqc, cqctx, c_eqn, attr->eqn);
1672         MLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id);
1673         MLX5_SET(cqc, cqctx, cqe_comp_en, !!attr->cqe_comp_en);
1674         MLX5_SET(cqc, cqctx, mini_cqe_res_format, attr->mini_cqe_res_format);
1675         MLX5_SET(cqc, cqctx, mini_cqe_res_format_ext,
1676                  attr->mini_cqe_res_format_ext);
1677         if (attr->q_umem_valid) {
1678                 MLX5_SET(create_cq_in, in, cq_umem_valid, attr->q_umem_valid);
1679                 MLX5_SET(create_cq_in, in, cq_umem_id, attr->q_umem_id);
1680                 MLX5_SET64(create_cq_in, in, cq_umem_offset,
1681                            attr->q_umem_offset);
1682         }
1683         cq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
1684                                                  sizeof(out));
1685         if (!cq_obj->obj) {
1686                 rte_errno = errno;
1687                 DRV_LOG(ERR, "Failed to create CQ using DevX errno=%d.", errno);
1688                 mlx5_free(cq_obj);
1689                 return NULL;
1690         }
1691         cq_obj->id = MLX5_GET(create_cq_out, out, cqn);
1692         return cq_obj;
1693 }
1694
1695 /**
1696  * Create VIRTQ using DevX API.
1697  *
1698  * @param[in] ctx
1699  *   Context returned from mlx5 open_device() glue function.
1700  * @param [in] attr
1701  *   Pointer to VIRTQ attributes structure.
1702  *
1703  * @return
1704  *   The DevX object created, NULL otherwise and rte_errno is set.
1705  */
1706 struct mlx5_devx_obj *
1707 mlx5_devx_cmd_create_virtq(void *ctx,
1708                            struct mlx5_devx_virtq_attr *attr)
1709 {
1710         uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0};
1711         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
1712         struct mlx5_devx_obj *virtq_obj = mlx5_malloc(MLX5_MEM_ZERO,
1713                                                      sizeof(*virtq_obj),
1714                                                      0, SOCKET_ID_ANY);
1715         void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq);
1716         void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr);
1717         void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context);
1718
1719         if (!virtq_obj) {
1720                 DRV_LOG(ERR, "Failed to allocate virtq data.");
1721                 rte_errno = ENOMEM;
1722                 return NULL;
1723         }
1724         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
1725                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
1726         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
1727                  MLX5_GENERAL_OBJ_TYPE_VIRTQ);
1728         MLX5_SET16(virtio_net_q, virtq, hw_available_index,
1729                    attr->hw_available_index);
1730         MLX5_SET16(virtio_net_q, virtq, hw_used_index, attr->hw_used_index);
1731         MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4);
1732         MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6);
1733         MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum);
1734         MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum);
1735         MLX5_SET16(virtio_q, virtctx, virtio_version_1_0,
1736                    attr->virtio_version_1_0);
1737         MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode);
1738         MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id);
1739         MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr);
1740         MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr);
1741         MLX5_SET64(virtio_q, virtctx, available_addr, attr->available_addr);
1742         MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index);
1743         MLX5_SET16(virtio_q, virtctx, queue_size, attr->q_size);
1744         MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey);
1745         MLX5_SET(virtio_q, virtctx, umem_1_id, attr->umems[0].id);
1746         MLX5_SET(virtio_q, virtctx, umem_1_size, attr->umems[0].size);
1747         MLX5_SET64(virtio_q, virtctx, umem_1_offset, attr->umems[0].offset);
1748         MLX5_SET(virtio_q, virtctx, umem_2_id, attr->umems[1].id);
1749         MLX5_SET(virtio_q, virtctx, umem_2_size, attr->umems[1].size);
1750         MLX5_SET64(virtio_q, virtctx, umem_2_offset, attr->umems[1].offset);
1751         MLX5_SET(virtio_q, virtctx, umem_3_id, attr->umems[2].id);
1752         MLX5_SET(virtio_q, virtctx, umem_3_size, attr->umems[2].size);
1753         MLX5_SET64(virtio_q, virtctx, umem_3_offset, attr->umems[2].offset);
1754         MLX5_SET(virtio_q, virtctx, counter_set_id, attr->counters_obj_id);
1755         MLX5_SET(virtio_q, virtctx, pd, attr->pd);
1756         MLX5_SET(virtio_q, virtctx, queue_period_mode, attr->hw_latency_mode);
1757         MLX5_SET(virtio_q, virtctx, queue_period_us, attr->hw_max_latency_us);
1758         MLX5_SET(virtio_q, virtctx, queue_max_count, attr->hw_max_pending_comp);
1759         MLX5_SET(virtio_net_q, virtq, tisn_or_qpn, attr->tis_id);
1760         virtq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
1761                                                     sizeof(out));
1762         if (!virtq_obj->obj) {
1763                 rte_errno = errno;
1764                 DRV_LOG(ERR, "Failed to create VIRTQ Obj using DevX.");
1765                 mlx5_free(virtq_obj);
1766                 return NULL;
1767         }
1768         virtq_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
1769         return virtq_obj;
1770 }
1771
1772 /**
1773  * Modify VIRTQ using DevX API.
1774  *
1775  * @param[in] virtq_obj
1776  *   Pointer to virtq object structure.
1777  * @param [in] attr
1778  *   Pointer to modify virtq attributes structure.
1779  *
1780  * @return
1781  *   0 on success, a negative errno value otherwise and rte_errno is set.
1782  */
1783 int
1784 mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj,
1785                            struct mlx5_devx_virtq_attr *attr)
1786 {
1787         uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0};
1788         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
1789         void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq);
1790         void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr);
1791         void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context);
1792         int ret;
1793
1794         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
1795                  MLX5_CMD_OP_MODIFY_GENERAL_OBJECT);
1796         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
1797                  MLX5_GENERAL_OBJ_TYPE_VIRTQ);
1798         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id);
1799         MLX5_SET64(virtio_net_q, virtq, modify_field_select, attr->type);
1800         MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index);
1801         switch (attr->type) {
1802         case MLX5_VIRTQ_MODIFY_TYPE_STATE:
1803                 MLX5_SET16(virtio_net_q, virtq, state, attr->state);
1804                 break;
1805         case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS:
1806                 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_mkey,
1807                          attr->dirty_bitmap_mkey);
1808                 MLX5_SET64(virtio_net_q, virtq, dirty_bitmap_addr,
1809                          attr->dirty_bitmap_addr);
1810                 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_size,
1811                          attr->dirty_bitmap_size);
1812                 break;
1813         case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE:
1814                 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_dump_enable,
1815                          attr->dirty_bitmap_dump_enable);
1816                 break;
1817         default:
1818                 rte_errno = EINVAL;
1819                 return -rte_errno;
1820         }
1821         ret = mlx5_glue->devx_obj_modify(virtq_obj->obj, in, sizeof(in),
1822                                          out, sizeof(out));
1823         if (ret) {
1824                 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX.");
1825                 rte_errno = errno;
1826                 return -rte_errno;
1827         }
1828         return ret;
1829 }
1830
1831 /**
1832  * Query VIRTQ using DevX API.
1833  *
1834  * @param[in] virtq_obj
1835  *   Pointer to virtq object structure.
1836  * @param [in/out] attr
1837  *   Pointer to virtq attributes structure.
1838  *
1839  * @return
1840  *   0 on success, a negative errno value otherwise and rte_errno is set.
1841  */
1842 int
1843 mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj,
1844                            struct mlx5_devx_virtq_attr *attr)
1845 {
1846         uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
1847         uint32_t out[MLX5_ST_SZ_DW(query_virtq_out)] = {0};
1848         void *hdr = MLX5_ADDR_OF(query_virtq_out, in, hdr);
1849         void *virtq = MLX5_ADDR_OF(query_virtq_out, out, virtq);
1850         int ret;
1851
1852         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
1853                  MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
1854         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
1855                  MLX5_GENERAL_OBJ_TYPE_VIRTQ);
1856         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id);
1857         ret = mlx5_glue->devx_obj_query(virtq_obj->obj, in, sizeof(in),
1858                                          out, sizeof(out));
1859         if (ret) {
1860                 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX.");
1861                 rte_errno = errno;
1862                 return -errno;
1863         }
1864         attr->hw_available_index = MLX5_GET16(virtio_net_q, virtq,
1865                                               hw_available_index);
1866         attr->hw_used_index = MLX5_GET16(virtio_net_q, virtq, hw_used_index);
1867         attr->state = MLX5_GET16(virtio_net_q, virtq, state);
1868         attr->error_type = MLX5_GET16(virtio_net_q, virtq,
1869                                       virtio_q_context.error_type);
1870         return ret;
1871 }
1872
1873 /**
1874  * Create QP using DevX API.
1875  *
1876  * @param[in] ctx
1877  *   Context returned from mlx5 open_device() glue function.
1878  * @param [in] attr
1879  *   Pointer to QP attributes structure.
1880  *
1881  * @return
1882  *   The DevX object created, NULL otherwise and rte_errno is set.
1883  */
1884 struct mlx5_devx_obj *
1885 mlx5_devx_cmd_create_qp(void *ctx,
1886                         struct mlx5_devx_qp_attr *attr)
1887 {
1888         uint32_t in[MLX5_ST_SZ_DW(create_qp_in)] = {0};
1889         uint32_t out[MLX5_ST_SZ_DW(create_qp_out)] = {0};
1890         struct mlx5_devx_obj *qp_obj = mlx5_malloc(MLX5_MEM_ZERO,
1891                                                    sizeof(*qp_obj),
1892                                                    0, SOCKET_ID_ANY);
1893         void *qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1894
1895         if (!qp_obj) {
1896                 DRV_LOG(ERR, "Failed to allocate QP data.");
1897                 rte_errno = ENOMEM;
1898                 return NULL;
1899         }
1900         MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP);
1901         MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC);
1902         MLX5_SET(qpc, qpc, pd, attr->pd);
1903         MLX5_SET(qpc, qpc, ts_format, attr->ts_format);
1904         if (attr->uar_index) {
1905                 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
1906                 MLX5_SET(qpc, qpc, uar_page, attr->uar_index);
1907                 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT)
1908                         MLX5_SET(qpc, qpc, log_page_size,
1909                                  attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT);
1910                 if (attr->sq_size) {
1911                         MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->sq_size));
1912                         MLX5_SET(qpc, qpc, cqn_snd, attr->cqn);
1913                         MLX5_SET(qpc, qpc, log_sq_size,
1914                                  rte_log2_u32(attr->sq_size));
1915                 } else {
1916                         MLX5_SET(qpc, qpc, no_sq, 1);
1917                 }
1918                 if (attr->rq_size) {
1919                         MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->rq_size));
1920                         MLX5_SET(qpc, qpc, cqn_rcv, attr->cqn);
1921                         MLX5_SET(qpc, qpc, log_rq_stride, attr->log_rq_stride -
1922                                  MLX5_LOG_RQ_STRIDE_SHIFT);
1923                         MLX5_SET(qpc, qpc, log_rq_size,
1924                                  rte_log2_u32(attr->rq_size));
1925                         MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ);
1926                 } else {
1927                         MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ);
1928                 }
1929                 if (attr->dbr_umem_valid) {
1930                         MLX5_SET(qpc, qpc, dbr_umem_valid,
1931                                  attr->dbr_umem_valid);
1932                         MLX5_SET(qpc, qpc, dbr_umem_id, attr->dbr_umem_id);
1933                 }
1934                 MLX5_SET64(qpc, qpc, dbr_addr, attr->dbr_address);
1935                 MLX5_SET64(create_qp_in, in, wq_umem_offset,
1936                            attr->wq_umem_offset);
1937                 MLX5_SET(create_qp_in, in, wq_umem_id, attr->wq_umem_id);
1938                 MLX5_SET(create_qp_in, in, wq_umem_valid, 1);
1939         } else {
1940                 /* Special QP to be managed by FW - no SQ\RQ\CQ\UAR\DB rec. */
1941                 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ);
1942                 MLX5_SET(qpc, qpc, no_sq, 1);
1943         }
1944         qp_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
1945                                                  sizeof(out));
1946         if (!qp_obj->obj) {
1947                 rte_errno = errno;
1948                 DRV_LOG(ERR, "Failed to create QP Obj using DevX.");
1949                 mlx5_free(qp_obj);
1950                 return NULL;
1951         }
1952         qp_obj->id = MLX5_GET(create_qp_out, out, qpn);
1953         return qp_obj;
1954 }
1955
1956 /**
1957  * Modify QP using DevX API.
1958  * Currently supports only force loop-back QP.
1959  *
1960  * @param[in] qp
1961  *   Pointer to QP object structure.
1962  * @param [in] qp_st_mod_op
1963  *   The QP state modification operation.
1964  * @param [in] remote_qp_id
1965  *   The remote QP ID for MLX5_CMD_OP_INIT2RTR_QP operation.
1966  *
1967  * @return
1968  *   0 on success, a negative errno value otherwise and rte_errno is set.
1969  */
1970 int
1971 mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op,
1972                               uint32_t remote_qp_id)
1973 {
1974         union {
1975                 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)];
1976                 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)];
1977                 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)];
1978         } in;
1979         union {
1980                 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)];
1981                 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)];
1982                 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)];
1983         } out;
1984         void *qpc;
1985         int ret;
1986         unsigned int inlen;
1987         unsigned int outlen;
1988
1989         memset(&in, 0, sizeof(in));
1990         memset(&out, 0, sizeof(out));
1991         MLX5_SET(rst2init_qp_in, &in, opcode, qp_st_mod_op);
1992         switch (qp_st_mod_op) {
1993         case MLX5_CMD_OP_RST2INIT_QP:
1994                 MLX5_SET(rst2init_qp_in, &in, qpn, qp->id);
1995                 qpc = MLX5_ADDR_OF(rst2init_qp_in, &in, qpc);
1996                 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1);
1997                 MLX5_SET(qpc, qpc, rre, 1);
1998                 MLX5_SET(qpc, qpc, rwe, 1);
1999                 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
2000                 inlen = sizeof(in.rst2init);
2001                 outlen = sizeof(out.rst2init);
2002                 break;
2003         case MLX5_CMD_OP_INIT2RTR_QP:
2004                 MLX5_SET(init2rtr_qp_in, &in, qpn, qp->id);
2005                 qpc = MLX5_ADDR_OF(init2rtr_qp_in, &in, qpc);
2006                 MLX5_SET(qpc, qpc, primary_address_path.fl, 1);
2007                 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1);
2008                 MLX5_SET(qpc, qpc, mtu, 1);
2009                 MLX5_SET(qpc, qpc, log_msg_max, 30);
2010                 MLX5_SET(qpc, qpc, remote_qpn, remote_qp_id);
2011                 MLX5_SET(qpc, qpc, min_rnr_nak, 0);
2012                 inlen = sizeof(in.init2rtr);
2013                 outlen = sizeof(out.init2rtr);
2014                 break;
2015         case MLX5_CMD_OP_RTR2RTS_QP:
2016                 qpc = MLX5_ADDR_OF(rtr2rts_qp_in, &in, qpc);
2017                 MLX5_SET(rtr2rts_qp_in, &in, qpn, qp->id);
2018                 MLX5_SET(qpc, qpc, primary_address_path.ack_timeout, 14);
2019                 MLX5_SET(qpc, qpc, log_ack_req_freq, 0);
2020                 MLX5_SET(qpc, qpc, retry_count, 7);
2021                 MLX5_SET(qpc, qpc, rnr_retry, 7);
2022                 inlen = sizeof(in.rtr2rts);
2023                 outlen = sizeof(out.rtr2rts);
2024                 break;
2025         default:
2026                 DRV_LOG(ERR, "Invalid or unsupported QP modify op %u.",
2027                         qp_st_mod_op);
2028                 rte_errno = EINVAL;
2029                 return -rte_errno;
2030         }
2031         ret = mlx5_glue->devx_obj_modify(qp->obj, &in, inlen, &out, outlen);
2032         if (ret) {
2033                 DRV_LOG(ERR, "Failed to modify QP using DevX.");
2034                 rte_errno = errno;
2035                 return -rte_errno;
2036         }
2037         return ret;
2038 }
2039
2040 struct mlx5_devx_obj *
2041 mlx5_devx_cmd_create_virtio_q_counters(void *ctx)
2042 {
2043         uint32_t in[MLX5_ST_SZ_DW(create_virtio_q_counters_in)] = {0};
2044         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2045         struct mlx5_devx_obj *couners_obj = mlx5_malloc(MLX5_MEM_ZERO,
2046                                                        sizeof(*couners_obj), 0,
2047                                                        SOCKET_ID_ANY);
2048         void *hdr = MLX5_ADDR_OF(create_virtio_q_counters_in, in, hdr);
2049
2050         if (!couners_obj) {
2051                 DRV_LOG(ERR, "Failed to allocate virtio queue counters data.");
2052                 rte_errno = ENOMEM;
2053                 return NULL;
2054         }
2055         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2056                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2057         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2058                  MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS);
2059         couners_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
2060                                                       sizeof(out));
2061         if (!couners_obj->obj) {
2062                 rte_errno = errno;
2063                 DRV_LOG(ERR, "Failed to create virtio queue counters Obj using"
2064                         " DevX.");
2065                 mlx5_free(couners_obj);
2066                 return NULL;
2067         }
2068         couners_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2069         return couners_obj;
2070 }
2071
2072 int
2073 mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj,
2074                                    struct mlx5_devx_virtio_q_couners_attr *attr)
2075 {
2076         uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
2077         uint32_t out[MLX5_ST_SZ_DW(query_virtio_q_counters_out)] = {0};
2078         void *hdr = MLX5_ADDR_OF(query_virtio_q_counters_out, in, hdr);
2079         void *virtio_q_counters = MLX5_ADDR_OF(query_virtio_q_counters_out, out,
2080                                                virtio_q_counters);
2081         int ret;
2082
2083         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2084                  MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
2085         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2086                  MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS);
2087         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, couners_obj->id);
2088         ret = mlx5_glue->devx_obj_query(couners_obj->obj, in, sizeof(in), out,
2089                                         sizeof(out));
2090         if (ret) {
2091                 DRV_LOG(ERR, "Failed to query virtio q counters using DevX.");
2092                 rte_errno = errno;
2093                 return -errno;
2094         }
2095         attr->received_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters,
2096                                          received_desc);
2097         attr->completed_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters,
2098                                           completed_desc);
2099         attr->error_cqes = MLX5_GET(virtio_q_counters, virtio_q_counters,
2100                                     error_cqes);
2101         attr->bad_desc_errors = MLX5_GET(virtio_q_counters, virtio_q_counters,
2102                                          bad_desc_errors);
2103         attr->exceed_max_chain = MLX5_GET(virtio_q_counters, virtio_q_counters,
2104                                           exceed_max_chain);
2105         attr->invalid_buffer = MLX5_GET(virtio_q_counters, virtio_q_counters,
2106                                         invalid_buffer);
2107         return ret;
2108 }
2109
2110 /**
2111  * Create general object of type FLOW_HIT_ASO using DevX API.
2112  *
2113  * @param[in] ctx
2114  *   Context returned from mlx5 open_device() glue function.
2115  * @param [in] pd
2116  *   PD value to associate the FLOW_HIT_ASO object with.
2117  *
2118  * @return
2119  *   The DevX object created, NULL otherwise and rte_errno is set.
2120  */
2121 struct mlx5_devx_obj *
2122 mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, uint32_t pd)
2123 {
2124         uint32_t in[MLX5_ST_SZ_DW(create_flow_hit_aso_in)] = {0};
2125         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2126         struct mlx5_devx_obj *flow_hit_aso_obj = NULL;
2127         void *ptr = NULL;
2128
2129         flow_hit_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*flow_hit_aso_obj),
2130                                        0, SOCKET_ID_ANY);
2131         if (!flow_hit_aso_obj) {
2132                 DRV_LOG(ERR, "Failed to allocate FLOW_HIT_ASO object data");
2133                 rte_errno = ENOMEM;
2134                 return NULL;
2135         }
2136         ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, hdr);
2137         MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2138                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2139         MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2140                  MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO);
2141         ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, flow_hit_aso);
2142         MLX5_SET(flow_hit_aso, ptr, access_pd, pd);
2143         flow_hit_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2144                                                            out, sizeof(out));
2145         if (!flow_hit_aso_obj->obj) {
2146                 rte_errno = errno;
2147                 DRV_LOG(ERR, "Failed to create FLOW_HIT_ASO obj using DevX.");
2148                 mlx5_free(flow_hit_aso_obj);
2149                 return NULL;
2150         }
2151         flow_hit_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2152         return flow_hit_aso_obj;
2153 }
2154
2155 /*
2156  * Create PD using DevX API.
2157  *
2158  * @param[in] ctx
2159  *   Context returned from mlx5 open_device() glue function.
2160  *
2161  * @return
2162  *   The DevX object created, NULL otherwise and rte_errno is set.
2163  */
2164 struct mlx5_devx_obj *
2165 mlx5_devx_cmd_alloc_pd(void *ctx)
2166 {
2167         struct mlx5_devx_obj *ppd =
2168                 mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ppd), 0, SOCKET_ID_ANY);
2169         u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {0};
2170         u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {0};
2171
2172         if (!ppd) {
2173                 DRV_LOG(ERR, "Failed to allocate PD data.");
2174                 rte_errno = ENOMEM;
2175                 return NULL;
2176         }
2177         MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD);
2178         ppd->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2179                                 out, sizeof(out));
2180         if (!ppd->obj) {
2181                 mlx5_free(ppd);
2182                 DRV_LOG(ERR, "Failed to allocate PD Obj using DevX.");
2183                 rte_errno = errno;
2184                 return NULL;
2185         }
2186         ppd->id = MLX5_GET(alloc_pd_out, out, pd);
2187         return ppd;
2188 }
2189
2190 /**
2191  * Create general object of type FLOW_METER_ASO using DevX API.
2192  *
2193  * @param[in] ctx
2194  *   Context returned from mlx5 open_device() glue function.
2195  * @param [in] pd
2196  *   PD value to associate the FLOW_METER_ASO object with.
2197  * @param [in] log_obj_size
2198  *   log_obj_size define to allocate number of 2 * meters
2199  *   in one FLOW_METER_ASO object.
2200  *
2201  * @return
2202  *   The DevX object created, NULL otherwise and rte_errno is set.
2203  */
2204 struct mlx5_devx_obj *
2205 mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx, uint32_t pd,
2206                                                 uint32_t log_obj_size)
2207 {
2208         uint32_t in[MLX5_ST_SZ_DW(create_flow_meter_aso_in)] = {0};
2209         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)];
2210         struct mlx5_devx_obj *flow_meter_aso_obj;
2211         void *ptr;
2212
2213         flow_meter_aso_obj = mlx5_malloc(MLX5_MEM_ZERO,
2214                                                 sizeof(*flow_meter_aso_obj),
2215                                                 0, SOCKET_ID_ANY);
2216         if (!flow_meter_aso_obj) {
2217                 DRV_LOG(ERR, "Failed to allocate FLOW_METER_ASO object data");
2218                 rte_errno = ENOMEM;
2219                 return NULL;
2220         }
2221         ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, hdr);
2222         MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2223                 MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2224         MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2225                 MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO);
2226         MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range,
2227                 log_obj_size);
2228         ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, flow_meter_aso);
2229         MLX5_SET(flow_meter_aso, ptr, access_pd, pd);
2230         flow_meter_aso_obj->obj = mlx5_glue->devx_obj_create(
2231                                                         ctx, in, sizeof(in),
2232                                                         out, sizeof(out));
2233         if (!flow_meter_aso_obj->obj) {
2234                 rte_errno = errno;
2235                 DRV_LOG(ERR, "Failed to create FLOW_METER_ASO obj using DevX.");
2236                 mlx5_free(flow_meter_aso_obj);
2237                 return NULL;
2238         }
2239         flow_meter_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr,
2240                                                                 out, obj_id);
2241         return flow_meter_aso_obj;
2242 }
2243
2244 /**
2245  * Create general object of type GENEVE TLV option using DevX API.
2246  *
2247  * @param[in] ctx
2248  *   Context returned from mlx5 open_device() glue function.
2249  * @param [in] class
2250  *   TLV option variable value of class
2251  * @param [in] type
2252  *   TLV option variable value of type
2253  * @param [in] len
2254  *   TLV option variable value of len
2255  *
2256  * @return
2257  *   The DevX object created, NULL otherwise and rte_errno is set.
2258  */
2259 struct mlx5_devx_obj *
2260 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx,
2261                 uint16_t class, uint8_t type, uint8_t len)
2262 {
2263         uint32_t in[MLX5_ST_SZ_DW(create_geneve_tlv_option_in)] = {0};
2264         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2265         struct mlx5_devx_obj *geneve_tlv_opt_obj = mlx5_malloc(MLX5_MEM_ZERO,
2266                                                    sizeof(*geneve_tlv_opt_obj),
2267                                                    0, SOCKET_ID_ANY);
2268
2269         if (!geneve_tlv_opt_obj) {
2270                 DRV_LOG(ERR, "Failed to allocate geneve tlv option object.");
2271                 rte_errno = ENOMEM;
2272                 return NULL;
2273         }
2274         void *hdr = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, hdr);
2275         void *opt = MLX5_ADDR_OF(create_geneve_tlv_option_in, in,
2276                         geneve_tlv_opt);
2277         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2278                         MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2279         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2280                  MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT);
2281         MLX5_SET(geneve_tlv_option, opt, option_class,
2282                         rte_be_to_cpu_16(class));
2283         MLX5_SET(geneve_tlv_option, opt, option_type, type);
2284         MLX5_SET(geneve_tlv_option, opt, option_data_length, len);
2285         geneve_tlv_opt_obj->obj = mlx5_glue->devx_obj_create(ctx, in,
2286                                         sizeof(in), out, sizeof(out));
2287         if (!geneve_tlv_opt_obj->obj) {
2288                 rte_errno = errno;
2289                 DRV_LOG(ERR, "Failed to create Geneve tlv option "
2290                                 "Obj using DevX.");
2291                 mlx5_free(geneve_tlv_opt_obj);
2292                 return NULL;
2293         }
2294         geneve_tlv_opt_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2295         return geneve_tlv_opt_obj;
2296 }
2297
2298 int
2299 mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id)
2300 {
2301 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2302         uint32_t in[MLX5_ST_SZ_DW(query_rq_in)] = {0};
2303         uint32_t out[MLX5_ST_SZ_DW(query_rq_out)] = {0};
2304         int rc;
2305         void *rq_ctx;
2306
2307         MLX5_SET(query_rq_in, in, opcode, MLX5_CMD_OP_QUERY_RQ);
2308         MLX5_SET(query_rq_in, in, rqn, ((struct ibv_wq *)wq)->wq_num);
2309         rc = mlx5_glue->devx_wq_query(wq, in, sizeof(in), out, sizeof(out));
2310         if (rc) {
2311                 rte_errno = errno;
2312                 DRV_LOG(ERR, "Failed to query WQ counter set ID using DevX - "
2313                         "rc = %d, errno = %d.", rc, errno);
2314                 return -rc;
2315         };
2316         rq_ctx = MLX5_ADDR_OF(query_rq_out, out, rq_context);
2317         *counter_set_id = MLX5_GET(rqc, rq_ctx, counter_set_id);
2318         return 0;
2319 #else
2320         (void)wq;
2321         (void)counter_set_id;
2322         return -ENOTSUP;
2323 #endif
2324 }
2325
2326 /*
2327  * Allocate queue counters via devx interface.
2328  *
2329  * @param[in] ctx
2330  *   Context returned from mlx5 open_device() glue function.
2331  *
2332  * @return
2333  *   Pointer to counter object on success, a NULL value otherwise and
2334  *   rte_errno is set.
2335  */
2336 struct mlx5_devx_obj *
2337 mlx5_devx_cmd_queue_counter_alloc(void *ctx)
2338 {
2339         struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 0,
2340                                                 SOCKET_ID_ANY);
2341         uint32_t in[MLX5_ST_SZ_DW(alloc_q_counter_in)]   = {0};
2342         uint32_t out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {0};
2343
2344         if (!dcs) {
2345                 rte_errno = ENOMEM;
2346                 return NULL;
2347         }
2348         MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER);
2349         dcs->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
2350                                               sizeof(out));
2351         if (!dcs->obj) {
2352                 DRV_LOG(DEBUG, "Can't allocate q counter set by DevX - error "
2353                         "%d.", errno);
2354                 rte_errno = errno;
2355                 mlx5_free(dcs);
2356                 return NULL;
2357         }
2358         dcs->id = MLX5_GET(alloc_q_counter_out, out, counter_set_id);
2359         return dcs;
2360 }
2361
2362 /**
2363  * Query queue counters values.
2364  *
2365  * @param[in] dcs
2366  *   devx object of the queue counter set.
2367  * @param[in] clear
2368  *   Whether hardware should clear the counters after the query or not.
2369  *  @param[out] out_of_buffers
2370  *   Number of dropped occurred due to lack of WQE for the associated QPs/RQs.
2371  *
2372  * @return
2373  *   0 on success, a negative value otherwise.
2374  */
2375 int
2376 mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear,
2377                                   uint32_t *out_of_buffers)
2378 {
2379         uint32_t out[MLX5_ST_SZ_BYTES(query_q_counter_out)] = {0};
2380         uint32_t in[MLX5_ST_SZ_DW(query_q_counter_in)] = {0};
2381         int rc;
2382
2383         MLX5_SET(query_q_counter_in, in, opcode,
2384                  MLX5_CMD_OP_QUERY_Q_COUNTER);
2385         MLX5_SET(query_q_counter_in, in, op_mod, 0);
2386         MLX5_SET(query_q_counter_in, in, counter_set_id, dcs->id);
2387         MLX5_SET(query_q_counter_in, in, clear, !!clear);
2388         rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out,
2389                                        sizeof(out));
2390         if (rc) {
2391                 DRV_LOG(ERR, "Failed to query devx q counter set - rc %d", rc);
2392                 rte_errno = rc;
2393                 return -rc;
2394         }
2395         *out_of_buffers = MLX5_GET(query_q_counter_out, out, out_of_buffer);
2396         return 0;
2397 }