drivers/common/mlx5/mlx5_devx_cmds.c

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /* Copyright 2018 Mellanox Technologies, Ltd */
   3
   4 #include <unistd.h>
   5
   6 #include <rte_errno.h>
   7 #include <rte_malloc.h>
   8 #include <rte_eal_paging.h>
   9
  10 #include "mlx5_prm.h"
  11 #include "mlx5_devx_cmds.h"
  12 #include "mlx5_common_log.h"
  13 #include "mlx5_malloc.h"
  14
  15
  16 /**
  17  * Perform read access to the registers. Reads data from register
  18  * and writes ones to the specified buffer.
  19  *
  20  * @param[in] ctx
  21  *   Context returned from mlx5 open_device() glue function.
  22  * @param[in] reg_id
  23  *   Register identifier according to the PRM.
  24  * @param[in] arg
  25  *   Register access auxiliary parameter according to the PRM.
  26  * @param[out] data
  27  *   Pointer to the buffer to store read data.
  28  * @param[in] dw_cnt
  29  *   Buffer size in double words.
  30  *
  31  * @return
  32  *   0 on success, a negative value otherwise.
  33  */
  34 int
  35 mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg,
  36                             uint32_t *data, uint32_t dw_cnt)
  37 {
  38         uint32_t in[MLX5_ST_SZ_DW(access_register_in)]   = {0};
  39         uint32_t out[MLX5_ST_SZ_DW(access_register_out) +
  40                      MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0};
  41         int status, rc;
  42
  43         MLX5_ASSERT(data && dw_cnt);
  44         MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX);
  45         if (dw_cnt  > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) {
  46                 DRV_LOG(ERR, "Not enough  buffer for register read data");
  47                 return -1;
  48         }
  49         MLX5_SET(access_register_in, in, opcode,
  50                  MLX5_CMD_OP_ACCESS_REGISTER_USER);
  51         MLX5_SET(access_register_in, in, op_mod,
  52                                         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ);
  53         MLX5_SET(access_register_in, in, register_id, reg_id);
  54         MLX5_SET(access_register_in, in, argument, arg);
  55         rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out,
  56                                          MLX5_ST_SZ_BYTES(access_register_out) +
  57                                          sizeof(uint32_t) * dw_cnt);
  58         if (rc)
  59                 goto error;
  60         status = MLX5_GET(access_register_out, out, status);
  61         if (status) {
  62                 int syndrome = MLX5_GET(access_register_out, out, syndrome);
  63
  64                 DRV_LOG(DEBUG, "Failed to access NIC register 0x%X, "
  65                                "status %x, syndrome = %x",
  66                                reg_id, status, syndrome);
  67                 return -1;
  68         }
  69         memcpy(data, &out[MLX5_ST_SZ_DW(access_register_out)],
  70                dw_cnt * sizeof(uint32_t));
  71         return 0;
  72 error:
  73         rc = (rc > 0) ? -rc : rc;
  74         return rc;
  75 }
  76
  77 /**
  78  * Allocate flow counters via devx interface.
  79  *
  80  * @param[in] ctx
  81  *   Context returned from mlx5 open_device() glue function.
  82  * @param dcs
  83  *   Pointer to counters properties structure to be filled by the routine.
  84  * @param bulk_n_128
  85  *   Bulk counter numbers in 128 counters units.
  86  *
  87  * @return
  88  *   Pointer to counter object on success, a negative value otherwise and
  89  *   rte_errno is set.
  90  */
  91 struct mlx5_devx_obj *
  92 mlx5_devx_cmd_flow_counter_alloc(void *ctx, uint32_t bulk_n_128)
  93 {
  94         struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs),
  95                                                 0, SOCKET_ID_ANY);
  96         uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)]   = {0};
  97         uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0};
  98
  99         if (!dcs) {
 100                 rte_errno = ENOMEM;
 101                 return NULL;
 102         }
 103         MLX5_SET(alloc_flow_counter_in, in, opcode,
 104                  MLX5_CMD_OP_ALLOC_FLOW_COUNTER);
 105         MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128);
 106         dcs->obj = mlx5_glue->devx_obj_create(ctx, in,
 107                                               sizeof(in), out, sizeof(out));
 108         if (!dcs->obj) {
 109                 DRV_LOG(ERR, "Can't allocate counters - error %d", errno);
 110                 rte_errno = errno;
 111                 mlx5_free(dcs);
 112                 return NULL;
 113         }
 114         dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id);
 115         return dcs;
 116 }
 117
 118 /**
 119  * Query flow counters values.
 120  *
 121  * @param[in] dcs
 122  *   devx object that was obtained from mlx5_devx_cmd_fc_alloc.
 123  * @param[in] clear
 124  *   Whether hardware should clear the counters after the query or not.
 125  * @param[in] n_counters
 126  *   0 in case of 1 counter to read, otherwise the counter number to read.
 127  *  @param pkts
 128  *   The number of packets that matched the flow.
 129  *  @param bytes
 130  *    The number of bytes that matched the flow.
 131  *  @param mkey
 132  *   The mkey key for batch query.
 133  *  @param addr
 134  *    The address in the mkey range for batch query.
 135  *  @param cmd_comp
 136  *   The completion object for asynchronous batch query.
 137  *  @param async_id
 138  *    The ID to be returned in the asynchronous batch query response.
 139  *
 140  * @return
 141  *   0 on success, a negative value otherwise.
 142  */
 143 int
 144 mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs,
 145                                  int clear, uint32_t n_counters,
 146                                  uint64_t *pkts, uint64_t *bytes,
 147                                  uint32_t mkey, void *addr,
 148                                  void *cmd_comp,
 149                                  uint64_t async_id)
 150 {
 151         int out_len = MLX5_ST_SZ_BYTES(query_flow_counter_out) +
 152                         MLX5_ST_SZ_BYTES(traffic_counter);
 153         uint32_t out[out_len];
 154         uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0};
 155         void *stats;
 156         int rc;
 157
 158         MLX5_SET(query_flow_counter_in, in, opcode,
 159                  MLX5_CMD_OP_QUERY_FLOW_COUNTER);
 160         MLX5_SET(query_flow_counter_in, in, op_mod, 0);
 161         MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id);
 162         MLX5_SET(query_flow_counter_in, in, clear, !!clear);
 163
 164         if (n_counters) {
 165                 MLX5_SET(query_flow_counter_in, in, num_of_counters,
 166                          n_counters);
 167                 MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1);
 168                 MLX5_SET(query_flow_counter_in, in, mkey, mkey);
 169                 MLX5_SET64(query_flow_counter_in, in, address,
 170                            (uint64_t)(uintptr_t)addr);
 171         }
 172         if (!cmd_comp)
 173                 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out,
 174                                                out_len);
 175         else
 176                 rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in),
 177                                                      out_len, async_id,
 178                                                      cmd_comp);
 179         if (rc) {
 180                 DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc);
 181                 rte_errno = rc;
 182                 return -rc;
 183         }
 184         if (!n_counters) {
 185                 stats = MLX5_ADDR_OF(query_flow_counter_out,
 186                                      out, flow_statistics);
 187                 *pkts = MLX5_GET64(traffic_counter, stats, packets);
 188                 *bytes = MLX5_GET64(traffic_counter, stats, octets);
 189         }
 190         return 0;
 191 }
 192
 193 /**
 194  * Create a new mkey.
 195  *
 196  * @param[in] ctx
 197  *   Context returned from mlx5 open_device() glue function.
 198  * @param[in] attr
 199  *   Attributes of the requested mkey.
 200  *
 201  * @return
 202  *   Pointer to Devx mkey on success, a negative value otherwise and rte_errno
 203  *   is set.
 204  */
 205 struct mlx5_devx_obj *
 206 mlx5_devx_cmd_mkey_create(void *ctx,
 207                           struct mlx5_devx_mkey_attr *attr)
 208 {
 209         struct mlx5_klm *klm_array = attr->klm_array;
 210         int klm_num = attr->klm_num;
 211         int in_size_dw = MLX5_ST_SZ_DW(create_mkey_in) +
 212                      (klm_num ? RTE_ALIGN(klm_num, 4) : 0) * MLX5_ST_SZ_DW(klm);
 213         uint32_t in[in_size_dw];
 214         uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0};
 215         void *mkc;
 216         struct mlx5_devx_obj *mkey = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mkey),
 217                                                  0, SOCKET_ID_ANY);
 218         size_t pgsize;
 219         uint32_t translation_size;
 220
 221         if (!mkey) {
 222                 rte_errno = ENOMEM;
 223                 return NULL;
 224         }
 225         memset(in, 0, in_size_dw * 4);
 226         pgsize = rte_mem_page_size();
 227         if (pgsize == (size_t)-1) {
 228                 mlx5_free(mkey);
 229                 DRV_LOG(ERR, "Failed to get page size");
 230                 rte_errno = ENOMEM;
 231                 return NULL;
 232         }
 233         MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY);
 234         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 235         if (klm_num > 0) {
 236                 int i;
 237                 uint8_t *klm = (uint8_t *)MLX5_ADDR_OF(create_mkey_in, in,
 238                                                        klm_pas_mtt);
 239                 translation_size = RTE_ALIGN(klm_num, 4);
 240                 for (i = 0; i < klm_num; i++) {
 241                         MLX5_SET(klm, klm, byte_count, klm_array[i].byte_count);
 242                         MLX5_SET(klm, klm, mkey, klm_array[i].mkey);
 243                         MLX5_SET64(klm, klm, address, klm_array[i].address);
 244                         klm += MLX5_ST_SZ_BYTES(klm);
 245                 }
 246                 for (; i < (int)translation_size; i++) {
 247                         MLX5_SET(klm, klm, mkey, 0x0);
 248                         MLX5_SET64(klm, klm, address, 0x0);
 249                         klm += MLX5_ST_SZ_BYTES(klm);
 250                 }
 251                 MLX5_SET(mkc, mkc, access_mode_1_0, attr->log_entity_size ?
 252                          MLX5_MKC_ACCESS_MODE_KLM_FBS :
 253                          MLX5_MKC_ACCESS_MODE_KLM);
 254                 MLX5_SET(mkc, mkc, log_page_size, attr->log_entity_size);
 255         } else {
 256                 translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16;
 257                 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
 258                 MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize));
 259         }
 260         MLX5_SET(create_mkey_in, in, translations_octword_actual_size,
 261                  translation_size);
 262         MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id);
 263         MLX5_SET(create_mkey_in, in, pg_access, attr->pg_access);
 264         MLX5_SET(mkc, mkc, lw, 0x1);
 265         MLX5_SET(mkc, mkc, lr, 0x1);
 266         if (attr->set_remote_rw) {
 267                 MLX5_SET(mkc, mkc, rw, 0x1);
 268                 MLX5_SET(mkc, mkc, rr, 0x1);
 269         }
 270         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 271         MLX5_SET(mkc, mkc, pd, attr->pd);
 272         MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF);
 273         MLX5_SET(mkc, mkc, umr_en, attr->umr_en);
 274         MLX5_SET(mkc, mkc, translations_octword_size, translation_size);
 275         MLX5_SET(mkc, mkc, relaxed_ordering_write,
 276                  attr->relaxed_ordering_write);
 277         MLX5_SET(mkc, mkc, relaxed_ordering_read, attr->relaxed_ordering_read);
 278         MLX5_SET64(mkc, mkc, start_addr, attr->addr);
 279         MLX5_SET64(mkc, mkc, len, attr->size);
 280         MLX5_SET(mkc, mkc, crypto_en, attr->crypto_en);
 281         if (attr->crypto_en) {
 282                 MLX5_SET(mkc, mkc, bsf_en, attr->crypto_en);
 283                 MLX5_SET(mkc, mkc, bsf_octword_size, 4);
 284         }
 285         mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out,
 286                                                sizeof(out));
 287         if (!mkey->obj) {
 288                 DRV_LOG(ERR, "Can't create %sdirect mkey - error %d",
 289                         klm_num ? "an in" : "a ", errno);
 290                 rte_errno = errno;
 291                 mlx5_free(mkey);
 292                 return NULL;
 293         }
 294         mkey->id = MLX5_GET(create_mkey_out, out, mkey_index);
 295         mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF);
 296         return mkey;
 297 }
 298
 299 /**
 300  * Get status of devx command response.
 301  * Mainly used for asynchronous commands.
 302  *
 303  * @param[in] out
 304  *   The out response buffer.
 305  *
 306  * @return
 307  *   0 on success, non-zero value otherwise.
 308  */
 309 int
 310 mlx5_devx_get_out_command_status(void *out)
 311 {
 312         int status;
 313
 314         if (!out)
 315                 return -EINVAL;
 316         status = MLX5_GET(query_flow_counter_out, out, status);
 317         if (status) {
 318                 int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome);
 319
 320                 DRV_LOG(ERR, "Bad DevX status %x, syndrome = %x", status,
 321                         syndrome);
 322         }
 323         return status;
 324 }
 325
 326 /**
 327  * Destroy any object allocated by a Devx API.
 328  *
 329  * @param[in] obj
 330  *   Pointer to a general object.
 331  *
 332  * @return
 333  *   0 on success, a negative value otherwise.
 334  */
 335 int
 336 mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj)
 337 {
 338         int ret;
 339
 340         if (!obj)
 341                 return 0;
 342         ret =  mlx5_glue->devx_obj_destroy(obj->obj);
 343         mlx5_free(obj);
 344         return ret;
 345 }
 346
 347 /**
 348  * Query NIC vport context.
 349  * Fills minimal inline attribute.
 350  *
 351  * @param[in] ctx
 352  *   ibv contexts returned from mlx5dv_open_device.
 353  * @param[in] vport
 354  *   vport index
 355  * @param[out] attr
 356  *   Attributes device values.
 357  *
 358  * @return
 359  *   0 on success, a negative value otherwise.
 360  */
 361 static int
 362 mlx5_devx_cmd_query_nic_vport_context(void *ctx,
 363                                       unsigned int vport,
 364                                       struct mlx5_hca_attr *attr)
 365 {
 366         uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0};
 367         uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0};
 368         void *vctx;
 369         int status, syndrome, rc;
 370
 371         /* Query NIC vport context to determine inline mode. */
 372         MLX5_SET(query_nic_vport_context_in, in, opcode,
 373                  MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT);
 374         MLX5_SET(query_nic_vport_context_in, in, vport_number, vport);
 375         if (vport)
 376                 MLX5_SET(query_nic_vport_context_in, in, other_vport, 1);
 377         rc = mlx5_glue->devx_general_cmd(ctx,
 378                                          in, sizeof(in),
 379                                          out, sizeof(out));
 380         if (rc)
 381                 goto error;
 382         status = MLX5_GET(query_nic_vport_context_out, out, status);
 383         syndrome = MLX5_GET(query_nic_vport_context_out, out, syndrome);
 384         if (status) {
 385                 DRV_LOG(DEBUG, "Failed to query NIC vport context, "
 386                         "status %x, syndrome = %x", status, syndrome);
 387                 return -1;
 388         }
 389         vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out,
 390                             nic_vport_context);
 391         attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx,
 392                                            min_wqe_inline_mode);
 393         return 0;
 394 error:
 395         rc = (rc > 0) ? -rc : rc;
 396         return rc;
 397 }
 398
 399 /**
 400  * Query NIC vDPA attributes.
 401  *
 402  * @param[in] ctx
 403  *   Context returned from mlx5 open_device() glue function.
 404  * @param[out] vdpa_attr
 405  *   vDPA Attributes structure to fill.
 406  */
 407 static void
 408 mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx,
 409                                   struct mlx5_hca_vdpa_attr *vdpa_attr)
 410 {
 411         uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0};
 412         uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0};
 413         void *hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 414         int status, syndrome, rc;
 415
 416         MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
 417         MLX5_SET(query_hca_cap_in, in, op_mod,
 418                  MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION |
 419                  MLX5_HCA_CAP_OPMOD_GET_CUR);
 420         rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
 421         status = MLX5_GET(query_hca_cap_out, out, status);
 422         syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
 423         if (rc || status) {
 424                 RTE_LOG(DEBUG, PMD, "Failed to query devx VDPA capabilities,"
 425                         " status %x, syndrome = %x", status, syndrome);
 426                 vdpa_attr->valid = 0;
 427         } else {
 428                 vdpa_attr->valid = 1;
 429                 vdpa_attr->desc_tunnel_offload_type =
 430                         MLX5_GET(virtio_emulation_cap, hcattr,
 431                                  desc_tunnel_offload_type);
 432                 vdpa_attr->eth_frame_offload_type =
 433                         MLX5_GET(virtio_emulation_cap, hcattr,
 434                                  eth_frame_offload_type);
 435                 vdpa_attr->virtio_version_1_0 =
 436                         MLX5_GET(virtio_emulation_cap, hcattr,
 437                                  virtio_version_1_0);
 438                 vdpa_attr->tso_ipv4 = MLX5_GET(virtio_emulation_cap, hcattr,
 439                                                tso_ipv4);
 440                 vdpa_attr->tso_ipv6 = MLX5_GET(virtio_emulation_cap, hcattr,
 441                                                tso_ipv6);
 442                 vdpa_attr->tx_csum = MLX5_GET(virtio_emulation_cap, hcattr,
 443                                               tx_csum);
 444                 vdpa_attr->rx_csum = MLX5_GET(virtio_emulation_cap, hcattr,
 445                                               rx_csum);
 446                 vdpa_attr->event_mode = MLX5_GET(virtio_emulation_cap, hcattr,
 447                                                  event_mode);
 448                 vdpa_attr->virtio_queue_type =
 449                         MLX5_GET(virtio_emulation_cap, hcattr,
 450                                  virtio_queue_type);
 451                 vdpa_attr->log_doorbell_stride =
 452                         MLX5_GET(virtio_emulation_cap, hcattr,
 453                                  log_doorbell_stride);
 454                 vdpa_attr->log_doorbell_bar_size =
 455                         MLX5_GET(virtio_emulation_cap, hcattr,
 456                                  log_doorbell_bar_size);
 457                 vdpa_attr->doorbell_bar_offset =
 458                         MLX5_GET64(virtio_emulation_cap, hcattr,
 459                                    doorbell_bar_offset);
 460                 vdpa_attr->max_num_virtio_queues =
 461                         MLX5_GET(virtio_emulation_cap, hcattr,
 462                                  max_num_virtio_queues);
 463                 vdpa_attr->umems[0].a = MLX5_GET(virtio_emulation_cap, hcattr,
 464                                                  umem_1_buffer_param_a);
 465                 vdpa_attr->umems[0].b = MLX5_GET(virtio_emulation_cap, hcattr,
 466                                                  umem_1_buffer_param_b);
 467                 vdpa_attr->umems[1].a = MLX5_GET(virtio_emulation_cap, hcattr,
 468                                                  umem_2_buffer_param_a);
 469                 vdpa_attr->umems[1].b = MLX5_GET(virtio_emulation_cap, hcattr,
 470                                                  umem_2_buffer_param_b);
 471                 vdpa_attr->umems[2].a = MLX5_GET(virtio_emulation_cap, hcattr,
 472                                                  umem_3_buffer_param_a);
 473                 vdpa_attr->umems[2].b = MLX5_GET(virtio_emulation_cap, hcattr,
 474                                                  umem_3_buffer_param_b);
 475         }
 476 }
 477
 478 int
 479 mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj,
 480                                   uint32_t ids[], uint32_t num)
 481 {
 482         uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
 483         uint32_t out[MLX5_ST_SZ_DW(create_flex_parser_out)] = {0};
 484         void *hdr = MLX5_ADDR_OF(create_flex_parser_out, in, hdr);
 485         void *flex = MLX5_ADDR_OF(create_flex_parser_out, out, flex);
 486         void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table);
 487         int ret;
 488         uint32_t idx = 0;
 489         uint32_t i;
 490
 491         if (num > MLX5_GRAPH_NODE_SAMPLE_NUM) {
 492                 rte_errno = EINVAL;
 493                 DRV_LOG(ERR, "Too many sample IDs to be fetched.");
 494                 return -rte_errno;
 495         }
 496         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
 497                  MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
 498         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
 499                  MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH);
 500         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, flex_obj->id);
 501         ret = mlx5_glue->devx_obj_query(flex_obj->obj, in, sizeof(in),
 502                                         out, sizeof(out));
 503         if (ret) {
 504                 rte_errno = ret;
 505                 DRV_LOG(ERR, "Failed to query sample IDs with object %p.",
 506                         (void *)flex_obj);
 507                 return -rte_errno;
 508         }
 509         for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) {
 510                 void *s_off = (void *)((char *)sample + i *
 511                               MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample));
 512                 uint32_t en;
 513
 514                 en = MLX5_GET(parse_graph_flow_match_sample, s_off,
 515                               flow_match_sample_en);
 516                 if (!en)
 517                         continue;
 518                 ids[idx++] = MLX5_GET(parse_graph_flow_match_sample, s_off,
 519                                   flow_match_sample_field_id);
 520         }
 521         if (num != idx) {
 522                 rte_errno = EINVAL;
 523                 DRV_LOG(ERR, "Number of sample IDs are not as expected.");
 524                 return -rte_errno;
 525         }
 526         return ret;
 527 }
 528
 529
 530 struct mlx5_devx_obj *
 531 mlx5_devx_cmd_create_flex_parser(void *ctx,
 532                               struct mlx5_devx_graph_node_attr *data)
 533 {
 534         uint32_t in[MLX5_ST_SZ_DW(create_flex_parser_in)] = {0};
 535         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
 536         void *hdr = MLX5_ADDR_OF(create_flex_parser_in, in, hdr);
 537         void *flex = MLX5_ADDR_OF(create_flex_parser_in, in, flex);
 538         void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table);
 539         void *in_arc = MLX5_ADDR_OF(parse_graph_flex, flex, input_arc);
 540         void *out_arc = MLX5_ADDR_OF(parse_graph_flex, flex, output_arc);
 541         struct mlx5_devx_obj *parse_flex_obj = mlx5_malloc
 542                      (MLX5_MEM_ZERO, sizeof(*parse_flex_obj), 0, SOCKET_ID_ANY);
 543         uint32_t i;
 544
 545         if (!parse_flex_obj) {
 546                 DRV_LOG(ERR, "Failed to allocate flex parser data.");
 547                 rte_errno = ENOMEM;
 548                 return NULL;
 549         }
 550         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
 551                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
 552         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
 553                  MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH);
 554         MLX5_SET(parse_graph_flex, flex, header_length_mode,
 555                  data->header_length_mode);
 556         MLX5_SET(parse_graph_flex, flex, header_length_base_value,
 557                  data->header_length_base_value);
 558         MLX5_SET(parse_graph_flex, flex, header_length_field_offset,
 559                  data->header_length_field_offset);
 560         MLX5_SET(parse_graph_flex, flex, header_length_field_shift,
 561                  data->header_length_field_shift);
 562         MLX5_SET(parse_graph_flex, flex, header_length_field_mask,
 563                  data->header_length_field_mask);
 564         for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) {
 565                 struct mlx5_devx_match_sample_attr *s = &data->sample[i];
 566                 void *s_off = (void *)((char *)sample + i *
 567                               MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample));
 568
 569                 if (!s->flow_match_sample_en)
 570                         continue;
 571                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 572                          flow_match_sample_en, !!s->flow_match_sample_en);
 573                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 574                          flow_match_sample_field_offset,
 575                          s->flow_match_sample_field_offset);
 576                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 577                          flow_match_sample_offset_mode,
 578                          s->flow_match_sample_offset_mode);
 579                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 580                          flow_match_sample_field_offset_mask,
 581                          s->flow_match_sample_field_offset_mask);
 582                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 583                          flow_match_sample_field_offset_shift,
 584                          s->flow_match_sample_field_offset_shift);
 585                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 586                          flow_match_sample_field_base_offset,
 587                          s->flow_match_sample_field_base_offset);
 588                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 589                          flow_match_sample_tunnel_mode,
 590                          s->flow_match_sample_tunnel_mode);
 591         }
 592         for (i = 0; i < MLX5_GRAPH_NODE_ARC_NUM; i++) {
 593                 struct mlx5_devx_graph_arc_attr *ia = &data->in[i];
 594                 struct mlx5_devx_graph_arc_attr *oa = &data->out[i];
 595                 void *in_off = (void *)((char *)in_arc + i *
 596                               MLX5_ST_SZ_BYTES(parse_graph_arc));
 597                 void *out_off = (void *)((char *)out_arc + i *
 598                               MLX5_ST_SZ_BYTES(parse_graph_arc));
 599
 600                 if (ia->arc_parse_graph_node != 0) {
 601                         MLX5_SET(parse_graph_arc, in_off,
 602                                  compare_condition_value,
 603                                  ia->compare_condition_value);
 604                         MLX5_SET(parse_graph_arc, in_off, start_inner_tunnel,
 605                                  ia->start_inner_tunnel);
 606                         MLX5_SET(parse_graph_arc, in_off, arc_parse_graph_node,
 607                                  ia->arc_parse_graph_node);
 608                         MLX5_SET(parse_graph_arc, in_off,
 609                                  parse_graph_node_handle,
 610                                  ia->parse_graph_node_handle);
 611                 }
 612                 if (oa->arc_parse_graph_node != 0) {
 613                         MLX5_SET(parse_graph_arc, out_off,
 614                                  compare_condition_value,
 615                                  oa->compare_condition_value);
 616                         MLX5_SET(parse_graph_arc, out_off, start_inner_tunnel,
 617                                  oa->start_inner_tunnel);
 618                         MLX5_SET(parse_graph_arc, out_off, arc_parse_graph_node,
 619                                  oa->arc_parse_graph_node);
 620                         MLX5_SET(parse_graph_arc, out_off,
 621                                  parse_graph_node_handle,
 622                                  oa->parse_graph_node_handle);
 623                 }
 624         }
 625         parse_flex_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
 626                                                          out, sizeof(out));
 627         if (!parse_flex_obj->obj) {
 628                 rte_errno = errno;
 629                 DRV_LOG(ERR, "Failed to create FLEX PARSE GRAPH object "
 630                         "by using DevX.");
 631                 mlx5_free(parse_flex_obj);
 632                 return NULL;
 633         }
 634         parse_flex_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
 635         return parse_flex_obj;
 636 }
 637
 638 /**
 639  * Query HCA attributes.
 640  * Using those attributes we can check on run time if the device
 641  * is having the required capabilities.
 642  *
 643  * @param[in] ctx
 644  *   Context returned from mlx5 open_device() glue function.
 645  * @param[out] attr
 646  *   Attributes device values.
 647  *
 648  * @return
 649  *   0 on success, a negative value otherwise.
 650  */
 651 int
 652 mlx5_devx_cmd_query_hca_attr(void *ctx,
 653                              struct mlx5_hca_attr *attr)
 654 {
 655         uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0};
 656         uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0};
 657         void *hcattr;
 658         int status, syndrome, rc, i;
 659         uint64_t general_obj_types_supported = 0;
 660
 661         MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
 662         MLX5_SET(query_hca_cap_in, in, op_mod,
 663                  MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE |
 664                  MLX5_HCA_CAP_OPMOD_GET_CUR);
 665
 666         rc = mlx5_glue->devx_general_cmd(ctx,
 667                                          in, sizeof(in), out, sizeof(out));
 668         if (rc)
 669                 goto error;
 670         status = MLX5_GET(query_hca_cap_out, out, status);
 671         syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
 672         if (status) {
 673                 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, "
 674                         "status %x, syndrome = %x", status, syndrome);
 675                 return -1;
 676         }
 677         hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 678         attr->flow_counter_bulk_alloc_bitmap =
 679                         MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc);
 680         attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr,
 681                                             flow_counters_dump);
 682         attr->log_max_rqt_size = MLX5_GET(cmd_hca_cap, hcattr,
 683                                           log_max_rqt_size);
 684         attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager);
 685         attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin);
 686         attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr,
 687                                                 log_max_hairpin_queues);
 688         attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr,
 689                                                     log_max_hairpin_wq_data_sz);
 690         attr->log_max_hairpin_num_packets = MLX5_GET
 691                 (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz);
 692         attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id);
 693         attr->relaxed_ordering_write = MLX5_GET(cmd_hca_cap, hcattr,
 694                                                 relaxed_ordering_write);
 695         attr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr,
 696                                                relaxed_ordering_read);
 697         attr->access_register_user = MLX5_GET(cmd_hca_cap, hcattr,
 698                                               access_register_user);
 699         attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr,
 700                                           eth_net_offloads);
 701         attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt);
 702         attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr,
 703                                                flex_parser_protocols);
 704         attr->max_geneve_tlv_options = MLX5_GET(cmd_hca_cap, hcattr,
 705                         max_geneve_tlv_options);
 706         attr->max_geneve_tlv_option_data_len = MLX5_GET(cmd_hca_cap, hcattr,
 707                         max_geneve_tlv_option_data_len);
 708         attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos);
 709         attr->qos.flow_meter_aso_sup = !!(MLX5_GET64(cmd_hca_cap, hcattr,
 710                                          general_obj_types) &
 711                               MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO);
 712         attr->vdpa.valid = !!(MLX5_GET64(cmd_hca_cap, hcattr,
 713                                          general_obj_types) &
 714                               MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q);
 715         attr->vdpa.queue_counters_valid = !!(MLX5_GET64(cmd_hca_cap, hcattr,
 716                                                         general_obj_types) &
 717                                   MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS);
 718         attr->parse_graph_flex_node = !!(MLX5_GET64(cmd_hca_cap, hcattr,
 719                                          general_obj_types) &
 720                               MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE);
 721         attr->wqe_index_ignore = MLX5_GET(cmd_hca_cap, hcattr,
 722                                           wqe_index_ignore_cap);
 723         attr->cross_channel = MLX5_GET(cmd_hca_cap, hcattr, cd);
 724         attr->non_wire_sq = MLX5_GET(cmd_hca_cap, hcattr, non_wire_sq);
 725         attr->log_max_static_sq_wq = MLX5_GET(cmd_hca_cap, hcattr,
 726                                               log_max_static_sq_wq);
 727         attr->num_lag_ports = MLX5_GET(cmd_hca_cap, hcattr, num_lag_ports);
 728         attr->dev_freq_khz = MLX5_GET(cmd_hca_cap, hcattr,
 729                                       device_frequency_khz);
 730         attr->scatter_fcs_w_decap_disable =
 731                 MLX5_GET(cmd_hca_cap, hcattr, scatter_fcs_w_decap_disable);
 732         attr->roce = MLX5_GET(cmd_hca_cap, hcattr, roce);
 733         attr->rq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, rq_ts_format);
 734         attr->sq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, sq_ts_format);
 735         attr->regex = MLX5_GET(cmd_hca_cap, hcattr, regexp);
 736         attr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr,
 737                                                regexp_num_of_engines);
 738         /* Read the general_obj_types bitmap and extract the relevant bits. */
 739         general_obj_types_supported = MLX5_GET64(cmd_hca_cap, hcattr,
 740                                                  general_obj_types);
 741         attr->vdpa.valid = !!(general_obj_types_supported &
 742                               MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q);
 743         attr->vdpa.queue_counters_valid =
 744                         !!(general_obj_types_supported &
 745                            MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS);
 746         attr->parse_graph_flex_node =
 747                         !!(general_obj_types_supported &
 748                            MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE);
 749         attr->flow_hit_aso = !!(general_obj_types_supported &
 750                                 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO);
 751         attr->geneve_tlv_opt = !!(general_obj_types_supported &
 752                                   MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT);
 753         attr->dek = !!(general_obj_types_supported &
 754                        MLX5_GENERAL_OBJ_TYPES_CAP_DEK);
 755         attr->import_kek = !!(general_obj_types_supported &
 756                               MLX5_GENERAL_OBJ_TYPES_CAP_IMPORT_KEK);
 757         attr->crypto_login = !!(general_obj_types_supported &
 758                                 MLX5_GENERAL_OBJ_TYPES_CAP_CRYPTO_LOGIN);
 759         /* Add reading of other GENERAL_OBJ_TYPES_CAP bits above this line. */
 760         attr->log_max_cq = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq);
 761         attr->log_max_qp = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp);
 762         attr->log_max_cq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq_sz);
 763         attr->log_max_qp_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp_sz);
 764         attr->log_max_mrw_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_mrw_sz);
 765         attr->log_max_pd = MLX5_GET(cmd_hca_cap, hcattr, log_max_pd);
 766         attr->log_max_srq = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq);
 767         attr->log_max_srq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq_sz);
 768         attr->reg_c_preserve =
 769                 MLX5_GET(cmd_hca_cap, hcattr, reg_c_preserve);
 770         attr->mmo_dma_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo);
 771         attr->mmo_compress_en = MLX5_GET(cmd_hca_cap, hcattr, compress);
 772         attr->mmo_decompress_en = MLX5_GET(cmd_hca_cap, hcattr, decompress);
 773         attr->compress_min_block_size = MLX5_GET(cmd_hca_cap, hcattr,
 774                                                  compress_min_block_size);
 775         attr->log_max_mmo_dma = MLX5_GET(cmd_hca_cap, hcattr, log_dma_mmo_size);
 776         attr->log_max_mmo_compress = MLX5_GET(cmd_hca_cap, hcattr,
 777                                               log_compress_mmo_size);
 778         attr->log_max_mmo_decompress = MLX5_GET(cmd_hca_cap, hcattr,
 779                                                 log_decompress_mmo_size);
 780         attr->cqe_compression = MLX5_GET(cmd_hca_cap, hcattr, cqe_compression);
 781         attr->mini_cqe_resp_flow_tag = MLX5_GET(cmd_hca_cap, hcattr,
 782                                                 mini_cqe_resp_flow_tag);
 783         attr->mini_cqe_resp_l3_l4_tag = MLX5_GET(cmd_hca_cap, hcattr,
 784                                                  mini_cqe_resp_l3_l4_tag);
 785         attr->umr_indirect_mkey_disabled =
 786                 MLX5_GET(cmd_hca_cap, hcattr, umr_indirect_mkey_disabled);
 787         attr->umr_modify_entity_size_disabled =
 788                 MLX5_GET(cmd_hca_cap, hcattr, umr_modify_entity_size_disabled);
 789         attr->crypto = MLX5_GET(cmd_hca_cap, hcattr, crypto);
 790         if (attr->crypto)
 791                 attr->aes_xts = MLX5_GET(cmd_hca_cap, hcattr, aes_xts);
 792         if (attr->qos.sup) {
 793                 MLX5_SET(query_hca_cap_in, in, op_mod,
 794                          MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP |
 795                          MLX5_HCA_CAP_OPMOD_GET_CUR);
 796                 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in),
 797                                                  out, sizeof(out));
 798                 if (rc)
 799                         goto error;
 800                 if (status) {
 801                         DRV_LOG(DEBUG, "Failed to query devx QOS capabilities,"
 802                                 " status %x, syndrome = %x", status, syndrome);
 803                         return -1;
 804                 }
 805                 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 806                 attr->qos.flow_meter_old =
 807                                 MLX5_GET(qos_cap, hcattr, flow_meter_old);
 808                 attr->qos.log_max_flow_meter =
 809                                 MLX5_GET(qos_cap, hcattr, log_max_flow_meter);
 810                 attr->qos.flow_meter_reg_c_ids =
 811                                 MLX5_GET(qos_cap, hcattr, flow_meter_reg_id);
 812                 attr->qos.flow_meter =
 813                                 MLX5_GET(qos_cap, hcattr, flow_meter);
 814                 attr->qos.packet_pacing =
 815                                 MLX5_GET(qos_cap, hcattr, packet_pacing);
 816                 attr->qos.wqe_rate_pp =
 817                                 MLX5_GET(qos_cap, hcattr, wqe_rate_pp);
 818                 if (attr->qos.flow_meter_aso_sup) {
 819                         attr->qos.log_meter_aso_granularity =
 820                                 MLX5_GET(qos_cap, hcattr,
 821                                         log_meter_aso_granularity);
 822                         attr->qos.log_meter_aso_max_alloc =
 823                                 MLX5_GET(qos_cap, hcattr,
 824                                         log_meter_aso_max_alloc);
 825                         attr->qos.log_max_num_meter_aso =
 826                                 MLX5_GET(qos_cap, hcattr,
 827                                         log_max_num_meter_aso);
 828                 }
 829         }
 830         if (attr->vdpa.valid)
 831                 mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa);
 832         if (!attr->eth_net_offloads)
 833                 return 0;
 834
 835         /* Query Flow Sampler Capability From FLow Table Properties Layout. */
 836         memset(in, 0, sizeof(in));
 837         memset(out, 0, sizeof(out));
 838         MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
 839         MLX5_SET(query_hca_cap_in, in, op_mod,
 840                  MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE |
 841                  MLX5_HCA_CAP_OPMOD_GET_CUR);
 842
 843         rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
 844         if (rc)
 845                 goto error;
 846         status = MLX5_GET(query_hca_cap_out, out, status);
 847         syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
 848         if (status) {
 849                 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, "
 850                         "status %x, syndrome = %x", status, syndrome);
 851                 attr->log_max_ft_sampler_num = 0;
 852                 return -1;
 853         }
 854         hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 855         attr->log_max_ft_sampler_num =
 856                         MLX5_GET(flow_table_nic_cap,
 857                         hcattr, flow_table_properties.log_max_ft_sampler_num);
 858
 859         /* Query HCA offloads for Ethernet protocol. */
 860         memset(in, 0, sizeof(in));
 861         memset(out, 0, sizeof(out));
 862         MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
 863         MLX5_SET(query_hca_cap_in, in, op_mod,
 864                  MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS |
 865                  MLX5_HCA_CAP_OPMOD_GET_CUR);
 866
 867         rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
 868         if (rc) {
 869                 attr->eth_net_offloads = 0;
 870                 goto error;
 871         }
 872         status = MLX5_GET(query_hca_cap_out, out, status);
 873         syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
 874         if (status) {
 875                 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, "
 876                         "status %x, syndrome = %x", status, syndrome);
 877                 attr->eth_net_offloads = 0;
 878                 return -1;
 879         }
 880         hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 881         attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps,
 882                                          hcattr, wqe_vlan_insert);
 883         attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr,
 884                                  lro_cap);
 885         attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps,
 886                                         hcattr, tunnel_lro_gre);
 887         attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps,
 888                                           hcattr, tunnel_lro_vxlan);
 889         attr->lro_max_msg_sz_mode = MLX5_GET
 890                                         (per_protocol_networking_offload_caps,
 891                                          hcattr, lro_max_msg_sz_mode);
 892         for (i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) {
 893                 attr->lro_timer_supported_periods[i] =
 894                         MLX5_GET(per_protocol_networking_offload_caps, hcattr,
 895                                  lro_timer_supported_periods[i]);
 896         }
 897         attr->lro_min_mss_size = MLX5_GET(per_protocol_networking_offload_caps,
 898                                           hcattr, lro_min_mss_size);
 899         attr->tunnel_stateless_geneve_rx =
 900                             MLX5_GET(per_protocol_networking_offload_caps,
 901                                      hcattr, tunnel_stateless_geneve_rx);
 902         attr->geneve_max_opt_len =
 903                     MLX5_GET(per_protocol_networking_offload_caps,
 904                              hcattr, max_geneve_opt_len);
 905         attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps,
 906                                          hcattr, wqe_inline_mode);
 907         attr->tunnel_stateless_gtp = MLX5_GET
 908                                         (per_protocol_networking_offload_caps,
 909                                          hcattr, tunnel_stateless_gtp);
 910         attr->rss_ind_tbl_cap = MLX5_GET
 911                                         (per_protocol_networking_offload_caps,
 912                                          hcattr, rss_ind_tbl_cap);
 913         /* Query HCA attribute for ROCE. */
 914         if (attr->roce) {
 915                 memset(in, 0, sizeof(in));
 916                 memset(out, 0, sizeof(out));
 917                 MLX5_SET(query_hca_cap_in, in, opcode,
 918                          MLX5_CMD_OP_QUERY_HCA_CAP);
 919                 MLX5_SET(query_hca_cap_in, in, op_mod,
 920                          MLX5_GET_HCA_CAP_OP_MOD_ROCE |
 921                          MLX5_HCA_CAP_OPMOD_GET_CUR);
 922                 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in),
 923                                                  out, sizeof(out));
 924                 if (rc)
 925                         goto error;
 926                 status = MLX5_GET(query_hca_cap_out, out, status);
 927                 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
 928                 if (status) {
 929                         DRV_LOG(DEBUG,
 930                                 "Failed to query devx HCA ROCE capabilities, "
 931                                 "status %x, syndrome = %x", status, syndrome);
 932                         return -1;
 933                 }
 934                 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 935                 attr->qp_ts_format = MLX5_GET(roce_caps, hcattr, qp_ts_format);
 936         }
 937         if (attr->eth_virt &&
 938             attr->wqe_inline_mode == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT) {
 939                 rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr);
 940                 if (rc) {
 941                         attr->eth_virt = 0;
 942                         goto error;
 943                 }
 944         }
 945         return 0;
 946 error:
 947         rc = (rc > 0) ? -rc : rc;
 948         return rc;
 949 }
 950
 951 /**
 952  * Query TIS transport domain from QP verbs object using DevX API.
 953  *
 954  * @param[in] qp
 955  *   Pointer to verbs QP returned by ibv_create_qp .
 956  * @param[in] tis_num
 957  *   TIS number of TIS to query.
 958  * @param[out] tis_td
 959  *   Pointer to TIS transport domain variable, to be set by the routine.
 960  *
 961  * @return
 962  *   0 on success, a negative value otherwise.
 963  */
 964 int
 965 mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num,
 966                               uint32_t *tis_td)
 967 {
 968 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 969         uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0};
 970         uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0};
 971         int rc;
 972         void *tis_ctx;
 973
 974         MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS);
 975         MLX5_SET(query_tis_in, in, tisn, tis_num);
 976         rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out));
 977         if (rc) {
 978                 DRV_LOG(ERR, "Failed to query QP using DevX");
 979                 return -rc;
 980         };
 981         tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context);
 982         *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain);
 983         return 0;
 984 #else
 985         (void)qp;
 986         (void)tis_num;
 987         (void)tis_td;
 988         return -ENOTSUP;
 989 #endif
 990 }
 991
 992 /**
 993  * Fill WQ data for DevX API command.
 994  * Utility function for use when creating DevX objects containing a WQ.
 995  *
 996  * @param[in] wq_ctx
 997  *   Pointer to WQ context to fill with data.
 998  * @param [in] wq_attr
 999  *   Pointer to WQ attributes structure to fill in WQ context.
1000  */
1001 static void
1002 devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr)
1003 {
1004         MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type);
1005         MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature);
1006         MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode);
1007         MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave);
1008         MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge);
1009         MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size);
1010         MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset);
1011         MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm);
1012         MLX5_SET(wq, wq_ctx, pd, wq_attr->pd);
1013         MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page);
1014         MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr);
1015         MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter);
1016         MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter);
1017         MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride);
1018         if (wq_attr->log_wq_pg_sz > MLX5_ADAPTER_PAGE_SHIFT)
1019                 MLX5_SET(wq, wq_ctx, log_wq_pg_sz,
1020                          wq_attr->log_wq_pg_sz - MLX5_ADAPTER_PAGE_SHIFT);
1021         MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz);
1022         MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid);
1023         MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid);
1024         MLX5_SET(wq, wq_ctx, log_hairpin_num_packets,
1025                  wq_attr->log_hairpin_num_packets);
1026         MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz);
1027         MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides,
1028                  wq_attr->single_wqe_log_num_of_strides);
1029         MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en);
1030         MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes,
1031                  wq_attr->single_stride_log_num_of_bytes);
1032         MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id);
1033         MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id);
1034         MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset);
1035 }
1036
1037 /**
1038  * Create RQ using DevX API.
1039  *
1040  * @param[in] ctx
1041  *   Context returned from mlx5 open_device() glue function.
1042  * @param [in] rq_attr
1043  *   Pointer to create RQ attributes structure.
1044  * @param [in] socket
1045  *   CPU socket ID for allocations.
1046  *
1047  * @return
1048  *   The DevX object created, NULL otherwise and rte_errno is set.
1049  */
1050 struct mlx5_devx_obj *
1051 mlx5_devx_cmd_create_rq(void *ctx,
1052                         struct mlx5_devx_create_rq_attr *rq_attr,
1053                         int socket)
1054 {
1055         uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0};
1056         uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0};
1057         void *rq_ctx, *wq_ctx;
1058         struct mlx5_devx_wq_attr *wq_attr;
1059         struct mlx5_devx_obj *rq = NULL;
1060
1061         rq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rq), 0, socket);
1062         if (!rq) {
1063                 DRV_LOG(ERR, "Failed to allocate RQ data");
1064                 rte_errno = ENOMEM;
1065                 return NULL;
1066         }
1067         MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ);
1068         rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx);
1069         MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky);
1070         MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en);
1071         MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);
1072         MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);
1073         MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type);
1074         MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
1075         MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en);
1076         MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin);
1077         MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index);
1078         MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn);
1079         MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
1080         MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn);
1081         MLX5_SET(sqc, rq_ctx, ts_format, rq_attr->ts_format);
1082         wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);
1083         wq_attr = &rq_attr->wq_attr;
1084         devx_cmd_fill_wq_data(wq_ctx, wq_attr);
1085         rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1086                                                   out, sizeof(out));
1087         if (!rq->obj) {
1088                 DRV_LOG(ERR, "Failed to create RQ using DevX");
1089                 rte_errno = errno;
1090                 mlx5_free(rq);
1091                 return NULL;
1092         }
1093         rq->id = MLX5_GET(create_rq_out, out, rqn);
1094         return rq;
1095 }
1096
1097 /**
1098  * Modify RQ using DevX API.
1099  *
1100  * @param[in] rq
1101  *   Pointer to RQ object structure.
1102  * @param [in] rq_attr
1103  *   Pointer to modify RQ attributes structure.
1104  *
1105  * @return
1106  *   0 on success, a negative errno value otherwise and rte_errno is set.
1107  */
1108 int
1109 mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,
1110                         struct mlx5_devx_modify_rq_attr *rq_attr)
1111 {
1112         uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0};
1113         uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0};
1114         void *rq_ctx, *wq_ctx;
1115         int ret;
1116
1117         MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ);
1118         MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state);
1119         MLX5_SET(modify_rq_in, in, rqn, rq->id);
1120         MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask);
1121         rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1122         MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
1123         if (rq_attr->modify_bitmask &
1124                         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS)
1125                 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);
1126         if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD)
1127                 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);
1128         if (rq_attr->modify_bitmask &
1129                         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID)
1130                 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
1131         MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq);
1132         MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca);
1133         if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) {
1134                 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);
1135                 MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm);
1136         }
1137         ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in),
1138                                          out, sizeof(out));
1139         if (ret) {
1140                 DRV_LOG(ERR, "Failed to modify RQ using DevX");
1141                 rte_errno = errno;
1142                 return -errno;
1143         }
1144         return ret;
1145 }
1146
1147 /**
1148  * Create TIR using DevX API.
1149  *
1150  * @param[in] ctx
1151  *  Context returned from mlx5 open_device() glue function.
1152  * @param [in] tir_attr
1153  *   Pointer to TIR attributes structure.
1154  *
1155  * @return
1156  *   The DevX object created, NULL otherwise and rte_errno is set.
1157  */
1158 struct mlx5_devx_obj *
1159 mlx5_devx_cmd_create_tir(void *ctx,
1160                          struct mlx5_devx_tir_attr *tir_attr)
1161 {
1162         uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
1163         uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0};
1164         void *tir_ctx, *outer, *inner, *rss_key;
1165         struct mlx5_devx_obj *tir = NULL;
1166
1167         tir = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tir), 0, SOCKET_ID_ANY);
1168         if (!tir) {
1169                 DRV_LOG(ERR, "Failed to allocate TIR data");
1170                 rte_errno = ENOMEM;
1171                 return NULL;
1172         }
1173         MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR);
1174         tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx);
1175         MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type);
1176         MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs,
1177                  tir_attr->lro_timeout_period_usecs);
1178         MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask);
1179         MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz);
1180         MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn);
1181         MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric);
1182         MLX5_SET(tirc, tir_ctx, tunneled_offload_en,
1183                  tir_attr->tunneled_offload_en);
1184         MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table);
1185         MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn);
1186         MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block);
1187         MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain);
1188         rss_key = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_toeplitz_key);
1189         memcpy(rss_key, tir_attr->rx_hash_toeplitz_key, MLX5_RSS_HASH_KEY_LEN);
1190         outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer);
1191         MLX5_SET(rx_hash_field_select, outer, l3_prot_type,
1192                  tir_attr->rx_hash_field_selector_outer.l3_prot_type);
1193         MLX5_SET(rx_hash_field_select, outer, l4_prot_type,
1194                  tir_attr->rx_hash_field_selector_outer.l4_prot_type);
1195         MLX5_SET(rx_hash_field_select, outer, selected_fields,
1196                  tir_attr->rx_hash_field_selector_outer.selected_fields);
1197         inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner);
1198         MLX5_SET(rx_hash_field_select, inner, l3_prot_type,
1199                  tir_attr->rx_hash_field_selector_inner.l3_prot_type);
1200         MLX5_SET(rx_hash_field_select, inner, l4_prot_type,
1201                  tir_attr->rx_hash_field_selector_inner.l4_prot_type);
1202         MLX5_SET(rx_hash_field_select, inner, selected_fields,
1203                  tir_attr->rx_hash_field_selector_inner.selected_fields);
1204         tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1205                                                    out, sizeof(out));
1206         if (!tir->obj) {
1207                 DRV_LOG(ERR, "Failed to create TIR using DevX");
1208                 rte_errno = errno;
1209                 mlx5_free(tir);
1210                 return NULL;
1211         }
1212         tir->id = MLX5_GET(create_tir_out, out, tirn);
1213         return tir;
1214 }
1215
1216 /**
1217  * Modify TIR using DevX API.
1218  *
1219  * @param[in] tir
1220  *   Pointer to TIR DevX object structure.
1221  * @param [in] modify_tir_attr
1222  *   Pointer to TIR modification attributes structure.
1223  *
1224  * @return
1225  *   0 on success, a negative errno value otherwise and rte_errno is set.
1226  */
1227 int
1228 mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir,
1229                          struct mlx5_devx_modify_tir_attr *modify_tir_attr)
1230 {
1231         struct mlx5_devx_tir_attr *tir_attr = &modify_tir_attr->tir;
1232         uint32_t in[MLX5_ST_SZ_DW(modify_tir_in)] = {0};
1233         uint32_t out[MLX5_ST_SZ_DW(modify_tir_out)] = {0};
1234         void *tir_ctx;
1235         int ret;
1236
1237         MLX5_SET(modify_tir_in, in, opcode, MLX5_CMD_OP_MODIFY_TIR);
1238         MLX5_SET(modify_tir_in, in, tirn, modify_tir_attr->tirn);
1239         MLX5_SET64(modify_tir_in, in, modify_bitmask,
1240                    modify_tir_attr->modify_bitmask);
1241         tir_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1242         if (modify_tir_attr->modify_bitmask &
1243                         MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO) {
1244                 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs,
1245                          tir_attr->lro_timeout_period_usecs);
1246                 MLX5_SET(tirc, tir_ctx, lro_enable_mask,
1247                          tir_attr->lro_enable_mask);
1248                 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz,
1249                          tir_attr->lro_max_msg_sz);
1250         }
1251         if (modify_tir_attr->modify_bitmask &
1252                         MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE)
1253                 MLX5_SET(tirc, tir_ctx, indirect_table,
1254                          tir_attr->indirect_table);
1255         if (modify_tir_attr->modify_bitmask &
1256                         MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH) {
1257                 int i;
1258                 void *outer, *inner;
1259
1260                 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric,
1261                          tir_attr->rx_hash_symmetric);
1262                 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn);
1263                 for (i = 0; i < 10; i++) {
1264                         MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i],
1265                                  tir_attr->rx_hash_toeplitz_key[i]);
1266                 }
1267                 outer = MLX5_ADDR_OF(tirc, tir_ctx,
1268                                      rx_hash_field_selector_outer);
1269                 MLX5_SET(rx_hash_field_select, outer, l3_prot_type,
1270                          tir_attr->rx_hash_field_selector_outer.l3_prot_type);
1271                 MLX5_SET(rx_hash_field_select, outer, l4_prot_type,
1272                          tir_attr->rx_hash_field_selector_outer.l4_prot_type);
1273                 MLX5_SET
1274                 (rx_hash_field_select, outer, selected_fields,
1275                  tir_attr->rx_hash_field_selector_outer.selected_fields);
1276                 inner = MLX5_ADDR_OF(tirc, tir_ctx,
1277                                      rx_hash_field_selector_inner);
1278                 MLX5_SET(rx_hash_field_select, inner, l3_prot_type,
1279                          tir_attr->rx_hash_field_selector_inner.l3_prot_type);
1280                 MLX5_SET(rx_hash_field_select, inner, l4_prot_type,
1281                          tir_attr->rx_hash_field_selector_inner.l4_prot_type);
1282                 MLX5_SET
1283                 (rx_hash_field_select, inner, selected_fields,
1284                  tir_attr->rx_hash_field_selector_inner.selected_fields);
1285         }
1286         if (modify_tir_attr->modify_bitmask &
1287             MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN) {
1288                 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block);
1289         }
1290         ret = mlx5_glue->devx_obj_modify(tir->obj, in, sizeof(in),
1291                                          out, sizeof(out));
1292         if (ret) {
1293                 DRV_LOG(ERR, "Failed to modify TIR using DevX");
1294                 rte_errno = errno;
1295                 return -errno;
1296         }
1297         return ret;
1298 }
1299
1300 /**
1301  * Create RQT using DevX API.
1302  *
1303  * @param[in] ctx
1304  *   Context returned from mlx5 open_device() glue function.
1305  * @param [in] rqt_attr
1306  *   Pointer to RQT attributes structure.
1307  *
1308  * @return
1309  *   The DevX object created, NULL otherwise and rte_errno is set.
1310  */
1311 struct mlx5_devx_obj *
1312 mlx5_devx_cmd_create_rqt(void *ctx,
1313                          struct mlx5_devx_rqt_attr *rqt_attr)
1314 {
1315         uint32_t *in = NULL;
1316         uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) +
1317                          rqt_attr->rqt_actual_size * sizeof(uint32_t);
1318         uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0};
1319         void *rqt_ctx;
1320         struct mlx5_devx_obj *rqt = NULL;
1321         int i;
1322
1323         in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY);
1324         if (!in) {
1325                 DRV_LOG(ERR, "Failed to allocate RQT IN data");
1326                 rte_errno = ENOMEM;
1327                 return NULL;
1328         }
1329         rqt = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt), 0, SOCKET_ID_ANY);
1330         if (!rqt) {
1331                 DRV_LOG(ERR, "Failed to allocate RQT data");
1332                 rte_errno = ENOMEM;
1333                 mlx5_free(in);
1334                 return NULL;
1335         }
1336         MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
1337         rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1338         MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type);
1339         MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size);
1340         MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size);
1341         for (i = 0; i < rqt_attr->rqt_actual_size; i++)
1342                 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]);
1343         rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out));
1344         mlx5_free(in);
1345         if (!rqt->obj) {
1346                 DRV_LOG(ERR, "Failed to create RQT using DevX");
1347                 rte_errno = errno;
1348                 mlx5_free(rqt);
1349                 return NULL;
1350         }
1351         rqt->id = MLX5_GET(create_rqt_out, out, rqtn);
1352         return rqt;
1353 }
1354
1355 /**
1356  * Modify RQT using DevX API.
1357  *
1358  * @param[in] rqt
1359  *   Pointer to RQT DevX object structure.
1360  * @param [in] rqt_attr
1361  *   Pointer to RQT attributes structure.
1362  *
1363  * @return
1364  *   0 on success, a negative errno value otherwise and rte_errno is set.
1365  */
1366 int
1367 mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt,
1368                          struct mlx5_devx_rqt_attr *rqt_attr)
1369 {
1370         uint32_t inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) +
1371                          rqt_attr->rqt_actual_size * sizeof(uint32_t);
1372         uint32_t out[MLX5_ST_SZ_DW(modify_rqt_out)] = {0};
1373         uint32_t *in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY);
1374         void *rqt_ctx;
1375         int i;
1376         int ret;
1377
1378         if (!in) {
1379                 DRV_LOG(ERR, "Failed to allocate RQT modify IN data.");
1380                 rte_errno = ENOMEM;
1381                 return -ENOMEM;
1382         }
1383         MLX5_SET(modify_rqt_in, in, opcode, MLX5_CMD_OP_MODIFY_RQT);
1384         MLX5_SET(modify_rqt_in, in, rqtn, rqt->id);
1385         MLX5_SET64(modify_rqt_in, in, modify_bitmask, 0x1);
1386         rqt_ctx = MLX5_ADDR_OF(modify_rqt_in, in, rqt_context);
1387         MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type);
1388         MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size);
1389         MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size);
1390         for (i = 0; i < rqt_attr->rqt_actual_size; i++)
1391                 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]);
1392         ret = mlx5_glue->devx_obj_modify(rqt->obj, in, inlen, out, sizeof(out));
1393         mlx5_free(in);
1394         if (ret) {
1395                 DRV_LOG(ERR, "Failed to modify RQT using DevX.");
1396                 rte_errno = errno;
1397                 return -rte_errno;
1398         }
1399         return ret;
1400 }
1401
1402 /**
1403  * Create SQ using DevX API.
1404  *
1405  * @param[in] ctx
1406  *   Context returned from mlx5 open_device() glue function.
1407  * @param [in] sq_attr
1408  *   Pointer to SQ attributes structure.
1409  * @param [in] socket
1410  *   CPU socket ID for allocations.
1411  *
1412  * @return
1413  *   The DevX object created, NULL otherwise and rte_errno is set.
1414  **/
1415 struct mlx5_devx_obj *
1416 mlx5_devx_cmd_create_sq(void *ctx,
1417                         struct mlx5_devx_create_sq_attr *sq_attr)
1418 {
1419         uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0};
1420         uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0};
1421         void *sq_ctx;
1422         void *wq_ctx;
1423         struct mlx5_devx_wq_attr *wq_attr;
1424         struct mlx5_devx_obj *sq = NULL;
1425
1426         sq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sq), 0, SOCKET_ID_ANY);
1427         if (!sq) {
1428                 DRV_LOG(ERR, "Failed to allocate SQ data");
1429                 rte_errno = ENOMEM;
1430                 return NULL;
1431         }
1432         MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ);
1433         sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx);
1434         MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky);
1435         MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master);
1436         MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre);
1437         MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en);
1438         MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe,
1439                  sq_attr->allow_multi_pkt_send_wqe);
1440         MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode,
1441                  sq_attr->min_wqe_inline_mode);
1442         MLX5_SET(sqc, sq_ctx, state, sq_attr->state);
1443         MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr);
1444         MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp);
1445         MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin);
1446         MLX5_SET(sqc, sq_ctx, non_wire, sq_attr->non_wire);
1447         MLX5_SET(sqc, sq_ctx, static_sq_wq, sq_attr->static_sq_wq);
1448         MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index);
1449         MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn);
1450         MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index,
1451                  sq_attr->packet_pacing_rate_limit_index);
1452         MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz);
1453         MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num);
1454         MLX5_SET(sqc, sq_ctx, ts_format, sq_attr->ts_format);
1455         wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq);
1456         wq_attr = &sq_attr->wq_attr;
1457         devx_cmd_fill_wq_data(wq_ctx, wq_attr);
1458         sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1459                                              out, sizeof(out));
1460         if (!sq->obj) {
1461                 DRV_LOG(ERR, "Failed to create SQ using DevX");
1462                 rte_errno = errno;
1463                 mlx5_free(sq);
1464                 return NULL;
1465         }
1466         sq->id = MLX5_GET(create_sq_out, out, sqn);
1467         return sq;
1468 }
1469
1470 /**
1471  * Modify SQ using DevX API.
1472  *
1473  * @param[in] sq
1474  *   Pointer to SQ object structure.
1475  * @param [in] sq_attr
1476  *   Pointer to SQ attributes structure.
1477  *
1478  * @return
1479  *   0 on success, a negative errno value otherwise and rte_errno is set.
1480  */
1481 int
1482 mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq,
1483                         struct mlx5_devx_modify_sq_attr *sq_attr)
1484 {
1485         uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0};
1486         uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0};
1487         void *sq_ctx;
1488         int ret;
1489
1490         MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ);
1491         MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state);
1492         MLX5_SET(modify_sq_in, in, sqn, sq->id);
1493         sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1494         MLX5_SET(sqc, sq_ctx, state, sq_attr->state);
1495         MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq);
1496         MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca);
1497         ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in),
1498                                          out, sizeof(out));
1499         if (ret) {
1500                 DRV_LOG(ERR, "Failed to modify SQ using DevX");
1501                 rte_errno = errno;
1502                 return -rte_errno;
1503         }
1504         return ret;
1505 }
1506
1507 /**
1508  * Create TIS using DevX API.
1509  *
1510  * @param[in] ctx
1511  *   Context returned from mlx5 open_device() glue function.
1512  * @param [in] tis_attr
1513  *   Pointer to TIS attributes structure.
1514  *
1515  * @return
1516  *   The DevX object created, NULL otherwise and rte_errno is set.
1517  */
1518 struct mlx5_devx_obj *
1519 mlx5_devx_cmd_create_tis(void *ctx,
1520                          struct mlx5_devx_tis_attr *tis_attr)
1521 {
1522         uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
1523         uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0};
1524         struct mlx5_devx_obj *tis = NULL;
1525         void *tis_ctx;
1526
1527         tis = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tis), 0, SOCKET_ID_ANY);
1528         if (!tis) {
1529                 DRV_LOG(ERR, "Failed to allocate TIS object");
1530                 rte_errno = ENOMEM;
1531                 return NULL;
1532         }
1533         MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS);
1534         tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx);
1535         MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity,
1536                  tis_attr->strict_lag_tx_port_affinity);
1537         MLX5_SET(tisc, tis_ctx, lag_tx_port_affinity,
1538                  tis_attr->lag_tx_port_affinity);
1539         MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio);
1540         MLX5_SET(tisc, tis_ctx, transport_domain,
1541                  tis_attr->transport_domain);
1542         tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1543                                               out, sizeof(out));
1544         if (!tis->obj) {
1545                 DRV_LOG(ERR, "Failed to create TIS using DevX");
1546                 rte_errno = errno;
1547                 mlx5_free(tis);
1548                 return NULL;
1549         }
1550         tis->id = MLX5_GET(create_tis_out, out, tisn);
1551         return tis;
1552 }
1553
1554 /**
1555  * Create transport domain using DevX API.
1556  *
1557  * @param[in] ctx
1558  *   Context returned from mlx5 open_device() glue function.
1559  * @return
1560  *   The DevX object created, NULL otherwise and rte_errno is set.
1561  */
1562 struct mlx5_devx_obj *
1563 mlx5_devx_cmd_create_td(void *ctx)
1564 {
1565         uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0};
1566         uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0};
1567         struct mlx5_devx_obj *td = NULL;
1568
1569         td = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*td), 0, SOCKET_ID_ANY);
1570         if (!td) {
1571                 DRV_LOG(ERR, "Failed to allocate TD object");
1572                 rte_errno = ENOMEM;
1573                 return NULL;
1574         }
1575         MLX5_SET(alloc_transport_domain_in, in, opcode,
1576                  MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN);
1577         td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1578                                              out, sizeof(out));
1579         if (!td->obj) {
1580                 DRV_LOG(ERR, "Failed to create TIS using DevX");
1581                 rte_errno = errno;
1582                 mlx5_free(td);
1583                 return NULL;
1584         }
1585         td->id = MLX5_GET(alloc_transport_domain_out, out,
1586                            transport_domain);
1587         return td;
1588 }
1589
1590 /**
1591  * Dump all flows to file.
1592  *
1593  * @param[in] fdb_domain
1594  *   FDB domain.
1595  * @param[in] rx_domain
1596  *   RX domain.
1597  * @param[in] tx_domain
1598  *   TX domain.
1599  * @param[out] file
1600  *   Pointer to file stream.
1601  *
1602  * @return
1603  *   0 on success, a nagative value otherwise.
1604  */
1605 int
1606 mlx5_devx_cmd_flow_dump(void *fdb_domain __rte_unused,
1607                         void *rx_domain __rte_unused,
1608                         void *tx_domain __rte_unused, FILE *file __rte_unused)
1609 {
1610         int ret = 0;
1611
1612 #ifdef HAVE_MLX5_DR_FLOW_DUMP
1613         if (fdb_domain) {
1614                 ret = mlx5_glue->dr_dump_domain(file, fdb_domain);
1615                 if (ret)
1616                         return ret;
1617         }
1618         MLX5_ASSERT(rx_domain);
1619         ret = mlx5_glue->dr_dump_domain(file, rx_domain);
1620         if (ret)
1621                 return ret;
1622         MLX5_ASSERT(tx_domain);
1623         ret = mlx5_glue->dr_dump_domain(file, tx_domain);
1624 #else
1625         ret = ENOTSUP;
1626 #endif
1627         return -ret;
1628 }
1629
1630 int
1631 mlx5_devx_cmd_flow_single_dump(void *rule_info __rte_unused,
1632                         FILE *file __rte_unused)
1633 {
1634         int ret = 0;
1635 #ifdef HAVE_MLX5_DR_FLOW_DUMP_RULE
1636         if (rule_info)
1637                 ret = mlx5_glue->dr_dump_rule(file, rule_info);
1638 #else
1639         ret = ENOTSUP;
1640 #endif
1641         return -ret;
1642 }
1643
1644 /*
1645  * Create CQ using DevX API.
1646  *
1647  * @param[in] ctx
1648  *   Context returned from mlx5 open_device() glue function.
1649  * @param [in] attr
1650  *   Pointer to CQ attributes structure.
1651  *
1652  * @return
1653  *   The DevX object created, NULL otherwise and rte_errno is set.
1654  */
1655 struct mlx5_devx_obj *
1656 mlx5_devx_cmd_create_cq(void *ctx, struct mlx5_devx_cq_attr *attr)
1657 {
1658         uint32_t in[MLX5_ST_SZ_DW(create_cq_in)] = {0};
1659         uint32_t out[MLX5_ST_SZ_DW(create_cq_out)] = {0};
1660         struct mlx5_devx_obj *cq_obj = mlx5_malloc(MLX5_MEM_ZERO,
1661                                                    sizeof(*cq_obj),
1662                                                    0, SOCKET_ID_ANY);
1663         void *cqctx = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1664
1665         if (!cq_obj) {
1666                 DRV_LOG(ERR, "Failed to allocate CQ object memory.");
1667                 rte_errno = ENOMEM;
1668                 return NULL;
1669         }
1670         MLX5_SET(create_cq_in, in, opcode, MLX5_CMD_OP_CREATE_CQ);
1671         if (attr->db_umem_valid) {
1672                 MLX5_SET(cqc, cqctx, dbr_umem_valid, attr->db_umem_valid);
1673                 MLX5_SET(cqc, cqctx, dbr_umem_id, attr->db_umem_id);
1674                 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_umem_offset);
1675         } else {
1676                 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_addr);
1677         }
1678         MLX5_SET(cqc, cqctx, cqe_sz, (RTE_CACHE_LINE_SIZE == 128) ?
1679                                      MLX5_CQE_SIZE_128B : MLX5_CQE_SIZE_64B);
1680         MLX5_SET(cqc, cqctx, cc, attr->use_first_only);
1681         MLX5_SET(cqc, cqctx, oi, attr->overrun_ignore);
1682         MLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size);
1683         if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT)
1684                 MLX5_SET(cqc, cqctx, log_page_size,
1685                          attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT);
1686         MLX5_SET(cqc, cqctx, c_eqn, attr->eqn);
1687         MLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id);
1688         MLX5_SET(cqc, cqctx, cqe_comp_en, !!attr->cqe_comp_en);
1689         MLX5_SET(cqc, cqctx, mini_cqe_res_format, attr->mini_cqe_res_format);
1690         MLX5_SET(cqc, cqctx, mini_cqe_res_format_ext,
1691                  attr->mini_cqe_res_format_ext);
1692         if (attr->q_umem_valid) {
1693                 MLX5_SET(create_cq_in, in, cq_umem_valid, attr->q_umem_valid);
1694                 MLX5_SET(create_cq_in, in, cq_umem_id, attr->q_umem_id);
1695                 MLX5_SET64(create_cq_in, in, cq_umem_offset,
1696                            attr->q_umem_offset);
1697         }
1698         cq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
1699                                                  sizeof(out));
1700         if (!cq_obj->obj) {
1701                 rte_errno = errno;
1702                 DRV_LOG(ERR, "Failed to create CQ using DevX errno=%d.", errno);
1703                 mlx5_free(cq_obj);
1704                 return NULL;
1705         }
1706         cq_obj->id = MLX5_GET(create_cq_out, out, cqn);
1707         return cq_obj;
1708 }
1709
1710 /**
1711  * Create VIRTQ using DevX API.
1712  *
1713  * @param[in] ctx
1714  *   Context returned from mlx5 open_device() glue function.
1715  * @param [in] attr
1716  *   Pointer to VIRTQ attributes structure.
1717  *
1718  * @return
1719  *   The DevX object created, NULL otherwise and rte_errno is set.
1720  */
1721 struct mlx5_devx_obj *
1722 mlx5_devx_cmd_create_virtq(void *ctx,
1723                            struct mlx5_devx_virtq_attr *attr)
1724 {
1725         uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0};
1726         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
1727         struct mlx5_devx_obj *virtq_obj = mlx5_malloc(MLX5_MEM_ZERO,
1728                                                      sizeof(*virtq_obj),
1729                                                      0, SOCKET_ID_ANY);
1730         void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq);
1731         void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr);
1732         void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context);
1733
1734         if (!virtq_obj) {
1735                 DRV_LOG(ERR, "Failed to allocate virtq data.");
1736                 rte_errno = ENOMEM;
1737                 return NULL;
1738         }
1739         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
1740                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
1741         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
1742                  MLX5_GENERAL_OBJ_TYPE_VIRTQ);
1743         MLX5_SET16(virtio_net_q, virtq, hw_available_index,
1744                    attr->hw_available_index);
1745         MLX5_SET16(virtio_net_q, virtq, hw_used_index, attr->hw_used_index);
1746         MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4);
1747         MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6);
1748         MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum);
1749         MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum);
1750         MLX5_SET16(virtio_q, virtctx, virtio_version_1_0,
1751                    attr->virtio_version_1_0);
1752         MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode);
1753         MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id);
1754         MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr);
1755         MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr);
1756         MLX5_SET64(virtio_q, virtctx, available_addr, attr->available_addr);
1757         MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index);
1758         MLX5_SET16(virtio_q, virtctx, queue_size, attr->q_size);
1759         MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey);
1760         MLX5_SET(virtio_q, virtctx, umem_1_id, attr->umems[0].id);
1761         MLX5_SET(virtio_q, virtctx, umem_1_size, attr->umems[0].size);
1762         MLX5_SET64(virtio_q, virtctx, umem_1_offset, attr->umems[0].offset);
1763         MLX5_SET(virtio_q, virtctx, umem_2_id, attr->umems[1].id);
1764         MLX5_SET(virtio_q, virtctx, umem_2_size, attr->umems[1].size);
1765         MLX5_SET64(virtio_q, virtctx, umem_2_offset, attr->umems[1].offset);
1766         MLX5_SET(virtio_q, virtctx, umem_3_id, attr->umems[2].id);
1767         MLX5_SET(virtio_q, virtctx, umem_3_size, attr->umems[2].size);
1768         MLX5_SET64(virtio_q, virtctx, umem_3_offset, attr->umems[2].offset);
1769         MLX5_SET(virtio_q, virtctx, counter_set_id, attr->counters_obj_id);
1770         MLX5_SET(virtio_q, virtctx, pd, attr->pd);
1771         MLX5_SET(virtio_q, virtctx, queue_period_mode, attr->hw_latency_mode);
1772         MLX5_SET(virtio_q, virtctx, queue_period_us, attr->hw_max_latency_us);
1773         MLX5_SET(virtio_q, virtctx, queue_max_count, attr->hw_max_pending_comp);
1774         MLX5_SET(virtio_net_q, virtq, tisn_or_qpn, attr->tis_id);
1775         virtq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
1776                                                     sizeof(out));
1777         if (!virtq_obj->obj) {
1778                 rte_errno = errno;
1779                 DRV_LOG(ERR, "Failed to create VIRTQ Obj using DevX.");
1780                 mlx5_free(virtq_obj);
1781                 return NULL;
1782         }
1783         virtq_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
1784         return virtq_obj;
1785 }
1786
1787 /**
1788  * Modify VIRTQ using DevX API.
1789  *
1790  * @param[in] virtq_obj
1791  *   Pointer to virtq object structure.
1792  * @param [in] attr
1793  *   Pointer to modify virtq attributes structure.
1794  *
1795  * @return
1796  *   0 on success, a negative errno value otherwise and rte_errno is set.
1797  */
1798 int
1799 mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj,
1800                            struct mlx5_devx_virtq_attr *attr)
1801 {
1802         uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0};
1803         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
1804         void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq);
1805         void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr);
1806         void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context);
1807         int ret;
1808
1809         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
1810                  MLX5_CMD_OP_MODIFY_GENERAL_OBJECT);
1811         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
1812                  MLX5_GENERAL_OBJ_TYPE_VIRTQ);
1813         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id);
1814         MLX5_SET64(virtio_net_q, virtq, modify_field_select, attr->type);
1815         MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index);
1816         switch (attr->type) {
1817         case MLX5_VIRTQ_MODIFY_TYPE_STATE:
1818                 MLX5_SET16(virtio_net_q, virtq, state, attr->state);
1819                 break;
1820         case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS:
1821                 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_mkey,
1822                          attr->dirty_bitmap_mkey);
1823                 MLX5_SET64(virtio_net_q, virtq, dirty_bitmap_addr,
1824                          attr->dirty_bitmap_addr);
1825                 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_size,
1826                          attr->dirty_bitmap_size);
1827                 break;
1828         case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE:
1829                 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_dump_enable,
1830                          attr->dirty_bitmap_dump_enable);
1831                 break;
1832         default:
1833                 rte_errno = EINVAL;
1834                 return -rte_errno;
1835         }
1836         ret = mlx5_glue->devx_obj_modify(virtq_obj->obj, in, sizeof(in),
1837                                          out, sizeof(out));
1838         if (ret) {
1839                 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX.");
1840                 rte_errno = errno;
1841                 return -rte_errno;
1842         }
1843         return ret;
1844 }
1845
1846 /**
1847  * Query VIRTQ using DevX API.
1848  *
1849  * @param[in] virtq_obj
1850  *   Pointer to virtq object structure.
1851  * @param [in/out] attr
1852  *   Pointer to virtq attributes structure.
1853  *
1854  * @return
1855  *   0 on success, a negative errno value otherwise and rte_errno is set.
1856  */
1857 int
1858 mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj,
1859                            struct mlx5_devx_virtq_attr *attr)
1860 {
1861         uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
1862         uint32_t out[MLX5_ST_SZ_DW(query_virtq_out)] = {0};
1863         void *hdr = MLX5_ADDR_OF(query_virtq_out, in, hdr);
1864         void *virtq = MLX5_ADDR_OF(query_virtq_out, out, virtq);
1865         int ret;
1866
1867         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
1868                  MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
1869         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
1870                  MLX5_GENERAL_OBJ_TYPE_VIRTQ);
1871         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id);
1872         ret = mlx5_glue->devx_obj_query(virtq_obj->obj, in, sizeof(in),
1873                                          out, sizeof(out));
1874         if (ret) {
1875                 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX.");
1876                 rte_errno = errno;
1877                 return -errno;
1878         }
1879         attr->hw_available_index = MLX5_GET16(virtio_net_q, virtq,
1880                                               hw_available_index);
1881         attr->hw_used_index = MLX5_GET16(virtio_net_q, virtq, hw_used_index);
1882         attr->state = MLX5_GET16(virtio_net_q, virtq, state);
1883         attr->error_type = MLX5_GET16(virtio_net_q, virtq,
1884                                       virtio_q_context.error_type);
1885         return ret;
1886 }
1887
1888 /**
1889  * Create QP using DevX API.
1890  *
1891  * @param[in] ctx
1892  *   Context returned from mlx5 open_device() glue function.
1893  * @param [in] attr
1894  *   Pointer to QP attributes structure.
1895  *
1896  * @return
1897  *   The DevX object created, NULL otherwise and rte_errno is set.
1898  */
1899 struct mlx5_devx_obj *
1900 mlx5_devx_cmd_create_qp(void *ctx,
1901                         struct mlx5_devx_qp_attr *attr)
1902 {
1903         uint32_t in[MLX5_ST_SZ_DW(create_qp_in)] = {0};
1904         uint32_t out[MLX5_ST_SZ_DW(create_qp_out)] = {0};
1905         struct mlx5_devx_obj *qp_obj = mlx5_malloc(MLX5_MEM_ZERO,
1906                                                    sizeof(*qp_obj),
1907                                                    0, SOCKET_ID_ANY);
1908         void *qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1909
1910         if (!qp_obj) {
1911                 DRV_LOG(ERR, "Failed to allocate QP data.");
1912                 rte_errno = ENOMEM;
1913                 return NULL;
1914         }
1915         MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP);
1916         MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC);
1917         MLX5_SET(qpc, qpc, pd, attr->pd);
1918         MLX5_SET(qpc, qpc, ts_format, attr->ts_format);
1919         if (attr->uar_index) {
1920                 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
1921                 MLX5_SET(qpc, qpc, uar_page, attr->uar_index);
1922                 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT)
1923                         MLX5_SET(qpc, qpc, log_page_size,
1924                                  attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT);
1925                 if (attr->sq_size) {
1926                         MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->sq_size));
1927                         MLX5_SET(qpc, qpc, cqn_snd, attr->cqn);
1928                         MLX5_SET(qpc, qpc, log_sq_size,
1929                                  rte_log2_u32(attr->sq_size));
1930                 } else {
1931                         MLX5_SET(qpc, qpc, no_sq, 1);
1932                 }
1933                 if (attr->rq_size) {
1934                         MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->rq_size));
1935                         MLX5_SET(qpc, qpc, cqn_rcv, attr->cqn);
1936                         MLX5_SET(qpc, qpc, log_rq_stride, attr->log_rq_stride -
1937                                  MLX5_LOG_RQ_STRIDE_SHIFT);
1938                         MLX5_SET(qpc, qpc, log_rq_size,
1939                                  rte_log2_u32(attr->rq_size));
1940                         MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ);
1941                 } else {
1942                         MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ);
1943                 }
1944                 if (attr->dbr_umem_valid) {
1945                         MLX5_SET(qpc, qpc, dbr_umem_valid,
1946                                  attr->dbr_umem_valid);
1947                         MLX5_SET(qpc, qpc, dbr_umem_id, attr->dbr_umem_id);
1948                 }
1949                 MLX5_SET64(qpc, qpc, dbr_addr, attr->dbr_address);
1950                 MLX5_SET64(create_qp_in, in, wq_umem_offset,
1951                            attr->wq_umem_offset);
1952                 MLX5_SET(create_qp_in, in, wq_umem_id, attr->wq_umem_id);
1953                 MLX5_SET(create_qp_in, in, wq_umem_valid, 1);
1954         } else {
1955                 /* Special QP to be managed by FW - no SQ\RQ\CQ\UAR\DB rec. */
1956                 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ);
1957                 MLX5_SET(qpc, qpc, no_sq, 1);
1958         }
1959         qp_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
1960                                                  sizeof(out));
1961         if (!qp_obj->obj) {
1962                 rte_errno = errno;
1963                 DRV_LOG(ERR, "Failed to create QP Obj using DevX.");
1964                 mlx5_free(qp_obj);
1965                 return NULL;
1966         }
1967         qp_obj->id = MLX5_GET(create_qp_out, out, qpn);
1968         return qp_obj;
1969 }
1970
1971 /**
1972  * Modify QP using DevX API.
1973  * Currently supports only force loop-back QP.
1974  *
1975  * @param[in] qp
1976  *   Pointer to QP object structure.
1977  * @param [in] qp_st_mod_op
1978  *   The QP state modification operation.
1979  * @param [in] remote_qp_id
1980  *   The remote QP ID for MLX5_CMD_OP_INIT2RTR_QP operation.
1981  *
1982  * @return
1983  *   0 on success, a negative errno value otherwise and rte_errno is set.
1984  */
1985 int
1986 mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op,
1987                               uint32_t remote_qp_id)
1988 {
1989         union {
1990                 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)];
1991                 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)];
1992                 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)];
1993         } in;
1994         union {
1995                 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)];
1996                 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)];
1997                 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)];
1998         } out;
1999         void *qpc;
2000         int ret;
2001         unsigned int inlen;
2002         unsigned int outlen;
2003
2004         memset(&in, 0, sizeof(in));
2005         memset(&out, 0, sizeof(out));
2006         MLX5_SET(rst2init_qp_in, &in, opcode, qp_st_mod_op);
2007         switch (qp_st_mod_op) {
2008         case MLX5_CMD_OP_RST2INIT_QP:
2009                 MLX5_SET(rst2init_qp_in, &in, qpn, qp->id);
2010                 qpc = MLX5_ADDR_OF(rst2init_qp_in, &in, qpc);
2011                 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1);
2012                 MLX5_SET(qpc, qpc, rre, 1);
2013                 MLX5_SET(qpc, qpc, rwe, 1);
2014                 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
2015                 inlen = sizeof(in.rst2init);
2016                 outlen = sizeof(out.rst2init);
2017                 break;
2018         case MLX5_CMD_OP_INIT2RTR_QP:
2019                 MLX5_SET(init2rtr_qp_in, &in, qpn, qp->id);
2020                 qpc = MLX5_ADDR_OF(init2rtr_qp_in, &in, qpc);
2021                 MLX5_SET(qpc, qpc, primary_address_path.fl, 1);
2022                 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1);
2023                 MLX5_SET(qpc, qpc, mtu, 1);
2024                 MLX5_SET(qpc, qpc, log_msg_max, 30);
2025                 MLX5_SET(qpc, qpc, remote_qpn, remote_qp_id);
2026                 MLX5_SET(qpc, qpc, min_rnr_nak, 0);
2027                 inlen = sizeof(in.init2rtr);
2028                 outlen = sizeof(out.init2rtr);
2029                 break;
2030         case MLX5_CMD_OP_RTR2RTS_QP:
2031                 qpc = MLX5_ADDR_OF(rtr2rts_qp_in, &in, qpc);
2032                 MLX5_SET(rtr2rts_qp_in, &in, qpn, qp->id);
2033                 MLX5_SET(qpc, qpc, primary_address_path.ack_timeout, 14);
2034                 MLX5_SET(qpc, qpc, log_ack_req_freq, 0);
2035                 MLX5_SET(qpc, qpc, retry_count, 7);
2036                 MLX5_SET(qpc, qpc, rnr_retry, 7);
2037                 inlen = sizeof(in.rtr2rts);
2038                 outlen = sizeof(out.rtr2rts);
2039                 break;
2040         default:
2041                 DRV_LOG(ERR, "Invalid or unsupported QP modify op %u.",
2042                         qp_st_mod_op);
2043                 rte_errno = EINVAL;
2044                 return -rte_errno;
2045         }
2046         ret = mlx5_glue->devx_obj_modify(qp->obj, &in, inlen, &out, outlen);
2047         if (ret) {
2048                 DRV_LOG(ERR, "Failed to modify QP using DevX.");
2049                 rte_errno = errno;
2050                 return -rte_errno;
2051         }
2052         return ret;
2053 }
2054
2055 struct mlx5_devx_obj *
2056 mlx5_devx_cmd_create_virtio_q_counters(void *ctx)
2057 {
2058         uint32_t in[MLX5_ST_SZ_DW(create_virtio_q_counters_in)] = {0};
2059         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2060         struct mlx5_devx_obj *couners_obj = mlx5_malloc(MLX5_MEM_ZERO,
2061                                                        sizeof(*couners_obj), 0,
2062                                                        SOCKET_ID_ANY);
2063         void *hdr = MLX5_ADDR_OF(create_virtio_q_counters_in, in, hdr);
2064
2065         if (!couners_obj) {
2066                 DRV_LOG(ERR, "Failed to allocate virtio queue counters data.");
2067                 rte_errno = ENOMEM;
2068                 return NULL;
2069         }
2070         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2071                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2072         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2073                  MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS);
2074         couners_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
2075                                                       sizeof(out));
2076         if (!couners_obj->obj) {
2077                 rte_errno = errno;
2078                 DRV_LOG(ERR, "Failed to create virtio queue counters Obj using"
2079                         " DevX.");
2080                 mlx5_free(couners_obj);
2081                 return NULL;
2082         }
2083         couners_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2084         return couners_obj;
2085 }
2086
2087 int
2088 mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj,
2089                                    struct mlx5_devx_virtio_q_couners_attr *attr)
2090 {
2091         uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
2092         uint32_t out[MLX5_ST_SZ_DW(query_virtio_q_counters_out)] = {0};
2093         void *hdr = MLX5_ADDR_OF(query_virtio_q_counters_out, in, hdr);
2094         void *virtio_q_counters = MLX5_ADDR_OF(query_virtio_q_counters_out, out,
2095                                                virtio_q_counters);
2096         int ret;
2097
2098         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2099                  MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
2100         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2101                  MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS);
2102         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, couners_obj->id);
2103         ret = mlx5_glue->devx_obj_query(couners_obj->obj, in, sizeof(in), out,
2104                                         sizeof(out));
2105         if (ret) {
2106                 DRV_LOG(ERR, "Failed to query virtio q counters using DevX.");
2107                 rte_errno = errno;
2108                 return -errno;
2109         }
2110         attr->received_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters,
2111                                          received_desc);
2112         attr->completed_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters,
2113                                           completed_desc);
2114         attr->error_cqes = MLX5_GET(virtio_q_counters, virtio_q_counters,
2115                                     error_cqes);
2116         attr->bad_desc_errors = MLX5_GET(virtio_q_counters, virtio_q_counters,
2117                                          bad_desc_errors);
2118         attr->exceed_max_chain = MLX5_GET(virtio_q_counters, virtio_q_counters,
2119                                           exceed_max_chain);
2120         attr->invalid_buffer = MLX5_GET(virtio_q_counters, virtio_q_counters,
2121                                         invalid_buffer);
2122         return ret;
2123 }
2124
2125 /**
2126  * Create general object of type FLOW_HIT_ASO using DevX API.
2127  *
2128  * @param[in] ctx
2129  *   Context returned from mlx5 open_device() glue function.
2130  * @param [in] pd
2131  *   PD value to associate the FLOW_HIT_ASO object with.
2132  *
2133  * @return
2134  *   The DevX object created, NULL otherwise and rte_errno is set.
2135  */
2136 struct mlx5_devx_obj *
2137 mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, uint32_t pd)
2138 {
2139         uint32_t in[MLX5_ST_SZ_DW(create_flow_hit_aso_in)] = {0};
2140         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2141         struct mlx5_devx_obj *flow_hit_aso_obj = NULL;
2142         void *ptr = NULL;
2143
2144         flow_hit_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*flow_hit_aso_obj),
2145                                        0, SOCKET_ID_ANY);
2146         if (!flow_hit_aso_obj) {
2147                 DRV_LOG(ERR, "Failed to allocate FLOW_HIT_ASO object data");
2148                 rte_errno = ENOMEM;
2149                 return NULL;
2150         }
2151         ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, hdr);
2152         MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2153                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2154         MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2155                  MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO);
2156         ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, flow_hit_aso);
2157         MLX5_SET(flow_hit_aso, ptr, access_pd, pd);
2158         flow_hit_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2159                                                            out, sizeof(out));
2160         if (!flow_hit_aso_obj->obj) {
2161                 rte_errno = errno;
2162                 DRV_LOG(ERR, "Failed to create FLOW_HIT_ASO obj using DevX.");
2163                 mlx5_free(flow_hit_aso_obj);
2164                 return NULL;
2165         }
2166         flow_hit_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2167         return flow_hit_aso_obj;
2168 }
2169
2170 /*
2171  * Create PD using DevX API.
2172  *
2173  * @param[in] ctx
2174  *   Context returned from mlx5 open_device() glue function.
2175  *
2176  * @return
2177  *   The DevX object created, NULL otherwise and rte_errno is set.
2178  */
2179 struct mlx5_devx_obj *
2180 mlx5_devx_cmd_alloc_pd(void *ctx)
2181 {
2182         struct mlx5_devx_obj *ppd =
2183                 mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ppd), 0, SOCKET_ID_ANY);
2184         u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {0};
2185         u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {0};
2186
2187         if (!ppd) {
2188                 DRV_LOG(ERR, "Failed to allocate PD data.");
2189                 rte_errno = ENOMEM;
2190                 return NULL;
2191         }
2192         MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD);
2193         ppd->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2194                                 out, sizeof(out));
2195         if (!ppd->obj) {
2196                 mlx5_free(ppd);
2197                 DRV_LOG(ERR, "Failed to allocate PD Obj using DevX.");
2198                 rte_errno = errno;
2199                 return NULL;
2200         }
2201         ppd->id = MLX5_GET(alloc_pd_out, out, pd);
2202         return ppd;
2203 }
2204
2205 /**
2206  * Create general object of type FLOW_METER_ASO using DevX API.
2207  *
2208  * @param[in] ctx
2209  *   Context returned from mlx5 open_device() glue function.
2210  * @param [in] pd
2211  *   PD value to associate the FLOW_METER_ASO object with.
2212  * @param [in] log_obj_size
2213  *   log_obj_size define to allocate number of 2 * meters
2214  *   in one FLOW_METER_ASO object.
2215  *
2216  * @return
2217  *   The DevX object created, NULL otherwise and rte_errno is set.
2218  */
2219 struct mlx5_devx_obj *
2220 mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx, uint32_t pd,
2221                                                 uint32_t log_obj_size)
2222 {
2223         uint32_t in[MLX5_ST_SZ_DW(create_flow_meter_aso_in)] = {0};
2224         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)];
2225         struct mlx5_devx_obj *flow_meter_aso_obj;
2226         void *ptr;
2227
2228         flow_meter_aso_obj = mlx5_malloc(MLX5_MEM_ZERO,
2229                                                 sizeof(*flow_meter_aso_obj),
2230                                                 0, SOCKET_ID_ANY);
2231         if (!flow_meter_aso_obj) {
2232                 DRV_LOG(ERR, "Failed to allocate FLOW_METER_ASO object data");
2233                 rte_errno = ENOMEM;
2234                 return NULL;
2235         }
2236         ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, hdr);
2237         MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2238                 MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2239         MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2240                 MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO);
2241         MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range,
2242                 log_obj_size);
2243         ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, flow_meter_aso);
2244         MLX5_SET(flow_meter_aso, ptr, access_pd, pd);
2245         flow_meter_aso_obj->obj = mlx5_glue->devx_obj_create(
2246                                                         ctx, in, sizeof(in),
2247                                                         out, sizeof(out));
2248         if (!flow_meter_aso_obj->obj) {
2249                 rte_errno = errno;
2250                 DRV_LOG(ERR, "Failed to create FLOW_METER_ASO obj using DevX.");
2251                 mlx5_free(flow_meter_aso_obj);
2252                 return NULL;
2253         }
2254         flow_meter_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr,
2255                                                                 out, obj_id);
2256         return flow_meter_aso_obj;
2257 }
2258
2259 /**
2260  * Create general object of type GENEVE TLV option using DevX API.
2261  *
2262  * @param[in] ctx
2263  *   Context returned from mlx5 open_device() glue function.
2264  * @param [in] class
2265  *   TLV option variable value of class
2266  * @param [in] type
2267  *   TLV option variable value of type
2268  * @param [in] len
2269  *   TLV option variable value of len
2270  *
2271  * @return
2272  *   The DevX object created, NULL otherwise and rte_errno is set.
2273  */
2274 struct mlx5_devx_obj *
2275 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx,
2276                 uint16_t class, uint8_t type, uint8_t len)
2277 {
2278         uint32_t in[MLX5_ST_SZ_DW(create_geneve_tlv_option_in)] = {0};
2279         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2280         struct mlx5_devx_obj *geneve_tlv_opt_obj = mlx5_malloc(MLX5_MEM_ZERO,
2281                                                    sizeof(*geneve_tlv_opt_obj),
2282                                                    0, SOCKET_ID_ANY);
2283
2284         if (!geneve_tlv_opt_obj) {
2285                 DRV_LOG(ERR, "Failed to allocate geneve tlv option object.");
2286                 rte_errno = ENOMEM;
2287                 return NULL;
2288         }
2289         void *hdr = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, hdr);
2290         void *opt = MLX5_ADDR_OF(create_geneve_tlv_option_in, in,
2291                         geneve_tlv_opt);
2292         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2293                         MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2294         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2295                  MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT);
2296         MLX5_SET(geneve_tlv_option, opt, option_class,
2297                         rte_be_to_cpu_16(class));
2298         MLX5_SET(geneve_tlv_option, opt, option_type, type);
2299         MLX5_SET(geneve_tlv_option, opt, option_data_length, len);
2300         geneve_tlv_opt_obj->obj = mlx5_glue->devx_obj_create(ctx, in,
2301                                         sizeof(in), out, sizeof(out));
2302         if (!geneve_tlv_opt_obj->obj) {
2303                 rte_errno = errno;
2304                 DRV_LOG(ERR, "Failed to create Geneve tlv option "
2305                                 "Obj using DevX.");
2306                 mlx5_free(geneve_tlv_opt_obj);
2307                 return NULL;
2308         }
2309         geneve_tlv_opt_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2310         return geneve_tlv_opt_obj;
2311 }
2312
2313 int
2314 mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id)
2315 {
2316 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2317         uint32_t in[MLX5_ST_SZ_DW(query_rq_in)] = {0};
2318         uint32_t out[MLX5_ST_SZ_DW(query_rq_out)] = {0};
2319         int rc;
2320         void *rq_ctx;
2321
2322         MLX5_SET(query_rq_in, in, opcode, MLX5_CMD_OP_QUERY_RQ);
2323         MLX5_SET(query_rq_in, in, rqn, ((struct ibv_wq *)wq)->wq_num);
2324         rc = mlx5_glue->devx_wq_query(wq, in, sizeof(in), out, sizeof(out));
2325         if (rc) {
2326                 rte_errno = errno;
2327                 DRV_LOG(ERR, "Failed to query WQ counter set ID using DevX - "
2328                         "rc = %d, errno = %d.", rc, errno);
2329                 return -rc;
2330         };
2331         rq_ctx = MLX5_ADDR_OF(query_rq_out, out, rq_context);
2332         *counter_set_id = MLX5_GET(rqc, rq_ctx, counter_set_id);
2333         return 0;
2334 #else
2335         (void)wq;
2336         (void)counter_set_id;
2337         return -ENOTSUP;
2338 #endif
2339 }
2340
2341 /*
2342  * Allocate queue counters via devx interface.
2343  *
2344  * @param[in] ctx
2345  *   Context returned from mlx5 open_device() glue function.
2346  *
2347  * @return
2348  *   Pointer to counter object on success, a NULL value otherwise and
2349  *   rte_errno is set.
2350  */
2351 struct mlx5_devx_obj *
2352 mlx5_devx_cmd_queue_counter_alloc(void *ctx)
2353 {
2354         struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 0,
2355                                                 SOCKET_ID_ANY);
2356         uint32_t in[MLX5_ST_SZ_DW(alloc_q_counter_in)]   = {0};
2357         uint32_t out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {0};
2358
2359         if (!dcs) {
2360                 rte_errno = ENOMEM;
2361                 return NULL;
2362         }
2363         MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER);
2364         dcs->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
2365                                               sizeof(out));
2366         if (!dcs->obj) {
2367                 DRV_LOG(DEBUG, "Can't allocate q counter set by DevX - error "
2368                         "%d.", errno);
2369                 rte_errno = errno;
2370                 mlx5_free(dcs);
2371                 return NULL;
2372         }
2373         dcs->id = MLX5_GET(alloc_q_counter_out, out, counter_set_id);
2374         return dcs;
2375 }
2376
2377 /**
2378  * Query queue counters values.
2379  *
2380  * @param[in] dcs
2381  *   devx object of the queue counter set.
2382  * @param[in] clear
2383  *   Whether hardware should clear the counters after the query or not.
2384  *  @param[out] out_of_buffers
2385  *   Number of dropped occurred due to lack of WQE for the associated QPs/RQs.
2386  *
2387  * @return
2388  *   0 on success, a negative value otherwise.
2389  */
2390 int
2391 mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear,
2392                                   uint32_t *out_of_buffers)
2393 {
2394         uint32_t out[MLX5_ST_SZ_BYTES(query_q_counter_out)] = {0};
2395         uint32_t in[MLX5_ST_SZ_DW(query_q_counter_in)] = {0};
2396         int rc;
2397
2398         MLX5_SET(query_q_counter_in, in, opcode,
2399                  MLX5_CMD_OP_QUERY_Q_COUNTER);
2400         MLX5_SET(query_q_counter_in, in, op_mod, 0);
2401         MLX5_SET(query_q_counter_in, in, counter_set_id, dcs->id);
2402         MLX5_SET(query_q_counter_in, in, clear, !!clear);
2403         rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out,
2404                                        sizeof(out));
2405         if (rc) {
2406                 DRV_LOG(ERR, "Failed to query devx q counter set - rc %d", rc);
2407                 rte_errno = rc;
2408                 return -rc;
2409         }
2410         *out_of_buffers = MLX5_GET(query_q_counter_out, out, out_of_buffer);
2411         return 0;
2412 }
2413
2414 /**
2415  * Create general object of type DEK using DevX API.
2416  *
2417  * @param[in] ctx
2418  *   Context returned from mlx5 open_device() glue function.
2419  * @param [in] attr
2420  *   Pointer to DEK attributes structure.
2421  *
2422  * @return
2423  *   The DevX object created, NULL otherwise and rte_errno is set.
2424  */
2425 struct mlx5_devx_obj *
2426 mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr)
2427 {
2428         uint32_t in[MLX5_ST_SZ_DW(create_dek_in)] = {0};
2429         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2430         struct mlx5_devx_obj *dek_obj = NULL;
2431         void *ptr = NULL, *key_addr = NULL;
2432
2433         dek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dek_obj),
2434                               0, SOCKET_ID_ANY);
2435         if (dek_obj == NULL) {
2436                 DRV_LOG(ERR, "Failed to allocate DEK object data");
2437                 rte_errno = ENOMEM;
2438                 return NULL;
2439         }
2440         ptr = MLX5_ADDR_OF(create_dek_in, in, hdr);
2441         MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2442                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2443         MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2444                  MLX5_GENERAL_OBJ_TYPE_DEK);
2445         ptr = MLX5_ADDR_OF(create_dek_in, in, dek);
2446         MLX5_SET(dek, ptr, key_size, attr->key_size);
2447         MLX5_SET(dek, ptr, has_keytag, attr->has_keytag);
2448         MLX5_SET(dek, ptr, key_purpose, attr->key_purpose);
2449         MLX5_SET(dek, ptr, pd, attr->pd);
2450         MLX5_SET64(dek, ptr, opaque, attr->opaque);
2451         key_addr = MLX5_ADDR_OF(dek, ptr, key);
2452         memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE);
2453         dek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2454                                                   out, sizeof(out));
2455         if (dek_obj->obj == NULL) {
2456                 rte_errno = errno;
2457                 DRV_LOG(ERR, "Failed to create DEK obj using DevX.");
2458                 mlx5_free(dek_obj);
2459                 return NULL;
2460         }
2461         dek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2462         return dek_obj;
2463 }
2464
2465 /**
2466  * Create general object of type IMPORT_KEK using DevX API.
2467  *
2468  * @param[in] ctx
2469  *   Context returned from mlx5 open_device() glue function.
2470  * @param [in] attr
2471  *   Pointer to IMPORT_KEK attributes structure.
2472  *
2473  * @return
2474  *   The DevX object created, NULL otherwise and rte_errno is set.
2475  */
2476 struct mlx5_devx_obj *
2477 mlx5_devx_cmd_create_import_kek_obj(void *ctx,
2478                                     struct mlx5_devx_import_kek_attr *attr)
2479 {
2480         uint32_t in[MLX5_ST_SZ_DW(create_import_kek_in)] = {0};
2481         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2482         struct mlx5_devx_obj *import_kek_obj = NULL;
2483         void *ptr = NULL, *key_addr = NULL;
2484
2485         import_kek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*import_kek_obj),
2486                                      0, SOCKET_ID_ANY);
2487         if (import_kek_obj == NULL) {
2488                 DRV_LOG(ERR, "Failed to allocate IMPORT_KEK object data");
2489                 rte_errno = ENOMEM;
2490                 return NULL;
2491         }
2492         ptr = MLX5_ADDR_OF(create_import_kek_in, in, hdr);
2493         MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2494                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2495         MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2496                  MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK);
2497         ptr = MLX5_ADDR_OF(create_import_kek_in, in, import_kek);
2498         MLX5_SET(import_kek, ptr, key_size, attr->key_size);
2499         key_addr = MLX5_ADDR_OF(import_kek, ptr, key);
2500         memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE);
2501         import_kek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2502                                                          out, sizeof(out));
2503         if (import_kek_obj->obj == NULL) {
2504                 rte_errno = errno;
2505                 DRV_LOG(ERR, "Failed to create IMPORT_KEK object using DevX.");
2506                 mlx5_free(import_kek_obj);
2507                 return NULL;
2508         }
2509         import_kek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2510         return import_kek_obj;
2511 }
2512
2513 /**
2514  * Create general object of type CRYPTO_LOGIN using DevX API.
2515  *
2516  * @param[in] ctx
2517  *   Context returned from mlx5 open_device() glue function.
2518  * @param [in] attr
2519  *   Pointer to CRYPTO_LOGIN attributes structure.
2520  *
2521  * @return
2522  *   The DevX object created, NULL otherwise and rte_errno is set.
2523  */
2524 struct mlx5_devx_obj *
2525 mlx5_devx_cmd_create_crypto_login_obj(void *ctx,
2526                                       struct mlx5_devx_crypto_login_attr *attr)
2527 {
2528         uint32_t in[MLX5_ST_SZ_DW(create_crypto_login_in)] = {0};
2529         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2530         struct mlx5_devx_obj *crypto_login_obj = NULL;
2531         void *ptr = NULL, *credential_addr = NULL;
2532
2533         crypto_login_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*crypto_login_obj),
2534                                        0, SOCKET_ID_ANY);
2535         if (crypto_login_obj == NULL) {
2536                 DRV_LOG(ERR, "Failed to allocate CRYPTO_LOGIN object data");
2537                 rte_errno = ENOMEM;
2538                 return NULL;
2539         }
2540         ptr = MLX5_ADDR_OF(create_crypto_login_in, in, hdr);
2541         MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2542                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2543         MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2544                  MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN);
2545         ptr = MLX5_ADDR_OF(create_crypto_login_in, in, crypto_login);
2546         MLX5_SET(crypto_login, ptr, credential_pointer,
2547                  attr->credential_pointer);
2548         MLX5_SET(crypto_login, ptr, session_import_kek_ptr,
2549                  attr->session_import_kek_ptr);
2550         credential_addr = MLX5_ADDR_OF(crypto_login, ptr, credential);
2551         memcpy(credential_addr, (void *)(attr->credential),
2552                MLX5_CRYPTO_LOGIN_CREDENTIAL_SIZE);
2553         crypto_login_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2554                                                            out, sizeof(out));
2555         if (crypto_login_obj->obj == NULL) {
2556                 rte_errno = errno;
2557                 DRV_LOG(ERR, "Failed to create CRYPTO_LOGIN obj using DevX.");
2558                 mlx5_free(crypto_login_obj);
2559                 return NULL;
2560         }
2561         crypto_login_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2562         return crypto_login_obj;
2563 }