1 // SPDX-License-Identifier: BSD-3-Clause
2 /* Copyright 2018 Mellanox Technologies, Ltd */
7 #include <rte_malloc.h>
8 #include <rte_eal_paging.h>
11 #include "mlx5_devx_cmds.h"
12 #include "mlx5_common_utils.h"
13 #include "mlx5_malloc.h"
17 * Perform read access to the registers. Reads data from register
18 * and writes ones to the specified buffer.
21 * Context returned from mlx5 open_device() glue function.
23 * Register identifier according to the PRM.
25 * Register access auxiliary parameter according to the PRM.
27 * Pointer to the buffer to store read data.
29 * Buffer size in double words.
32 * 0 on success, a negative value otherwise.
35 mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg,
36 uint32_t *data, uint32_t dw_cnt)
38 uint32_t in[MLX5_ST_SZ_DW(access_register_in)] = {0};
39 uint32_t out[MLX5_ST_SZ_DW(access_register_out) +
40 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0};
43 MLX5_ASSERT(data && dw_cnt);
44 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX);
45 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) {
46 DRV_LOG(ERR, "Not enough buffer for register read data");
49 MLX5_SET(access_register_in, in, opcode,
50 MLX5_CMD_OP_ACCESS_REGISTER_USER);
51 MLX5_SET(access_register_in, in, op_mod,
52 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ);
53 MLX5_SET(access_register_in, in, register_id, reg_id);
54 MLX5_SET(access_register_in, in, argument, arg);
55 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out,
56 MLX5_ST_SZ_BYTES(access_register_out) +
57 sizeof(uint32_t) * dw_cnt);
60 status = MLX5_GET(access_register_out, out, status);
62 int syndrome = MLX5_GET(access_register_out, out, syndrome);
64 DRV_LOG(DEBUG, "Failed to access NIC register 0x%X, "
65 "status %x, syndrome = %x",
66 reg_id, status, syndrome);
69 memcpy(data, &out[MLX5_ST_SZ_DW(access_register_out)],
70 dw_cnt * sizeof(uint32_t));
73 rc = (rc > 0) ? -rc : rc;
78 * Allocate flow counters via devx interface.
81 * Context returned from mlx5 open_device() glue function.
83 * Pointer to counters properties structure to be filled by the routine.
85 * Bulk counter numbers in 128 counters units.
88 * Pointer to counter object on success, a negative value otherwise and
91 struct mlx5_devx_obj *
92 mlx5_devx_cmd_flow_counter_alloc(void *ctx, uint32_t bulk_n_128)
94 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs),
96 uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0};
97 uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0};
103 MLX5_SET(alloc_flow_counter_in, in, opcode,
104 MLX5_CMD_OP_ALLOC_FLOW_COUNTER);
105 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128);
106 dcs->obj = mlx5_glue->devx_obj_create(ctx, in,
107 sizeof(in), out, sizeof(out));
109 DRV_LOG(ERR, "Can't allocate counters - error %d", errno);
114 dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id);
119 * Query flow counters values.
122 * devx object that was obtained from mlx5_devx_cmd_fc_alloc.
124 * Whether hardware should clear the counters after the query or not.
125 * @param[in] n_counters
126 * 0 in case of 1 counter to read, otherwise the counter number to read.
128 * The number of packets that matched the flow.
130 * The number of bytes that matched the flow.
132 * The mkey key for batch query.
134 * The address in the mkey range for batch query.
136 * The completion object for asynchronous batch query.
138 * The ID to be returned in the asynchronous batch query response.
141 * 0 on success, a negative value otherwise.
144 mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs,
145 int clear, uint32_t n_counters,
146 uint64_t *pkts, uint64_t *bytes,
147 uint32_t mkey, void *addr,
151 int out_len = MLX5_ST_SZ_BYTES(query_flow_counter_out) +
152 MLX5_ST_SZ_BYTES(traffic_counter);
153 uint32_t out[out_len];
154 uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0};
158 MLX5_SET(query_flow_counter_in, in, opcode,
159 MLX5_CMD_OP_QUERY_FLOW_COUNTER);
160 MLX5_SET(query_flow_counter_in, in, op_mod, 0);
161 MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id);
162 MLX5_SET(query_flow_counter_in, in, clear, !!clear);
165 MLX5_SET(query_flow_counter_in, in, num_of_counters,
167 MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1);
168 MLX5_SET(query_flow_counter_in, in, mkey, mkey);
169 MLX5_SET64(query_flow_counter_in, in, address,
170 (uint64_t)(uintptr_t)addr);
173 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out,
176 rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in),
180 DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc);
185 stats = MLX5_ADDR_OF(query_flow_counter_out,
186 out, flow_statistics);
187 *pkts = MLX5_GET64(traffic_counter, stats, packets);
188 *bytes = MLX5_GET64(traffic_counter, stats, octets);
197 * Context returned from mlx5 open_device() glue function.
199 * Attributes of the requested mkey.
202 * Pointer to Devx mkey on success, a negative value otherwise and rte_errno
205 struct mlx5_devx_obj *
206 mlx5_devx_cmd_mkey_create(void *ctx,
207 struct mlx5_devx_mkey_attr *attr)
209 struct mlx5_klm *klm_array = attr->klm_array;
210 int klm_num = attr->klm_num;
211 int in_size_dw = MLX5_ST_SZ_DW(create_mkey_in) +
212 (klm_num ? RTE_ALIGN(klm_num, 4) : 0) * MLX5_ST_SZ_DW(klm);
213 uint32_t in[in_size_dw];
214 uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0};
216 struct mlx5_devx_obj *mkey = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mkey),
219 uint32_t translation_size;
225 memset(in, 0, in_size_dw * 4);
226 pgsize = rte_mem_page_size();
227 if (pgsize == (size_t)-1) {
229 DRV_LOG(ERR, "Failed to get page size");
233 MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY);
234 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
237 uint8_t *klm = (uint8_t *)MLX5_ADDR_OF(create_mkey_in, in,
239 translation_size = RTE_ALIGN(klm_num, 4);
240 for (i = 0; i < klm_num; i++) {
241 MLX5_SET(klm, klm, byte_count, klm_array[i].byte_count);
242 MLX5_SET(klm, klm, mkey, klm_array[i].mkey);
243 MLX5_SET64(klm, klm, address, klm_array[i].address);
244 klm += MLX5_ST_SZ_BYTES(klm);
246 for (; i < (int)translation_size; i++) {
247 MLX5_SET(klm, klm, mkey, 0x0);
248 MLX5_SET64(klm, klm, address, 0x0);
249 klm += MLX5_ST_SZ_BYTES(klm);
251 MLX5_SET(mkc, mkc, access_mode_1_0, attr->log_entity_size ?
252 MLX5_MKC_ACCESS_MODE_KLM_FBS :
253 MLX5_MKC_ACCESS_MODE_KLM);
254 MLX5_SET(mkc, mkc, log_page_size, attr->log_entity_size);
256 translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16;
257 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
258 MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize));
260 MLX5_SET(create_mkey_in, in, translations_octword_actual_size,
262 MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id);
263 MLX5_SET(create_mkey_in, in, pg_access, attr->pg_access);
264 MLX5_SET(mkc, mkc, lw, 0x1);
265 MLX5_SET(mkc, mkc, lr, 0x1);
266 if (attr->set_remote_rw) {
267 MLX5_SET(mkc, mkc, rw, 0x1);
268 MLX5_SET(mkc, mkc, rr, 0x1);
270 MLX5_SET(mkc, mkc, qpn, 0xffffff);
271 MLX5_SET(mkc, mkc, pd, attr->pd);
272 MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF);
273 MLX5_SET(mkc, mkc, umr_en, attr->umr_en);
274 MLX5_SET(mkc, mkc, translations_octword_size, translation_size);
275 MLX5_SET(mkc, mkc, relaxed_ordering_write,
276 attr->relaxed_ordering_write);
277 MLX5_SET(mkc, mkc, relaxed_ordering_read, attr->relaxed_ordering_read);
278 MLX5_SET64(mkc, mkc, start_addr, attr->addr);
279 MLX5_SET64(mkc, mkc, len, attr->size);
280 MLX5_SET(mkc, mkc, crypto_en, attr->crypto_en);
281 if (attr->crypto_en) {
282 MLX5_SET(mkc, mkc, bsf_en, attr->crypto_en);
283 MLX5_SET(mkc, mkc, bsf_octword_size, 4);
285 mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out,
288 DRV_LOG(ERR, "Can't create %sdirect mkey - error %d",
289 klm_num ? "an in" : "a ", errno);
294 mkey->id = MLX5_GET(create_mkey_out, out, mkey_index);
295 mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF);
300 * Get status of devx command response.
301 * Mainly used for asynchronous commands.
304 * The out response buffer.
307 * 0 on success, non-zero value otherwise.
310 mlx5_devx_get_out_command_status(void *out)
316 status = MLX5_GET(query_flow_counter_out, out, status);
318 int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome);
320 DRV_LOG(ERR, "Bad DevX status %x, syndrome = %x", status,
327 * Destroy any object allocated by a Devx API.
330 * Pointer to a general object.
333 * 0 on success, a negative value otherwise.
336 mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj)
342 ret = mlx5_glue->devx_obj_destroy(obj->obj);
348 * Query NIC vport context.
349 * Fills minimal inline attribute.
352 * ibv contexts returned from mlx5dv_open_device.
356 * Attributes device values.
359 * 0 on success, a negative value otherwise.
362 mlx5_devx_cmd_query_nic_vport_context(void *ctx,
364 struct mlx5_hca_attr *attr)
366 uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0};
367 uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0};
369 int status, syndrome, rc;
371 /* Query NIC vport context to determine inline mode. */
372 MLX5_SET(query_nic_vport_context_in, in, opcode,
373 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT);
374 MLX5_SET(query_nic_vport_context_in, in, vport_number, vport);
376 MLX5_SET(query_nic_vport_context_in, in, other_vport, 1);
377 rc = mlx5_glue->devx_general_cmd(ctx,
382 status = MLX5_GET(query_nic_vport_context_out, out, status);
383 syndrome = MLX5_GET(query_nic_vport_context_out, out, syndrome);
385 DRV_LOG(DEBUG, "Failed to query NIC vport context, "
386 "status %x, syndrome = %x", status, syndrome);
389 vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out,
391 attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx,
392 min_wqe_inline_mode);
395 rc = (rc > 0) ? -rc : rc;
400 * Query NIC vDPA attributes.
403 * Context returned from mlx5 open_device() glue function.
404 * @param[out] vdpa_attr
405 * vDPA Attributes structure to fill.
408 mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx,
409 struct mlx5_hca_vdpa_attr *vdpa_attr)
411 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0};
412 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0};
413 void *hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
414 int status, syndrome, rc;
416 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
417 MLX5_SET(query_hca_cap_in, in, op_mod,
418 MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION |
419 MLX5_HCA_CAP_OPMOD_GET_CUR);
420 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
421 status = MLX5_GET(query_hca_cap_out, out, status);
422 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
424 RTE_LOG(DEBUG, PMD, "Failed to query devx VDPA capabilities,"
425 " status %x, syndrome = %x", status, syndrome);
426 vdpa_attr->valid = 0;
428 vdpa_attr->valid = 1;
429 vdpa_attr->desc_tunnel_offload_type =
430 MLX5_GET(virtio_emulation_cap, hcattr,
431 desc_tunnel_offload_type);
432 vdpa_attr->eth_frame_offload_type =
433 MLX5_GET(virtio_emulation_cap, hcattr,
434 eth_frame_offload_type);
435 vdpa_attr->virtio_version_1_0 =
436 MLX5_GET(virtio_emulation_cap, hcattr,
438 vdpa_attr->tso_ipv4 = MLX5_GET(virtio_emulation_cap, hcattr,
440 vdpa_attr->tso_ipv6 = MLX5_GET(virtio_emulation_cap, hcattr,
442 vdpa_attr->tx_csum = MLX5_GET(virtio_emulation_cap, hcattr,
444 vdpa_attr->rx_csum = MLX5_GET(virtio_emulation_cap, hcattr,
446 vdpa_attr->event_mode = MLX5_GET(virtio_emulation_cap, hcattr,
448 vdpa_attr->virtio_queue_type =
449 MLX5_GET(virtio_emulation_cap, hcattr,
451 vdpa_attr->log_doorbell_stride =
452 MLX5_GET(virtio_emulation_cap, hcattr,
453 log_doorbell_stride);
454 vdpa_attr->log_doorbell_bar_size =
455 MLX5_GET(virtio_emulation_cap, hcattr,
456 log_doorbell_bar_size);
457 vdpa_attr->doorbell_bar_offset =
458 MLX5_GET64(virtio_emulation_cap, hcattr,
459 doorbell_bar_offset);
460 vdpa_attr->max_num_virtio_queues =
461 MLX5_GET(virtio_emulation_cap, hcattr,
462 max_num_virtio_queues);
463 vdpa_attr->umems[0].a = MLX5_GET(virtio_emulation_cap, hcattr,
464 umem_1_buffer_param_a);
465 vdpa_attr->umems[0].b = MLX5_GET(virtio_emulation_cap, hcattr,
466 umem_1_buffer_param_b);
467 vdpa_attr->umems[1].a = MLX5_GET(virtio_emulation_cap, hcattr,
468 umem_2_buffer_param_a);
469 vdpa_attr->umems[1].b = MLX5_GET(virtio_emulation_cap, hcattr,
470 umem_2_buffer_param_b);
471 vdpa_attr->umems[2].a = MLX5_GET(virtio_emulation_cap, hcattr,
472 umem_3_buffer_param_a);
473 vdpa_attr->umems[2].b = MLX5_GET(virtio_emulation_cap, hcattr,
474 umem_3_buffer_param_b);
479 mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj,
480 uint32_t ids[], uint32_t num)
482 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
483 uint32_t out[MLX5_ST_SZ_DW(create_flex_parser_out)] = {0};
484 void *hdr = MLX5_ADDR_OF(create_flex_parser_out, in, hdr);
485 void *flex = MLX5_ADDR_OF(create_flex_parser_out, out, flex);
486 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table);
491 if (num > MLX5_GRAPH_NODE_SAMPLE_NUM) {
493 DRV_LOG(ERR, "Too many sample IDs to be fetched.");
496 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
497 MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
498 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
499 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH);
500 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, flex_obj->id);
501 ret = mlx5_glue->devx_obj_query(flex_obj->obj, in, sizeof(in),
505 DRV_LOG(ERR, "Failed to query sample IDs with object %p.",
509 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) {
510 void *s_off = (void *)((char *)sample + i *
511 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample));
514 en = MLX5_GET(parse_graph_flow_match_sample, s_off,
515 flow_match_sample_en);
518 ids[idx++] = MLX5_GET(parse_graph_flow_match_sample, s_off,
519 flow_match_sample_field_id);
523 DRV_LOG(ERR, "Number of sample IDs are not as expected.");
530 struct mlx5_devx_obj *
531 mlx5_devx_cmd_create_flex_parser(void *ctx,
532 struct mlx5_devx_graph_node_attr *data)
534 uint32_t in[MLX5_ST_SZ_DW(create_flex_parser_in)] = {0};
535 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
536 void *hdr = MLX5_ADDR_OF(create_flex_parser_in, in, hdr);
537 void *flex = MLX5_ADDR_OF(create_flex_parser_in, in, flex);
538 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table);
539 void *in_arc = MLX5_ADDR_OF(parse_graph_flex, flex, input_arc);
540 void *out_arc = MLX5_ADDR_OF(parse_graph_flex, flex, output_arc);
541 struct mlx5_devx_obj *parse_flex_obj = mlx5_malloc
542 (MLX5_MEM_ZERO, sizeof(*parse_flex_obj), 0, SOCKET_ID_ANY);
545 if (!parse_flex_obj) {
546 DRV_LOG(ERR, "Failed to allocate flex parser data.");
550 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
551 MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
552 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
553 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH);
554 MLX5_SET(parse_graph_flex, flex, header_length_mode,
555 data->header_length_mode);
556 MLX5_SET(parse_graph_flex, flex, header_length_base_value,
557 data->header_length_base_value);
558 MLX5_SET(parse_graph_flex, flex, header_length_field_offset,
559 data->header_length_field_offset);
560 MLX5_SET(parse_graph_flex, flex, header_length_field_shift,
561 data->header_length_field_shift);
562 MLX5_SET(parse_graph_flex, flex, header_length_field_mask,
563 data->header_length_field_mask);
564 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) {
565 struct mlx5_devx_match_sample_attr *s = &data->sample[i];
566 void *s_off = (void *)((char *)sample + i *
567 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample));
569 if (!s->flow_match_sample_en)
571 MLX5_SET(parse_graph_flow_match_sample, s_off,
572 flow_match_sample_en, !!s->flow_match_sample_en);
573 MLX5_SET(parse_graph_flow_match_sample, s_off,
574 flow_match_sample_field_offset,
575 s->flow_match_sample_field_offset);
576 MLX5_SET(parse_graph_flow_match_sample, s_off,
577 flow_match_sample_offset_mode,
578 s->flow_match_sample_offset_mode);
579 MLX5_SET(parse_graph_flow_match_sample, s_off,
580 flow_match_sample_field_offset_mask,
581 s->flow_match_sample_field_offset_mask);
582 MLX5_SET(parse_graph_flow_match_sample, s_off,
583 flow_match_sample_field_offset_shift,
584 s->flow_match_sample_field_offset_shift);
585 MLX5_SET(parse_graph_flow_match_sample, s_off,
586 flow_match_sample_field_base_offset,
587 s->flow_match_sample_field_base_offset);
588 MLX5_SET(parse_graph_flow_match_sample, s_off,
589 flow_match_sample_tunnel_mode,
590 s->flow_match_sample_tunnel_mode);
592 for (i = 0; i < MLX5_GRAPH_NODE_ARC_NUM; i++) {
593 struct mlx5_devx_graph_arc_attr *ia = &data->in[i];
594 struct mlx5_devx_graph_arc_attr *oa = &data->out[i];
595 void *in_off = (void *)((char *)in_arc + i *
596 MLX5_ST_SZ_BYTES(parse_graph_arc));
597 void *out_off = (void *)((char *)out_arc + i *
598 MLX5_ST_SZ_BYTES(parse_graph_arc));
600 if (ia->arc_parse_graph_node != 0) {
601 MLX5_SET(parse_graph_arc, in_off,
602 compare_condition_value,
603 ia->compare_condition_value);
604 MLX5_SET(parse_graph_arc, in_off, start_inner_tunnel,
605 ia->start_inner_tunnel);
606 MLX5_SET(parse_graph_arc, in_off, arc_parse_graph_node,
607 ia->arc_parse_graph_node);
608 MLX5_SET(parse_graph_arc, in_off,
609 parse_graph_node_handle,
610 ia->parse_graph_node_handle);
612 if (oa->arc_parse_graph_node != 0) {
613 MLX5_SET(parse_graph_arc, out_off,
614 compare_condition_value,
615 oa->compare_condition_value);
616 MLX5_SET(parse_graph_arc, out_off, start_inner_tunnel,
617 oa->start_inner_tunnel);
618 MLX5_SET(parse_graph_arc, out_off, arc_parse_graph_node,
619 oa->arc_parse_graph_node);
620 MLX5_SET(parse_graph_arc, out_off,
621 parse_graph_node_handle,
622 oa->parse_graph_node_handle);
625 parse_flex_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
627 if (!parse_flex_obj->obj) {
629 DRV_LOG(ERR, "Failed to create FLEX PARSE GRAPH object "
631 mlx5_free(parse_flex_obj);
634 parse_flex_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
635 return parse_flex_obj;
639 * Query HCA attributes.
640 * Using those attributes we can check on run time if the device
641 * is having the required capabilities.
644 * Context returned from mlx5 open_device() glue function.
646 * Attributes device values.
649 * 0 on success, a negative value otherwise.
652 mlx5_devx_cmd_query_hca_attr(void *ctx,
653 struct mlx5_hca_attr *attr)
655 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0};
656 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0};
658 int status, syndrome, rc, i;
659 uint64_t general_obj_types_supported = 0;
661 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
662 MLX5_SET(query_hca_cap_in, in, op_mod,
663 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE |
664 MLX5_HCA_CAP_OPMOD_GET_CUR);
666 rc = mlx5_glue->devx_general_cmd(ctx,
667 in, sizeof(in), out, sizeof(out));
670 status = MLX5_GET(query_hca_cap_out, out, status);
671 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
673 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, "
674 "status %x, syndrome = %x", status, syndrome);
677 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
678 attr->flow_counter_bulk_alloc_bitmap =
679 MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc);
680 attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr,
682 attr->log_max_rqt_size = MLX5_GET(cmd_hca_cap, hcattr,
684 attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager);
685 attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin);
686 attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr,
687 log_max_hairpin_queues);
688 attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr,
689 log_max_hairpin_wq_data_sz);
690 attr->log_max_hairpin_num_packets = MLX5_GET
691 (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz);
692 attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id);
693 attr->relaxed_ordering_write = MLX5_GET(cmd_hca_cap, hcattr,
694 relaxed_ordering_write);
695 attr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr,
696 relaxed_ordering_read);
697 attr->access_register_user = MLX5_GET(cmd_hca_cap, hcattr,
698 access_register_user);
699 attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr,
701 attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt);
702 attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr,
703 flex_parser_protocols);
704 attr->max_geneve_tlv_options = MLX5_GET(cmd_hca_cap, hcattr,
705 max_geneve_tlv_options);
706 attr->max_geneve_tlv_option_data_len = MLX5_GET(cmd_hca_cap, hcattr,
707 max_geneve_tlv_option_data_len);
708 attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos);
709 attr->qos.flow_meter_aso_sup = !!(MLX5_GET64(cmd_hca_cap, hcattr,
711 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO);
712 attr->vdpa.valid = !!(MLX5_GET64(cmd_hca_cap, hcattr,
714 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q);
715 attr->vdpa.queue_counters_valid = !!(MLX5_GET64(cmd_hca_cap, hcattr,
717 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS);
718 attr->parse_graph_flex_node = !!(MLX5_GET64(cmd_hca_cap, hcattr,
720 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE);
721 attr->wqe_index_ignore = MLX5_GET(cmd_hca_cap, hcattr,
722 wqe_index_ignore_cap);
723 attr->cross_channel = MLX5_GET(cmd_hca_cap, hcattr, cd);
724 attr->non_wire_sq = MLX5_GET(cmd_hca_cap, hcattr, non_wire_sq);
725 attr->log_max_static_sq_wq = MLX5_GET(cmd_hca_cap, hcattr,
726 log_max_static_sq_wq);
727 attr->num_lag_ports = MLX5_GET(cmd_hca_cap, hcattr, num_lag_ports);
728 attr->dev_freq_khz = MLX5_GET(cmd_hca_cap, hcattr,
729 device_frequency_khz);
730 attr->scatter_fcs_w_decap_disable =
731 MLX5_GET(cmd_hca_cap, hcattr, scatter_fcs_w_decap_disable);
732 attr->roce = MLX5_GET(cmd_hca_cap, hcattr, roce);
733 attr->rq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, rq_ts_format);
734 attr->sq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, sq_ts_format);
735 attr->regex = MLX5_GET(cmd_hca_cap, hcattr, regexp);
736 attr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr,
737 regexp_num_of_engines);
738 /* Read the general_obj_types bitmap and extract the relevant bits. */
739 general_obj_types_supported = MLX5_GET64(cmd_hca_cap, hcattr,
741 attr->vdpa.valid = !!(general_obj_types_supported &
742 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q);
743 attr->vdpa.queue_counters_valid =
744 !!(general_obj_types_supported &
745 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS);
746 attr->parse_graph_flex_node =
747 !!(general_obj_types_supported &
748 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE);
749 attr->flow_hit_aso = !!(general_obj_types_supported &
750 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO);
751 attr->geneve_tlv_opt = !!(general_obj_types_supported &
752 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT);
753 attr->dek = !!(general_obj_types_supported &
754 MLX5_GENERAL_OBJ_TYPES_CAP_DEK);
755 attr->import_kek = !!(general_obj_types_supported &
756 MLX5_GENERAL_OBJ_TYPES_CAP_IMPORT_KEK);
757 attr->crypto_login = !!(general_obj_types_supported &
758 MLX5_GENERAL_OBJ_TYPES_CAP_CRYPTO_LOGIN);
759 /* Add reading of other GENERAL_OBJ_TYPES_CAP bits above this line. */
760 attr->log_max_cq = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq);
761 attr->log_max_qp = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp);
762 attr->log_max_cq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq_sz);
763 attr->log_max_qp_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp_sz);
764 attr->log_max_mrw_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_mrw_sz);
765 attr->log_max_pd = MLX5_GET(cmd_hca_cap, hcattr, log_max_pd);
766 attr->log_max_srq = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq);
767 attr->log_max_srq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq_sz);
768 attr->reg_c_preserve =
769 MLX5_GET(cmd_hca_cap, hcattr, reg_c_preserve);
770 attr->mmo_dma_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo);
771 attr->mmo_compress_en = MLX5_GET(cmd_hca_cap, hcattr, compress);
772 attr->mmo_decompress_en = MLX5_GET(cmd_hca_cap, hcattr, decompress);
773 attr->compress_min_block_size = MLX5_GET(cmd_hca_cap, hcattr,
774 compress_min_block_size);
775 attr->log_max_mmo_dma = MLX5_GET(cmd_hca_cap, hcattr, log_dma_mmo_size);
776 attr->log_max_mmo_compress = MLX5_GET(cmd_hca_cap, hcattr,
777 log_compress_mmo_size);
778 attr->log_max_mmo_decompress = MLX5_GET(cmd_hca_cap, hcattr,
779 log_decompress_mmo_size);
780 attr->cqe_compression = MLX5_GET(cmd_hca_cap, hcattr, cqe_compression);
781 attr->mini_cqe_resp_flow_tag = MLX5_GET(cmd_hca_cap, hcattr,
782 mini_cqe_resp_flow_tag);
783 attr->mini_cqe_resp_l3_l4_tag = MLX5_GET(cmd_hca_cap, hcattr,
784 mini_cqe_resp_l3_l4_tag);
785 attr->umr_indirect_mkey_disabled =
786 MLX5_GET(cmd_hca_cap, hcattr, umr_indirect_mkey_disabled);
787 attr->umr_modify_entity_size_disabled =
788 MLX5_GET(cmd_hca_cap, hcattr, umr_modify_entity_size_disabled);
789 attr->crypto = MLX5_GET(cmd_hca_cap, hcattr, crypto);
791 attr->aes_xts = MLX5_GET(cmd_hca_cap, hcattr, aes_xts);
793 MLX5_SET(query_hca_cap_in, in, op_mod,
794 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP |
795 MLX5_HCA_CAP_OPMOD_GET_CUR);
796 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in),
801 DRV_LOG(DEBUG, "Failed to query devx QOS capabilities,"
802 " status %x, syndrome = %x", status, syndrome);
805 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
806 attr->qos.flow_meter_old =
807 MLX5_GET(qos_cap, hcattr, flow_meter_old);
808 attr->qos.log_max_flow_meter =
809 MLX5_GET(qos_cap, hcattr, log_max_flow_meter);
810 attr->qos.flow_meter_reg_c_ids =
811 MLX5_GET(qos_cap, hcattr, flow_meter_reg_id);
812 attr->qos.flow_meter =
813 MLX5_GET(qos_cap, hcattr, flow_meter);
814 attr->qos.packet_pacing =
815 MLX5_GET(qos_cap, hcattr, packet_pacing);
816 attr->qos.wqe_rate_pp =
817 MLX5_GET(qos_cap, hcattr, wqe_rate_pp);
818 if (attr->qos.flow_meter_aso_sup) {
819 attr->qos.log_meter_aso_granularity =
820 MLX5_GET(qos_cap, hcattr,
821 log_meter_aso_granularity);
822 attr->qos.log_meter_aso_max_alloc =
823 MLX5_GET(qos_cap, hcattr,
824 log_meter_aso_max_alloc);
825 attr->qos.log_max_num_meter_aso =
826 MLX5_GET(qos_cap, hcattr,
827 log_max_num_meter_aso);
830 if (attr->vdpa.valid)
831 mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa);
832 if (!attr->eth_net_offloads)
835 /* Query Flow Sampler Capability From FLow Table Properties Layout. */
836 memset(in, 0, sizeof(in));
837 memset(out, 0, sizeof(out));
838 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
839 MLX5_SET(query_hca_cap_in, in, op_mod,
840 MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE |
841 MLX5_HCA_CAP_OPMOD_GET_CUR);
843 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
846 status = MLX5_GET(query_hca_cap_out, out, status);
847 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
849 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, "
850 "status %x, syndrome = %x", status, syndrome);
851 attr->log_max_ft_sampler_num = 0;
854 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
855 attr->log_max_ft_sampler_num =
856 MLX5_GET(flow_table_nic_cap,
857 hcattr, flow_table_properties.log_max_ft_sampler_num);
859 /* Query HCA offloads for Ethernet protocol. */
860 memset(in, 0, sizeof(in));
861 memset(out, 0, sizeof(out));
862 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
863 MLX5_SET(query_hca_cap_in, in, op_mod,
864 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS |
865 MLX5_HCA_CAP_OPMOD_GET_CUR);
867 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
869 attr->eth_net_offloads = 0;
872 status = MLX5_GET(query_hca_cap_out, out, status);
873 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
875 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, "
876 "status %x, syndrome = %x", status, syndrome);
877 attr->eth_net_offloads = 0;
880 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
881 attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps,
882 hcattr, wqe_vlan_insert);
883 attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr,
885 attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps,
886 hcattr, tunnel_lro_gre);
887 attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps,
888 hcattr, tunnel_lro_vxlan);
889 attr->lro_max_msg_sz_mode = MLX5_GET
890 (per_protocol_networking_offload_caps,
891 hcattr, lro_max_msg_sz_mode);
892 for (i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) {
893 attr->lro_timer_supported_periods[i] =
894 MLX5_GET(per_protocol_networking_offload_caps, hcattr,
895 lro_timer_supported_periods[i]);
897 attr->lro_min_mss_size = MLX5_GET(per_protocol_networking_offload_caps,
898 hcattr, lro_min_mss_size);
899 attr->tunnel_stateless_geneve_rx =
900 MLX5_GET(per_protocol_networking_offload_caps,
901 hcattr, tunnel_stateless_geneve_rx);
902 attr->geneve_max_opt_len =
903 MLX5_GET(per_protocol_networking_offload_caps,
904 hcattr, max_geneve_opt_len);
905 attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps,
906 hcattr, wqe_inline_mode);
907 attr->tunnel_stateless_gtp = MLX5_GET
908 (per_protocol_networking_offload_caps,
909 hcattr, tunnel_stateless_gtp);
910 attr->rss_ind_tbl_cap = MLX5_GET
911 (per_protocol_networking_offload_caps,
912 hcattr, rss_ind_tbl_cap);
913 /* Query HCA attribute for ROCE. */
915 memset(in, 0, sizeof(in));
916 memset(out, 0, sizeof(out));
917 MLX5_SET(query_hca_cap_in, in, opcode,
918 MLX5_CMD_OP_QUERY_HCA_CAP);
919 MLX5_SET(query_hca_cap_in, in, op_mod,
920 MLX5_GET_HCA_CAP_OP_MOD_ROCE |
921 MLX5_HCA_CAP_OPMOD_GET_CUR);
922 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in),
926 status = MLX5_GET(query_hca_cap_out, out, status);
927 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
930 "Failed to query devx HCA ROCE capabilities, "
931 "status %x, syndrome = %x", status, syndrome);
934 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
935 attr->qp_ts_format = MLX5_GET(roce_caps, hcattr, qp_ts_format);
937 if (attr->eth_virt &&
938 attr->wqe_inline_mode == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT) {
939 rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr);
947 rc = (rc > 0) ? -rc : rc;
952 * Query TIS transport domain from QP verbs object using DevX API.
955 * Pointer to verbs QP returned by ibv_create_qp .
957 * TIS number of TIS to query.
959 * Pointer to TIS transport domain variable, to be set by the routine.
962 * 0 on success, a negative value otherwise.
965 mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num,
968 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
969 uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0};
970 uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0};
974 MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS);
975 MLX5_SET(query_tis_in, in, tisn, tis_num);
976 rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out));
978 DRV_LOG(ERR, "Failed to query QP using DevX");
981 tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context);
982 *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain);
993 * Fill WQ data for DevX API command.
994 * Utility function for use when creating DevX objects containing a WQ.
997 * Pointer to WQ context to fill with data.
998 * @param [in] wq_attr
999 * Pointer to WQ attributes structure to fill in WQ context.
1002 devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr)
1004 MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type);
1005 MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature);
1006 MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode);
1007 MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave);
1008 MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge);
1009 MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size);
1010 MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset);
1011 MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm);
1012 MLX5_SET(wq, wq_ctx, pd, wq_attr->pd);
1013 MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page);
1014 MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr);
1015 MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter);
1016 MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter);
1017 MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride);
1018 if (wq_attr->log_wq_pg_sz > MLX5_ADAPTER_PAGE_SHIFT)
1019 MLX5_SET(wq, wq_ctx, log_wq_pg_sz,
1020 wq_attr->log_wq_pg_sz - MLX5_ADAPTER_PAGE_SHIFT);
1021 MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz);
1022 MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid);
1023 MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid);
1024 MLX5_SET(wq, wq_ctx, log_hairpin_num_packets,
1025 wq_attr->log_hairpin_num_packets);
1026 MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz);
1027 MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides,
1028 wq_attr->single_wqe_log_num_of_strides);
1029 MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en);
1030 MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes,
1031 wq_attr->single_stride_log_num_of_bytes);
1032 MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id);
1033 MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id);
1034 MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset);
1038 * Create RQ using DevX API.
1041 * Context returned from mlx5 open_device() glue function.
1042 * @param [in] rq_attr
1043 * Pointer to create RQ attributes structure.
1044 * @param [in] socket
1045 * CPU socket ID for allocations.
1048 * The DevX object created, NULL otherwise and rte_errno is set.
1050 struct mlx5_devx_obj *
1051 mlx5_devx_cmd_create_rq(void *ctx,
1052 struct mlx5_devx_create_rq_attr *rq_attr,
1055 uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0};
1056 uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0};
1057 void *rq_ctx, *wq_ctx;
1058 struct mlx5_devx_wq_attr *wq_attr;
1059 struct mlx5_devx_obj *rq = NULL;
1061 rq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rq), 0, socket);
1063 DRV_LOG(ERR, "Failed to allocate RQ data");
1067 MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ);
1068 rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx);
1069 MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky);
1070 MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en);
1071 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);
1072 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);
1073 MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type);
1074 MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
1075 MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en);
1076 MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin);
1077 MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index);
1078 MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn);
1079 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
1080 MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn);
1081 MLX5_SET(sqc, rq_ctx, ts_format, rq_attr->ts_format);
1082 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);
1083 wq_attr = &rq_attr->wq_attr;
1084 devx_cmd_fill_wq_data(wq_ctx, wq_attr);
1085 rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1088 DRV_LOG(ERR, "Failed to create RQ using DevX");
1093 rq->id = MLX5_GET(create_rq_out, out, rqn);
1098 * Modify RQ using DevX API.
1101 * Pointer to RQ object structure.
1102 * @param [in] rq_attr
1103 * Pointer to modify RQ attributes structure.
1106 * 0 on success, a negative errno value otherwise and rte_errno is set.
1109 mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,
1110 struct mlx5_devx_modify_rq_attr *rq_attr)
1112 uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0};
1113 uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0};
1114 void *rq_ctx, *wq_ctx;
1117 MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ);
1118 MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state);
1119 MLX5_SET(modify_rq_in, in, rqn, rq->id);
1120 MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask);
1121 rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1122 MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
1123 if (rq_attr->modify_bitmask &
1124 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS)
1125 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);
1126 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD)
1127 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);
1128 if (rq_attr->modify_bitmask &
1129 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID)
1130 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
1131 MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq);
1132 MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca);
1133 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) {
1134 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);
1135 MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm);
1137 ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in),
1140 DRV_LOG(ERR, "Failed to modify RQ using DevX");
1148 * Create TIR using DevX API.
1151 * Context returned from mlx5 open_device() glue function.
1152 * @param [in] tir_attr
1153 * Pointer to TIR attributes structure.
1156 * The DevX object created, NULL otherwise and rte_errno is set.
1158 struct mlx5_devx_obj *
1159 mlx5_devx_cmd_create_tir(void *ctx,
1160 struct mlx5_devx_tir_attr *tir_attr)
1162 uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
1163 uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0};
1164 void *tir_ctx, *outer, *inner, *rss_key;
1165 struct mlx5_devx_obj *tir = NULL;
1167 tir = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tir), 0, SOCKET_ID_ANY);
1169 DRV_LOG(ERR, "Failed to allocate TIR data");
1173 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR);
1174 tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx);
1175 MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type);
1176 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs,
1177 tir_attr->lro_timeout_period_usecs);
1178 MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask);
1179 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz);
1180 MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn);
1181 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric);
1182 MLX5_SET(tirc, tir_ctx, tunneled_offload_en,
1183 tir_attr->tunneled_offload_en);
1184 MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table);
1185 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn);
1186 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block);
1187 MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain);
1188 rss_key = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_toeplitz_key);
1189 memcpy(rss_key, tir_attr->rx_hash_toeplitz_key, MLX5_RSS_HASH_KEY_LEN);
1190 outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer);
1191 MLX5_SET(rx_hash_field_select, outer, l3_prot_type,
1192 tir_attr->rx_hash_field_selector_outer.l3_prot_type);
1193 MLX5_SET(rx_hash_field_select, outer, l4_prot_type,
1194 tir_attr->rx_hash_field_selector_outer.l4_prot_type);
1195 MLX5_SET(rx_hash_field_select, outer, selected_fields,
1196 tir_attr->rx_hash_field_selector_outer.selected_fields);
1197 inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner);
1198 MLX5_SET(rx_hash_field_select, inner, l3_prot_type,
1199 tir_attr->rx_hash_field_selector_inner.l3_prot_type);
1200 MLX5_SET(rx_hash_field_select, inner, l4_prot_type,
1201 tir_attr->rx_hash_field_selector_inner.l4_prot_type);
1202 MLX5_SET(rx_hash_field_select, inner, selected_fields,
1203 tir_attr->rx_hash_field_selector_inner.selected_fields);
1204 tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1207 DRV_LOG(ERR, "Failed to create TIR using DevX");
1212 tir->id = MLX5_GET(create_tir_out, out, tirn);
1217 * Modify TIR using DevX API.
1220 * Pointer to TIR DevX object structure.
1221 * @param [in] modify_tir_attr
1222 * Pointer to TIR modification attributes structure.
1225 * 0 on success, a negative errno value otherwise and rte_errno is set.
1228 mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir,
1229 struct mlx5_devx_modify_tir_attr *modify_tir_attr)
1231 struct mlx5_devx_tir_attr *tir_attr = &modify_tir_attr->tir;
1232 uint32_t in[MLX5_ST_SZ_DW(modify_tir_in)] = {0};
1233 uint32_t out[MLX5_ST_SZ_DW(modify_tir_out)] = {0};
1237 MLX5_SET(modify_tir_in, in, opcode, MLX5_CMD_OP_MODIFY_TIR);
1238 MLX5_SET(modify_tir_in, in, tirn, modify_tir_attr->tirn);
1239 MLX5_SET64(modify_tir_in, in, modify_bitmask,
1240 modify_tir_attr->modify_bitmask);
1241 tir_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1242 if (modify_tir_attr->modify_bitmask &
1243 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO) {
1244 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs,
1245 tir_attr->lro_timeout_period_usecs);
1246 MLX5_SET(tirc, tir_ctx, lro_enable_mask,
1247 tir_attr->lro_enable_mask);
1248 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz,
1249 tir_attr->lro_max_msg_sz);
1251 if (modify_tir_attr->modify_bitmask &
1252 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE)
1253 MLX5_SET(tirc, tir_ctx, indirect_table,
1254 tir_attr->indirect_table);
1255 if (modify_tir_attr->modify_bitmask &
1256 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH) {
1258 void *outer, *inner;
1260 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric,
1261 tir_attr->rx_hash_symmetric);
1262 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn);
1263 for (i = 0; i < 10; i++) {
1264 MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i],
1265 tir_attr->rx_hash_toeplitz_key[i]);
1267 outer = MLX5_ADDR_OF(tirc, tir_ctx,
1268 rx_hash_field_selector_outer);
1269 MLX5_SET(rx_hash_field_select, outer, l3_prot_type,
1270 tir_attr->rx_hash_field_selector_outer.l3_prot_type);
1271 MLX5_SET(rx_hash_field_select, outer, l4_prot_type,
1272 tir_attr->rx_hash_field_selector_outer.l4_prot_type);
1274 (rx_hash_field_select, outer, selected_fields,
1275 tir_attr->rx_hash_field_selector_outer.selected_fields);
1276 inner = MLX5_ADDR_OF(tirc, tir_ctx,
1277 rx_hash_field_selector_inner);
1278 MLX5_SET(rx_hash_field_select, inner, l3_prot_type,
1279 tir_attr->rx_hash_field_selector_inner.l3_prot_type);
1280 MLX5_SET(rx_hash_field_select, inner, l4_prot_type,
1281 tir_attr->rx_hash_field_selector_inner.l4_prot_type);
1283 (rx_hash_field_select, inner, selected_fields,
1284 tir_attr->rx_hash_field_selector_inner.selected_fields);
1286 if (modify_tir_attr->modify_bitmask &
1287 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN) {
1288 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block);
1290 ret = mlx5_glue->devx_obj_modify(tir->obj, in, sizeof(in),
1293 DRV_LOG(ERR, "Failed to modify TIR using DevX");
1301 * Create RQT using DevX API.
1304 * Context returned from mlx5 open_device() glue function.
1305 * @param [in] rqt_attr
1306 * Pointer to RQT attributes structure.
1309 * The DevX object created, NULL otherwise and rte_errno is set.
1311 struct mlx5_devx_obj *
1312 mlx5_devx_cmd_create_rqt(void *ctx,
1313 struct mlx5_devx_rqt_attr *rqt_attr)
1315 uint32_t *in = NULL;
1316 uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) +
1317 rqt_attr->rqt_actual_size * sizeof(uint32_t);
1318 uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0};
1320 struct mlx5_devx_obj *rqt = NULL;
1323 in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY);
1325 DRV_LOG(ERR, "Failed to allocate RQT IN data");
1329 rqt = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt), 0, SOCKET_ID_ANY);
1331 DRV_LOG(ERR, "Failed to allocate RQT data");
1336 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
1337 rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1338 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type);
1339 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size);
1340 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size);
1341 for (i = 0; i < rqt_attr->rqt_actual_size; i++)
1342 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]);
1343 rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out));
1346 DRV_LOG(ERR, "Failed to create RQT using DevX");
1351 rqt->id = MLX5_GET(create_rqt_out, out, rqtn);
1356 * Modify RQT using DevX API.
1359 * Pointer to RQT DevX object structure.
1360 * @param [in] rqt_attr
1361 * Pointer to RQT attributes structure.
1364 * 0 on success, a negative errno value otherwise and rte_errno is set.
1367 mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt,
1368 struct mlx5_devx_rqt_attr *rqt_attr)
1370 uint32_t inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) +
1371 rqt_attr->rqt_actual_size * sizeof(uint32_t);
1372 uint32_t out[MLX5_ST_SZ_DW(modify_rqt_out)] = {0};
1373 uint32_t *in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY);
1379 DRV_LOG(ERR, "Failed to allocate RQT modify IN data.");
1383 MLX5_SET(modify_rqt_in, in, opcode, MLX5_CMD_OP_MODIFY_RQT);
1384 MLX5_SET(modify_rqt_in, in, rqtn, rqt->id);
1385 MLX5_SET64(modify_rqt_in, in, modify_bitmask, 0x1);
1386 rqt_ctx = MLX5_ADDR_OF(modify_rqt_in, in, rqt_context);
1387 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type);
1388 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size);
1389 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size);
1390 for (i = 0; i < rqt_attr->rqt_actual_size; i++)
1391 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]);
1392 ret = mlx5_glue->devx_obj_modify(rqt->obj, in, inlen, out, sizeof(out));
1395 DRV_LOG(ERR, "Failed to modify RQT using DevX.");
1403 * Create SQ using DevX API.
1406 * Context returned from mlx5 open_device() glue function.
1407 * @param [in] sq_attr
1408 * Pointer to SQ attributes structure.
1409 * @param [in] socket
1410 * CPU socket ID for allocations.
1413 * The DevX object created, NULL otherwise and rte_errno is set.
1415 struct mlx5_devx_obj *
1416 mlx5_devx_cmd_create_sq(void *ctx,
1417 struct mlx5_devx_create_sq_attr *sq_attr)
1419 uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0};
1420 uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0};
1423 struct mlx5_devx_wq_attr *wq_attr;
1424 struct mlx5_devx_obj *sq = NULL;
1426 sq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sq), 0, SOCKET_ID_ANY);
1428 DRV_LOG(ERR, "Failed to allocate SQ data");
1432 MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ);
1433 sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx);
1434 MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky);
1435 MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master);
1436 MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre);
1437 MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en);
1438 MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe,
1439 sq_attr->allow_multi_pkt_send_wqe);
1440 MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode,
1441 sq_attr->min_wqe_inline_mode);
1442 MLX5_SET(sqc, sq_ctx, state, sq_attr->state);
1443 MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr);
1444 MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp);
1445 MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin);
1446 MLX5_SET(sqc, sq_ctx, non_wire, sq_attr->non_wire);
1447 MLX5_SET(sqc, sq_ctx, static_sq_wq, sq_attr->static_sq_wq);
1448 MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index);
1449 MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn);
1450 MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index,
1451 sq_attr->packet_pacing_rate_limit_index);
1452 MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz);
1453 MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num);
1454 MLX5_SET(sqc, sq_ctx, ts_format, sq_attr->ts_format);
1455 wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq);
1456 wq_attr = &sq_attr->wq_attr;
1457 devx_cmd_fill_wq_data(wq_ctx, wq_attr);
1458 sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1461 DRV_LOG(ERR, "Failed to create SQ using DevX");
1466 sq->id = MLX5_GET(create_sq_out, out, sqn);
1471 * Modify SQ using DevX API.
1474 * Pointer to SQ object structure.
1475 * @param [in] sq_attr
1476 * Pointer to SQ attributes structure.
1479 * 0 on success, a negative errno value otherwise and rte_errno is set.
1482 mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq,
1483 struct mlx5_devx_modify_sq_attr *sq_attr)
1485 uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0};
1486 uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0};
1490 MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ);
1491 MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state);
1492 MLX5_SET(modify_sq_in, in, sqn, sq->id);
1493 sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1494 MLX5_SET(sqc, sq_ctx, state, sq_attr->state);
1495 MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq);
1496 MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca);
1497 ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in),
1500 DRV_LOG(ERR, "Failed to modify SQ using DevX");
1508 * Create TIS using DevX API.
1511 * Context returned from mlx5 open_device() glue function.
1512 * @param [in] tis_attr
1513 * Pointer to TIS attributes structure.
1516 * The DevX object created, NULL otherwise and rte_errno is set.
1518 struct mlx5_devx_obj *
1519 mlx5_devx_cmd_create_tis(void *ctx,
1520 struct mlx5_devx_tis_attr *tis_attr)
1522 uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
1523 uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0};
1524 struct mlx5_devx_obj *tis = NULL;
1527 tis = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tis), 0, SOCKET_ID_ANY);
1529 DRV_LOG(ERR, "Failed to allocate TIS object");
1533 MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS);
1534 tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx);
1535 MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity,
1536 tis_attr->strict_lag_tx_port_affinity);
1537 MLX5_SET(tisc, tis_ctx, lag_tx_port_affinity,
1538 tis_attr->lag_tx_port_affinity);
1539 MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio);
1540 MLX5_SET(tisc, tis_ctx, transport_domain,
1541 tis_attr->transport_domain);
1542 tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1545 DRV_LOG(ERR, "Failed to create TIS using DevX");
1550 tis->id = MLX5_GET(create_tis_out, out, tisn);
1555 * Create transport domain using DevX API.
1558 * Context returned from mlx5 open_device() glue function.
1560 * The DevX object created, NULL otherwise and rte_errno is set.
1562 struct mlx5_devx_obj *
1563 mlx5_devx_cmd_create_td(void *ctx)
1565 uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0};
1566 uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0};
1567 struct mlx5_devx_obj *td = NULL;
1569 td = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*td), 0, SOCKET_ID_ANY);
1571 DRV_LOG(ERR, "Failed to allocate TD object");
1575 MLX5_SET(alloc_transport_domain_in, in, opcode,
1576 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN);
1577 td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1580 DRV_LOG(ERR, "Failed to create TIS using DevX");
1585 td->id = MLX5_GET(alloc_transport_domain_out, out,
1591 * Dump all flows to file.
1593 * @param[in] fdb_domain
1595 * @param[in] rx_domain
1597 * @param[in] tx_domain
1600 * Pointer to file stream.
1603 * 0 on success, a nagative value otherwise.
1606 mlx5_devx_cmd_flow_dump(void *fdb_domain __rte_unused,
1607 void *rx_domain __rte_unused,
1608 void *tx_domain __rte_unused, FILE *file __rte_unused)
1612 #ifdef HAVE_MLX5_DR_FLOW_DUMP
1614 ret = mlx5_glue->dr_dump_domain(file, fdb_domain);
1618 MLX5_ASSERT(rx_domain);
1619 ret = mlx5_glue->dr_dump_domain(file, rx_domain);
1622 MLX5_ASSERT(tx_domain);
1623 ret = mlx5_glue->dr_dump_domain(file, tx_domain);
1631 mlx5_devx_cmd_flow_single_dump(void *rule_info __rte_unused,
1632 FILE *file __rte_unused)
1635 #ifdef HAVE_MLX5_DR_FLOW_DUMP_RULE
1637 ret = mlx5_glue->dr_dump_rule(file, rule_info);
1645 * Create CQ using DevX API.
1648 * Context returned from mlx5 open_device() glue function.
1650 * Pointer to CQ attributes structure.
1653 * The DevX object created, NULL otherwise and rte_errno is set.
1655 struct mlx5_devx_obj *
1656 mlx5_devx_cmd_create_cq(void *ctx, struct mlx5_devx_cq_attr *attr)
1658 uint32_t in[MLX5_ST_SZ_DW(create_cq_in)] = {0};
1659 uint32_t out[MLX5_ST_SZ_DW(create_cq_out)] = {0};
1660 struct mlx5_devx_obj *cq_obj = mlx5_malloc(MLX5_MEM_ZERO,
1663 void *cqctx = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1666 DRV_LOG(ERR, "Failed to allocate CQ object memory.");
1670 MLX5_SET(create_cq_in, in, opcode, MLX5_CMD_OP_CREATE_CQ);
1671 if (attr->db_umem_valid) {
1672 MLX5_SET(cqc, cqctx, dbr_umem_valid, attr->db_umem_valid);
1673 MLX5_SET(cqc, cqctx, dbr_umem_id, attr->db_umem_id);
1674 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_umem_offset);
1676 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_addr);
1678 MLX5_SET(cqc, cqctx, cqe_sz, (RTE_CACHE_LINE_SIZE == 128) ?
1679 MLX5_CQE_SIZE_128B : MLX5_CQE_SIZE_64B);
1680 MLX5_SET(cqc, cqctx, cc, attr->use_first_only);
1681 MLX5_SET(cqc, cqctx, oi, attr->overrun_ignore);
1682 MLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size);
1683 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT)
1684 MLX5_SET(cqc, cqctx, log_page_size,
1685 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT);
1686 MLX5_SET(cqc, cqctx, c_eqn, attr->eqn);
1687 MLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id);
1688 MLX5_SET(cqc, cqctx, cqe_comp_en, !!attr->cqe_comp_en);
1689 MLX5_SET(cqc, cqctx, mini_cqe_res_format, attr->mini_cqe_res_format);
1690 MLX5_SET(cqc, cqctx, mini_cqe_res_format_ext,
1691 attr->mini_cqe_res_format_ext);
1692 if (attr->q_umem_valid) {
1693 MLX5_SET(create_cq_in, in, cq_umem_valid, attr->q_umem_valid);
1694 MLX5_SET(create_cq_in, in, cq_umem_id, attr->q_umem_id);
1695 MLX5_SET64(create_cq_in, in, cq_umem_offset,
1696 attr->q_umem_offset);
1698 cq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
1702 DRV_LOG(ERR, "Failed to create CQ using DevX errno=%d.", errno);
1706 cq_obj->id = MLX5_GET(create_cq_out, out, cqn);
1711 * Create VIRTQ using DevX API.
1714 * Context returned from mlx5 open_device() glue function.
1716 * Pointer to VIRTQ attributes structure.
1719 * The DevX object created, NULL otherwise and rte_errno is set.
1721 struct mlx5_devx_obj *
1722 mlx5_devx_cmd_create_virtq(void *ctx,
1723 struct mlx5_devx_virtq_attr *attr)
1725 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0};
1726 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
1727 struct mlx5_devx_obj *virtq_obj = mlx5_malloc(MLX5_MEM_ZERO,
1730 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq);
1731 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr);
1732 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context);
1735 DRV_LOG(ERR, "Failed to allocate virtq data.");
1739 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
1740 MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
1741 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
1742 MLX5_GENERAL_OBJ_TYPE_VIRTQ);
1743 MLX5_SET16(virtio_net_q, virtq, hw_available_index,
1744 attr->hw_available_index);
1745 MLX5_SET16(virtio_net_q, virtq, hw_used_index, attr->hw_used_index);
1746 MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4);
1747 MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6);
1748 MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum);
1749 MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum);
1750 MLX5_SET16(virtio_q, virtctx, virtio_version_1_0,
1751 attr->virtio_version_1_0);
1752 MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode);
1753 MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id);
1754 MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr);
1755 MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr);
1756 MLX5_SET64(virtio_q, virtctx, available_addr, attr->available_addr);
1757 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index);
1758 MLX5_SET16(virtio_q, virtctx, queue_size, attr->q_size);
1759 MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey);
1760 MLX5_SET(virtio_q, virtctx, umem_1_id, attr->umems[0].id);
1761 MLX5_SET(virtio_q, virtctx, umem_1_size, attr->umems[0].size);
1762 MLX5_SET64(virtio_q, virtctx, umem_1_offset, attr->umems[0].offset);
1763 MLX5_SET(virtio_q, virtctx, umem_2_id, attr->umems[1].id);
1764 MLX5_SET(virtio_q, virtctx, umem_2_size, attr->umems[1].size);
1765 MLX5_SET64(virtio_q, virtctx, umem_2_offset, attr->umems[1].offset);
1766 MLX5_SET(virtio_q, virtctx, umem_3_id, attr->umems[2].id);
1767 MLX5_SET(virtio_q, virtctx, umem_3_size, attr->umems[2].size);
1768 MLX5_SET64(virtio_q, virtctx, umem_3_offset, attr->umems[2].offset);
1769 MLX5_SET(virtio_q, virtctx, counter_set_id, attr->counters_obj_id);
1770 MLX5_SET(virtio_q, virtctx, pd, attr->pd);
1771 MLX5_SET(virtio_q, virtctx, queue_period_mode, attr->hw_latency_mode);
1772 MLX5_SET(virtio_q, virtctx, queue_period_us, attr->hw_max_latency_us);
1773 MLX5_SET(virtio_q, virtctx, queue_max_count, attr->hw_max_pending_comp);
1774 MLX5_SET(virtio_net_q, virtq, tisn_or_qpn, attr->tis_id);
1775 virtq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
1777 if (!virtq_obj->obj) {
1779 DRV_LOG(ERR, "Failed to create VIRTQ Obj using DevX.");
1780 mlx5_free(virtq_obj);
1783 virtq_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
1788 * Modify VIRTQ using DevX API.
1790 * @param[in] virtq_obj
1791 * Pointer to virtq object structure.
1793 * Pointer to modify virtq attributes structure.
1796 * 0 on success, a negative errno value otherwise and rte_errno is set.
1799 mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj,
1800 struct mlx5_devx_virtq_attr *attr)
1802 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0};
1803 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
1804 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq);
1805 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr);
1806 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context);
1809 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
1810 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT);
1811 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
1812 MLX5_GENERAL_OBJ_TYPE_VIRTQ);
1813 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id);
1814 MLX5_SET64(virtio_net_q, virtq, modify_field_select, attr->type);
1815 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index);
1816 switch (attr->type) {
1817 case MLX5_VIRTQ_MODIFY_TYPE_STATE:
1818 MLX5_SET16(virtio_net_q, virtq, state, attr->state);
1820 case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS:
1821 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_mkey,
1822 attr->dirty_bitmap_mkey);
1823 MLX5_SET64(virtio_net_q, virtq, dirty_bitmap_addr,
1824 attr->dirty_bitmap_addr);
1825 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_size,
1826 attr->dirty_bitmap_size);
1828 case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE:
1829 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_dump_enable,
1830 attr->dirty_bitmap_dump_enable);
1836 ret = mlx5_glue->devx_obj_modify(virtq_obj->obj, in, sizeof(in),
1839 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX.");
1847 * Query VIRTQ using DevX API.
1849 * @param[in] virtq_obj
1850 * Pointer to virtq object structure.
1851 * @param [in/out] attr
1852 * Pointer to virtq attributes structure.
1855 * 0 on success, a negative errno value otherwise and rte_errno is set.
1858 mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj,
1859 struct mlx5_devx_virtq_attr *attr)
1861 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
1862 uint32_t out[MLX5_ST_SZ_DW(query_virtq_out)] = {0};
1863 void *hdr = MLX5_ADDR_OF(query_virtq_out, in, hdr);
1864 void *virtq = MLX5_ADDR_OF(query_virtq_out, out, virtq);
1867 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
1868 MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
1869 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
1870 MLX5_GENERAL_OBJ_TYPE_VIRTQ);
1871 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id);
1872 ret = mlx5_glue->devx_obj_query(virtq_obj->obj, in, sizeof(in),
1875 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX.");
1879 attr->hw_available_index = MLX5_GET16(virtio_net_q, virtq,
1880 hw_available_index);
1881 attr->hw_used_index = MLX5_GET16(virtio_net_q, virtq, hw_used_index);
1882 attr->state = MLX5_GET16(virtio_net_q, virtq, state);
1883 attr->error_type = MLX5_GET16(virtio_net_q, virtq,
1884 virtio_q_context.error_type);
1889 * Create QP using DevX API.
1892 * Context returned from mlx5 open_device() glue function.
1894 * Pointer to QP attributes structure.
1897 * The DevX object created, NULL otherwise and rte_errno is set.
1899 struct mlx5_devx_obj *
1900 mlx5_devx_cmd_create_qp(void *ctx,
1901 struct mlx5_devx_qp_attr *attr)
1903 uint32_t in[MLX5_ST_SZ_DW(create_qp_in)] = {0};
1904 uint32_t out[MLX5_ST_SZ_DW(create_qp_out)] = {0};
1905 struct mlx5_devx_obj *qp_obj = mlx5_malloc(MLX5_MEM_ZERO,
1908 void *qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1911 DRV_LOG(ERR, "Failed to allocate QP data.");
1915 MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP);
1916 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC);
1917 MLX5_SET(qpc, qpc, pd, attr->pd);
1918 MLX5_SET(qpc, qpc, ts_format, attr->ts_format);
1919 if (attr->uar_index) {
1920 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
1921 MLX5_SET(qpc, qpc, uar_page, attr->uar_index);
1922 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT)
1923 MLX5_SET(qpc, qpc, log_page_size,
1924 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT);
1925 if (attr->sq_size) {
1926 MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->sq_size));
1927 MLX5_SET(qpc, qpc, cqn_snd, attr->cqn);
1928 MLX5_SET(qpc, qpc, log_sq_size,
1929 rte_log2_u32(attr->sq_size));
1931 MLX5_SET(qpc, qpc, no_sq, 1);
1933 if (attr->rq_size) {
1934 MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->rq_size));
1935 MLX5_SET(qpc, qpc, cqn_rcv, attr->cqn);
1936 MLX5_SET(qpc, qpc, log_rq_stride, attr->log_rq_stride -
1937 MLX5_LOG_RQ_STRIDE_SHIFT);
1938 MLX5_SET(qpc, qpc, log_rq_size,
1939 rte_log2_u32(attr->rq_size));
1940 MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ);
1942 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ);
1944 if (attr->dbr_umem_valid) {
1945 MLX5_SET(qpc, qpc, dbr_umem_valid,
1946 attr->dbr_umem_valid);
1947 MLX5_SET(qpc, qpc, dbr_umem_id, attr->dbr_umem_id);
1949 MLX5_SET64(qpc, qpc, dbr_addr, attr->dbr_address);
1950 MLX5_SET64(create_qp_in, in, wq_umem_offset,
1951 attr->wq_umem_offset);
1952 MLX5_SET(create_qp_in, in, wq_umem_id, attr->wq_umem_id);
1953 MLX5_SET(create_qp_in, in, wq_umem_valid, 1);
1955 /* Special QP to be managed by FW - no SQ\RQ\CQ\UAR\DB rec. */
1956 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ);
1957 MLX5_SET(qpc, qpc, no_sq, 1);
1959 qp_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
1963 DRV_LOG(ERR, "Failed to create QP Obj using DevX.");
1967 qp_obj->id = MLX5_GET(create_qp_out, out, qpn);
1972 * Modify QP using DevX API.
1973 * Currently supports only force loop-back QP.
1976 * Pointer to QP object structure.
1977 * @param [in] qp_st_mod_op
1978 * The QP state modification operation.
1979 * @param [in] remote_qp_id
1980 * The remote QP ID for MLX5_CMD_OP_INIT2RTR_QP operation.
1983 * 0 on success, a negative errno value otherwise and rte_errno is set.
1986 mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op,
1987 uint32_t remote_qp_id)
1990 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)];
1991 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)];
1992 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)];
1995 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)];
1996 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)];
1997 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)];
2002 unsigned int outlen;
2004 memset(&in, 0, sizeof(in));
2005 memset(&out, 0, sizeof(out));
2006 MLX5_SET(rst2init_qp_in, &in, opcode, qp_st_mod_op);
2007 switch (qp_st_mod_op) {
2008 case MLX5_CMD_OP_RST2INIT_QP:
2009 MLX5_SET(rst2init_qp_in, &in, qpn, qp->id);
2010 qpc = MLX5_ADDR_OF(rst2init_qp_in, &in, qpc);
2011 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1);
2012 MLX5_SET(qpc, qpc, rre, 1);
2013 MLX5_SET(qpc, qpc, rwe, 1);
2014 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
2015 inlen = sizeof(in.rst2init);
2016 outlen = sizeof(out.rst2init);
2018 case MLX5_CMD_OP_INIT2RTR_QP:
2019 MLX5_SET(init2rtr_qp_in, &in, qpn, qp->id);
2020 qpc = MLX5_ADDR_OF(init2rtr_qp_in, &in, qpc);
2021 MLX5_SET(qpc, qpc, primary_address_path.fl, 1);
2022 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1);
2023 MLX5_SET(qpc, qpc, mtu, 1);
2024 MLX5_SET(qpc, qpc, log_msg_max, 30);
2025 MLX5_SET(qpc, qpc, remote_qpn, remote_qp_id);
2026 MLX5_SET(qpc, qpc, min_rnr_nak, 0);
2027 inlen = sizeof(in.init2rtr);
2028 outlen = sizeof(out.init2rtr);
2030 case MLX5_CMD_OP_RTR2RTS_QP:
2031 qpc = MLX5_ADDR_OF(rtr2rts_qp_in, &in, qpc);
2032 MLX5_SET(rtr2rts_qp_in, &in, qpn, qp->id);
2033 MLX5_SET(qpc, qpc, primary_address_path.ack_timeout, 14);
2034 MLX5_SET(qpc, qpc, log_ack_req_freq, 0);
2035 MLX5_SET(qpc, qpc, retry_count, 7);
2036 MLX5_SET(qpc, qpc, rnr_retry, 7);
2037 inlen = sizeof(in.rtr2rts);
2038 outlen = sizeof(out.rtr2rts);
2041 DRV_LOG(ERR, "Invalid or unsupported QP modify op %u.",
2046 ret = mlx5_glue->devx_obj_modify(qp->obj, &in, inlen, &out, outlen);
2048 DRV_LOG(ERR, "Failed to modify QP using DevX.");
2055 struct mlx5_devx_obj *
2056 mlx5_devx_cmd_create_virtio_q_counters(void *ctx)
2058 uint32_t in[MLX5_ST_SZ_DW(create_virtio_q_counters_in)] = {0};
2059 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2060 struct mlx5_devx_obj *couners_obj = mlx5_malloc(MLX5_MEM_ZERO,
2061 sizeof(*couners_obj), 0,
2063 void *hdr = MLX5_ADDR_OF(create_virtio_q_counters_in, in, hdr);
2066 DRV_LOG(ERR, "Failed to allocate virtio queue counters data.");
2070 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2071 MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2072 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2073 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS);
2074 couners_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
2076 if (!couners_obj->obj) {
2078 DRV_LOG(ERR, "Failed to create virtio queue counters Obj using"
2080 mlx5_free(couners_obj);
2083 couners_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2088 mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj,
2089 struct mlx5_devx_virtio_q_couners_attr *attr)
2091 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
2092 uint32_t out[MLX5_ST_SZ_DW(query_virtio_q_counters_out)] = {0};
2093 void *hdr = MLX5_ADDR_OF(query_virtio_q_counters_out, in, hdr);
2094 void *virtio_q_counters = MLX5_ADDR_OF(query_virtio_q_counters_out, out,
2098 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2099 MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
2100 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2101 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS);
2102 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, couners_obj->id);
2103 ret = mlx5_glue->devx_obj_query(couners_obj->obj, in, sizeof(in), out,
2106 DRV_LOG(ERR, "Failed to query virtio q counters using DevX.");
2110 attr->received_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters,
2112 attr->completed_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters,
2114 attr->error_cqes = MLX5_GET(virtio_q_counters, virtio_q_counters,
2116 attr->bad_desc_errors = MLX5_GET(virtio_q_counters, virtio_q_counters,
2118 attr->exceed_max_chain = MLX5_GET(virtio_q_counters, virtio_q_counters,
2120 attr->invalid_buffer = MLX5_GET(virtio_q_counters, virtio_q_counters,
2126 * Create general object of type FLOW_HIT_ASO using DevX API.
2129 * Context returned from mlx5 open_device() glue function.
2131 * PD value to associate the FLOW_HIT_ASO object with.
2134 * The DevX object created, NULL otherwise and rte_errno is set.
2136 struct mlx5_devx_obj *
2137 mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, uint32_t pd)
2139 uint32_t in[MLX5_ST_SZ_DW(create_flow_hit_aso_in)] = {0};
2140 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2141 struct mlx5_devx_obj *flow_hit_aso_obj = NULL;
2144 flow_hit_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*flow_hit_aso_obj),
2146 if (!flow_hit_aso_obj) {
2147 DRV_LOG(ERR, "Failed to allocate FLOW_HIT_ASO object data");
2151 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, hdr);
2152 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2153 MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2154 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2155 MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO);
2156 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, flow_hit_aso);
2157 MLX5_SET(flow_hit_aso, ptr, access_pd, pd);
2158 flow_hit_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2160 if (!flow_hit_aso_obj->obj) {
2162 DRV_LOG(ERR, "Failed to create FLOW_HIT_ASO obj using DevX.");
2163 mlx5_free(flow_hit_aso_obj);
2166 flow_hit_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2167 return flow_hit_aso_obj;
2171 * Create PD using DevX API.
2174 * Context returned from mlx5 open_device() glue function.
2177 * The DevX object created, NULL otherwise and rte_errno is set.
2179 struct mlx5_devx_obj *
2180 mlx5_devx_cmd_alloc_pd(void *ctx)
2182 struct mlx5_devx_obj *ppd =
2183 mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ppd), 0, SOCKET_ID_ANY);
2184 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {0};
2185 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {0};
2188 DRV_LOG(ERR, "Failed to allocate PD data.");
2192 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD);
2193 ppd->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2197 DRV_LOG(ERR, "Failed to allocate PD Obj using DevX.");
2201 ppd->id = MLX5_GET(alloc_pd_out, out, pd);
2206 * Create general object of type FLOW_METER_ASO using DevX API.
2209 * Context returned from mlx5 open_device() glue function.
2211 * PD value to associate the FLOW_METER_ASO object with.
2212 * @param [in] log_obj_size
2213 * log_obj_size define to allocate number of 2 * meters
2214 * in one FLOW_METER_ASO object.
2217 * The DevX object created, NULL otherwise and rte_errno is set.
2219 struct mlx5_devx_obj *
2220 mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx, uint32_t pd,
2221 uint32_t log_obj_size)
2223 uint32_t in[MLX5_ST_SZ_DW(create_flow_meter_aso_in)] = {0};
2224 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)];
2225 struct mlx5_devx_obj *flow_meter_aso_obj;
2228 flow_meter_aso_obj = mlx5_malloc(MLX5_MEM_ZERO,
2229 sizeof(*flow_meter_aso_obj),
2231 if (!flow_meter_aso_obj) {
2232 DRV_LOG(ERR, "Failed to allocate FLOW_METER_ASO object data");
2236 ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, hdr);
2237 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2238 MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2239 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2240 MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO);
2241 MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range,
2243 ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, flow_meter_aso);
2244 MLX5_SET(flow_meter_aso, ptr, access_pd, pd);
2245 flow_meter_aso_obj->obj = mlx5_glue->devx_obj_create(
2246 ctx, in, sizeof(in),
2248 if (!flow_meter_aso_obj->obj) {
2250 DRV_LOG(ERR, "Failed to create FLOW_METER_ASO obj using DevX.");
2251 mlx5_free(flow_meter_aso_obj);
2254 flow_meter_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr,
2256 return flow_meter_aso_obj;
2260 * Create general object of type GENEVE TLV option using DevX API.
2263 * Context returned from mlx5 open_device() glue function.
2265 * TLV option variable value of class
2267 * TLV option variable value of type
2269 * TLV option variable value of len
2272 * The DevX object created, NULL otherwise and rte_errno is set.
2274 struct mlx5_devx_obj *
2275 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx,
2276 uint16_t class, uint8_t type, uint8_t len)
2278 uint32_t in[MLX5_ST_SZ_DW(create_geneve_tlv_option_in)] = {0};
2279 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2280 struct mlx5_devx_obj *geneve_tlv_opt_obj = mlx5_malloc(MLX5_MEM_ZERO,
2281 sizeof(*geneve_tlv_opt_obj),
2284 if (!geneve_tlv_opt_obj) {
2285 DRV_LOG(ERR, "Failed to allocate geneve tlv option object.");
2289 void *hdr = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, hdr);
2290 void *opt = MLX5_ADDR_OF(create_geneve_tlv_option_in, in,
2292 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2293 MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2294 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2295 MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT);
2296 MLX5_SET(geneve_tlv_option, opt, option_class,
2297 rte_be_to_cpu_16(class));
2298 MLX5_SET(geneve_tlv_option, opt, option_type, type);
2299 MLX5_SET(geneve_tlv_option, opt, option_data_length, len);
2300 geneve_tlv_opt_obj->obj = mlx5_glue->devx_obj_create(ctx, in,
2301 sizeof(in), out, sizeof(out));
2302 if (!geneve_tlv_opt_obj->obj) {
2304 DRV_LOG(ERR, "Failed to create Geneve tlv option "
2306 mlx5_free(geneve_tlv_opt_obj);
2309 geneve_tlv_opt_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2310 return geneve_tlv_opt_obj;
2314 mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id)
2316 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2317 uint32_t in[MLX5_ST_SZ_DW(query_rq_in)] = {0};
2318 uint32_t out[MLX5_ST_SZ_DW(query_rq_out)] = {0};
2322 MLX5_SET(query_rq_in, in, opcode, MLX5_CMD_OP_QUERY_RQ);
2323 MLX5_SET(query_rq_in, in, rqn, ((struct ibv_wq *)wq)->wq_num);
2324 rc = mlx5_glue->devx_wq_query(wq, in, sizeof(in), out, sizeof(out));
2327 DRV_LOG(ERR, "Failed to query WQ counter set ID using DevX - "
2328 "rc = %d, errno = %d.", rc, errno);
2331 rq_ctx = MLX5_ADDR_OF(query_rq_out, out, rq_context);
2332 *counter_set_id = MLX5_GET(rqc, rq_ctx, counter_set_id);
2336 (void)counter_set_id;
2342 * Allocate queue counters via devx interface.
2345 * Context returned from mlx5 open_device() glue function.
2348 * Pointer to counter object on success, a NULL value otherwise and
2351 struct mlx5_devx_obj *
2352 mlx5_devx_cmd_queue_counter_alloc(void *ctx)
2354 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 0,
2356 uint32_t in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {0};
2357 uint32_t out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {0};
2363 MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER);
2364 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
2367 DRV_LOG(DEBUG, "Can't allocate q counter set by DevX - error "
2373 dcs->id = MLX5_GET(alloc_q_counter_out, out, counter_set_id);
2378 * Query queue counters values.
2381 * devx object of the queue counter set.
2383 * Whether hardware should clear the counters after the query or not.
2384 * @param[out] out_of_buffers
2385 * Number of dropped occurred due to lack of WQE for the associated QPs/RQs.
2388 * 0 on success, a negative value otherwise.
2391 mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear,
2392 uint32_t *out_of_buffers)
2394 uint32_t out[MLX5_ST_SZ_BYTES(query_q_counter_out)] = {0};
2395 uint32_t in[MLX5_ST_SZ_DW(query_q_counter_in)] = {0};
2398 MLX5_SET(query_q_counter_in, in, opcode,
2399 MLX5_CMD_OP_QUERY_Q_COUNTER);
2400 MLX5_SET(query_q_counter_in, in, op_mod, 0);
2401 MLX5_SET(query_q_counter_in, in, counter_set_id, dcs->id);
2402 MLX5_SET(query_q_counter_in, in, clear, !!clear);
2403 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out,
2406 DRV_LOG(ERR, "Failed to query devx q counter set - rc %d", rc);
2410 *out_of_buffers = MLX5_GET(query_q_counter_out, out, out_of_buffer);
2415 * Create general object of type DEK using DevX API.
2418 * Context returned from mlx5 open_device() glue function.
2420 * Pointer to DEK attributes structure.
2423 * The DevX object created, NULL otherwise and rte_errno is set.
2425 struct mlx5_devx_obj *
2426 mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr)
2428 uint32_t in[MLX5_ST_SZ_DW(create_dek_in)] = {0};
2429 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2430 struct mlx5_devx_obj *dek_obj = NULL;
2431 void *ptr = NULL, *key_addr = NULL;
2433 dek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dek_obj),
2435 if (dek_obj == NULL) {
2436 DRV_LOG(ERR, "Failed to allocate DEK object data");
2440 ptr = MLX5_ADDR_OF(create_dek_in, in, hdr);
2441 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2442 MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2443 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2444 MLX5_GENERAL_OBJ_TYPE_DEK);
2445 ptr = MLX5_ADDR_OF(create_dek_in, in, dek);
2446 MLX5_SET(dek, ptr, key_size, attr->key_size);
2447 MLX5_SET(dek, ptr, has_keytag, attr->has_keytag);
2448 MLX5_SET(dek, ptr, key_purpose, attr->key_purpose);
2449 MLX5_SET(dek, ptr, pd, attr->pd);
2450 MLX5_SET64(dek, ptr, opaque, attr->opaque);
2451 key_addr = MLX5_ADDR_OF(dek, ptr, key);
2452 memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE);
2453 dek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2455 if (dek_obj->obj == NULL) {
2457 DRV_LOG(ERR, "Failed to create DEK obj using DevX.");
2461 dek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2466 * Create general object of type IMPORT_KEK using DevX API.
2469 * Context returned from mlx5 open_device() glue function.
2471 * Pointer to IMPORT_KEK attributes structure.
2474 * The DevX object created, NULL otherwise and rte_errno is set.
2476 struct mlx5_devx_obj *
2477 mlx5_devx_cmd_create_import_kek_obj(void *ctx,
2478 struct mlx5_devx_import_kek_attr *attr)
2480 uint32_t in[MLX5_ST_SZ_DW(create_import_kek_in)] = {0};
2481 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2482 struct mlx5_devx_obj *import_kek_obj = NULL;
2483 void *ptr = NULL, *key_addr = NULL;
2485 import_kek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*import_kek_obj),
2487 if (import_kek_obj == NULL) {
2488 DRV_LOG(ERR, "Failed to allocate IMPORT_KEK object data");
2492 ptr = MLX5_ADDR_OF(create_import_kek_in, in, hdr);
2493 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2494 MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2495 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2496 MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK);
2497 ptr = MLX5_ADDR_OF(create_import_kek_in, in, import_kek);
2498 MLX5_SET(import_kek, ptr, key_size, attr->key_size);
2499 key_addr = MLX5_ADDR_OF(import_kek, ptr, key);
2500 memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE);
2501 import_kek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2503 if (import_kek_obj->obj == NULL) {
2505 DRV_LOG(ERR, "Failed to create IMPORT_KEK object using DevX.");
2506 mlx5_free(import_kek_obj);
2509 import_kek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2510 return import_kek_obj;
2514 * Create general object of type CRYPTO_LOGIN using DevX API.
2517 * Context returned from mlx5 open_device() glue function.
2519 * Pointer to CRYPTO_LOGIN attributes structure.
2522 * The DevX object created, NULL otherwise and rte_errno is set.
2524 struct mlx5_devx_obj *
2525 mlx5_devx_cmd_create_crypto_login_obj(void *ctx,
2526 struct mlx5_devx_crypto_login_attr *attr)
2528 uint32_t in[MLX5_ST_SZ_DW(create_crypto_login_in)] = {0};
2529 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2530 struct mlx5_devx_obj *crypto_login_obj = NULL;
2531 void *ptr = NULL, *credential_addr = NULL;
2533 crypto_login_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*crypto_login_obj),
2535 if (crypto_login_obj == NULL) {
2536 DRV_LOG(ERR, "Failed to allocate CRYPTO_LOGIN object data");
2540 ptr = MLX5_ADDR_OF(create_crypto_login_in, in, hdr);
2541 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2542 MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2543 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2544 MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN);
2545 ptr = MLX5_ADDR_OF(create_crypto_login_in, in, crypto_login);
2546 MLX5_SET(crypto_login, ptr, credential_pointer,
2547 attr->credential_pointer);
2548 MLX5_SET(crypto_login, ptr, session_import_kek_ptr,
2549 attr->session_import_kek_ptr);
2550 credential_addr = MLX5_ADDR_OF(crypto_login, ptr, credential);
2551 memcpy(credential_addr, (void *)(attr->credential),
2552 MLX5_CRYPTO_LOGIN_CREDENTIAL_SIZE);
2553 crypto_login_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2555 if (crypto_login_obj->obj == NULL) {
2557 DRV_LOG(ERR, "Failed to create CRYPTO_LOGIN obj using DevX.");
2558 mlx5_free(crypto_login_obj);
2561 crypto_login_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2562 return crypto_login_obj;