1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
8 #include <rte_malloc.h>
9 #include <rte_eal_paging.h>
12 #include "mlx5_devx_cmds.h"
13 #include "mlx5_common_log.h"
14 #include "mlx5_malloc.h"
17 mlx5_devx_get_hca_cap(void *ctx, uint32_t *in, uint32_t *out,
18 int *err, uint32_t flags)
20 const size_t size_in = MLX5_ST_SZ_DW(query_hca_cap_in) * sizeof(int);
21 const size_t size_out = MLX5_ST_SZ_DW(query_hca_cap_out) * sizeof(int);
22 int status, syndrome, rc;
26 memset(in, 0, size_in);
27 memset(out, 0, size_out);
28 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
29 MLX5_SET(query_hca_cap_in, in, op_mod, flags);
30 rc = mlx5_glue->devx_general_cmd(ctx, in, size_in, out, size_out);
33 "Failed to query devx HCA capabilities func %#02x",
36 *err = rc > 0 ? -rc : rc;
39 status = MLX5_GET(query_hca_cap_out, out, status);
40 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
43 "Failed to query devx HCA capabilities func %#02x status %x, syndrome = %x",
44 flags >> 1, status, syndrome);
49 return MLX5_ADDR_OF(query_hca_cap_out, out, capability);
53 * Perform read access to the registers. Reads data from register
54 * and writes ones to the specified buffer.
57 * Context returned from mlx5 open_device() glue function.
59 * Register identifier according to the PRM.
61 * Register access auxiliary parameter according to the PRM.
63 * Pointer to the buffer to store read data.
65 * Buffer size in double words.
68 * 0 on success, a negative value otherwise.
71 mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg,
72 uint32_t *data, uint32_t dw_cnt)
74 uint32_t in[MLX5_ST_SZ_DW(access_register_in)] = {0};
75 uint32_t out[MLX5_ST_SZ_DW(access_register_out) +
76 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0};
79 MLX5_ASSERT(data && dw_cnt);
80 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX);
81 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) {
82 DRV_LOG(ERR, "Not enough buffer for register read data");
85 MLX5_SET(access_register_in, in, opcode,
86 MLX5_CMD_OP_ACCESS_REGISTER_USER);
87 MLX5_SET(access_register_in, in, op_mod,
88 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ);
89 MLX5_SET(access_register_in, in, register_id, reg_id);
90 MLX5_SET(access_register_in, in, argument, arg);
91 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out,
92 MLX5_ST_SZ_BYTES(access_register_out) +
93 sizeof(uint32_t) * dw_cnt);
96 status = MLX5_GET(access_register_out, out, status);
98 int syndrome = MLX5_GET(access_register_out, out, syndrome);
100 DRV_LOG(DEBUG, "Failed to read access NIC register 0x%X, "
101 "status %x, syndrome = %x",
102 reg_id, status, syndrome);
105 memcpy(data, &out[MLX5_ST_SZ_DW(access_register_out)],
106 dw_cnt * sizeof(uint32_t));
109 rc = (rc > 0) ? -rc : rc;
114 * Perform write access to the registers.
117 * Context returned from mlx5 open_device() glue function.
119 * Register identifier according to the PRM.
121 * Register access auxiliary parameter according to the PRM.
123 * Pointer to the buffer containing data to write.
125 * Buffer size in double words (32bit units).
128 * 0 on success, a negative value otherwise.
131 mlx5_devx_cmd_register_write(void *ctx, uint16_t reg_id, uint32_t arg,
132 uint32_t *data, uint32_t dw_cnt)
134 uint32_t in[MLX5_ST_SZ_DW(access_register_in) +
135 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0};
136 uint32_t out[MLX5_ST_SZ_DW(access_register_out)] = {0};
140 MLX5_ASSERT(data && dw_cnt);
141 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX);
142 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) {
143 DRV_LOG(ERR, "Data to write exceeds max size");
146 MLX5_SET(access_register_in, in, opcode,
147 MLX5_CMD_OP_ACCESS_REGISTER_USER);
148 MLX5_SET(access_register_in, in, op_mod,
149 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE);
150 MLX5_SET(access_register_in, in, register_id, reg_id);
151 MLX5_SET(access_register_in, in, argument, arg);
152 ptr = MLX5_ADDR_OF(access_register_in, in, register_data);
153 memcpy(ptr, data, dw_cnt * sizeof(uint32_t));
154 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
156 rc = mlx5_glue->devx_general_cmd(ctx, in,
157 MLX5_ST_SZ_BYTES(access_register_in) +
158 dw_cnt * sizeof(uint32_t),
162 status = MLX5_GET(access_register_out, out, status);
164 int syndrome = MLX5_GET(access_register_out, out, syndrome);
166 DRV_LOG(DEBUG, "Failed to write access NIC register 0x%X, "
167 "status %x, syndrome = %x",
168 reg_id, status, syndrome);
173 rc = (rc > 0) ? -rc : rc;
178 * Allocate flow counters via devx interface.
181 * Context returned from mlx5 open_device() glue function.
183 * Pointer to counters properties structure to be filled by the routine.
185 * Bulk counter numbers in 128 counters units.
188 * Pointer to counter object on success, a negative value otherwise and
191 struct mlx5_devx_obj *
192 mlx5_devx_cmd_flow_counter_alloc(void *ctx, uint32_t bulk_n_128)
194 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs),
196 uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0};
197 uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0};
203 MLX5_SET(alloc_flow_counter_in, in, opcode,
204 MLX5_CMD_OP_ALLOC_FLOW_COUNTER);
205 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128);
206 dcs->obj = mlx5_glue->devx_obj_create(ctx, in,
207 sizeof(in), out, sizeof(out));
209 DRV_LOG(ERR, "Can't allocate counters - error %d", errno);
214 dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id);
219 * Query flow counters values.
222 * devx object that was obtained from mlx5_devx_cmd_fc_alloc.
224 * Whether hardware should clear the counters after the query or not.
225 * @param[in] n_counters
226 * 0 in case of 1 counter to read, otherwise the counter number to read.
228 * The number of packets that matched the flow.
230 * The number of bytes that matched the flow.
232 * The mkey key for batch query.
234 * The address in the mkey range for batch query.
236 * The completion object for asynchronous batch query.
238 * The ID to be returned in the asynchronous batch query response.
241 * 0 on success, a negative value otherwise.
244 mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs,
245 int clear, uint32_t n_counters,
246 uint64_t *pkts, uint64_t *bytes,
247 uint32_t mkey, void *addr,
251 int out_len = MLX5_ST_SZ_BYTES(query_flow_counter_out) +
252 MLX5_ST_SZ_BYTES(traffic_counter);
253 uint32_t out[out_len];
254 uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0};
258 MLX5_SET(query_flow_counter_in, in, opcode,
259 MLX5_CMD_OP_QUERY_FLOW_COUNTER);
260 MLX5_SET(query_flow_counter_in, in, op_mod, 0);
261 MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id);
262 MLX5_SET(query_flow_counter_in, in, clear, !!clear);
265 MLX5_SET(query_flow_counter_in, in, num_of_counters,
267 MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1);
268 MLX5_SET(query_flow_counter_in, in, mkey, mkey);
269 MLX5_SET64(query_flow_counter_in, in, address,
270 (uint64_t)(uintptr_t)addr);
273 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out,
276 rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in),
280 DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc);
285 stats = MLX5_ADDR_OF(query_flow_counter_out,
286 out, flow_statistics);
287 *pkts = MLX5_GET64(traffic_counter, stats, packets);
288 *bytes = MLX5_GET64(traffic_counter, stats, octets);
297 * Context returned from mlx5 open_device() glue function.
299 * Attributes of the requested mkey.
302 * Pointer to Devx mkey on success, a negative value otherwise and rte_errno
305 struct mlx5_devx_obj *
306 mlx5_devx_cmd_mkey_create(void *ctx,
307 struct mlx5_devx_mkey_attr *attr)
309 struct mlx5_klm *klm_array = attr->klm_array;
310 int klm_num = attr->klm_num;
311 int in_size_dw = MLX5_ST_SZ_DW(create_mkey_in) +
312 (klm_num ? RTE_ALIGN(klm_num, 4) : 0) * MLX5_ST_SZ_DW(klm);
313 uint32_t in[in_size_dw];
314 uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0};
316 struct mlx5_devx_obj *mkey = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mkey),
319 uint32_t translation_size;
325 memset(in, 0, in_size_dw * 4);
326 pgsize = rte_mem_page_size();
327 if (pgsize == (size_t)-1) {
329 DRV_LOG(ERR, "Failed to get page size");
333 MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY);
334 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
337 uint8_t *klm = (uint8_t *)MLX5_ADDR_OF(create_mkey_in, in,
339 translation_size = RTE_ALIGN(klm_num, 4);
340 for (i = 0; i < klm_num; i++) {
341 MLX5_SET(klm, klm, byte_count, klm_array[i].byte_count);
342 MLX5_SET(klm, klm, mkey, klm_array[i].mkey);
343 MLX5_SET64(klm, klm, address, klm_array[i].address);
344 klm += MLX5_ST_SZ_BYTES(klm);
346 for (; i < (int)translation_size; i++) {
347 MLX5_SET(klm, klm, mkey, 0x0);
348 MLX5_SET64(klm, klm, address, 0x0);
349 klm += MLX5_ST_SZ_BYTES(klm);
351 MLX5_SET(mkc, mkc, access_mode_1_0, attr->log_entity_size ?
352 MLX5_MKC_ACCESS_MODE_KLM_FBS :
353 MLX5_MKC_ACCESS_MODE_KLM);
354 MLX5_SET(mkc, mkc, log_page_size, attr->log_entity_size);
356 translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16;
357 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
358 MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize));
360 MLX5_SET(create_mkey_in, in, translations_octword_actual_size,
362 MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id);
363 MLX5_SET(create_mkey_in, in, pg_access, attr->pg_access);
364 MLX5_SET(mkc, mkc, lw, 0x1);
365 MLX5_SET(mkc, mkc, lr, 0x1);
366 if (attr->set_remote_rw) {
367 MLX5_SET(mkc, mkc, rw, 0x1);
368 MLX5_SET(mkc, mkc, rr, 0x1);
370 MLX5_SET(mkc, mkc, qpn, 0xffffff);
371 MLX5_SET(mkc, mkc, pd, attr->pd);
372 MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF);
373 MLX5_SET(mkc, mkc, umr_en, attr->umr_en);
374 MLX5_SET(mkc, mkc, translations_octword_size, translation_size);
375 MLX5_SET(mkc, mkc, relaxed_ordering_write,
376 attr->relaxed_ordering_write);
377 MLX5_SET(mkc, mkc, relaxed_ordering_read, attr->relaxed_ordering_read);
378 MLX5_SET64(mkc, mkc, start_addr, attr->addr);
379 MLX5_SET64(mkc, mkc, len, attr->size);
380 MLX5_SET(mkc, mkc, crypto_en, attr->crypto_en);
381 if (attr->crypto_en) {
382 MLX5_SET(mkc, mkc, bsf_en, attr->crypto_en);
383 MLX5_SET(mkc, mkc, bsf_octword_size, 4);
385 mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out,
388 DRV_LOG(ERR, "Can't create %sdirect mkey - error %d",
389 klm_num ? "an in" : "a ", errno);
394 mkey->id = MLX5_GET(create_mkey_out, out, mkey_index);
395 mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF);
400 * Get status of devx command response.
401 * Mainly used for asynchronous commands.
404 * The out response buffer.
407 * 0 on success, non-zero value otherwise.
410 mlx5_devx_get_out_command_status(void *out)
416 status = MLX5_GET(query_flow_counter_out, out, status);
418 int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome);
420 DRV_LOG(ERR, "Bad DevX status %x, syndrome = %x", status,
427 * Destroy any object allocated by a Devx API.
430 * Pointer to a general object.
433 * 0 on success, a negative value otherwise.
436 mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj)
442 ret = mlx5_glue->devx_obj_destroy(obj->obj);
448 * Query NIC vport context.
449 * Fills minimal inline attribute.
452 * ibv contexts returned from mlx5dv_open_device.
456 * Attributes device values.
459 * 0 on success, a negative value otherwise.
462 mlx5_devx_cmd_query_nic_vport_context(void *ctx,
464 struct mlx5_hca_attr *attr)
466 uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0};
467 uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0};
469 int status, syndrome, rc;
471 /* Query NIC vport context to determine inline mode. */
472 MLX5_SET(query_nic_vport_context_in, in, opcode,
473 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT);
474 MLX5_SET(query_nic_vport_context_in, in, vport_number, vport);
476 MLX5_SET(query_nic_vport_context_in, in, other_vport, 1);
477 rc = mlx5_glue->devx_general_cmd(ctx,
482 status = MLX5_GET(query_nic_vport_context_out, out, status);
483 syndrome = MLX5_GET(query_nic_vport_context_out, out, syndrome);
485 DRV_LOG(DEBUG, "Failed to query NIC vport context, "
486 "status %x, syndrome = %x", status, syndrome);
489 vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out,
491 attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx,
492 min_wqe_inline_mode);
495 rc = (rc > 0) ? -rc : rc;
500 * Query NIC vDPA attributes.
503 * Context returned from mlx5 open_device() glue function.
504 * @param[out] vdpa_attr
505 * vDPA Attributes structure to fill.
508 mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx,
509 struct mlx5_hca_vdpa_attr *vdpa_attr)
511 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)];
512 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)];
515 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, NULL,
516 MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION |
517 MLX5_HCA_CAP_OPMOD_GET_CUR);
519 RTE_LOG(DEBUG, PMD, "Failed to query devx VDPA capabilities");
520 vdpa_attr->valid = 0;
522 vdpa_attr->valid = 1;
523 vdpa_attr->desc_tunnel_offload_type =
524 MLX5_GET(virtio_emulation_cap, hcattr,
525 desc_tunnel_offload_type);
526 vdpa_attr->eth_frame_offload_type =
527 MLX5_GET(virtio_emulation_cap, hcattr,
528 eth_frame_offload_type);
529 vdpa_attr->virtio_version_1_0 =
530 MLX5_GET(virtio_emulation_cap, hcattr,
532 vdpa_attr->tso_ipv4 = MLX5_GET(virtio_emulation_cap, hcattr,
534 vdpa_attr->tso_ipv6 = MLX5_GET(virtio_emulation_cap, hcattr,
536 vdpa_attr->tx_csum = MLX5_GET(virtio_emulation_cap, hcattr,
538 vdpa_attr->rx_csum = MLX5_GET(virtio_emulation_cap, hcattr,
540 vdpa_attr->event_mode = MLX5_GET(virtio_emulation_cap, hcattr,
542 vdpa_attr->virtio_queue_type =
543 MLX5_GET(virtio_emulation_cap, hcattr,
545 vdpa_attr->log_doorbell_stride =
546 MLX5_GET(virtio_emulation_cap, hcattr,
547 log_doorbell_stride);
548 vdpa_attr->log_doorbell_bar_size =
549 MLX5_GET(virtio_emulation_cap, hcattr,
550 log_doorbell_bar_size);
551 vdpa_attr->doorbell_bar_offset =
552 MLX5_GET64(virtio_emulation_cap, hcattr,
553 doorbell_bar_offset);
554 vdpa_attr->max_num_virtio_queues =
555 MLX5_GET(virtio_emulation_cap, hcattr,
556 max_num_virtio_queues);
557 vdpa_attr->umems[0].a = MLX5_GET(virtio_emulation_cap, hcattr,
558 umem_1_buffer_param_a);
559 vdpa_attr->umems[0].b = MLX5_GET(virtio_emulation_cap, hcattr,
560 umem_1_buffer_param_b);
561 vdpa_attr->umems[1].a = MLX5_GET(virtio_emulation_cap, hcattr,
562 umem_2_buffer_param_a);
563 vdpa_attr->umems[1].b = MLX5_GET(virtio_emulation_cap, hcattr,
564 umem_2_buffer_param_b);
565 vdpa_attr->umems[2].a = MLX5_GET(virtio_emulation_cap, hcattr,
566 umem_3_buffer_param_a);
567 vdpa_attr->umems[2].b = MLX5_GET(virtio_emulation_cap, hcattr,
568 umem_3_buffer_param_b);
573 mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj,
574 uint32_t ids[], uint32_t num)
576 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
577 uint32_t out[MLX5_ST_SZ_DW(create_flex_parser_out)] = {0};
578 void *hdr = MLX5_ADDR_OF(create_flex_parser_out, in, hdr);
579 void *flex = MLX5_ADDR_OF(create_flex_parser_out, out, flex);
580 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table);
585 if (num > MLX5_GRAPH_NODE_SAMPLE_NUM) {
587 DRV_LOG(ERR, "Too many sample IDs to be fetched.");
590 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
591 MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
592 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
593 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH);
594 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, flex_obj->id);
595 ret = mlx5_glue->devx_obj_query(flex_obj->obj, in, sizeof(in),
599 DRV_LOG(ERR, "Failed to query sample IDs with object %p.",
603 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) {
604 void *s_off = (void *)((char *)sample + i *
605 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample));
608 en = MLX5_GET(parse_graph_flow_match_sample, s_off,
609 flow_match_sample_en);
612 ids[idx++] = MLX5_GET(parse_graph_flow_match_sample, s_off,
613 flow_match_sample_field_id);
617 DRV_LOG(ERR, "Number of sample IDs are not as expected.");
623 struct mlx5_devx_obj *
624 mlx5_devx_cmd_create_flex_parser(void *ctx,
625 struct mlx5_devx_graph_node_attr *data)
627 uint32_t in[MLX5_ST_SZ_DW(create_flex_parser_in)] = {0};
628 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
629 void *hdr = MLX5_ADDR_OF(create_flex_parser_in, in, hdr);
630 void *flex = MLX5_ADDR_OF(create_flex_parser_in, in, flex);
631 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table);
632 void *in_arc = MLX5_ADDR_OF(parse_graph_flex, flex, input_arc);
633 void *out_arc = MLX5_ADDR_OF(parse_graph_flex, flex, output_arc);
634 struct mlx5_devx_obj *parse_flex_obj = mlx5_malloc
635 (MLX5_MEM_ZERO, sizeof(*parse_flex_obj), 0, SOCKET_ID_ANY);
638 if (!parse_flex_obj) {
639 DRV_LOG(ERR, "Failed to allocate flex parser data.");
643 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
644 MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
645 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
646 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH);
647 MLX5_SET(parse_graph_flex, flex, header_length_mode,
648 data->header_length_mode);
649 MLX5_SET64(parse_graph_flex, flex, modify_field_select,
650 data->modify_field_select);
651 MLX5_SET(parse_graph_flex, flex, header_length_base_value,
652 data->header_length_base_value);
653 MLX5_SET(parse_graph_flex, flex, header_length_field_offset,
654 data->header_length_field_offset);
655 MLX5_SET(parse_graph_flex, flex, header_length_field_shift,
656 data->header_length_field_shift);
657 MLX5_SET(parse_graph_flex, flex, next_header_field_offset,
658 data->next_header_field_offset);
659 MLX5_SET(parse_graph_flex, flex, next_header_field_size,
660 data->next_header_field_size);
661 MLX5_SET(parse_graph_flex, flex, header_length_field_mask,
662 data->header_length_field_mask);
663 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) {
664 struct mlx5_devx_match_sample_attr *s = &data->sample[i];
665 void *s_off = (void *)((char *)sample + i *
666 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample));
668 if (!s->flow_match_sample_en)
670 MLX5_SET(parse_graph_flow_match_sample, s_off,
671 flow_match_sample_en, !!s->flow_match_sample_en);
672 MLX5_SET(parse_graph_flow_match_sample, s_off,
673 flow_match_sample_field_offset,
674 s->flow_match_sample_field_offset);
675 MLX5_SET(parse_graph_flow_match_sample, s_off,
676 flow_match_sample_offset_mode,
677 s->flow_match_sample_offset_mode);
678 MLX5_SET(parse_graph_flow_match_sample, s_off,
679 flow_match_sample_field_offset_mask,
680 s->flow_match_sample_field_offset_mask);
681 MLX5_SET(parse_graph_flow_match_sample, s_off,
682 flow_match_sample_field_offset_shift,
683 s->flow_match_sample_field_offset_shift);
684 MLX5_SET(parse_graph_flow_match_sample, s_off,
685 flow_match_sample_field_base_offset,
686 s->flow_match_sample_field_base_offset);
687 MLX5_SET(parse_graph_flow_match_sample, s_off,
688 flow_match_sample_tunnel_mode,
689 s->flow_match_sample_tunnel_mode);
691 for (i = 0; i < MLX5_GRAPH_NODE_ARC_NUM; i++) {
692 struct mlx5_devx_graph_arc_attr *ia = &data->in[i];
693 struct mlx5_devx_graph_arc_attr *oa = &data->out[i];
694 void *in_off = (void *)((char *)in_arc + i *
695 MLX5_ST_SZ_BYTES(parse_graph_arc));
696 void *out_off = (void *)((char *)out_arc + i *
697 MLX5_ST_SZ_BYTES(parse_graph_arc));
699 if (ia->arc_parse_graph_node != 0) {
700 MLX5_SET(parse_graph_arc, in_off,
701 compare_condition_value,
702 ia->compare_condition_value);
703 MLX5_SET(parse_graph_arc, in_off, start_inner_tunnel,
704 ia->start_inner_tunnel);
705 MLX5_SET(parse_graph_arc, in_off, arc_parse_graph_node,
706 ia->arc_parse_graph_node);
707 MLX5_SET(parse_graph_arc, in_off,
708 parse_graph_node_handle,
709 ia->parse_graph_node_handle);
711 if (oa->arc_parse_graph_node != 0) {
712 MLX5_SET(parse_graph_arc, out_off,
713 compare_condition_value,
714 oa->compare_condition_value);
715 MLX5_SET(parse_graph_arc, out_off, start_inner_tunnel,
716 oa->start_inner_tunnel);
717 MLX5_SET(parse_graph_arc, out_off, arc_parse_graph_node,
718 oa->arc_parse_graph_node);
719 MLX5_SET(parse_graph_arc, out_off,
720 parse_graph_node_handle,
721 oa->parse_graph_node_handle);
724 parse_flex_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
726 if (!parse_flex_obj->obj) {
728 DRV_LOG(ERR, "Failed to create FLEX PARSE GRAPH object "
730 mlx5_free(parse_flex_obj);
733 parse_flex_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
734 return parse_flex_obj;
738 mlx5_devx_cmd_query_hca_parse_graph_node_cap
739 (void *ctx, struct mlx5_hca_flex_attr *attr)
741 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)];
742 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)];
746 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
747 MLX5_GET_HCA_CAP_OP_MOD_PARSE_GRAPH_NODE_CAP |
748 MLX5_HCA_CAP_OPMOD_GET_CUR);
751 attr->node_in = MLX5_GET(parse_graph_node_cap, hcattr, node_in);
752 attr->node_out = MLX5_GET(parse_graph_node_cap, hcattr, node_out);
753 attr->header_length_mode = MLX5_GET(parse_graph_node_cap, hcattr,
755 attr->sample_offset_mode = MLX5_GET(parse_graph_node_cap, hcattr,
757 attr->max_num_arc_in = MLX5_GET(parse_graph_node_cap, hcattr,
759 attr->max_num_arc_out = MLX5_GET(parse_graph_node_cap, hcattr,
761 attr->max_num_sample = MLX5_GET(parse_graph_node_cap, hcattr,
763 attr->sample_id_in_out = MLX5_GET(parse_graph_node_cap, hcattr,
765 attr->max_base_header_length = MLX5_GET(parse_graph_node_cap, hcattr,
766 max_base_header_length);
767 attr->max_sample_base_offset = MLX5_GET(parse_graph_node_cap, hcattr,
768 max_sample_base_offset);
769 attr->max_next_header_offset = MLX5_GET(parse_graph_node_cap, hcattr,
770 max_next_header_offset);
771 attr->header_length_mask_width = MLX5_GET(parse_graph_node_cap, hcattr,
772 header_length_mask_width);
773 /* Get the max supported samples from HCA CAP 2 */
774 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
775 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 |
776 MLX5_HCA_CAP_OPMOD_GET_CUR);
779 attr->max_num_prog_sample =
780 MLX5_GET(cmd_hca_cap_2, hcattr, max_num_prog_sample_field);
785 mlx5_devx_query_pkt_integrity_match(void *hcattr)
787 return MLX5_GET(flow_table_nic_cap, hcattr,
788 ft_field_support_2_nic_receive.inner_l3_ok) &&
789 MLX5_GET(flow_table_nic_cap, hcattr,
790 ft_field_support_2_nic_receive.inner_l4_ok) &&
791 MLX5_GET(flow_table_nic_cap, hcattr,
792 ft_field_support_2_nic_receive.outer_l3_ok) &&
793 MLX5_GET(flow_table_nic_cap, hcattr,
794 ft_field_support_2_nic_receive.outer_l4_ok) &&
795 MLX5_GET(flow_table_nic_cap, hcattr,
796 ft_field_support_2_nic_receive
797 .inner_ipv4_checksum_ok) &&
798 MLX5_GET(flow_table_nic_cap, hcattr,
799 ft_field_support_2_nic_receive.inner_l4_checksum_ok) &&
800 MLX5_GET(flow_table_nic_cap, hcattr,
801 ft_field_support_2_nic_receive
802 .outer_ipv4_checksum_ok) &&
803 MLX5_GET(flow_table_nic_cap, hcattr,
804 ft_field_support_2_nic_receive.outer_l4_checksum_ok);
808 * Query HCA attributes.
809 * Using those attributes we can check on run time if the device
810 * is having the required capabilities.
813 * Context returned from mlx5 open_device() glue function.
815 * Attributes device values.
818 * 0 on success, a negative value otherwise.
821 mlx5_devx_cmd_query_hca_attr(void *ctx,
822 struct mlx5_hca_attr *attr)
824 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0};
825 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0};
826 uint64_t general_obj_types_supported = 0;
830 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
831 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE |
832 MLX5_HCA_CAP_OPMOD_GET_CUR);
835 attr->max_wqe_sz_sq = MLX5_GET(cmd_hca_cap, hcattr, max_wqe_sz_sq);
836 attr->flow_counter_bulk_alloc_bitmap =
837 MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc);
838 attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr,
840 attr->log_max_rmp = MLX5_GET(cmd_hca_cap, hcattr, log_max_rmp);
841 attr->mem_rq_rmp = MLX5_GET(cmd_hca_cap, hcattr, mem_rq_rmp);
842 attr->log_max_rqt_size = MLX5_GET(cmd_hca_cap, hcattr,
844 attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager);
845 attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin);
846 attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr,
847 log_max_hairpin_queues);
848 attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr,
849 log_max_hairpin_wq_data_sz);
850 attr->log_max_hairpin_num_packets = MLX5_GET
851 (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz);
852 attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id);
853 attr->relaxed_ordering_write = MLX5_GET(cmd_hca_cap, hcattr,
854 relaxed_ordering_write);
855 attr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr,
856 relaxed_ordering_read);
857 attr->access_register_user = MLX5_GET(cmd_hca_cap, hcattr,
858 access_register_user);
859 attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr,
861 attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt);
862 attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr,
863 flex_parser_protocols);
864 attr->max_geneve_tlv_options = MLX5_GET(cmd_hca_cap, hcattr,
865 max_geneve_tlv_options);
866 attr->max_geneve_tlv_option_data_len = MLX5_GET(cmd_hca_cap, hcattr,
867 max_geneve_tlv_option_data_len);
868 attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos);
869 attr->qos.flow_meter_aso_sup = !!(MLX5_GET64(cmd_hca_cap, hcattr,
871 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO);
872 attr->vdpa.valid = !!(MLX5_GET64(cmd_hca_cap, hcattr,
874 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q);
875 attr->vdpa.queue_counters_valid = !!(MLX5_GET64(cmd_hca_cap, hcattr,
877 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS);
878 attr->parse_graph_flex_node = !!(MLX5_GET64(cmd_hca_cap, hcattr,
880 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE);
881 attr->wqe_index_ignore = MLX5_GET(cmd_hca_cap, hcattr,
882 wqe_index_ignore_cap);
883 attr->cross_channel = MLX5_GET(cmd_hca_cap, hcattr, cd);
884 attr->non_wire_sq = MLX5_GET(cmd_hca_cap, hcattr, non_wire_sq);
885 attr->log_max_static_sq_wq = MLX5_GET(cmd_hca_cap, hcattr,
886 log_max_static_sq_wq);
887 attr->num_lag_ports = MLX5_GET(cmd_hca_cap, hcattr, num_lag_ports);
888 attr->dev_freq_khz = MLX5_GET(cmd_hca_cap, hcattr,
889 device_frequency_khz);
890 attr->scatter_fcs_w_decap_disable =
891 MLX5_GET(cmd_hca_cap, hcattr, scatter_fcs_w_decap_disable);
892 attr->roce = MLX5_GET(cmd_hca_cap, hcattr, roce);
893 attr->rq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, rq_ts_format);
894 attr->sq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, sq_ts_format);
895 attr->steering_format_version =
896 MLX5_GET(cmd_hca_cap, hcattr, steering_format_version);
897 attr->regexp_params = MLX5_GET(cmd_hca_cap, hcattr, regexp_params);
898 attr->regexp_version = MLX5_GET(cmd_hca_cap, hcattr, regexp_version);
899 attr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr,
900 regexp_num_of_engines);
901 /* Read the general_obj_types bitmap and extract the relevant bits. */
902 general_obj_types_supported = MLX5_GET64(cmd_hca_cap, hcattr,
904 attr->vdpa.valid = !!(general_obj_types_supported &
905 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q);
906 attr->vdpa.queue_counters_valid =
907 !!(general_obj_types_supported &
908 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS);
909 attr->parse_graph_flex_node =
910 !!(general_obj_types_supported &
911 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE);
912 attr->flow_hit_aso = !!(general_obj_types_supported &
913 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO);
914 attr->geneve_tlv_opt = !!(general_obj_types_supported &
915 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT);
916 attr->dek = !!(general_obj_types_supported &
917 MLX5_GENERAL_OBJ_TYPES_CAP_DEK);
918 attr->import_kek = !!(general_obj_types_supported &
919 MLX5_GENERAL_OBJ_TYPES_CAP_IMPORT_KEK);
920 attr->credential = !!(general_obj_types_supported &
921 MLX5_GENERAL_OBJ_TYPES_CAP_CREDENTIAL);
922 attr->crypto_login = !!(general_obj_types_supported &
923 MLX5_GENERAL_OBJ_TYPES_CAP_CRYPTO_LOGIN);
924 /* Add reading of other GENERAL_OBJ_TYPES_CAP bits above this line. */
925 attr->log_max_cq = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq);
926 attr->log_max_qp = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp);
927 attr->log_max_cq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq_sz);
928 attr->log_max_qp_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp_sz);
929 attr->log_max_mrw_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_mrw_sz);
930 attr->log_max_pd = MLX5_GET(cmd_hca_cap, hcattr, log_max_pd);
931 attr->log_max_srq = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq);
932 attr->log_max_srq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq_sz);
933 attr->reg_c_preserve =
934 MLX5_GET(cmd_hca_cap, hcattr, reg_c_preserve);
935 attr->mmo_regex_qp_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_qp);
936 attr->mmo_regex_sq_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_sq);
937 attr->mmo_dma_sq_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_sq);
938 attr->mmo_compress_sq_en = MLX5_GET(cmd_hca_cap, hcattr,
940 attr->mmo_decompress_sq_en = MLX5_GET(cmd_hca_cap, hcattr,
942 attr->mmo_dma_qp_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_qp);
943 attr->mmo_compress_qp_en = MLX5_GET(cmd_hca_cap, hcattr,
945 attr->mmo_decompress_qp_en = MLX5_GET(cmd_hca_cap, hcattr,
947 attr->compress_min_block_size = MLX5_GET(cmd_hca_cap, hcattr,
948 compress_min_block_size);
949 attr->log_max_mmo_dma = MLX5_GET(cmd_hca_cap, hcattr, log_dma_mmo_size);
950 attr->log_max_mmo_compress = MLX5_GET(cmd_hca_cap, hcattr,
951 log_compress_mmo_size);
952 attr->log_max_mmo_decompress = MLX5_GET(cmd_hca_cap, hcattr,
953 log_decompress_mmo_size);
954 attr->cqe_compression = MLX5_GET(cmd_hca_cap, hcattr, cqe_compression);
955 attr->mini_cqe_resp_flow_tag = MLX5_GET(cmd_hca_cap, hcattr,
956 mini_cqe_resp_flow_tag);
957 attr->mini_cqe_resp_l3_l4_tag = MLX5_GET(cmd_hca_cap, hcattr,
958 mini_cqe_resp_l3_l4_tag);
959 attr->umr_indirect_mkey_disabled =
960 MLX5_GET(cmd_hca_cap, hcattr, umr_indirect_mkey_disabled);
961 attr->umr_modify_entity_size_disabled =
962 MLX5_GET(cmd_hca_cap, hcattr, umr_modify_entity_size_disabled);
963 attr->crypto = MLX5_GET(cmd_hca_cap, hcattr, crypto);
965 attr->aes_xts = MLX5_GET(cmd_hca_cap, hcattr, aes_xts);
966 attr->ct_offload = !!(MLX5_GET64(cmd_hca_cap, hcattr,
968 MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD);
969 attr->rq_delay_drop = MLX5_GET(cmd_hca_cap, hcattr, rq_delay_drop);
971 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
972 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP |
973 MLX5_HCA_CAP_OPMOD_GET_CUR);
975 DRV_LOG(DEBUG, "Failed to query devx QOS capabilities");
978 attr->qos.flow_meter_old =
979 MLX5_GET(qos_cap, hcattr, flow_meter_old);
980 attr->qos.log_max_flow_meter =
981 MLX5_GET(qos_cap, hcattr, log_max_flow_meter);
982 attr->qos.flow_meter_reg_c_ids =
983 MLX5_GET(qos_cap, hcattr, flow_meter_reg_id);
984 attr->qos.flow_meter =
985 MLX5_GET(qos_cap, hcattr, flow_meter);
986 attr->qos.packet_pacing =
987 MLX5_GET(qos_cap, hcattr, packet_pacing);
988 attr->qos.wqe_rate_pp =
989 MLX5_GET(qos_cap, hcattr, wqe_rate_pp);
990 if (attr->qos.flow_meter_aso_sup) {
991 attr->qos.log_meter_aso_granularity =
992 MLX5_GET(qos_cap, hcattr,
993 log_meter_aso_granularity);
994 attr->qos.log_meter_aso_max_alloc =
995 MLX5_GET(qos_cap, hcattr,
996 log_meter_aso_max_alloc);
997 attr->qos.log_max_num_meter_aso =
998 MLX5_GET(qos_cap, hcattr,
999 log_max_num_meter_aso);
1003 * Flex item support needs max_num_prog_sample_field
1004 * from the Capabilities 2 table for PARSE_GRAPH_NODE
1006 if (attr->parse_graph_flex_node) {
1007 rc = mlx5_devx_cmd_query_hca_parse_graph_node_cap
1012 if (attr->vdpa.valid)
1013 mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa);
1014 if (!attr->eth_net_offloads)
1016 /* Query Flow Sampler Capability From FLow Table Properties Layout. */
1017 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1018 MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE |
1019 MLX5_HCA_CAP_OPMOD_GET_CUR);
1021 attr->log_max_ft_sampler_num = 0;
1024 attr->log_max_ft_sampler_num = MLX5_GET
1025 (flow_table_nic_cap, hcattr,
1026 flow_table_properties_nic_receive.log_max_ft_sampler_num);
1027 attr->flow.tunnel_header_0_1 = MLX5_GET
1028 (flow_table_nic_cap, hcattr,
1029 ft_field_support_2_nic_receive.tunnel_header_0_1);
1030 attr->pkt_integrity_match = mlx5_devx_query_pkt_integrity_match(hcattr);
1031 attr->inner_ipv4_ihl = MLX5_GET
1032 (flow_table_nic_cap, hcattr,
1033 ft_field_support_2_nic_receive.inner_ipv4_ihl);
1034 attr->outer_ipv4_ihl = MLX5_GET
1035 (flow_table_nic_cap, hcattr,
1036 ft_field_support_2_nic_receive.outer_ipv4_ihl);
1037 /* Query HCA offloads for Ethernet protocol. */
1038 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1039 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS |
1040 MLX5_HCA_CAP_OPMOD_GET_CUR);
1042 attr->eth_net_offloads = 0;
1045 attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps,
1046 hcattr, wqe_vlan_insert);
1047 attr->csum_cap = MLX5_GET(per_protocol_networking_offload_caps,
1049 attr->vlan_cap = MLX5_GET(per_protocol_networking_offload_caps,
1051 attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr,
1053 attr->max_lso_cap = MLX5_GET(per_protocol_networking_offload_caps,
1054 hcattr, max_lso_cap);
1055 attr->scatter_fcs = MLX5_GET(per_protocol_networking_offload_caps,
1056 hcattr, scatter_fcs);
1057 attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps,
1058 hcattr, tunnel_lro_gre);
1059 attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps,
1060 hcattr, tunnel_lro_vxlan);
1061 attr->swp = MLX5_GET(per_protocol_networking_offload_caps,
1063 attr->tunnel_stateless_gre =
1064 MLX5_GET(per_protocol_networking_offload_caps,
1065 hcattr, tunnel_stateless_gre);
1066 attr->tunnel_stateless_vxlan =
1067 MLX5_GET(per_protocol_networking_offload_caps,
1068 hcattr, tunnel_stateless_vxlan);
1069 attr->swp_csum = MLX5_GET(per_protocol_networking_offload_caps,
1071 attr->swp_lso = MLX5_GET(per_protocol_networking_offload_caps,
1073 attr->lro_max_msg_sz_mode = MLX5_GET
1074 (per_protocol_networking_offload_caps,
1075 hcattr, lro_max_msg_sz_mode);
1076 for (i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) {
1077 attr->lro_timer_supported_periods[i] =
1078 MLX5_GET(per_protocol_networking_offload_caps, hcattr,
1079 lro_timer_supported_periods[i]);
1081 attr->lro_min_mss_size = MLX5_GET(per_protocol_networking_offload_caps,
1082 hcattr, lro_min_mss_size);
1083 attr->tunnel_stateless_geneve_rx =
1084 MLX5_GET(per_protocol_networking_offload_caps,
1085 hcattr, tunnel_stateless_geneve_rx);
1086 attr->geneve_max_opt_len =
1087 MLX5_GET(per_protocol_networking_offload_caps,
1088 hcattr, max_geneve_opt_len);
1089 attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps,
1090 hcattr, wqe_inline_mode);
1091 attr->tunnel_stateless_gtp = MLX5_GET
1092 (per_protocol_networking_offload_caps,
1093 hcattr, tunnel_stateless_gtp);
1094 attr->rss_ind_tbl_cap = MLX5_GET
1095 (per_protocol_networking_offload_caps,
1096 hcattr, rss_ind_tbl_cap);
1097 /* Query HCA attribute for ROCE. */
1099 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1100 MLX5_GET_HCA_CAP_OP_MOD_ROCE |
1101 MLX5_HCA_CAP_OPMOD_GET_CUR);
1104 "Failed to query devx HCA ROCE capabilities");
1107 attr->qp_ts_format = MLX5_GET(roce_caps, hcattr, qp_ts_format);
1109 if (attr->eth_virt &&
1110 attr->wqe_inline_mode == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT) {
1111 rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr);
1119 rc = (rc > 0) ? -rc : rc;
1124 * Query TIS transport domain from QP verbs object using DevX API.
1127 * Pointer to verbs QP returned by ibv_create_qp .
1128 * @param[in] tis_num
1129 * TIS number of TIS to query.
1130 * @param[out] tis_td
1131 * Pointer to TIS transport domain variable, to be set by the routine.
1134 * 0 on success, a negative value otherwise.
1137 mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num,
1140 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
1141 uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0};
1142 uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0};
1146 MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS);
1147 MLX5_SET(query_tis_in, in, tisn, tis_num);
1148 rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out));
1150 DRV_LOG(ERR, "Failed to query QP using DevX");
1153 tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context);
1154 *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain);
1165 * Fill WQ data for DevX API command.
1166 * Utility function for use when creating DevX objects containing a WQ.
1169 * Pointer to WQ context to fill with data.
1170 * @param [in] wq_attr
1171 * Pointer to WQ attributes structure to fill in WQ context.
1174 devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr)
1176 MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type);
1177 MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature);
1178 MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode);
1179 MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave);
1180 MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge);
1181 MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size);
1182 MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset);
1183 MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm);
1184 MLX5_SET(wq, wq_ctx, pd, wq_attr->pd);
1185 MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page);
1186 MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr);
1187 MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter);
1188 MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter);
1189 MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride);
1190 if (wq_attr->log_wq_pg_sz > MLX5_ADAPTER_PAGE_SHIFT)
1191 MLX5_SET(wq, wq_ctx, log_wq_pg_sz,
1192 wq_attr->log_wq_pg_sz - MLX5_ADAPTER_PAGE_SHIFT);
1193 MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz);
1194 MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid);
1195 MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid);
1196 MLX5_SET(wq, wq_ctx, log_hairpin_num_packets,
1197 wq_attr->log_hairpin_num_packets);
1198 MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz);
1199 MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides,
1200 wq_attr->single_wqe_log_num_of_strides);
1201 MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en);
1202 MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes,
1203 wq_attr->single_stride_log_num_of_bytes);
1204 MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id);
1205 MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id);
1206 MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset);
1210 * Create RQ using DevX API.
1213 * Context returned from mlx5 open_device() glue function.
1214 * @param [in] rq_attr
1215 * Pointer to create RQ attributes structure.
1216 * @param [in] socket
1217 * CPU socket ID for allocations.
1220 * The DevX object created, NULL otherwise and rte_errno is set.
1222 struct mlx5_devx_obj *
1223 mlx5_devx_cmd_create_rq(void *ctx,
1224 struct mlx5_devx_create_rq_attr *rq_attr,
1227 uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0};
1228 uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0};
1229 void *rq_ctx, *wq_ctx;
1230 struct mlx5_devx_wq_attr *wq_attr;
1231 struct mlx5_devx_obj *rq = NULL;
1233 rq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rq), 0, socket);
1235 DRV_LOG(ERR, "Failed to allocate RQ data");
1239 MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ);
1240 rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx);
1241 MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky);
1242 MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en);
1243 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);
1244 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);
1245 MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type);
1246 MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
1247 MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en);
1248 MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin);
1249 MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index);
1250 MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn);
1251 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
1252 MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn);
1253 MLX5_SET(sqc, rq_ctx, ts_format, rq_attr->ts_format);
1254 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);
1255 wq_attr = &rq_attr->wq_attr;
1256 devx_cmd_fill_wq_data(wq_ctx, wq_attr);
1257 rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1260 DRV_LOG(ERR, "Failed to create RQ using DevX");
1265 rq->id = MLX5_GET(create_rq_out, out, rqn);
1270 * Modify RQ using DevX API.
1273 * Pointer to RQ object structure.
1274 * @param [in] rq_attr
1275 * Pointer to modify RQ attributes structure.
1278 * 0 on success, a negative errno value otherwise and rte_errno is set.
1281 mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,
1282 struct mlx5_devx_modify_rq_attr *rq_attr)
1284 uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0};
1285 uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0};
1286 void *rq_ctx, *wq_ctx;
1289 MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ);
1290 MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state);
1291 MLX5_SET(modify_rq_in, in, rqn, rq->id);
1292 MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask);
1293 rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1294 MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
1295 if (rq_attr->modify_bitmask &
1296 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS)
1297 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);
1298 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD)
1299 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);
1300 if (rq_attr->modify_bitmask &
1301 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID)
1302 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
1303 MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq);
1304 MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca);
1305 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) {
1306 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);
1307 MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm);
1309 ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in),
1312 DRV_LOG(ERR, "Failed to modify RQ using DevX");
1320 * Create RMP using DevX API.
1323 * Context returned from mlx5 open_device() glue function.
1324 * @param [in] rmp_attr
1325 * Pointer to create RMP attributes structure.
1326 * @param [in] socket
1327 * CPU socket ID for allocations.
1330 * The DevX object created, NULL otherwise and rte_errno is set.
1332 struct mlx5_devx_obj *
1333 mlx5_devx_cmd_create_rmp(void *ctx,
1334 struct mlx5_devx_create_rmp_attr *rmp_attr,
1337 uint32_t in[MLX5_ST_SZ_DW(create_rmp_in)] = {0};
1338 uint32_t out[MLX5_ST_SZ_DW(create_rmp_out)] = {0};
1339 void *rmp_ctx, *wq_ctx;
1340 struct mlx5_devx_wq_attr *wq_attr;
1341 struct mlx5_devx_obj *rmp = NULL;
1343 rmp = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rmp), 0, socket);
1345 DRV_LOG(ERR, "Failed to allocate RMP data");
1349 MLX5_SET(create_rmp_in, in, opcode, MLX5_CMD_OP_CREATE_RMP);
1350 rmp_ctx = MLX5_ADDR_OF(create_rmp_in, in, ctx);
1351 MLX5_SET(rmpc, rmp_ctx, state, rmp_attr->state);
1352 MLX5_SET(rmpc, rmp_ctx, basic_cyclic_rcv_wqe,
1353 rmp_attr->basic_cyclic_rcv_wqe);
1354 wq_ctx = MLX5_ADDR_OF(rmpc, rmp_ctx, wq);
1355 wq_attr = &rmp_attr->wq_attr;
1356 devx_cmd_fill_wq_data(wq_ctx, wq_attr);
1357 rmp->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
1360 DRV_LOG(ERR, "Failed to create RMP using DevX");
1365 rmp->id = MLX5_GET(create_rmp_out, out, rmpn);
1370 * Create TIR using DevX API.
1373 * Context returned from mlx5 open_device() glue function.
1374 * @param [in] tir_attr
1375 * Pointer to TIR attributes structure.
1378 * The DevX object created, NULL otherwise and rte_errno is set.
1380 struct mlx5_devx_obj *
1381 mlx5_devx_cmd_create_tir(void *ctx,
1382 struct mlx5_devx_tir_attr *tir_attr)
1384 uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
1385 uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0};
1386 void *tir_ctx, *outer, *inner, *rss_key;
1387 struct mlx5_devx_obj *tir = NULL;
1389 tir = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tir), 0, SOCKET_ID_ANY);
1391 DRV_LOG(ERR, "Failed to allocate TIR data");
1395 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR);
1396 tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx);
1397 MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type);
1398 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs,
1399 tir_attr->lro_timeout_period_usecs);
1400 MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask);
1401 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz);
1402 MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn);
1403 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric);
1404 MLX5_SET(tirc, tir_ctx, tunneled_offload_en,
1405 tir_attr->tunneled_offload_en);
1406 MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table);
1407 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn);
1408 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block);
1409 MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain);
1410 rss_key = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_toeplitz_key);
1411 memcpy(rss_key, tir_attr->rx_hash_toeplitz_key, MLX5_RSS_HASH_KEY_LEN);
1412 outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer);
1413 MLX5_SET(rx_hash_field_select, outer, l3_prot_type,
1414 tir_attr->rx_hash_field_selector_outer.l3_prot_type);
1415 MLX5_SET(rx_hash_field_select, outer, l4_prot_type,
1416 tir_attr->rx_hash_field_selector_outer.l4_prot_type);
1417 MLX5_SET(rx_hash_field_select, outer, selected_fields,
1418 tir_attr->rx_hash_field_selector_outer.selected_fields);
1419 inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner);
1420 MLX5_SET(rx_hash_field_select, inner, l3_prot_type,
1421 tir_attr->rx_hash_field_selector_inner.l3_prot_type);
1422 MLX5_SET(rx_hash_field_select, inner, l4_prot_type,
1423 tir_attr->rx_hash_field_selector_inner.l4_prot_type);
1424 MLX5_SET(rx_hash_field_select, inner, selected_fields,
1425 tir_attr->rx_hash_field_selector_inner.selected_fields);
1426 tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1429 DRV_LOG(ERR, "Failed to create TIR using DevX");
1434 tir->id = MLX5_GET(create_tir_out, out, tirn);
1439 * Modify TIR using DevX API.
1442 * Pointer to TIR DevX object structure.
1443 * @param [in] modify_tir_attr
1444 * Pointer to TIR modification attributes structure.
1447 * 0 on success, a negative errno value otherwise and rte_errno is set.
1450 mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir,
1451 struct mlx5_devx_modify_tir_attr *modify_tir_attr)
1453 struct mlx5_devx_tir_attr *tir_attr = &modify_tir_attr->tir;
1454 uint32_t in[MLX5_ST_SZ_DW(modify_tir_in)] = {0};
1455 uint32_t out[MLX5_ST_SZ_DW(modify_tir_out)] = {0};
1459 MLX5_SET(modify_tir_in, in, opcode, MLX5_CMD_OP_MODIFY_TIR);
1460 MLX5_SET(modify_tir_in, in, tirn, modify_tir_attr->tirn);
1461 MLX5_SET64(modify_tir_in, in, modify_bitmask,
1462 modify_tir_attr->modify_bitmask);
1463 tir_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1464 if (modify_tir_attr->modify_bitmask &
1465 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO) {
1466 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs,
1467 tir_attr->lro_timeout_period_usecs);
1468 MLX5_SET(tirc, tir_ctx, lro_enable_mask,
1469 tir_attr->lro_enable_mask);
1470 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz,
1471 tir_attr->lro_max_msg_sz);
1473 if (modify_tir_attr->modify_bitmask &
1474 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE)
1475 MLX5_SET(tirc, tir_ctx, indirect_table,
1476 tir_attr->indirect_table);
1477 if (modify_tir_attr->modify_bitmask &
1478 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH) {
1480 void *outer, *inner;
1482 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric,
1483 tir_attr->rx_hash_symmetric);
1484 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn);
1485 for (i = 0; i < 10; i++) {
1486 MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i],
1487 tir_attr->rx_hash_toeplitz_key[i]);
1489 outer = MLX5_ADDR_OF(tirc, tir_ctx,
1490 rx_hash_field_selector_outer);
1491 MLX5_SET(rx_hash_field_select, outer, l3_prot_type,
1492 tir_attr->rx_hash_field_selector_outer.l3_prot_type);
1493 MLX5_SET(rx_hash_field_select, outer, l4_prot_type,
1494 tir_attr->rx_hash_field_selector_outer.l4_prot_type);
1496 (rx_hash_field_select, outer, selected_fields,
1497 tir_attr->rx_hash_field_selector_outer.selected_fields);
1498 inner = MLX5_ADDR_OF(tirc, tir_ctx,
1499 rx_hash_field_selector_inner);
1500 MLX5_SET(rx_hash_field_select, inner, l3_prot_type,
1501 tir_attr->rx_hash_field_selector_inner.l3_prot_type);
1502 MLX5_SET(rx_hash_field_select, inner, l4_prot_type,
1503 tir_attr->rx_hash_field_selector_inner.l4_prot_type);
1505 (rx_hash_field_select, inner, selected_fields,
1506 tir_attr->rx_hash_field_selector_inner.selected_fields);
1508 if (modify_tir_attr->modify_bitmask &
1509 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN) {
1510 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block);
1512 ret = mlx5_glue->devx_obj_modify(tir->obj, in, sizeof(in),
1515 DRV_LOG(ERR, "Failed to modify TIR using DevX");
1523 * Create RQT using DevX API.
1526 * Context returned from mlx5 open_device() glue function.
1527 * @param [in] rqt_attr
1528 * Pointer to RQT attributes structure.
1531 * The DevX object created, NULL otherwise and rte_errno is set.
1533 struct mlx5_devx_obj *
1534 mlx5_devx_cmd_create_rqt(void *ctx,
1535 struct mlx5_devx_rqt_attr *rqt_attr)
1537 uint32_t *in = NULL;
1538 uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) +
1539 rqt_attr->rqt_actual_size * sizeof(uint32_t);
1540 uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0};
1542 struct mlx5_devx_obj *rqt = NULL;
1545 in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY);
1547 DRV_LOG(ERR, "Failed to allocate RQT IN data");
1551 rqt = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt), 0, SOCKET_ID_ANY);
1553 DRV_LOG(ERR, "Failed to allocate RQT data");
1558 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
1559 rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1560 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type);
1561 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size);
1562 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size);
1563 for (i = 0; i < rqt_attr->rqt_actual_size; i++)
1564 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]);
1565 rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out));
1568 DRV_LOG(ERR, "Failed to create RQT using DevX");
1573 rqt->id = MLX5_GET(create_rqt_out, out, rqtn);
1578 * Modify RQT using DevX API.
1581 * Pointer to RQT DevX object structure.
1582 * @param [in] rqt_attr
1583 * Pointer to RQT attributes structure.
1586 * 0 on success, a negative errno value otherwise and rte_errno is set.
1589 mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt,
1590 struct mlx5_devx_rqt_attr *rqt_attr)
1592 uint32_t inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) +
1593 rqt_attr->rqt_actual_size * sizeof(uint32_t);
1594 uint32_t out[MLX5_ST_SZ_DW(modify_rqt_out)] = {0};
1595 uint32_t *in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY);
1601 DRV_LOG(ERR, "Failed to allocate RQT modify IN data.");
1605 MLX5_SET(modify_rqt_in, in, opcode, MLX5_CMD_OP_MODIFY_RQT);
1606 MLX5_SET(modify_rqt_in, in, rqtn, rqt->id);
1607 MLX5_SET64(modify_rqt_in, in, modify_bitmask, 0x1);
1608 rqt_ctx = MLX5_ADDR_OF(modify_rqt_in, in, rqt_context);
1609 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type);
1610 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size);
1611 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size);
1612 for (i = 0; i < rqt_attr->rqt_actual_size; i++)
1613 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]);
1614 ret = mlx5_glue->devx_obj_modify(rqt->obj, in, inlen, out, sizeof(out));
1617 DRV_LOG(ERR, "Failed to modify RQT using DevX.");
1625 * Create SQ using DevX API.
1628 * Context returned from mlx5 open_device() glue function.
1629 * @param [in] sq_attr
1630 * Pointer to SQ attributes structure.
1631 * @param [in] socket
1632 * CPU socket ID for allocations.
1635 * The DevX object created, NULL otherwise and rte_errno is set.
1637 struct mlx5_devx_obj *
1638 mlx5_devx_cmd_create_sq(void *ctx,
1639 struct mlx5_devx_create_sq_attr *sq_attr)
1641 uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0};
1642 uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0};
1645 struct mlx5_devx_wq_attr *wq_attr;
1646 struct mlx5_devx_obj *sq = NULL;
1648 sq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sq), 0, SOCKET_ID_ANY);
1650 DRV_LOG(ERR, "Failed to allocate SQ data");
1654 MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ);
1655 sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx);
1656 MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky);
1657 MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master);
1658 MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre);
1659 MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en);
1660 MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe,
1661 sq_attr->allow_multi_pkt_send_wqe);
1662 MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode,
1663 sq_attr->min_wqe_inline_mode);
1664 MLX5_SET(sqc, sq_ctx, state, sq_attr->state);
1665 MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr);
1666 MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp);
1667 MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin);
1668 MLX5_SET(sqc, sq_ctx, non_wire, sq_attr->non_wire);
1669 MLX5_SET(sqc, sq_ctx, static_sq_wq, sq_attr->static_sq_wq);
1670 MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index);
1671 MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn);
1672 MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index,
1673 sq_attr->packet_pacing_rate_limit_index);
1674 MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz);
1675 MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num);
1676 MLX5_SET(sqc, sq_ctx, ts_format, sq_attr->ts_format);
1677 wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq);
1678 wq_attr = &sq_attr->wq_attr;
1679 devx_cmd_fill_wq_data(wq_ctx, wq_attr);
1680 sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1683 DRV_LOG(ERR, "Failed to create SQ using DevX");
1688 sq->id = MLX5_GET(create_sq_out, out, sqn);
1693 * Modify SQ using DevX API.
1696 * Pointer to SQ object structure.
1697 * @param [in] sq_attr
1698 * Pointer to SQ attributes structure.
1701 * 0 on success, a negative errno value otherwise and rte_errno is set.
1704 mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq,
1705 struct mlx5_devx_modify_sq_attr *sq_attr)
1707 uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0};
1708 uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0};
1712 MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ);
1713 MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state);
1714 MLX5_SET(modify_sq_in, in, sqn, sq->id);
1715 sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1716 MLX5_SET(sqc, sq_ctx, state, sq_attr->state);
1717 MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq);
1718 MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca);
1719 ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in),
1722 DRV_LOG(ERR, "Failed to modify SQ using DevX");
1730 * Create TIS using DevX API.
1733 * Context returned from mlx5 open_device() glue function.
1734 * @param [in] tis_attr
1735 * Pointer to TIS attributes structure.
1738 * The DevX object created, NULL otherwise and rte_errno is set.
1740 struct mlx5_devx_obj *
1741 mlx5_devx_cmd_create_tis(void *ctx,
1742 struct mlx5_devx_tis_attr *tis_attr)
1744 uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
1745 uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0};
1746 struct mlx5_devx_obj *tis = NULL;
1749 tis = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tis), 0, SOCKET_ID_ANY);
1751 DRV_LOG(ERR, "Failed to allocate TIS object");
1755 MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS);
1756 tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx);
1757 MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity,
1758 tis_attr->strict_lag_tx_port_affinity);
1759 MLX5_SET(tisc, tis_ctx, lag_tx_port_affinity,
1760 tis_attr->lag_tx_port_affinity);
1761 MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio);
1762 MLX5_SET(tisc, tis_ctx, transport_domain,
1763 tis_attr->transport_domain);
1764 tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1767 DRV_LOG(ERR, "Failed to create TIS using DevX");
1772 tis->id = MLX5_GET(create_tis_out, out, tisn);
1777 * Create transport domain using DevX API.
1780 * Context returned from mlx5 open_device() glue function.
1782 * The DevX object created, NULL otherwise and rte_errno is set.
1784 struct mlx5_devx_obj *
1785 mlx5_devx_cmd_create_td(void *ctx)
1787 uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0};
1788 uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0};
1789 struct mlx5_devx_obj *td = NULL;
1791 td = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*td), 0, SOCKET_ID_ANY);
1793 DRV_LOG(ERR, "Failed to allocate TD object");
1797 MLX5_SET(alloc_transport_domain_in, in, opcode,
1798 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN);
1799 td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1802 DRV_LOG(ERR, "Failed to create TIS using DevX");
1807 td->id = MLX5_GET(alloc_transport_domain_out, out,
1813 * Dump all flows to file.
1815 * @param[in] fdb_domain
1817 * @param[in] rx_domain
1819 * @param[in] tx_domain
1822 * Pointer to file stream.
1825 * 0 on success, a negative value otherwise.
1828 mlx5_devx_cmd_flow_dump(void *fdb_domain __rte_unused,
1829 void *rx_domain __rte_unused,
1830 void *tx_domain __rte_unused, FILE *file __rte_unused)
1834 #ifdef HAVE_MLX5_DR_FLOW_DUMP
1836 ret = mlx5_glue->dr_dump_domain(file, fdb_domain);
1840 MLX5_ASSERT(rx_domain);
1841 ret = mlx5_glue->dr_dump_domain(file, rx_domain);
1844 MLX5_ASSERT(tx_domain);
1845 ret = mlx5_glue->dr_dump_domain(file, tx_domain);
1853 mlx5_devx_cmd_flow_single_dump(void *rule_info __rte_unused,
1854 FILE *file __rte_unused)
1857 #ifdef HAVE_MLX5_DR_FLOW_DUMP_RULE
1859 ret = mlx5_glue->dr_dump_rule(file, rule_info);
1867 * Create CQ using DevX API.
1870 * Context returned from mlx5 open_device() glue function.
1872 * Pointer to CQ attributes structure.
1875 * The DevX object created, NULL otherwise and rte_errno is set.
1877 struct mlx5_devx_obj *
1878 mlx5_devx_cmd_create_cq(void *ctx, struct mlx5_devx_cq_attr *attr)
1880 uint32_t in[MLX5_ST_SZ_DW(create_cq_in)] = {0};
1881 uint32_t out[MLX5_ST_SZ_DW(create_cq_out)] = {0};
1882 struct mlx5_devx_obj *cq_obj = mlx5_malloc(MLX5_MEM_ZERO,
1885 void *cqctx = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1888 DRV_LOG(ERR, "Failed to allocate CQ object memory.");
1892 MLX5_SET(create_cq_in, in, opcode, MLX5_CMD_OP_CREATE_CQ);
1893 if (attr->db_umem_valid) {
1894 MLX5_SET(cqc, cqctx, dbr_umem_valid, attr->db_umem_valid);
1895 MLX5_SET(cqc, cqctx, dbr_umem_id, attr->db_umem_id);
1896 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_umem_offset);
1898 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_addr);
1900 MLX5_SET(cqc, cqctx, cqe_sz, (RTE_CACHE_LINE_SIZE == 128) ?
1901 MLX5_CQE_SIZE_128B : MLX5_CQE_SIZE_64B);
1902 MLX5_SET(cqc, cqctx, cc, attr->use_first_only);
1903 MLX5_SET(cqc, cqctx, oi, attr->overrun_ignore);
1904 MLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size);
1905 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT)
1906 MLX5_SET(cqc, cqctx, log_page_size,
1907 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT);
1908 MLX5_SET(cqc, cqctx, c_eqn, attr->eqn);
1909 MLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id);
1910 MLX5_SET(cqc, cqctx, cqe_comp_en, !!attr->cqe_comp_en);
1911 MLX5_SET(cqc, cqctx, mini_cqe_res_format, attr->mini_cqe_res_format);
1912 MLX5_SET(cqc, cqctx, mini_cqe_res_format_ext,
1913 attr->mini_cqe_res_format_ext);
1914 if (attr->q_umem_valid) {
1915 MLX5_SET(create_cq_in, in, cq_umem_valid, attr->q_umem_valid);
1916 MLX5_SET(create_cq_in, in, cq_umem_id, attr->q_umem_id);
1917 MLX5_SET64(create_cq_in, in, cq_umem_offset,
1918 attr->q_umem_offset);
1920 cq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
1924 DRV_LOG(ERR, "Failed to create CQ using DevX errno=%d.", errno);
1928 cq_obj->id = MLX5_GET(create_cq_out, out, cqn);
1933 * Create VIRTQ using DevX API.
1936 * Context returned from mlx5 open_device() glue function.
1938 * Pointer to VIRTQ attributes structure.
1941 * The DevX object created, NULL otherwise and rte_errno is set.
1943 struct mlx5_devx_obj *
1944 mlx5_devx_cmd_create_virtq(void *ctx,
1945 struct mlx5_devx_virtq_attr *attr)
1947 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0};
1948 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
1949 struct mlx5_devx_obj *virtq_obj = mlx5_malloc(MLX5_MEM_ZERO,
1952 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq);
1953 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr);
1954 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context);
1957 DRV_LOG(ERR, "Failed to allocate virtq data.");
1961 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
1962 MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
1963 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
1964 MLX5_GENERAL_OBJ_TYPE_VIRTQ);
1965 MLX5_SET16(virtio_net_q, virtq, hw_available_index,
1966 attr->hw_available_index);
1967 MLX5_SET16(virtio_net_q, virtq, hw_used_index, attr->hw_used_index);
1968 MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4);
1969 MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6);
1970 MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum);
1971 MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum);
1972 MLX5_SET16(virtio_q, virtctx, virtio_version_1_0,
1973 attr->virtio_version_1_0);
1974 MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode);
1975 MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id);
1976 MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr);
1977 MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr);
1978 MLX5_SET64(virtio_q, virtctx, available_addr, attr->available_addr);
1979 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index);
1980 MLX5_SET16(virtio_q, virtctx, queue_size, attr->q_size);
1981 MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey);
1982 MLX5_SET(virtio_q, virtctx, umem_1_id, attr->umems[0].id);
1983 MLX5_SET(virtio_q, virtctx, umem_1_size, attr->umems[0].size);
1984 MLX5_SET64(virtio_q, virtctx, umem_1_offset, attr->umems[0].offset);
1985 MLX5_SET(virtio_q, virtctx, umem_2_id, attr->umems[1].id);
1986 MLX5_SET(virtio_q, virtctx, umem_2_size, attr->umems[1].size);
1987 MLX5_SET64(virtio_q, virtctx, umem_2_offset, attr->umems[1].offset);
1988 MLX5_SET(virtio_q, virtctx, umem_3_id, attr->umems[2].id);
1989 MLX5_SET(virtio_q, virtctx, umem_3_size, attr->umems[2].size);
1990 MLX5_SET64(virtio_q, virtctx, umem_3_offset, attr->umems[2].offset);
1991 MLX5_SET(virtio_q, virtctx, counter_set_id, attr->counters_obj_id);
1992 MLX5_SET(virtio_q, virtctx, pd, attr->pd);
1993 MLX5_SET(virtio_q, virtctx, queue_period_mode, attr->hw_latency_mode);
1994 MLX5_SET(virtio_q, virtctx, queue_period_us, attr->hw_max_latency_us);
1995 MLX5_SET(virtio_q, virtctx, queue_max_count, attr->hw_max_pending_comp);
1996 MLX5_SET(virtio_net_q, virtq, tisn_or_qpn, attr->tis_id);
1997 virtq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
1999 if (!virtq_obj->obj) {
2001 DRV_LOG(ERR, "Failed to create VIRTQ Obj using DevX.");
2002 mlx5_free(virtq_obj);
2005 virtq_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2010 * Modify VIRTQ using DevX API.
2012 * @param[in] virtq_obj
2013 * Pointer to virtq object structure.
2015 * Pointer to modify virtq attributes structure.
2018 * 0 on success, a negative errno value otherwise and rte_errno is set.
2021 mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj,
2022 struct mlx5_devx_virtq_attr *attr)
2024 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0};
2025 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2026 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq);
2027 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr);
2028 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context);
2031 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2032 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT);
2033 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2034 MLX5_GENERAL_OBJ_TYPE_VIRTQ);
2035 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id);
2036 MLX5_SET64(virtio_net_q, virtq, modify_field_select, attr->type);
2037 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index);
2038 switch (attr->type) {
2039 case MLX5_VIRTQ_MODIFY_TYPE_STATE:
2040 MLX5_SET16(virtio_net_q, virtq, state, attr->state);
2042 case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS:
2043 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_mkey,
2044 attr->dirty_bitmap_mkey);
2045 MLX5_SET64(virtio_net_q, virtq, dirty_bitmap_addr,
2046 attr->dirty_bitmap_addr);
2047 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_size,
2048 attr->dirty_bitmap_size);
2050 case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE:
2051 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_dump_enable,
2052 attr->dirty_bitmap_dump_enable);
2058 ret = mlx5_glue->devx_obj_modify(virtq_obj->obj, in, sizeof(in),
2061 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX.");
2069 * Query VIRTQ using DevX API.
2071 * @param[in] virtq_obj
2072 * Pointer to virtq object structure.
2073 * @param [in/out] attr
2074 * Pointer to virtq attributes structure.
2077 * 0 on success, a negative errno value otherwise and rte_errno is set.
2080 mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj,
2081 struct mlx5_devx_virtq_attr *attr)
2083 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
2084 uint32_t out[MLX5_ST_SZ_DW(query_virtq_out)] = {0};
2085 void *hdr = MLX5_ADDR_OF(query_virtq_out, in, hdr);
2086 void *virtq = MLX5_ADDR_OF(query_virtq_out, out, virtq);
2089 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2090 MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
2091 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2092 MLX5_GENERAL_OBJ_TYPE_VIRTQ);
2093 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id);
2094 ret = mlx5_glue->devx_obj_query(virtq_obj->obj, in, sizeof(in),
2097 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX.");
2101 attr->hw_available_index = MLX5_GET16(virtio_net_q, virtq,
2102 hw_available_index);
2103 attr->hw_used_index = MLX5_GET16(virtio_net_q, virtq, hw_used_index);
2104 attr->state = MLX5_GET16(virtio_net_q, virtq, state);
2105 attr->error_type = MLX5_GET16(virtio_net_q, virtq,
2106 virtio_q_context.error_type);
2111 * Create QP using DevX API.
2114 * Context returned from mlx5 open_device() glue function.
2116 * Pointer to QP attributes structure.
2119 * The DevX object created, NULL otherwise and rte_errno is set.
2121 struct mlx5_devx_obj *
2122 mlx5_devx_cmd_create_qp(void *ctx,
2123 struct mlx5_devx_qp_attr *attr)
2125 uint32_t in[MLX5_ST_SZ_DW(create_qp_in)] = {0};
2126 uint32_t out[MLX5_ST_SZ_DW(create_qp_out)] = {0};
2127 struct mlx5_devx_obj *qp_obj = mlx5_malloc(MLX5_MEM_ZERO,
2130 void *qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
2133 DRV_LOG(ERR, "Failed to allocate QP data.");
2137 MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP);
2138 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC);
2139 MLX5_SET(qpc, qpc, pd, attr->pd);
2140 MLX5_SET(qpc, qpc, ts_format, attr->ts_format);
2141 MLX5_SET(qpc, qpc, user_index, attr->user_index);
2142 if (attr->uar_index) {
2144 void *qpc_ext_and_pas_list = MLX5_ADDR_OF(create_qp_in,
2145 in, qpc_extension_and_pas_list);
2146 void *qpc_ext = MLX5_ADDR_OF(qpc_extension_and_pas_list,
2147 qpc_ext_and_pas_list, qpc_data_extension);
2149 MLX5_SET(create_qp_in, in, qpc_ext, 1);
2150 MLX5_SET(qpc_extension, qpc_ext, mmo, 1);
2152 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
2153 MLX5_SET(qpc, qpc, uar_page, attr->uar_index);
2154 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT)
2155 MLX5_SET(qpc, qpc, log_page_size,
2156 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT);
2157 if (attr->num_of_send_wqbbs) {
2158 MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->num_of_send_wqbbs));
2159 MLX5_SET(qpc, qpc, cqn_snd, attr->cqn);
2160 MLX5_SET(qpc, qpc, log_sq_size,
2161 rte_log2_u32(attr->num_of_send_wqbbs));
2163 MLX5_SET(qpc, qpc, no_sq, 1);
2165 if (attr->num_of_receive_wqes) {
2166 MLX5_ASSERT(RTE_IS_POWER_OF_2(
2167 attr->num_of_receive_wqes));
2168 MLX5_SET(qpc, qpc, cqn_rcv, attr->cqn);
2169 MLX5_SET(qpc, qpc, log_rq_stride, attr->log_rq_stride -
2170 MLX5_LOG_RQ_STRIDE_SHIFT);
2171 MLX5_SET(qpc, qpc, log_rq_size,
2172 rte_log2_u32(attr->num_of_receive_wqes));
2173 MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ);
2175 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ);
2177 if (attr->dbr_umem_valid) {
2178 MLX5_SET(qpc, qpc, dbr_umem_valid,
2179 attr->dbr_umem_valid);
2180 MLX5_SET(qpc, qpc, dbr_umem_id, attr->dbr_umem_id);
2182 MLX5_SET64(qpc, qpc, dbr_addr, attr->dbr_address);
2183 MLX5_SET64(create_qp_in, in, wq_umem_offset,
2184 attr->wq_umem_offset);
2185 MLX5_SET(create_qp_in, in, wq_umem_id, attr->wq_umem_id);
2186 MLX5_SET(create_qp_in, in, wq_umem_valid, 1);
2188 /* Special QP to be managed by FW - no SQ\RQ\CQ\UAR\DB rec. */
2189 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ);
2190 MLX5_SET(qpc, qpc, no_sq, 1);
2192 qp_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
2196 DRV_LOG(ERR, "Failed to create QP Obj using DevX.");
2200 qp_obj->id = MLX5_GET(create_qp_out, out, qpn);
2205 * Modify QP using DevX API.
2206 * Currently supports only force loop-back QP.
2209 * Pointer to QP object structure.
2210 * @param [in] qp_st_mod_op
2211 * The QP state modification operation.
2212 * @param [in] remote_qp_id
2213 * The remote QP ID for MLX5_CMD_OP_INIT2RTR_QP operation.
2216 * 0 on success, a negative errno value otherwise and rte_errno is set.
2219 mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op,
2220 uint32_t remote_qp_id)
2223 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)];
2224 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)];
2225 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)];
2228 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)];
2229 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)];
2230 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)];
2235 unsigned int outlen;
2237 memset(&in, 0, sizeof(in));
2238 memset(&out, 0, sizeof(out));
2239 MLX5_SET(rst2init_qp_in, &in, opcode, qp_st_mod_op);
2240 switch (qp_st_mod_op) {
2241 case MLX5_CMD_OP_RST2INIT_QP:
2242 MLX5_SET(rst2init_qp_in, &in, qpn, qp->id);
2243 qpc = MLX5_ADDR_OF(rst2init_qp_in, &in, qpc);
2244 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1);
2245 MLX5_SET(qpc, qpc, rre, 1);
2246 MLX5_SET(qpc, qpc, rwe, 1);
2247 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
2248 inlen = sizeof(in.rst2init);
2249 outlen = sizeof(out.rst2init);
2251 case MLX5_CMD_OP_INIT2RTR_QP:
2252 MLX5_SET(init2rtr_qp_in, &in, qpn, qp->id);
2253 qpc = MLX5_ADDR_OF(init2rtr_qp_in, &in, qpc);
2254 MLX5_SET(qpc, qpc, primary_address_path.fl, 1);
2255 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1);
2256 MLX5_SET(qpc, qpc, mtu, 1);
2257 MLX5_SET(qpc, qpc, log_msg_max, 30);
2258 MLX5_SET(qpc, qpc, remote_qpn, remote_qp_id);
2259 MLX5_SET(qpc, qpc, min_rnr_nak, 0);
2260 inlen = sizeof(in.init2rtr);
2261 outlen = sizeof(out.init2rtr);
2263 case MLX5_CMD_OP_RTR2RTS_QP:
2264 qpc = MLX5_ADDR_OF(rtr2rts_qp_in, &in, qpc);
2265 MLX5_SET(rtr2rts_qp_in, &in, qpn, qp->id);
2266 MLX5_SET(qpc, qpc, primary_address_path.ack_timeout, 14);
2267 MLX5_SET(qpc, qpc, log_ack_req_freq, 0);
2268 MLX5_SET(qpc, qpc, retry_count, 7);
2269 MLX5_SET(qpc, qpc, rnr_retry, 7);
2270 inlen = sizeof(in.rtr2rts);
2271 outlen = sizeof(out.rtr2rts);
2274 DRV_LOG(ERR, "Invalid or unsupported QP modify op %u.",
2279 ret = mlx5_glue->devx_obj_modify(qp->obj, &in, inlen, &out, outlen);
2281 DRV_LOG(ERR, "Failed to modify QP using DevX.");
2288 struct mlx5_devx_obj *
2289 mlx5_devx_cmd_create_virtio_q_counters(void *ctx)
2291 uint32_t in[MLX5_ST_SZ_DW(create_virtio_q_counters_in)] = {0};
2292 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2293 struct mlx5_devx_obj *couners_obj = mlx5_malloc(MLX5_MEM_ZERO,
2294 sizeof(*couners_obj), 0,
2296 void *hdr = MLX5_ADDR_OF(create_virtio_q_counters_in, in, hdr);
2299 DRV_LOG(ERR, "Failed to allocate virtio queue counters data.");
2303 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2304 MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2305 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2306 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS);
2307 couners_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
2309 if (!couners_obj->obj) {
2311 DRV_LOG(ERR, "Failed to create virtio queue counters Obj using"
2313 mlx5_free(couners_obj);
2316 couners_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2321 mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj,
2322 struct mlx5_devx_virtio_q_couners_attr *attr)
2324 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
2325 uint32_t out[MLX5_ST_SZ_DW(query_virtio_q_counters_out)] = {0};
2326 void *hdr = MLX5_ADDR_OF(query_virtio_q_counters_out, in, hdr);
2327 void *virtio_q_counters = MLX5_ADDR_OF(query_virtio_q_counters_out, out,
2331 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2332 MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
2333 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2334 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS);
2335 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, couners_obj->id);
2336 ret = mlx5_glue->devx_obj_query(couners_obj->obj, in, sizeof(in), out,
2339 DRV_LOG(ERR, "Failed to query virtio q counters using DevX.");
2343 attr->received_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters,
2345 attr->completed_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters,
2347 attr->error_cqes = MLX5_GET(virtio_q_counters, virtio_q_counters,
2349 attr->bad_desc_errors = MLX5_GET(virtio_q_counters, virtio_q_counters,
2351 attr->exceed_max_chain = MLX5_GET(virtio_q_counters, virtio_q_counters,
2353 attr->invalid_buffer = MLX5_GET(virtio_q_counters, virtio_q_counters,
2359 * Create general object of type FLOW_HIT_ASO using DevX API.
2362 * Context returned from mlx5 open_device() glue function.
2364 * PD value to associate the FLOW_HIT_ASO object with.
2367 * The DevX object created, NULL otherwise and rte_errno is set.
2369 struct mlx5_devx_obj *
2370 mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, uint32_t pd)
2372 uint32_t in[MLX5_ST_SZ_DW(create_flow_hit_aso_in)] = {0};
2373 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2374 struct mlx5_devx_obj *flow_hit_aso_obj = NULL;
2377 flow_hit_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*flow_hit_aso_obj),
2379 if (!flow_hit_aso_obj) {
2380 DRV_LOG(ERR, "Failed to allocate FLOW_HIT_ASO object data");
2384 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, hdr);
2385 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2386 MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2387 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2388 MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO);
2389 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, flow_hit_aso);
2390 MLX5_SET(flow_hit_aso, ptr, access_pd, pd);
2391 flow_hit_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2393 if (!flow_hit_aso_obj->obj) {
2395 DRV_LOG(ERR, "Failed to create FLOW_HIT_ASO obj using DevX.");
2396 mlx5_free(flow_hit_aso_obj);
2399 flow_hit_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2400 return flow_hit_aso_obj;
2404 * Create PD using DevX API.
2407 * Context returned from mlx5 open_device() glue function.
2410 * The DevX object created, NULL otherwise and rte_errno is set.
2412 struct mlx5_devx_obj *
2413 mlx5_devx_cmd_alloc_pd(void *ctx)
2415 struct mlx5_devx_obj *ppd =
2416 mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ppd), 0, SOCKET_ID_ANY);
2417 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {0};
2418 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {0};
2421 DRV_LOG(ERR, "Failed to allocate PD data.");
2425 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD);
2426 ppd->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2430 DRV_LOG(ERR, "Failed to allocate PD Obj using DevX.");
2434 ppd->id = MLX5_GET(alloc_pd_out, out, pd);
2439 * Create general object of type FLOW_METER_ASO using DevX API.
2442 * Context returned from mlx5 open_device() glue function.
2444 * PD value to associate the FLOW_METER_ASO object with.
2445 * @param [in] log_obj_size
2446 * log_obj_size define to allocate number of 2 * meters
2447 * in one FLOW_METER_ASO object.
2450 * The DevX object created, NULL otherwise and rte_errno is set.
2452 struct mlx5_devx_obj *
2453 mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx, uint32_t pd,
2454 uint32_t log_obj_size)
2456 uint32_t in[MLX5_ST_SZ_DW(create_flow_meter_aso_in)] = {0};
2457 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)];
2458 struct mlx5_devx_obj *flow_meter_aso_obj;
2461 flow_meter_aso_obj = mlx5_malloc(MLX5_MEM_ZERO,
2462 sizeof(*flow_meter_aso_obj),
2464 if (!flow_meter_aso_obj) {
2465 DRV_LOG(ERR, "Failed to allocate FLOW_METER_ASO object data");
2469 ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, hdr);
2470 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2471 MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2472 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2473 MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO);
2474 MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range,
2476 ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, flow_meter_aso);
2477 MLX5_SET(flow_meter_aso, ptr, access_pd, pd);
2478 flow_meter_aso_obj->obj = mlx5_glue->devx_obj_create(
2479 ctx, in, sizeof(in),
2481 if (!flow_meter_aso_obj->obj) {
2483 DRV_LOG(ERR, "Failed to create FLOW_METER_ASO obj using DevX.");
2484 mlx5_free(flow_meter_aso_obj);
2487 flow_meter_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr,
2489 return flow_meter_aso_obj;
2493 * Create general object of type CONN_TRACK_OFFLOAD using DevX API.
2496 * Context returned from mlx5 open_device() glue function.
2498 * PD value to associate the CONN_TRACK_OFFLOAD ASO object with.
2499 * @param [in] log_obj_size
2500 * log_obj_size to allocate its power of 2 * objects
2501 * in one CONN_TRACK_OFFLOAD bulk allocation.
2504 * The DevX object created, NULL otherwise and rte_errno is set.
2506 struct mlx5_devx_obj *
2507 mlx5_devx_cmd_create_conn_track_offload_obj(void *ctx, uint32_t pd,
2508 uint32_t log_obj_size)
2510 uint32_t in[MLX5_ST_SZ_DW(create_conn_track_aso_in)] = {0};
2511 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)];
2512 struct mlx5_devx_obj *ct_aso_obj;
2515 ct_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ct_aso_obj),
2518 DRV_LOG(ERR, "Failed to allocate CONN_TRACK_OFFLOAD object.");
2522 ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, hdr);
2523 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2524 MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2525 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2526 MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD);
2527 MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range, log_obj_size);
2528 ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, conn_track_offload);
2529 MLX5_SET(conn_track_offload, ptr, conn_track_aso_access_pd, pd);
2530 ct_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2532 if (!ct_aso_obj->obj) {
2534 DRV_LOG(ERR, "Failed to create CONN_TRACK_OFFLOAD obj by using DevX.");
2535 mlx5_free(ct_aso_obj);
2538 ct_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2543 * Create general object of type GENEVE TLV option using DevX API.
2546 * Context returned from mlx5 open_device() glue function.
2548 * TLV option variable value of class
2550 * TLV option variable value of type
2552 * TLV option variable value of len
2555 * The DevX object created, NULL otherwise and rte_errno is set.
2557 struct mlx5_devx_obj *
2558 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx,
2559 uint16_t class, uint8_t type, uint8_t len)
2561 uint32_t in[MLX5_ST_SZ_DW(create_geneve_tlv_option_in)] = {0};
2562 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2563 struct mlx5_devx_obj *geneve_tlv_opt_obj = mlx5_malloc(MLX5_MEM_ZERO,
2564 sizeof(*geneve_tlv_opt_obj),
2567 if (!geneve_tlv_opt_obj) {
2568 DRV_LOG(ERR, "Failed to allocate geneve tlv option object.");
2572 void *hdr = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, hdr);
2573 void *opt = MLX5_ADDR_OF(create_geneve_tlv_option_in, in,
2575 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2576 MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2577 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2578 MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT);
2579 MLX5_SET(geneve_tlv_option, opt, option_class,
2580 rte_be_to_cpu_16(class));
2581 MLX5_SET(geneve_tlv_option, opt, option_type, type);
2582 MLX5_SET(geneve_tlv_option, opt, option_data_length, len);
2583 geneve_tlv_opt_obj->obj = mlx5_glue->devx_obj_create(ctx, in,
2584 sizeof(in), out, sizeof(out));
2585 if (!geneve_tlv_opt_obj->obj) {
2587 DRV_LOG(ERR, "Failed to create Geneve tlv option "
2589 mlx5_free(geneve_tlv_opt_obj);
2592 geneve_tlv_opt_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2593 return geneve_tlv_opt_obj;
2597 mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id)
2599 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2600 uint32_t in[MLX5_ST_SZ_DW(query_rq_in)] = {0};
2601 uint32_t out[MLX5_ST_SZ_DW(query_rq_out)] = {0};
2605 MLX5_SET(query_rq_in, in, opcode, MLX5_CMD_OP_QUERY_RQ);
2606 MLX5_SET(query_rq_in, in, rqn, ((struct ibv_wq *)wq)->wq_num);
2607 rc = mlx5_glue->devx_wq_query(wq, in, sizeof(in), out, sizeof(out));
2610 DRV_LOG(ERR, "Failed to query WQ counter set ID using DevX - "
2611 "rc = %d, errno = %d.", rc, errno);
2614 rq_ctx = MLX5_ADDR_OF(query_rq_out, out, rq_context);
2615 *counter_set_id = MLX5_GET(rqc, rq_ctx, counter_set_id);
2619 (void)counter_set_id;
2625 * Allocate queue counters via devx interface.
2628 * Context returned from mlx5 open_device() glue function.
2631 * Pointer to counter object on success, a NULL value otherwise and
2634 struct mlx5_devx_obj *
2635 mlx5_devx_cmd_queue_counter_alloc(void *ctx)
2637 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 0,
2639 uint32_t in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {0};
2640 uint32_t out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {0};
2646 MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER);
2647 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
2650 DRV_LOG(DEBUG, "Can't allocate q counter set by DevX - error "
2656 dcs->id = MLX5_GET(alloc_q_counter_out, out, counter_set_id);
2661 * Query queue counters values.
2664 * devx object of the queue counter set.
2666 * Whether hardware should clear the counters after the query or not.
2667 * @param[out] out_of_buffers
2668 * Number of dropped occurred due to lack of WQE for the associated QPs/RQs.
2671 * 0 on success, a negative value otherwise.
2674 mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear,
2675 uint32_t *out_of_buffers)
2677 uint32_t out[MLX5_ST_SZ_BYTES(query_q_counter_out)] = {0};
2678 uint32_t in[MLX5_ST_SZ_DW(query_q_counter_in)] = {0};
2681 MLX5_SET(query_q_counter_in, in, opcode,
2682 MLX5_CMD_OP_QUERY_Q_COUNTER);
2683 MLX5_SET(query_q_counter_in, in, op_mod, 0);
2684 MLX5_SET(query_q_counter_in, in, counter_set_id, dcs->id);
2685 MLX5_SET(query_q_counter_in, in, clear, !!clear);
2686 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out,
2689 DRV_LOG(ERR, "Failed to query devx q counter set - rc %d", rc);
2693 *out_of_buffers = MLX5_GET(query_q_counter_out, out, out_of_buffer);
2698 * Create general object of type DEK using DevX API.
2701 * Context returned from mlx5 open_device() glue function.
2703 * Pointer to DEK attributes structure.
2706 * The DevX object created, NULL otherwise and rte_errno is set.
2708 struct mlx5_devx_obj *
2709 mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr)
2711 uint32_t in[MLX5_ST_SZ_DW(create_dek_in)] = {0};
2712 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2713 struct mlx5_devx_obj *dek_obj = NULL;
2714 void *ptr = NULL, *key_addr = NULL;
2716 dek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dek_obj),
2718 if (dek_obj == NULL) {
2719 DRV_LOG(ERR, "Failed to allocate DEK object data");
2723 ptr = MLX5_ADDR_OF(create_dek_in, in, hdr);
2724 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2725 MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2726 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2727 MLX5_GENERAL_OBJ_TYPE_DEK);
2728 ptr = MLX5_ADDR_OF(create_dek_in, in, dek);
2729 MLX5_SET(dek, ptr, key_size, attr->key_size);
2730 MLX5_SET(dek, ptr, has_keytag, attr->has_keytag);
2731 MLX5_SET(dek, ptr, key_purpose, attr->key_purpose);
2732 MLX5_SET(dek, ptr, pd, attr->pd);
2733 MLX5_SET64(dek, ptr, opaque, attr->opaque);
2734 key_addr = MLX5_ADDR_OF(dek, ptr, key);
2735 memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE);
2736 dek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2738 if (dek_obj->obj == NULL) {
2740 DRV_LOG(ERR, "Failed to create DEK obj using DevX.");
2744 dek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2749 * Create general object of type IMPORT_KEK using DevX API.
2752 * Context returned from mlx5 open_device() glue function.
2754 * Pointer to IMPORT_KEK attributes structure.
2757 * The DevX object created, NULL otherwise and rte_errno is set.
2759 struct mlx5_devx_obj *
2760 mlx5_devx_cmd_create_import_kek_obj(void *ctx,
2761 struct mlx5_devx_import_kek_attr *attr)
2763 uint32_t in[MLX5_ST_SZ_DW(create_import_kek_in)] = {0};
2764 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2765 struct mlx5_devx_obj *import_kek_obj = NULL;
2766 void *ptr = NULL, *key_addr = NULL;
2768 import_kek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*import_kek_obj),
2770 if (import_kek_obj == NULL) {
2771 DRV_LOG(ERR, "Failed to allocate IMPORT_KEK object data");
2775 ptr = MLX5_ADDR_OF(create_import_kek_in, in, hdr);
2776 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2777 MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2778 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2779 MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK);
2780 ptr = MLX5_ADDR_OF(create_import_kek_in, in, import_kek);
2781 MLX5_SET(import_kek, ptr, key_size, attr->key_size);
2782 key_addr = MLX5_ADDR_OF(import_kek, ptr, key);
2783 memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE);
2784 import_kek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2786 if (import_kek_obj->obj == NULL) {
2788 DRV_LOG(ERR, "Failed to create IMPORT_KEK object using DevX.");
2789 mlx5_free(import_kek_obj);
2792 import_kek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2793 return import_kek_obj;
2797 * Create general object of type CREDENTIAL using DevX API.
2800 * Context returned from mlx5 open_device() glue function.
2802 * Pointer to CREDENTIAL attributes structure.
2805 * The DevX object created, NULL otherwise and rte_errno is set.
2807 struct mlx5_devx_obj *
2808 mlx5_devx_cmd_create_credential_obj(void *ctx,
2809 struct mlx5_devx_credential_attr *attr)
2811 uint32_t in[MLX5_ST_SZ_DW(create_credential_in)] = {0};
2812 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2813 struct mlx5_devx_obj *credential_obj = NULL;
2814 void *ptr = NULL, *credential_addr = NULL;
2816 credential_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*credential_obj),
2818 if (credential_obj == NULL) {
2819 DRV_LOG(ERR, "Failed to allocate CREDENTIAL object data");
2823 ptr = MLX5_ADDR_OF(create_credential_in, in, hdr);
2824 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2825 MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2826 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2827 MLX5_GENERAL_OBJ_TYPE_CREDENTIAL);
2828 ptr = MLX5_ADDR_OF(create_credential_in, in, credential);
2829 MLX5_SET(credential, ptr, credential_role, attr->credential_role);
2830 credential_addr = MLX5_ADDR_OF(credential, ptr, credential);
2831 memcpy(credential_addr, (void *)(attr->credential),
2832 MLX5_CRYPTO_CREDENTIAL_SIZE);
2833 credential_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2835 if (credential_obj->obj == NULL) {
2837 DRV_LOG(ERR, "Failed to create CREDENTIAL object using DevX.");
2838 mlx5_free(credential_obj);
2841 credential_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2842 return credential_obj;
2846 * Create general object of type CRYPTO_LOGIN using DevX API.
2849 * Context returned from mlx5 open_device() glue function.
2851 * Pointer to CRYPTO_LOGIN attributes structure.
2854 * The DevX object created, NULL otherwise and rte_errno is set.
2856 struct mlx5_devx_obj *
2857 mlx5_devx_cmd_create_crypto_login_obj(void *ctx,
2858 struct mlx5_devx_crypto_login_attr *attr)
2860 uint32_t in[MLX5_ST_SZ_DW(create_crypto_login_in)] = {0};
2861 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2862 struct mlx5_devx_obj *crypto_login_obj = NULL;
2863 void *ptr = NULL, *credential_addr = NULL;
2865 crypto_login_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*crypto_login_obj),
2867 if (crypto_login_obj == NULL) {
2868 DRV_LOG(ERR, "Failed to allocate CRYPTO_LOGIN object data");
2872 ptr = MLX5_ADDR_OF(create_crypto_login_in, in, hdr);
2873 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2874 MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2875 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2876 MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN);
2877 ptr = MLX5_ADDR_OF(create_crypto_login_in, in, crypto_login);
2878 MLX5_SET(crypto_login, ptr, credential_pointer,
2879 attr->credential_pointer);
2880 MLX5_SET(crypto_login, ptr, session_import_kek_ptr,
2881 attr->session_import_kek_ptr);
2882 credential_addr = MLX5_ADDR_OF(crypto_login, ptr, credential);
2883 memcpy(credential_addr, (void *)(attr->credential),
2884 MLX5_CRYPTO_CREDENTIAL_SIZE);
2885 crypto_login_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2887 if (crypto_login_obj->obj == NULL) {
2889 DRV_LOG(ERR, "Failed to create CRYPTO_LOGIN obj using DevX.");
2890 mlx5_free(crypto_login_obj);
2893 crypto_login_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2894 return crypto_login_obj;
2898 * Query LAG context.
2901 * Pointer to ibv_context, returned from mlx5dv_open_device.
2902 * @param[out] lag_ctx
2903 * Pointer to struct mlx5_devx_lag_context, to be set by the routine.
2906 * 0 on success, a negative value otherwise.
2909 mlx5_devx_cmd_query_lag(void *ctx,
2910 struct mlx5_devx_lag_context *lag_ctx)
2912 uint32_t in[MLX5_ST_SZ_DW(query_lag_in)] = {0};
2913 uint32_t out[MLX5_ST_SZ_DW(query_lag_out)] = {0};
2917 MLX5_SET(query_lag_in, in, opcode, MLX5_CMD_OP_QUERY_LAG);
2918 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
2921 lctx = MLX5_ADDR_OF(query_lag_out, out, context);
2922 lag_ctx->fdb_selection_mode = MLX5_GET(lag_context, lctx,
2923 fdb_selection_mode);
2924 lag_ctx->port_select_mode = MLX5_GET(lag_context, lctx,
2926 lag_ctx->lag_state = MLX5_GET(lag_context, lctx, lag_state);
2927 lag_ctx->tx_remap_affinity_2 = MLX5_GET(lag_context, lctx,
2928 tx_remap_affinity_2);
2929 lag_ctx->tx_remap_affinity_1 = MLX5_GET(lag_context, lctx,
2930 tx_remap_affinity_1);
2933 rc = (rc > 0) ? -rc : rc;