1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
8 #include <rte_malloc.h>
9 #include <rte_eal_paging.h>
12 #include "mlx5_devx_cmds.h"
13 #include "mlx5_common_log.h"
14 #include "mlx5_malloc.h"
17 mlx5_devx_get_hca_cap(void *ctx, uint32_t *in, uint32_t *out,
18 int *err, uint32_t flags)
20 const size_t size_in = MLX5_ST_SZ_DW(query_hca_cap_in) * sizeof(int);
21 const size_t size_out = MLX5_ST_SZ_DW(query_hca_cap_out) * sizeof(int);
22 int status, syndrome, rc;
26 memset(in, 0, size_in);
27 memset(out, 0, size_out);
28 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
29 MLX5_SET(query_hca_cap_in, in, op_mod, flags);
30 rc = mlx5_glue->devx_general_cmd(ctx, in, size_in, out, size_out);
33 "Failed to query devx HCA capabilities func %#02x",
36 *err = rc > 0 ? -rc : rc;
39 status = MLX5_GET(query_hca_cap_out, out, status);
40 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
43 "Failed to query devx HCA capabilities func %#02x status %x, syndrome = %x",
44 flags >> 1, status, syndrome);
49 return MLX5_ADDR_OF(query_hca_cap_out, out, capability);
53 * Perform read access to the registers. Reads data from register
54 * and writes ones to the specified buffer.
57 * Context returned from mlx5 open_device() glue function.
59 * Register identifier according to the PRM.
61 * Register access auxiliary parameter according to the PRM.
63 * Pointer to the buffer to store read data.
65 * Buffer size in double words.
68 * 0 on success, a negative value otherwise.
71 mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg,
72 uint32_t *data, uint32_t dw_cnt)
74 uint32_t in[MLX5_ST_SZ_DW(access_register_in)] = {0};
75 uint32_t out[MLX5_ST_SZ_DW(access_register_out) +
76 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0};
79 MLX5_ASSERT(data && dw_cnt);
80 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX);
81 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) {
82 DRV_LOG(ERR, "Not enough buffer for register read data");
85 MLX5_SET(access_register_in, in, opcode,
86 MLX5_CMD_OP_ACCESS_REGISTER_USER);
87 MLX5_SET(access_register_in, in, op_mod,
88 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ);
89 MLX5_SET(access_register_in, in, register_id, reg_id);
90 MLX5_SET(access_register_in, in, argument, arg);
91 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out,
92 MLX5_ST_SZ_BYTES(access_register_out) +
93 sizeof(uint32_t) * dw_cnt);
96 status = MLX5_GET(access_register_out, out, status);
98 int syndrome = MLX5_GET(access_register_out, out, syndrome);
100 DRV_LOG(DEBUG, "Failed to read access NIC register 0x%X, "
101 "status %x, syndrome = %x",
102 reg_id, status, syndrome);
105 memcpy(data, &out[MLX5_ST_SZ_DW(access_register_out)],
106 dw_cnt * sizeof(uint32_t));
109 rc = (rc > 0) ? -rc : rc;
114 * Perform write access to the registers.
117 * Context returned from mlx5 open_device() glue function.
119 * Register identifier according to the PRM.
121 * Register access auxiliary parameter according to the PRM.
123 * Pointer to the buffer containing data to write.
125 * Buffer size in double words (32bit units).
128 * 0 on success, a negative value otherwise.
131 mlx5_devx_cmd_register_write(void *ctx, uint16_t reg_id, uint32_t arg,
132 uint32_t *data, uint32_t dw_cnt)
134 uint32_t in[MLX5_ST_SZ_DW(access_register_in) +
135 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0};
136 uint32_t out[MLX5_ST_SZ_DW(access_register_out)] = {0};
140 MLX5_ASSERT(data && dw_cnt);
141 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX);
142 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) {
143 DRV_LOG(ERR, "Data to write exceeds max size");
146 MLX5_SET(access_register_in, in, opcode,
147 MLX5_CMD_OP_ACCESS_REGISTER_USER);
148 MLX5_SET(access_register_in, in, op_mod,
149 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE);
150 MLX5_SET(access_register_in, in, register_id, reg_id);
151 MLX5_SET(access_register_in, in, argument, arg);
152 ptr = MLX5_ADDR_OF(access_register_in, in, register_data);
153 memcpy(ptr, data, dw_cnt * sizeof(uint32_t));
154 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
156 rc = mlx5_glue->devx_general_cmd(ctx, in,
157 MLX5_ST_SZ_BYTES(access_register_in) +
158 dw_cnt * sizeof(uint32_t),
162 status = MLX5_GET(access_register_out, out, status);
164 int syndrome = MLX5_GET(access_register_out, out, syndrome);
166 DRV_LOG(DEBUG, "Failed to write access NIC register 0x%X, "
167 "status %x, syndrome = %x",
168 reg_id, status, syndrome);
173 rc = (rc > 0) ? -rc : rc;
178 * Allocate flow counters via devx interface.
181 * Context returned from mlx5 open_device() glue function.
183 * Pointer to counters properties structure to be filled by the routine.
185 * Bulk counter numbers in 128 counters units.
188 * Pointer to counter object on success, a negative value otherwise and
191 struct mlx5_devx_obj *
192 mlx5_devx_cmd_flow_counter_alloc(void *ctx, uint32_t bulk_n_128)
194 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs),
196 uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0};
197 uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0};
203 MLX5_SET(alloc_flow_counter_in, in, opcode,
204 MLX5_CMD_OP_ALLOC_FLOW_COUNTER);
205 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128);
206 dcs->obj = mlx5_glue->devx_obj_create(ctx, in,
207 sizeof(in), out, sizeof(out));
209 DRV_LOG(ERR, "Can't allocate counters - error %d", errno);
214 dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id);
219 * Query flow counters values.
222 * devx object that was obtained from mlx5_devx_cmd_fc_alloc.
224 * Whether hardware should clear the counters after the query or not.
225 * @param[in] n_counters
226 * 0 in case of 1 counter to read, otherwise the counter number to read.
228 * The number of packets that matched the flow.
230 * The number of bytes that matched the flow.
232 * The mkey key for batch query.
234 * The address in the mkey range for batch query.
236 * The completion object for asynchronous batch query.
238 * The ID to be returned in the asynchronous batch query response.
241 * 0 on success, a negative value otherwise.
244 mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs,
245 int clear, uint32_t n_counters,
246 uint64_t *pkts, uint64_t *bytes,
247 uint32_t mkey, void *addr,
251 int out_len = MLX5_ST_SZ_BYTES(query_flow_counter_out) +
252 MLX5_ST_SZ_BYTES(traffic_counter);
253 uint32_t out[out_len];
254 uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0};
258 MLX5_SET(query_flow_counter_in, in, opcode,
259 MLX5_CMD_OP_QUERY_FLOW_COUNTER);
260 MLX5_SET(query_flow_counter_in, in, op_mod, 0);
261 MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id);
262 MLX5_SET(query_flow_counter_in, in, clear, !!clear);
265 MLX5_SET(query_flow_counter_in, in, num_of_counters,
267 MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1);
268 MLX5_SET(query_flow_counter_in, in, mkey, mkey);
269 MLX5_SET64(query_flow_counter_in, in, address,
270 (uint64_t)(uintptr_t)addr);
273 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out,
276 rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in),
280 DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc);
285 stats = MLX5_ADDR_OF(query_flow_counter_out,
286 out, flow_statistics);
287 *pkts = MLX5_GET64(traffic_counter, stats, packets);
288 *bytes = MLX5_GET64(traffic_counter, stats, octets);
297 * Context returned from mlx5 open_device() glue function.
299 * Attributes of the requested mkey.
302 * Pointer to Devx mkey on success, a negative value otherwise and rte_errno
305 struct mlx5_devx_obj *
306 mlx5_devx_cmd_mkey_create(void *ctx,
307 struct mlx5_devx_mkey_attr *attr)
309 struct mlx5_klm *klm_array = attr->klm_array;
310 int klm_num = attr->klm_num;
311 int in_size_dw = MLX5_ST_SZ_DW(create_mkey_in) +
312 (klm_num ? RTE_ALIGN(klm_num, 4) : 0) * MLX5_ST_SZ_DW(klm);
313 uint32_t in[in_size_dw];
314 uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0};
316 struct mlx5_devx_obj *mkey = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mkey),
319 uint32_t translation_size;
325 memset(in, 0, in_size_dw * 4);
326 pgsize = rte_mem_page_size();
327 if (pgsize == (size_t)-1) {
329 DRV_LOG(ERR, "Failed to get page size");
333 MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY);
334 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
337 uint8_t *klm = (uint8_t *)MLX5_ADDR_OF(create_mkey_in, in,
339 translation_size = RTE_ALIGN(klm_num, 4);
340 for (i = 0; i < klm_num; i++) {
341 MLX5_SET(klm, klm, byte_count, klm_array[i].byte_count);
342 MLX5_SET(klm, klm, mkey, klm_array[i].mkey);
343 MLX5_SET64(klm, klm, address, klm_array[i].address);
344 klm += MLX5_ST_SZ_BYTES(klm);
346 for (; i < (int)translation_size; i++) {
347 MLX5_SET(klm, klm, mkey, 0x0);
348 MLX5_SET64(klm, klm, address, 0x0);
349 klm += MLX5_ST_SZ_BYTES(klm);
351 MLX5_SET(mkc, mkc, access_mode_1_0, attr->log_entity_size ?
352 MLX5_MKC_ACCESS_MODE_KLM_FBS :
353 MLX5_MKC_ACCESS_MODE_KLM);
354 MLX5_SET(mkc, mkc, log_page_size, attr->log_entity_size);
356 translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16;
357 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
358 MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize));
360 MLX5_SET(create_mkey_in, in, translations_octword_actual_size,
362 MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id);
363 MLX5_SET(create_mkey_in, in, pg_access, attr->pg_access);
364 MLX5_SET(mkc, mkc, lw, 0x1);
365 MLX5_SET(mkc, mkc, lr, 0x1);
366 if (attr->set_remote_rw) {
367 MLX5_SET(mkc, mkc, rw, 0x1);
368 MLX5_SET(mkc, mkc, rr, 0x1);
370 MLX5_SET(mkc, mkc, qpn, 0xffffff);
371 MLX5_SET(mkc, mkc, pd, attr->pd);
372 MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF);
373 MLX5_SET(mkc, mkc, umr_en, attr->umr_en);
374 MLX5_SET(mkc, mkc, translations_octword_size, translation_size);
375 MLX5_SET(mkc, mkc, relaxed_ordering_write,
376 attr->relaxed_ordering_write);
377 MLX5_SET(mkc, mkc, relaxed_ordering_read, attr->relaxed_ordering_read);
378 MLX5_SET64(mkc, mkc, start_addr, attr->addr);
379 MLX5_SET64(mkc, mkc, len, attr->size);
380 MLX5_SET(mkc, mkc, crypto_en, attr->crypto_en);
381 if (attr->crypto_en) {
382 MLX5_SET(mkc, mkc, bsf_en, attr->crypto_en);
383 MLX5_SET(mkc, mkc, bsf_octword_size, 4);
385 mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out,
388 DRV_LOG(ERR, "Can't create %sdirect mkey - error %d",
389 klm_num ? "an in" : "a ", errno);
394 mkey->id = MLX5_GET(create_mkey_out, out, mkey_index);
395 mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF);
400 * Get status of devx command response.
401 * Mainly used for asynchronous commands.
404 * The out response buffer.
407 * 0 on success, non-zero value otherwise.
410 mlx5_devx_get_out_command_status(void *out)
416 status = MLX5_GET(query_flow_counter_out, out, status);
418 int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome);
420 DRV_LOG(ERR, "Bad DevX status %x, syndrome = %x", status,
427 * Destroy any object allocated by a Devx API.
430 * Pointer to a general object.
433 * 0 on success, a negative value otherwise.
436 mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj)
442 ret = mlx5_glue->devx_obj_destroy(obj->obj);
448 * Query NIC vport context.
449 * Fills minimal inline attribute.
452 * ibv contexts returned from mlx5dv_open_device.
456 * Attributes device values.
459 * 0 on success, a negative value otherwise.
462 mlx5_devx_cmd_query_nic_vport_context(void *ctx,
464 struct mlx5_hca_attr *attr)
466 uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0};
467 uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0};
469 int status, syndrome, rc;
471 /* Query NIC vport context to determine inline mode. */
472 MLX5_SET(query_nic_vport_context_in, in, opcode,
473 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT);
474 MLX5_SET(query_nic_vport_context_in, in, vport_number, vport);
476 MLX5_SET(query_nic_vport_context_in, in, other_vport, 1);
477 rc = mlx5_glue->devx_general_cmd(ctx,
482 status = MLX5_GET(query_nic_vport_context_out, out, status);
483 syndrome = MLX5_GET(query_nic_vport_context_out, out, syndrome);
485 DRV_LOG(DEBUG, "Failed to query NIC vport context, "
486 "status %x, syndrome = %x", status, syndrome);
489 vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out,
491 attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx,
492 min_wqe_inline_mode);
495 rc = (rc > 0) ? -rc : rc;
500 * Query NIC vDPA attributes.
503 * Context returned from mlx5 open_device() glue function.
504 * @param[out] vdpa_attr
505 * vDPA Attributes structure to fill.
508 mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx,
509 struct mlx5_hca_vdpa_attr *vdpa_attr)
511 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)];
512 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)];
515 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, NULL,
516 MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION |
517 MLX5_HCA_CAP_OPMOD_GET_CUR);
519 RTE_LOG(DEBUG, PMD, "Failed to query devx VDPA capabilities");
520 vdpa_attr->valid = 0;
522 vdpa_attr->valid = 1;
523 vdpa_attr->desc_tunnel_offload_type =
524 MLX5_GET(virtio_emulation_cap, hcattr,
525 desc_tunnel_offload_type);
526 vdpa_attr->eth_frame_offload_type =
527 MLX5_GET(virtio_emulation_cap, hcattr,
528 eth_frame_offload_type);
529 vdpa_attr->virtio_version_1_0 =
530 MLX5_GET(virtio_emulation_cap, hcattr,
532 vdpa_attr->tso_ipv4 = MLX5_GET(virtio_emulation_cap, hcattr,
534 vdpa_attr->tso_ipv6 = MLX5_GET(virtio_emulation_cap, hcattr,
536 vdpa_attr->tx_csum = MLX5_GET(virtio_emulation_cap, hcattr,
538 vdpa_attr->rx_csum = MLX5_GET(virtio_emulation_cap, hcattr,
540 vdpa_attr->event_mode = MLX5_GET(virtio_emulation_cap, hcattr,
542 vdpa_attr->virtio_queue_type =
543 MLX5_GET(virtio_emulation_cap, hcattr,
545 vdpa_attr->log_doorbell_stride =
546 MLX5_GET(virtio_emulation_cap, hcattr,
547 log_doorbell_stride);
548 vdpa_attr->log_doorbell_bar_size =
549 MLX5_GET(virtio_emulation_cap, hcattr,
550 log_doorbell_bar_size);
551 vdpa_attr->doorbell_bar_offset =
552 MLX5_GET64(virtio_emulation_cap, hcattr,
553 doorbell_bar_offset);
554 vdpa_attr->max_num_virtio_queues =
555 MLX5_GET(virtio_emulation_cap, hcattr,
556 max_num_virtio_queues);
557 vdpa_attr->umems[0].a = MLX5_GET(virtio_emulation_cap, hcattr,
558 umem_1_buffer_param_a);
559 vdpa_attr->umems[0].b = MLX5_GET(virtio_emulation_cap, hcattr,
560 umem_1_buffer_param_b);
561 vdpa_attr->umems[1].a = MLX5_GET(virtio_emulation_cap, hcattr,
562 umem_2_buffer_param_a);
563 vdpa_attr->umems[1].b = MLX5_GET(virtio_emulation_cap, hcattr,
564 umem_2_buffer_param_b);
565 vdpa_attr->umems[2].a = MLX5_GET(virtio_emulation_cap, hcattr,
566 umem_3_buffer_param_a);
567 vdpa_attr->umems[2].b = MLX5_GET(virtio_emulation_cap, hcattr,
568 umem_3_buffer_param_b);
573 mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj,
574 uint32_t ids[], uint32_t num)
576 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
577 uint32_t out[MLX5_ST_SZ_DW(create_flex_parser_out)] = {0};
578 void *hdr = MLX5_ADDR_OF(create_flex_parser_out, in, hdr);
579 void *flex = MLX5_ADDR_OF(create_flex_parser_out, out, flex);
580 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table);
585 if (num > MLX5_GRAPH_NODE_SAMPLE_NUM) {
587 DRV_LOG(ERR, "Too many sample IDs to be fetched.");
590 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
591 MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
592 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
593 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH);
594 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, flex_obj->id);
595 ret = mlx5_glue->devx_obj_query(flex_obj->obj, in, sizeof(in),
599 DRV_LOG(ERR, "Failed to query sample IDs with object %p.",
603 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) {
604 void *s_off = (void *)((char *)sample + i *
605 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample));
608 en = MLX5_GET(parse_graph_flow_match_sample, s_off,
609 flow_match_sample_en);
612 ids[idx++] = MLX5_GET(parse_graph_flow_match_sample, s_off,
613 flow_match_sample_field_id);
617 DRV_LOG(ERR, "Number of sample IDs are not as expected.");
624 struct mlx5_devx_obj *
625 mlx5_devx_cmd_create_flex_parser(void *ctx,
626 struct mlx5_devx_graph_node_attr *data)
628 uint32_t in[MLX5_ST_SZ_DW(create_flex_parser_in)] = {0};
629 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
630 void *hdr = MLX5_ADDR_OF(create_flex_parser_in, in, hdr);
631 void *flex = MLX5_ADDR_OF(create_flex_parser_in, in, flex);
632 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table);
633 void *in_arc = MLX5_ADDR_OF(parse_graph_flex, flex, input_arc);
634 void *out_arc = MLX5_ADDR_OF(parse_graph_flex, flex, output_arc);
635 struct mlx5_devx_obj *parse_flex_obj = mlx5_malloc
636 (MLX5_MEM_ZERO, sizeof(*parse_flex_obj), 0, SOCKET_ID_ANY);
639 if (!parse_flex_obj) {
640 DRV_LOG(ERR, "Failed to allocate flex parser data.");
644 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
645 MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
646 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
647 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH);
648 MLX5_SET(parse_graph_flex, flex, header_length_mode,
649 data->header_length_mode);
650 MLX5_SET(parse_graph_flex, flex, header_length_base_value,
651 data->header_length_base_value);
652 MLX5_SET(parse_graph_flex, flex, header_length_field_offset,
653 data->header_length_field_offset);
654 MLX5_SET(parse_graph_flex, flex, header_length_field_shift,
655 data->header_length_field_shift);
656 MLX5_SET(parse_graph_flex, flex, header_length_field_mask,
657 data->header_length_field_mask);
658 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) {
659 struct mlx5_devx_match_sample_attr *s = &data->sample[i];
660 void *s_off = (void *)((char *)sample + i *
661 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample));
663 if (!s->flow_match_sample_en)
665 MLX5_SET(parse_graph_flow_match_sample, s_off,
666 flow_match_sample_en, !!s->flow_match_sample_en);
667 MLX5_SET(parse_graph_flow_match_sample, s_off,
668 flow_match_sample_field_offset,
669 s->flow_match_sample_field_offset);
670 MLX5_SET(parse_graph_flow_match_sample, s_off,
671 flow_match_sample_offset_mode,
672 s->flow_match_sample_offset_mode);
673 MLX5_SET(parse_graph_flow_match_sample, s_off,
674 flow_match_sample_field_offset_mask,
675 s->flow_match_sample_field_offset_mask);
676 MLX5_SET(parse_graph_flow_match_sample, s_off,
677 flow_match_sample_field_offset_shift,
678 s->flow_match_sample_field_offset_shift);
679 MLX5_SET(parse_graph_flow_match_sample, s_off,
680 flow_match_sample_field_base_offset,
681 s->flow_match_sample_field_base_offset);
682 MLX5_SET(parse_graph_flow_match_sample, s_off,
683 flow_match_sample_tunnel_mode,
684 s->flow_match_sample_tunnel_mode);
686 for (i = 0; i < MLX5_GRAPH_NODE_ARC_NUM; i++) {
687 struct mlx5_devx_graph_arc_attr *ia = &data->in[i];
688 struct mlx5_devx_graph_arc_attr *oa = &data->out[i];
689 void *in_off = (void *)((char *)in_arc + i *
690 MLX5_ST_SZ_BYTES(parse_graph_arc));
691 void *out_off = (void *)((char *)out_arc + i *
692 MLX5_ST_SZ_BYTES(parse_graph_arc));
694 if (ia->arc_parse_graph_node != 0) {
695 MLX5_SET(parse_graph_arc, in_off,
696 compare_condition_value,
697 ia->compare_condition_value);
698 MLX5_SET(parse_graph_arc, in_off, start_inner_tunnel,
699 ia->start_inner_tunnel);
700 MLX5_SET(parse_graph_arc, in_off, arc_parse_graph_node,
701 ia->arc_parse_graph_node);
702 MLX5_SET(parse_graph_arc, in_off,
703 parse_graph_node_handle,
704 ia->parse_graph_node_handle);
706 if (oa->arc_parse_graph_node != 0) {
707 MLX5_SET(parse_graph_arc, out_off,
708 compare_condition_value,
709 oa->compare_condition_value);
710 MLX5_SET(parse_graph_arc, out_off, start_inner_tunnel,
711 oa->start_inner_tunnel);
712 MLX5_SET(parse_graph_arc, out_off, arc_parse_graph_node,
713 oa->arc_parse_graph_node);
714 MLX5_SET(parse_graph_arc, out_off,
715 parse_graph_node_handle,
716 oa->parse_graph_node_handle);
719 parse_flex_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
721 if (!parse_flex_obj->obj) {
723 DRV_LOG(ERR, "Failed to create FLEX PARSE GRAPH object "
725 mlx5_free(parse_flex_obj);
728 parse_flex_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
729 return parse_flex_obj;
733 mlx5_devx_cmd_query_hca_parse_graph_node_cap
734 (void *ctx, struct mlx5_hca_flex_attr *attr)
736 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)];
737 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)];
741 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
742 MLX5_GET_HCA_CAP_OP_MOD_PARSE_GRAPH_NODE_CAP |
743 MLX5_HCA_CAP_OPMOD_GET_CUR);
746 attr->node_in = MLX5_GET(parse_graph_node_cap, hcattr, node_in);
747 attr->node_out = MLX5_GET(parse_graph_node_cap, hcattr, node_out);
748 attr->header_length_mode = MLX5_GET(parse_graph_node_cap, hcattr,
750 attr->sample_offset_mode = MLX5_GET(parse_graph_node_cap, hcattr,
752 attr->max_num_arc_in = MLX5_GET(parse_graph_node_cap, hcattr,
754 attr->max_num_arc_out = MLX5_GET(parse_graph_node_cap, hcattr,
756 attr->max_num_sample = MLX5_GET(parse_graph_node_cap, hcattr,
758 attr->sample_id_in_out = MLX5_GET(parse_graph_node_cap, hcattr,
760 attr->max_base_header_length = MLX5_GET(parse_graph_node_cap, hcattr,
761 max_base_header_length);
762 attr->max_sample_base_offset = MLX5_GET(parse_graph_node_cap, hcattr,
763 max_sample_base_offset);
764 attr->max_next_header_offset = MLX5_GET(parse_graph_node_cap, hcattr,
765 max_next_header_offset);
766 attr->header_length_mask_width = MLX5_GET(parse_graph_node_cap, hcattr,
767 header_length_mask_width);
768 /* Get the max supported samples from HCA CAP 2 */
769 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
770 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 |
771 MLX5_HCA_CAP_OPMOD_GET_CUR);
774 attr->max_num_prog_sample =
775 MLX5_GET(cmd_hca_cap_2, hcattr, max_num_prog_sample_field);
780 mlx5_devx_query_pkt_integrity_match(void *hcattr)
782 return MLX5_GET(flow_table_nic_cap, hcattr,
783 ft_field_support_2_nic_receive.inner_l3_ok) &&
784 MLX5_GET(flow_table_nic_cap, hcattr,
785 ft_field_support_2_nic_receive.inner_l4_ok) &&
786 MLX5_GET(flow_table_nic_cap, hcattr,
787 ft_field_support_2_nic_receive.outer_l3_ok) &&
788 MLX5_GET(flow_table_nic_cap, hcattr,
789 ft_field_support_2_nic_receive.outer_l4_ok) &&
790 MLX5_GET(flow_table_nic_cap, hcattr,
791 ft_field_support_2_nic_receive
792 .inner_ipv4_checksum_ok) &&
793 MLX5_GET(flow_table_nic_cap, hcattr,
794 ft_field_support_2_nic_receive.inner_l4_checksum_ok) &&
795 MLX5_GET(flow_table_nic_cap, hcattr,
796 ft_field_support_2_nic_receive
797 .outer_ipv4_checksum_ok) &&
798 MLX5_GET(flow_table_nic_cap, hcattr,
799 ft_field_support_2_nic_receive.outer_l4_checksum_ok);
803 * Query HCA attributes.
804 * Using those attributes we can check on run time if the device
805 * is having the required capabilities.
808 * Context returned from mlx5 open_device() glue function.
810 * Attributes device values.
813 * 0 on success, a negative value otherwise.
816 mlx5_devx_cmd_query_hca_attr(void *ctx,
817 struct mlx5_hca_attr *attr)
819 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0};
820 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0};
821 uint64_t general_obj_types_supported = 0;
825 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
826 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE |
827 MLX5_HCA_CAP_OPMOD_GET_CUR);
830 attr->flow_counter_bulk_alloc_bitmap =
831 MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc);
832 attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr,
834 attr->log_max_rqt_size = MLX5_GET(cmd_hca_cap, hcattr,
836 attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager);
837 attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin);
838 attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr,
839 log_max_hairpin_queues);
840 attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr,
841 log_max_hairpin_wq_data_sz);
842 attr->log_max_hairpin_num_packets = MLX5_GET
843 (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz);
844 attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id);
845 attr->relaxed_ordering_write = MLX5_GET(cmd_hca_cap, hcattr,
846 relaxed_ordering_write);
847 attr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr,
848 relaxed_ordering_read);
849 attr->access_register_user = MLX5_GET(cmd_hca_cap, hcattr,
850 access_register_user);
851 attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr,
853 attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt);
854 attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr,
855 flex_parser_protocols);
856 attr->max_geneve_tlv_options = MLX5_GET(cmd_hca_cap, hcattr,
857 max_geneve_tlv_options);
858 attr->max_geneve_tlv_option_data_len = MLX5_GET(cmd_hca_cap, hcattr,
859 max_geneve_tlv_option_data_len);
860 attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos);
861 attr->qos.flow_meter_aso_sup = !!(MLX5_GET64(cmd_hca_cap, hcattr,
863 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO);
864 attr->vdpa.valid = !!(MLX5_GET64(cmd_hca_cap, hcattr,
866 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q);
867 attr->vdpa.queue_counters_valid = !!(MLX5_GET64(cmd_hca_cap, hcattr,
869 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS);
870 attr->parse_graph_flex_node = !!(MLX5_GET64(cmd_hca_cap, hcattr,
872 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE);
873 attr->wqe_index_ignore = MLX5_GET(cmd_hca_cap, hcattr,
874 wqe_index_ignore_cap);
875 attr->cross_channel = MLX5_GET(cmd_hca_cap, hcattr, cd);
876 attr->non_wire_sq = MLX5_GET(cmd_hca_cap, hcattr, non_wire_sq);
877 attr->log_max_static_sq_wq = MLX5_GET(cmd_hca_cap, hcattr,
878 log_max_static_sq_wq);
879 attr->num_lag_ports = MLX5_GET(cmd_hca_cap, hcattr, num_lag_ports);
880 attr->dev_freq_khz = MLX5_GET(cmd_hca_cap, hcattr,
881 device_frequency_khz);
882 attr->scatter_fcs_w_decap_disable =
883 MLX5_GET(cmd_hca_cap, hcattr, scatter_fcs_w_decap_disable);
884 attr->roce = MLX5_GET(cmd_hca_cap, hcattr, roce);
885 attr->rq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, rq_ts_format);
886 attr->sq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, sq_ts_format);
887 attr->steering_format_version =
888 MLX5_GET(cmd_hca_cap, hcattr, steering_format_version);
889 attr->regexp_params = MLX5_GET(cmd_hca_cap, hcattr, regexp_params);
890 attr->regexp_version = MLX5_GET(cmd_hca_cap, hcattr, regexp_version);
891 attr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr,
892 regexp_num_of_engines);
893 /* Read the general_obj_types bitmap and extract the relevant bits. */
894 general_obj_types_supported = MLX5_GET64(cmd_hca_cap, hcattr,
896 attr->vdpa.valid = !!(general_obj_types_supported &
897 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q);
898 attr->vdpa.queue_counters_valid =
899 !!(general_obj_types_supported &
900 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS);
901 attr->parse_graph_flex_node =
902 !!(general_obj_types_supported &
903 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE);
904 attr->flow_hit_aso = !!(general_obj_types_supported &
905 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO);
906 attr->geneve_tlv_opt = !!(general_obj_types_supported &
907 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT);
908 attr->dek = !!(general_obj_types_supported &
909 MLX5_GENERAL_OBJ_TYPES_CAP_DEK);
910 attr->import_kek = !!(general_obj_types_supported &
911 MLX5_GENERAL_OBJ_TYPES_CAP_IMPORT_KEK);
912 attr->credential = !!(general_obj_types_supported &
913 MLX5_GENERAL_OBJ_TYPES_CAP_CREDENTIAL);
914 attr->crypto_login = !!(general_obj_types_supported &
915 MLX5_GENERAL_OBJ_TYPES_CAP_CRYPTO_LOGIN);
916 /* Add reading of other GENERAL_OBJ_TYPES_CAP bits above this line. */
917 attr->log_max_cq = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq);
918 attr->log_max_qp = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp);
919 attr->log_max_cq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq_sz);
920 attr->log_max_qp_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp_sz);
921 attr->log_max_mrw_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_mrw_sz);
922 attr->log_max_pd = MLX5_GET(cmd_hca_cap, hcattr, log_max_pd);
923 attr->log_max_srq = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq);
924 attr->log_max_srq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq_sz);
925 attr->reg_c_preserve =
926 MLX5_GET(cmd_hca_cap, hcattr, reg_c_preserve);
927 attr->mmo_regex_qp_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_qp);
928 attr->mmo_regex_sq_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_sq);
929 attr->mmo_dma_sq_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_sq);
930 attr->mmo_compress_sq_en = MLX5_GET(cmd_hca_cap, hcattr,
932 attr->mmo_decompress_sq_en = MLX5_GET(cmd_hca_cap, hcattr,
934 attr->mmo_dma_qp_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_qp);
935 attr->mmo_compress_qp_en = MLX5_GET(cmd_hca_cap, hcattr,
937 attr->mmo_decompress_qp_en = MLX5_GET(cmd_hca_cap, hcattr,
939 attr->compress_min_block_size = MLX5_GET(cmd_hca_cap, hcattr,
940 compress_min_block_size);
941 attr->log_max_mmo_dma = MLX5_GET(cmd_hca_cap, hcattr, log_dma_mmo_size);
942 attr->log_max_mmo_compress = MLX5_GET(cmd_hca_cap, hcattr,
943 log_compress_mmo_size);
944 attr->log_max_mmo_decompress = MLX5_GET(cmd_hca_cap, hcattr,
945 log_decompress_mmo_size);
946 attr->cqe_compression = MLX5_GET(cmd_hca_cap, hcattr, cqe_compression);
947 attr->mini_cqe_resp_flow_tag = MLX5_GET(cmd_hca_cap, hcattr,
948 mini_cqe_resp_flow_tag);
949 attr->mini_cqe_resp_l3_l4_tag = MLX5_GET(cmd_hca_cap, hcattr,
950 mini_cqe_resp_l3_l4_tag);
951 attr->umr_indirect_mkey_disabled =
952 MLX5_GET(cmd_hca_cap, hcattr, umr_indirect_mkey_disabled);
953 attr->umr_modify_entity_size_disabled =
954 MLX5_GET(cmd_hca_cap, hcattr, umr_modify_entity_size_disabled);
955 attr->crypto = MLX5_GET(cmd_hca_cap, hcattr, crypto);
957 attr->aes_xts = MLX5_GET(cmd_hca_cap, hcattr, aes_xts);
958 attr->ct_offload = !!(MLX5_GET64(cmd_hca_cap, hcattr,
960 MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD);
962 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
963 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP |
964 MLX5_HCA_CAP_OPMOD_GET_CUR);
966 DRV_LOG(DEBUG, "Failed to query devx QOS capabilities");
969 attr->qos.flow_meter_old =
970 MLX5_GET(qos_cap, hcattr, flow_meter_old);
971 attr->qos.log_max_flow_meter =
972 MLX5_GET(qos_cap, hcattr, log_max_flow_meter);
973 attr->qos.flow_meter_reg_c_ids =
974 MLX5_GET(qos_cap, hcattr, flow_meter_reg_id);
975 attr->qos.flow_meter =
976 MLX5_GET(qos_cap, hcattr, flow_meter);
977 attr->qos.packet_pacing =
978 MLX5_GET(qos_cap, hcattr, packet_pacing);
979 attr->qos.wqe_rate_pp =
980 MLX5_GET(qos_cap, hcattr, wqe_rate_pp);
981 if (attr->qos.flow_meter_aso_sup) {
982 attr->qos.log_meter_aso_granularity =
983 MLX5_GET(qos_cap, hcattr,
984 log_meter_aso_granularity);
985 attr->qos.log_meter_aso_max_alloc =
986 MLX5_GET(qos_cap, hcattr,
987 log_meter_aso_max_alloc);
988 attr->qos.log_max_num_meter_aso =
989 MLX5_GET(qos_cap, hcattr,
990 log_max_num_meter_aso);
994 * Flex item support needs max_num_prog_sample_field
995 * from the Capabilities 2 table for PARSE_GRAPH_NODE
997 if (attr->parse_graph_flex_node) {
998 rc = mlx5_devx_cmd_query_hca_parse_graph_node_cap
1003 if (attr->vdpa.valid)
1004 mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa);
1005 if (!attr->eth_net_offloads)
1007 /* Query Flow Sampler Capability From FLow Table Properties Layout. */
1008 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1009 MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE |
1010 MLX5_HCA_CAP_OPMOD_GET_CUR);
1012 attr->log_max_ft_sampler_num = 0;
1015 attr->log_max_ft_sampler_num = MLX5_GET
1016 (flow_table_nic_cap, hcattr,
1017 flow_table_properties_nic_receive.log_max_ft_sampler_num);
1018 attr->flow.tunnel_header_0_1 = MLX5_GET
1019 (flow_table_nic_cap, hcattr,
1020 ft_field_support_2_nic_receive.tunnel_header_0_1);
1021 attr->pkt_integrity_match = mlx5_devx_query_pkt_integrity_match(hcattr);
1022 attr->inner_ipv4_ihl = MLX5_GET
1023 (flow_table_nic_cap, hcattr,
1024 ft_field_support_2_nic_receive.inner_ipv4_ihl);
1025 attr->outer_ipv4_ihl = MLX5_GET
1026 (flow_table_nic_cap, hcattr,
1027 ft_field_support_2_nic_receive.outer_ipv4_ihl);
1028 /* Query HCA offloads for Ethernet protocol. */
1029 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1030 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS |
1031 MLX5_HCA_CAP_OPMOD_GET_CUR);
1033 attr->eth_net_offloads = 0;
1036 attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps,
1037 hcattr, wqe_vlan_insert);
1038 attr->csum_cap = MLX5_GET(per_protocol_networking_offload_caps,
1040 attr->vlan_cap = MLX5_GET(per_protocol_networking_offload_caps,
1042 attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr,
1044 attr->max_lso_cap = MLX5_GET(per_protocol_networking_offload_caps,
1045 hcattr, max_lso_cap);
1046 attr->scatter_fcs = MLX5_GET(per_protocol_networking_offload_caps,
1047 hcattr, scatter_fcs);
1048 attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps,
1049 hcattr, tunnel_lro_gre);
1050 attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps,
1051 hcattr, tunnel_lro_vxlan);
1052 attr->swp = MLX5_GET(per_protocol_networking_offload_caps,
1054 attr->tunnel_stateless_gre =
1055 MLX5_GET(per_protocol_networking_offload_caps,
1056 hcattr, tunnel_stateless_gre);
1057 attr->tunnel_stateless_vxlan =
1058 MLX5_GET(per_protocol_networking_offload_caps,
1059 hcattr, tunnel_stateless_vxlan);
1060 attr->swp_csum = MLX5_GET(per_protocol_networking_offload_caps,
1062 attr->swp_lso = MLX5_GET(per_protocol_networking_offload_caps,
1064 attr->lro_max_msg_sz_mode = MLX5_GET
1065 (per_protocol_networking_offload_caps,
1066 hcattr, lro_max_msg_sz_mode);
1067 for (i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) {
1068 attr->lro_timer_supported_periods[i] =
1069 MLX5_GET(per_protocol_networking_offload_caps, hcattr,
1070 lro_timer_supported_periods[i]);
1072 attr->lro_min_mss_size = MLX5_GET(per_protocol_networking_offload_caps,
1073 hcattr, lro_min_mss_size);
1074 attr->tunnel_stateless_geneve_rx =
1075 MLX5_GET(per_protocol_networking_offload_caps,
1076 hcattr, tunnel_stateless_geneve_rx);
1077 attr->geneve_max_opt_len =
1078 MLX5_GET(per_protocol_networking_offload_caps,
1079 hcattr, max_geneve_opt_len);
1080 attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps,
1081 hcattr, wqe_inline_mode);
1082 attr->tunnel_stateless_gtp = MLX5_GET
1083 (per_protocol_networking_offload_caps,
1084 hcattr, tunnel_stateless_gtp);
1085 attr->rss_ind_tbl_cap = MLX5_GET
1086 (per_protocol_networking_offload_caps,
1087 hcattr, rss_ind_tbl_cap);
1088 /* Query HCA attribute for ROCE. */
1090 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1091 MLX5_GET_HCA_CAP_OP_MOD_ROCE |
1092 MLX5_HCA_CAP_OPMOD_GET_CUR);
1095 "Failed to query devx HCA ROCE capabilities");
1098 attr->qp_ts_format = MLX5_GET(roce_caps, hcattr, qp_ts_format);
1100 if (attr->eth_virt &&
1101 attr->wqe_inline_mode == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT) {
1102 rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr);
1110 rc = (rc > 0) ? -rc : rc;
1115 * Query TIS transport domain from QP verbs object using DevX API.
1118 * Pointer to verbs QP returned by ibv_create_qp .
1119 * @param[in] tis_num
1120 * TIS number of TIS to query.
1121 * @param[out] tis_td
1122 * Pointer to TIS transport domain variable, to be set by the routine.
1125 * 0 on success, a negative value otherwise.
1128 mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num,
1131 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
1132 uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0};
1133 uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0};
1137 MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS);
1138 MLX5_SET(query_tis_in, in, tisn, tis_num);
1139 rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out));
1141 DRV_LOG(ERR, "Failed to query QP using DevX");
1144 tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context);
1145 *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain);
1156 * Fill WQ data for DevX API command.
1157 * Utility function for use when creating DevX objects containing a WQ.
1160 * Pointer to WQ context to fill with data.
1161 * @param [in] wq_attr
1162 * Pointer to WQ attributes structure to fill in WQ context.
1165 devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr)
1167 MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type);
1168 MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature);
1169 MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode);
1170 MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave);
1171 MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge);
1172 MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size);
1173 MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset);
1174 MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm);
1175 MLX5_SET(wq, wq_ctx, pd, wq_attr->pd);
1176 MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page);
1177 MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr);
1178 MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter);
1179 MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter);
1180 MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride);
1181 if (wq_attr->log_wq_pg_sz > MLX5_ADAPTER_PAGE_SHIFT)
1182 MLX5_SET(wq, wq_ctx, log_wq_pg_sz,
1183 wq_attr->log_wq_pg_sz - MLX5_ADAPTER_PAGE_SHIFT);
1184 MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz);
1185 MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid);
1186 MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid);
1187 MLX5_SET(wq, wq_ctx, log_hairpin_num_packets,
1188 wq_attr->log_hairpin_num_packets);
1189 MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz);
1190 MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides,
1191 wq_attr->single_wqe_log_num_of_strides);
1192 MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en);
1193 MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes,
1194 wq_attr->single_stride_log_num_of_bytes);
1195 MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id);
1196 MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id);
1197 MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset);
1201 * Create RQ using DevX API.
1204 * Context returned from mlx5 open_device() glue function.
1205 * @param [in] rq_attr
1206 * Pointer to create RQ attributes structure.
1207 * @param [in] socket
1208 * CPU socket ID for allocations.
1211 * The DevX object created, NULL otherwise and rte_errno is set.
1213 struct mlx5_devx_obj *
1214 mlx5_devx_cmd_create_rq(void *ctx,
1215 struct mlx5_devx_create_rq_attr *rq_attr,
1218 uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0};
1219 uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0};
1220 void *rq_ctx, *wq_ctx;
1221 struct mlx5_devx_wq_attr *wq_attr;
1222 struct mlx5_devx_obj *rq = NULL;
1224 rq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rq), 0, socket);
1226 DRV_LOG(ERR, "Failed to allocate RQ data");
1230 MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ);
1231 rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx);
1232 MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky);
1233 MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en);
1234 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);
1235 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);
1236 MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type);
1237 MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
1238 MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en);
1239 MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin);
1240 MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index);
1241 MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn);
1242 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
1243 MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn);
1244 MLX5_SET(sqc, rq_ctx, ts_format, rq_attr->ts_format);
1245 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);
1246 wq_attr = &rq_attr->wq_attr;
1247 devx_cmd_fill_wq_data(wq_ctx, wq_attr);
1248 rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1251 DRV_LOG(ERR, "Failed to create RQ using DevX");
1256 rq->id = MLX5_GET(create_rq_out, out, rqn);
1261 * Modify RQ using DevX API.
1264 * Pointer to RQ object structure.
1265 * @param [in] rq_attr
1266 * Pointer to modify RQ attributes structure.
1269 * 0 on success, a negative errno value otherwise and rte_errno is set.
1272 mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,
1273 struct mlx5_devx_modify_rq_attr *rq_attr)
1275 uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0};
1276 uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0};
1277 void *rq_ctx, *wq_ctx;
1280 MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ);
1281 MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state);
1282 MLX5_SET(modify_rq_in, in, rqn, rq->id);
1283 MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask);
1284 rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1285 MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
1286 if (rq_attr->modify_bitmask &
1287 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS)
1288 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);
1289 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD)
1290 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);
1291 if (rq_attr->modify_bitmask &
1292 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID)
1293 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
1294 MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq);
1295 MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca);
1296 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) {
1297 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);
1298 MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm);
1300 ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in),
1303 DRV_LOG(ERR, "Failed to modify RQ using DevX");
1311 * Create TIR using DevX API.
1314 * Context returned from mlx5 open_device() glue function.
1315 * @param [in] tir_attr
1316 * Pointer to TIR attributes structure.
1319 * The DevX object created, NULL otherwise and rte_errno is set.
1321 struct mlx5_devx_obj *
1322 mlx5_devx_cmd_create_tir(void *ctx,
1323 struct mlx5_devx_tir_attr *tir_attr)
1325 uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
1326 uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0};
1327 void *tir_ctx, *outer, *inner, *rss_key;
1328 struct mlx5_devx_obj *tir = NULL;
1330 tir = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tir), 0, SOCKET_ID_ANY);
1332 DRV_LOG(ERR, "Failed to allocate TIR data");
1336 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR);
1337 tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx);
1338 MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type);
1339 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs,
1340 tir_attr->lro_timeout_period_usecs);
1341 MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask);
1342 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz);
1343 MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn);
1344 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric);
1345 MLX5_SET(tirc, tir_ctx, tunneled_offload_en,
1346 tir_attr->tunneled_offload_en);
1347 MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table);
1348 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn);
1349 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block);
1350 MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain);
1351 rss_key = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_toeplitz_key);
1352 memcpy(rss_key, tir_attr->rx_hash_toeplitz_key, MLX5_RSS_HASH_KEY_LEN);
1353 outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer);
1354 MLX5_SET(rx_hash_field_select, outer, l3_prot_type,
1355 tir_attr->rx_hash_field_selector_outer.l3_prot_type);
1356 MLX5_SET(rx_hash_field_select, outer, l4_prot_type,
1357 tir_attr->rx_hash_field_selector_outer.l4_prot_type);
1358 MLX5_SET(rx_hash_field_select, outer, selected_fields,
1359 tir_attr->rx_hash_field_selector_outer.selected_fields);
1360 inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner);
1361 MLX5_SET(rx_hash_field_select, inner, l3_prot_type,
1362 tir_attr->rx_hash_field_selector_inner.l3_prot_type);
1363 MLX5_SET(rx_hash_field_select, inner, l4_prot_type,
1364 tir_attr->rx_hash_field_selector_inner.l4_prot_type);
1365 MLX5_SET(rx_hash_field_select, inner, selected_fields,
1366 tir_attr->rx_hash_field_selector_inner.selected_fields);
1367 tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1370 DRV_LOG(ERR, "Failed to create TIR using DevX");
1375 tir->id = MLX5_GET(create_tir_out, out, tirn);
1380 * Modify TIR using DevX API.
1383 * Pointer to TIR DevX object structure.
1384 * @param [in] modify_tir_attr
1385 * Pointer to TIR modification attributes structure.
1388 * 0 on success, a negative errno value otherwise and rte_errno is set.
1391 mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir,
1392 struct mlx5_devx_modify_tir_attr *modify_tir_attr)
1394 struct mlx5_devx_tir_attr *tir_attr = &modify_tir_attr->tir;
1395 uint32_t in[MLX5_ST_SZ_DW(modify_tir_in)] = {0};
1396 uint32_t out[MLX5_ST_SZ_DW(modify_tir_out)] = {0};
1400 MLX5_SET(modify_tir_in, in, opcode, MLX5_CMD_OP_MODIFY_TIR);
1401 MLX5_SET(modify_tir_in, in, tirn, modify_tir_attr->tirn);
1402 MLX5_SET64(modify_tir_in, in, modify_bitmask,
1403 modify_tir_attr->modify_bitmask);
1404 tir_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1405 if (modify_tir_attr->modify_bitmask &
1406 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO) {
1407 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs,
1408 tir_attr->lro_timeout_period_usecs);
1409 MLX5_SET(tirc, tir_ctx, lro_enable_mask,
1410 tir_attr->lro_enable_mask);
1411 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz,
1412 tir_attr->lro_max_msg_sz);
1414 if (modify_tir_attr->modify_bitmask &
1415 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE)
1416 MLX5_SET(tirc, tir_ctx, indirect_table,
1417 tir_attr->indirect_table);
1418 if (modify_tir_attr->modify_bitmask &
1419 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH) {
1421 void *outer, *inner;
1423 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric,
1424 tir_attr->rx_hash_symmetric);
1425 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn);
1426 for (i = 0; i < 10; i++) {
1427 MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i],
1428 tir_attr->rx_hash_toeplitz_key[i]);
1430 outer = MLX5_ADDR_OF(tirc, tir_ctx,
1431 rx_hash_field_selector_outer);
1432 MLX5_SET(rx_hash_field_select, outer, l3_prot_type,
1433 tir_attr->rx_hash_field_selector_outer.l3_prot_type);
1434 MLX5_SET(rx_hash_field_select, outer, l4_prot_type,
1435 tir_attr->rx_hash_field_selector_outer.l4_prot_type);
1437 (rx_hash_field_select, outer, selected_fields,
1438 tir_attr->rx_hash_field_selector_outer.selected_fields);
1439 inner = MLX5_ADDR_OF(tirc, tir_ctx,
1440 rx_hash_field_selector_inner);
1441 MLX5_SET(rx_hash_field_select, inner, l3_prot_type,
1442 tir_attr->rx_hash_field_selector_inner.l3_prot_type);
1443 MLX5_SET(rx_hash_field_select, inner, l4_prot_type,
1444 tir_attr->rx_hash_field_selector_inner.l4_prot_type);
1446 (rx_hash_field_select, inner, selected_fields,
1447 tir_attr->rx_hash_field_selector_inner.selected_fields);
1449 if (modify_tir_attr->modify_bitmask &
1450 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN) {
1451 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block);
1453 ret = mlx5_glue->devx_obj_modify(tir->obj, in, sizeof(in),
1456 DRV_LOG(ERR, "Failed to modify TIR using DevX");
1464 * Create RQT using DevX API.
1467 * Context returned from mlx5 open_device() glue function.
1468 * @param [in] rqt_attr
1469 * Pointer to RQT attributes structure.
1472 * The DevX object created, NULL otherwise and rte_errno is set.
1474 struct mlx5_devx_obj *
1475 mlx5_devx_cmd_create_rqt(void *ctx,
1476 struct mlx5_devx_rqt_attr *rqt_attr)
1478 uint32_t *in = NULL;
1479 uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) +
1480 rqt_attr->rqt_actual_size * sizeof(uint32_t);
1481 uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0};
1483 struct mlx5_devx_obj *rqt = NULL;
1486 in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY);
1488 DRV_LOG(ERR, "Failed to allocate RQT IN data");
1492 rqt = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt), 0, SOCKET_ID_ANY);
1494 DRV_LOG(ERR, "Failed to allocate RQT data");
1499 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
1500 rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1501 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type);
1502 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size);
1503 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size);
1504 for (i = 0; i < rqt_attr->rqt_actual_size; i++)
1505 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]);
1506 rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out));
1509 DRV_LOG(ERR, "Failed to create RQT using DevX");
1514 rqt->id = MLX5_GET(create_rqt_out, out, rqtn);
1519 * Modify RQT using DevX API.
1522 * Pointer to RQT DevX object structure.
1523 * @param [in] rqt_attr
1524 * Pointer to RQT attributes structure.
1527 * 0 on success, a negative errno value otherwise and rte_errno is set.
1530 mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt,
1531 struct mlx5_devx_rqt_attr *rqt_attr)
1533 uint32_t inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) +
1534 rqt_attr->rqt_actual_size * sizeof(uint32_t);
1535 uint32_t out[MLX5_ST_SZ_DW(modify_rqt_out)] = {0};
1536 uint32_t *in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY);
1542 DRV_LOG(ERR, "Failed to allocate RQT modify IN data.");
1546 MLX5_SET(modify_rqt_in, in, opcode, MLX5_CMD_OP_MODIFY_RQT);
1547 MLX5_SET(modify_rqt_in, in, rqtn, rqt->id);
1548 MLX5_SET64(modify_rqt_in, in, modify_bitmask, 0x1);
1549 rqt_ctx = MLX5_ADDR_OF(modify_rqt_in, in, rqt_context);
1550 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type);
1551 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size);
1552 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size);
1553 for (i = 0; i < rqt_attr->rqt_actual_size; i++)
1554 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]);
1555 ret = mlx5_glue->devx_obj_modify(rqt->obj, in, inlen, out, sizeof(out));
1558 DRV_LOG(ERR, "Failed to modify RQT using DevX.");
1566 * Create SQ using DevX API.
1569 * Context returned from mlx5 open_device() glue function.
1570 * @param [in] sq_attr
1571 * Pointer to SQ attributes structure.
1572 * @param [in] socket
1573 * CPU socket ID for allocations.
1576 * The DevX object created, NULL otherwise and rte_errno is set.
1578 struct mlx5_devx_obj *
1579 mlx5_devx_cmd_create_sq(void *ctx,
1580 struct mlx5_devx_create_sq_attr *sq_attr)
1582 uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0};
1583 uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0};
1586 struct mlx5_devx_wq_attr *wq_attr;
1587 struct mlx5_devx_obj *sq = NULL;
1589 sq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sq), 0, SOCKET_ID_ANY);
1591 DRV_LOG(ERR, "Failed to allocate SQ data");
1595 MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ);
1596 sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx);
1597 MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky);
1598 MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master);
1599 MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre);
1600 MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en);
1601 MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe,
1602 sq_attr->allow_multi_pkt_send_wqe);
1603 MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode,
1604 sq_attr->min_wqe_inline_mode);
1605 MLX5_SET(sqc, sq_ctx, state, sq_attr->state);
1606 MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr);
1607 MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp);
1608 MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin);
1609 MLX5_SET(sqc, sq_ctx, non_wire, sq_attr->non_wire);
1610 MLX5_SET(sqc, sq_ctx, static_sq_wq, sq_attr->static_sq_wq);
1611 MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index);
1612 MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn);
1613 MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index,
1614 sq_attr->packet_pacing_rate_limit_index);
1615 MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz);
1616 MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num);
1617 MLX5_SET(sqc, sq_ctx, ts_format, sq_attr->ts_format);
1618 wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq);
1619 wq_attr = &sq_attr->wq_attr;
1620 devx_cmd_fill_wq_data(wq_ctx, wq_attr);
1621 sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1624 DRV_LOG(ERR, "Failed to create SQ using DevX");
1629 sq->id = MLX5_GET(create_sq_out, out, sqn);
1634 * Modify SQ using DevX API.
1637 * Pointer to SQ object structure.
1638 * @param [in] sq_attr
1639 * Pointer to SQ attributes structure.
1642 * 0 on success, a negative errno value otherwise and rte_errno is set.
1645 mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq,
1646 struct mlx5_devx_modify_sq_attr *sq_attr)
1648 uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0};
1649 uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0};
1653 MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ);
1654 MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state);
1655 MLX5_SET(modify_sq_in, in, sqn, sq->id);
1656 sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1657 MLX5_SET(sqc, sq_ctx, state, sq_attr->state);
1658 MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq);
1659 MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca);
1660 ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in),
1663 DRV_LOG(ERR, "Failed to modify SQ using DevX");
1671 * Create TIS using DevX API.
1674 * Context returned from mlx5 open_device() glue function.
1675 * @param [in] tis_attr
1676 * Pointer to TIS attributes structure.
1679 * The DevX object created, NULL otherwise and rte_errno is set.
1681 struct mlx5_devx_obj *
1682 mlx5_devx_cmd_create_tis(void *ctx,
1683 struct mlx5_devx_tis_attr *tis_attr)
1685 uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
1686 uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0};
1687 struct mlx5_devx_obj *tis = NULL;
1690 tis = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tis), 0, SOCKET_ID_ANY);
1692 DRV_LOG(ERR, "Failed to allocate TIS object");
1696 MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS);
1697 tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx);
1698 MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity,
1699 tis_attr->strict_lag_tx_port_affinity);
1700 MLX5_SET(tisc, tis_ctx, lag_tx_port_affinity,
1701 tis_attr->lag_tx_port_affinity);
1702 MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio);
1703 MLX5_SET(tisc, tis_ctx, transport_domain,
1704 tis_attr->transport_domain);
1705 tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1708 DRV_LOG(ERR, "Failed to create TIS using DevX");
1713 tis->id = MLX5_GET(create_tis_out, out, tisn);
1718 * Create transport domain using DevX API.
1721 * Context returned from mlx5 open_device() glue function.
1723 * The DevX object created, NULL otherwise and rte_errno is set.
1725 struct mlx5_devx_obj *
1726 mlx5_devx_cmd_create_td(void *ctx)
1728 uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0};
1729 uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0};
1730 struct mlx5_devx_obj *td = NULL;
1732 td = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*td), 0, SOCKET_ID_ANY);
1734 DRV_LOG(ERR, "Failed to allocate TD object");
1738 MLX5_SET(alloc_transport_domain_in, in, opcode,
1739 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN);
1740 td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1743 DRV_LOG(ERR, "Failed to create TIS using DevX");
1748 td->id = MLX5_GET(alloc_transport_domain_out, out,
1754 * Dump all flows to file.
1756 * @param[in] fdb_domain
1758 * @param[in] rx_domain
1760 * @param[in] tx_domain
1763 * Pointer to file stream.
1766 * 0 on success, a nagative value otherwise.
1769 mlx5_devx_cmd_flow_dump(void *fdb_domain __rte_unused,
1770 void *rx_domain __rte_unused,
1771 void *tx_domain __rte_unused, FILE *file __rte_unused)
1775 #ifdef HAVE_MLX5_DR_FLOW_DUMP
1777 ret = mlx5_glue->dr_dump_domain(file, fdb_domain);
1781 MLX5_ASSERT(rx_domain);
1782 ret = mlx5_glue->dr_dump_domain(file, rx_domain);
1785 MLX5_ASSERT(tx_domain);
1786 ret = mlx5_glue->dr_dump_domain(file, tx_domain);
1794 mlx5_devx_cmd_flow_single_dump(void *rule_info __rte_unused,
1795 FILE *file __rte_unused)
1798 #ifdef HAVE_MLX5_DR_FLOW_DUMP_RULE
1800 ret = mlx5_glue->dr_dump_rule(file, rule_info);
1808 * Create CQ using DevX API.
1811 * Context returned from mlx5 open_device() glue function.
1813 * Pointer to CQ attributes structure.
1816 * The DevX object created, NULL otherwise and rte_errno is set.
1818 struct mlx5_devx_obj *
1819 mlx5_devx_cmd_create_cq(void *ctx, struct mlx5_devx_cq_attr *attr)
1821 uint32_t in[MLX5_ST_SZ_DW(create_cq_in)] = {0};
1822 uint32_t out[MLX5_ST_SZ_DW(create_cq_out)] = {0};
1823 struct mlx5_devx_obj *cq_obj = mlx5_malloc(MLX5_MEM_ZERO,
1826 void *cqctx = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1829 DRV_LOG(ERR, "Failed to allocate CQ object memory.");
1833 MLX5_SET(create_cq_in, in, opcode, MLX5_CMD_OP_CREATE_CQ);
1834 if (attr->db_umem_valid) {
1835 MLX5_SET(cqc, cqctx, dbr_umem_valid, attr->db_umem_valid);
1836 MLX5_SET(cqc, cqctx, dbr_umem_id, attr->db_umem_id);
1837 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_umem_offset);
1839 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_addr);
1841 MLX5_SET(cqc, cqctx, cqe_sz, (RTE_CACHE_LINE_SIZE == 128) ?
1842 MLX5_CQE_SIZE_128B : MLX5_CQE_SIZE_64B);
1843 MLX5_SET(cqc, cqctx, cc, attr->use_first_only);
1844 MLX5_SET(cqc, cqctx, oi, attr->overrun_ignore);
1845 MLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size);
1846 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT)
1847 MLX5_SET(cqc, cqctx, log_page_size,
1848 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT);
1849 MLX5_SET(cqc, cqctx, c_eqn, attr->eqn);
1850 MLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id);
1851 MLX5_SET(cqc, cqctx, cqe_comp_en, !!attr->cqe_comp_en);
1852 MLX5_SET(cqc, cqctx, mini_cqe_res_format, attr->mini_cqe_res_format);
1853 MLX5_SET(cqc, cqctx, mini_cqe_res_format_ext,
1854 attr->mini_cqe_res_format_ext);
1855 if (attr->q_umem_valid) {
1856 MLX5_SET(create_cq_in, in, cq_umem_valid, attr->q_umem_valid);
1857 MLX5_SET(create_cq_in, in, cq_umem_id, attr->q_umem_id);
1858 MLX5_SET64(create_cq_in, in, cq_umem_offset,
1859 attr->q_umem_offset);
1861 cq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
1865 DRV_LOG(ERR, "Failed to create CQ using DevX errno=%d.", errno);
1869 cq_obj->id = MLX5_GET(create_cq_out, out, cqn);
1874 * Create VIRTQ using DevX API.
1877 * Context returned from mlx5 open_device() glue function.
1879 * Pointer to VIRTQ attributes structure.
1882 * The DevX object created, NULL otherwise and rte_errno is set.
1884 struct mlx5_devx_obj *
1885 mlx5_devx_cmd_create_virtq(void *ctx,
1886 struct mlx5_devx_virtq_attr *attr)
1888 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0};
1889 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
1890 struct mlx5_devx_obj *virtq_obj = mlx5_malloc(MLX5_MEM_ZERO,
1893 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq);
1894 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr);
1895 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context);
1898 DRV_LOG(ERR, "Failed to allocate virtq data.");
1902 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
1903 MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
1904 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
1905 MLX5_GENERAL_OBJ_TYPE_VIRTQ);
1906 MLX5_SET16(virtio_net_q, virtq, hw_available_index,
1907 attr->hw_available_index);
1908 MLX5_SET16(virtio_net_q, virtq, hw_used_index, attr->hw_used_index);
1909 MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4);
1910 MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6);
1911 MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum);
1912 MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum);
1913 MLX5_SET16(virtio_q, virtctx, virtio_version_1_0,
1914 attr->virtio_version_1_0);
1915 MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode);
1916 MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id);
1917 MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr);
1918 MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr);
1919 MLX5_SET64(virtio_q, virtctx, available_addr, attr->available_addr);
1920 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index);
1921 MLX5_SET16(virtio_q, virtctx, queue_size, attr->q_size);
1922 MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey);
1923 MLX5_SET(virtio_q, virtctx, umem_1_id, attr->umems[0].id);
1924 MLX5_SET(virtio_q, virtctx, umem_1_size, attr->umems[0].size);
1925 MLX5_SET64(virtio_q, virtctx, umem_1_offset, attr->umems[0].offset);
1926 MLX5_SET(virtio_q, virtctx, umem_2_id, attr->umems[1].id);
1927 MLX5_SET(virtio_q, virtctx, umem_2_size, attr->umems[1].size);
1928 MLX5_SET64(virtio_q, virtctx, umem_2_offset, attr->umems[1].offset);
1929 MLX5_SET(virtio_q, virtctx, umem_3_id, attr->umems[2].id);
1930 MLX5_SET(virtio_q, virtctx, umem_3_size, attr->umems[2].size);
1931 MLX5_SET64(virtio_q, virtctx, umem_3_offset, attr->umems[2].offset);
1932 MLX5_SET(virtio_q, virtctx, counter_set_id, attr->counters_obj_id);
1933 MLX5_SET(virtio_q, virtctx, pd, attr->pd);
1934 MLX5_SET(virtio_q, virtctx, queue_period_mode, attr->hw_latency_mode);
1935 MLX5_SET(virtio_q, virtctx, queue_period_us, attr->hw_max_latency_us);
1936 MLX5_SET(virtio_q, virtctx, queue_max_count, attr->hw_max_pending_comp);
1937 MLX5_SET(virtio_net_q, virtq, tisn_or_qpn, attr->tis_id);
1938 virtq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
1940 if (!virtq_obj->obj) {
1942 DRV_LOG(ERR, "Failed to create VIRTQ Obj using DevX.");
1943 mlx5_free(virtq_obj);
1946 virtq_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
1951 * Modify VIRTQ using DevX API.
1953 * @param[in] virtq_obj
1954 * Pointer to virtq object structure.
1956 * Pointer to modify virtq attributes structure.
1959 * 0 on success, a negative errno value otherwise and rte_errno is set.
1962 mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj,
1963 struct mlx5_devx_virtq_attr *attr)
1965 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0};
1966 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
1967 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq);
1968 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr);
1969 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context);
1972 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
1973 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT);
1974 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
1975 MLX5_GENERAL_OBJ_TYPE_VIRTQ);
1976 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id);
1977 MLX5_SET64(virtio_net_q, virtq, modify_field_select, attr->type);
1978 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index);
1979 switch (attr->type) {
1980 case MLX5_VIRTQ_MODIFY_TYPE_STATE:
1981 MLX5_SET16(virtio_net_q, virtq, state, attr->state);
1983 case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS:
1984 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_mkey,
1985 attr->dirty_bitmap_mkey);
1986 MLX5_SET64(virtio_net_q, virtq, dirty_bitmap_addr,
1987 attr->dirty_bitmap_addr);
1988 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_size,
1989 attr->dirty_bitmap_size);
1991 case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE:
1992 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_dump_enable,
1993 attr->dirty_bitmap_dump_enable);
1999 ret = mlx5_glue->devx_obj_modify(virtq_obj->obj, in, sizeof(in),
2002 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX.");
2010 * Query VIRTQ using DevX API.
2012 * @param[in] virtq_obj
2013 * Pointer to virtq object structure.
2014 * @param [in/out] attr
2015 * Pointer to virtq attributes structure.
2018 * 0 on success, a negative errno value otherwise and rte_errno is set.
2021 mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj,
2022 struct mlx5_devx_virtq_attr *attr)
2024 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
2025 uint32_t out[MLX5_ST_SZ_DW(query_virtq_out)] = {0};
2026 void *hdr = MLX5_ADDR_OF(query_virtq_out, in, hdr);
2027 void *virtq = MLX5_ADDR_OF(query_virtq_out, out, virtq);
2030 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2031 MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
2032 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2033 MLX5_GENERAL_OBJ_TYPE_VIRTQ);
2034 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id);
2035 ret = mlx5_glue->devx_obj_query(virtq_obj->obj, in, sizeof(in),
2038 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX.");
2042 attr->hw_available_index = MLX5_GET16(virtio_net_q, virtq,
2043 hw_available_index);
2044 attr->hw_used_index = MLX5_GET16(virtio_net_q, virtq, hw_used_index);
2045 attr->state = MLX5_GET16(virtio_net_q, virtq, state);
2046 attr->error_type = MLX5_GET16(virtio_net_q, virtq,
2047 virtio_q_context.error_type);
2052 * Create QP using DevX API.
2055 * Context returned from mlx5 open_device() glue function.
2057 * Pointer to QP attributes structure.
2060 * The DevX object created, NULL otherwise and rte_errno is set.
2062 struct mlx5_devx_obj *
2063 mlx5_devx_cmd_create_qp(void *ctx,
2064 struct mlx5_devx_qp_attr *attr)
2066 uint32_t in[MLX5_ST_SZ_DW(create_qp_in)] = {0};
2067 uint32_t out[MLX5_ST_SZ_DW(create_qp_out)] = {0};
2068 struct mlx5_devx_obj *qp_obj = mlx5_malloc(MLX5_MEM_ZERO,
2071 void *qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
2074 DRV_LOG(ERR, "Failed to allocate QP data.");
2078 MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP);
2079 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC);
2080 MLX5_SET(qpc, qpc, pd, attr->pd);
2081 MLX5_SET(qpc, qpc, ts_format, attr->ts_format);
2082 MLX5_SET(qpc, qpc, user_index, attr->user_index);
2083 if (attr->uar_index) {
2085 void *qpc_ext_and_pas_list = MLX5_ADDR_OF(create_qp_in,
2086 in, qpc_extension_and_pas_list);
2087 void *qpc_ext = MLX5_ADDR_OF(qpc_extension_and_pas_list,
2088 qpc_ext_and_pas_list, qpc_data_extension);
2089 MLX5_SET(qpc_extension, qpc_ext, mmo, 1);
2091 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
2092 MLX5_SET(qpc, qpc, uar_page, attr->uar_index);
2093 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT)
2094 MLX5_SET(qpc, qpc, log_page_size,
2095 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT);
2096 if (attr->sq_size) {
2097 MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->sq_size));
2098 MLX5_SET(qpc, qpc, cqn_snd, attr->cqn);
2099 MLX5_SET(qpc, qpc, log_sq_size,
2100 rte_log2_u32(attr->sq_size));
2102 MLX5_SET(qpc, qpc, no_sq, 1);
2104 if (attr->rq_size) {
2105 MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->rq_size));
2106 MLX5_SET(qpc, qpc, cqn_rcv, attr->cqn);
2107 MLX5_SET(qpc, qpc, log_rq_stride, attr->log_rq_stride -
2108 MLX5_LOG_RQ_STRIDE_SHIFT);
2109 MLX5_SET(qpc, qpc, log_rq_size,
2110 rte_log2_u32(attr->rq_size));
2111 MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ);
2113 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ);
2115 if (attr->dbr_umem_valid) {
2116 MLX5_SET(qpc, qpc, dbr_umem_valid,
2117 attr->dbr_umem_valid);
2118 MLX5_SET(qpc, qpc, dbr_umem_id, attr->dbr_umem_id);
2120 MLX5_SET64(qpc, qpc, dbr_addr, attr->dbr_address);
2121 MLX5_SET64(create_qp_in, in, wq_umem_offset,
2122 attr->wq_umem_offset);
2123 MLX5_SET(create_qp_in, in, wq_umem_id, attr->wq_umem_id);
2124 MLX5_SET(create_qp_in, in, wq_umem_valid, 1);
2126 /* Special QP to be managed by FW - no SQ\RQ\CQ\UAR\DB rec. */
2127 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ);
2128 MLX5_SET(qpc, qpc, no_sq, 1);
2130 qp_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
2134 DRV_LOG(ERR, "Failed to create QP Obj using DevX.");
2138 qp_obj->id = MLX5_GET(create_qp_out, out, qpn);
2143 * Modify QP using DevX API.
2144 * Currently supports only force loop-back QP.
2147 * Pointer to QP object structure.
2148 * @param [in] qp_st_mod_op
2149 * The QP state modification operation.
2150 * @param [in] remote_qp_id
2151 * The remote QP ID for MLX5_CMD_OP_INIT2RTR_QP operation.
2154 * 0 on success, a negative errno value otherwise and rte_errno is set.
2157 mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op,
2158 uint32_t remote_qp_id)
2161 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)];
2162 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)];
2163 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)];
2166 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)];
2167 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)];
2168 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)];
2173 unsigned int outlen;
2175 memset(&in, 0, sizeof(in));
2176 memset(&out, 0, sizeof(out));
2177 MLX5_SET(rst2init_qp_in, &in, opcode, qp_st_mod_op);
2178 switch (qp_st_mod_op) {
2179 case MLX5_CMD_OP_RST2INIT_QP:
2180 MLX5_SET(rst2init_qp_in, &in, qpn, qp->id);
2181 qpc = MLX5_ADDR_OF(rst2init_qp_in, &in, qpc);
2182 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1);
2183 MLX5_SET(qpc, qpc, rre, 1);
2184 MLX5_SET(qpc, qpc, rwe, 1);
2185 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
2186 inlen = sizeof(in.rst2init);
2187 outlen = sizeof(out.rst2init);
2189 case MLX5_CMD_OP_INIT2RTR_QP:
2190 MLX5_SET(init2rtr_qp_in, &in, qpn, qp->id);
2191 qpc = MLX5_ADDR_OF(init2rtr_qp_in, &in, qpc);
2192 MLX5_SET(qpc, qpc, primary_address_path.fl, 1);
2193 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1);
2194 MLX5_SET(qpc, qpc, mtu, 1);
2195 MLX5_SET(qpc, qpc, log_msg_max, 30);
2196 MLX5_SET(qpc, qpc, remote_qpn, remote_qp_id);
2197 MLX5_SET(qpc, qpc, min_rnr_nak, 0);
2198 inlen = sizeof(in.init2rtr);
2199 outlen = sizeof(out.init2rtr);
2201 case MLX5_CMD_OP_RTR2RTS_QP:
2202 qpc = MLX5_ADDR_OF(rtr2rts_qp_in, &in, qpc);
2203 MLX5_SET(rtr2rts_qp_in, &in, qpn, qp->id);
2204 MLX5_SET(qpc, qpc, primary_address_path.ack_timeout, 14);
2205 MLX5_SET(qpc, qpc, log_ack_req_freq, 0);
2206 MLX5_SET(qpc, qpc, retry_count, 7);
2207 MLX5_SET(qpc, qpc, rnr_retry, 7);
2208 inlen = sizeof(in.rtr2rts);
2209 outlen = sizeof(out.rtr2rts);
2212 DRV_LOG(ERR, "Invalid or unsupported QP modify op %u.",
2217 ret = mlx5_glue->devx_obj_modify(qp->obj, &in, inlen, &out, outlen);
2219 DRV_LOG(ERR, "Failed to modify QP using DevX.");
2226 struct mlx5_devx_obj *
2227 mlx5_devx_cmd_create_virtio_q_counters(void *ctx)
2229 uint32_t in[MLX5_ST_SZ_DW(create_virtio_q_counters_in)] = {0};
2230 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2231 struct mlx5_devx_obj *couners_obj = mlx5_malloc(MLX5_MEM_ZERO,
2232 sizeof(*couners_obj), 0,
2234 void *hdr = MLX5_ADDR_OF(create_virtio_q_counters_in, in, hdr);
2237 DRV_LOG(ERR, "Failed to allocate virtio queue counters data.");
2241 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2242 MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2243 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2244 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS);
2245 couners_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
2247 if (!couners_obj->obj) {
2249 DRV_LOG(ERR, "Failed to create virtio queue counters Obj using"
2251 mlx5_free(couners_obj);
2254 couners_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2259 mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj,
2260 struct mlx5_devx_virtio_q_couners_attr *attr)
2262 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
2263 uint32_t out[MLX5_ST_SZ_DW(query_virtio_q_counters_out)] = {0};
2264 void *hdr = MLX5_ADDR_OF(query_virtio_q_counters_out, in, hdr);
2265 void *virtio_q_counters = MLX5_ADDR_OF(query_virtio_q_counters_out, out,
2269 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2270 MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
2271 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2272 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS);
2273 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, couners_obj->id);
2274 ret = mlx5_glue->devx_obj_query(couners_obj->obj, in, sizeof(in), out,
2277 DRV_LOG(ERR, "Failed to query virtio q counters using DevX.");
2281 attr->received_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters,
2283 attr->completed_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters,
2285 attr->error_cqes = MLX5_GET(virtio_q_counters, virtio_q_counters,
2287 attr->bad_desc_errors = MLX5_GET(virtio_q_counters, virtio_q_counters,
2289 attr->exceed_max_chain = MLX5_GET(virtio_q_counters, virtio_q_counters,
2291 attr->invalid_buffer = MLX5_GET(virtio_q_counters, virtio_q_counters,
2297 * Create general object of type FLOW_HIT_ASO using DevX API.
2300 * Context returned from mlx5 open_device() glue function.
2302 * PD value to associate the FLOW_HIT_ASO object with.
2305 * The DevX object created, NULL otherwise and rte_errno is set.
2307 struct mlx5_devx_obj *
2308 mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, uint32_t pd)
2310 uint32_t in[MLX5_ST_SZ_DW(create_flow_hit_aso_in)] = {0};
2311 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2312 struct mlx5_devx_obj *flow_hit_aso_obj = NULL;
2315 flow_hit_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*flow_hit_aso_obj),
2317 if (!flow_hit_aso_obj) {
2318 DRV_LOG(ERR, "Failed to allocate FLOW_HIT_ASO object data");
2322 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, hdr);
2323 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2324 MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2325 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2326 MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO);
2327 ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, flow_hit_aso);
2328 MLX5_SET(flow_hit_aso, ptr, access_pd, pd);
2329 flow_hit_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2331 if (!flow_hit_aso_obj->obj) {
2333 DRV_LOG(ERR, "Failed to create FLOW_HIT_ASO obj using DevX.");
2334 mlx5_free(flow_hit_aso_obj);
2337 flow_hit_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2338 return flow_hit_aso_obj;
2342 * Create PD using DevX API.
2345 * Context returned from mlx5 open_device() glue function.
2348 * The DevX object created, NULL otherwise and rte_errno is set.
2350 struct mlx5_devx_obj *
2351 mlx5_devx_cmd_alloc_pd(void *ctx)
2353 struct mlx5_devx_obj *ppd =
2354 mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ppd), 0, SOCKET_ID_ANY);
2355 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {0};
2356 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {0};
2359 DRV_LOG(ERR, "Failed to allocate PD data.");
2363 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD);
2364 ppd->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2368 DRV_LOG(ERR, "Failed to allocate PD Obj using DevX.");
2372 ppd->id = MLX5_GET(alloc_pd_out, out, pd);
2377 * Create general object of type FLOW_METER_ASO using DevX API.
2380 * Context returned from mlx5 open_device() glue function.
2382 * PD value to associate the FLOW_METER_ASO object with.
2383 * @param [in] log_obj_size
2384 * log_obj_size define to allocate number of 2 * meters
2385 * in one FLOW_METER_ASO object.
2388 * The DevX object created, NULL otherwise and rte_errno is set.
2390 struct mlx5_devx_obj *
2391 mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx, uint32_t pd,
2392 uint32_t log_obj_size)
2394 uint32_t in[MLX5_ST_SZ_DW(create_flow_meter_aso_in)] = {0};
2395 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)];
2396 struct mlx5_devx_obj *flow_meter_aso_obj;
2399 flow_meter_aso_obj = mlx5_malloc(MLX5_MEM_ZERO,
2400 sizeof(*flow_meter_aso_obj),
2402 if (!flow_meter_aso_obj) {
2403 DRV_LOG(ERR, "Failed to allocate FLOW_METER_ASO object data");
2407 ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, hdr);
2408 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2409 MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2410 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2411 MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO);
2412 MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range,
2414 ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, flow_meter_aso);
2415 MLX5_SET(flow_meter_aso, ptr, access_pd, pd);
2416 flow_meter_aso_obj->obj = mlx5_glue->devx_obj_create(
2417 ctx, in, sizeof(in),
2419 if (!flow_meter_aso_obj->obj) {
2421 DRV_LOG(ERR, "Failed to create FLOW_METER_ASO obj using DevX.");
2422 mlx5_free(flow_meter_aso_obj);
2425 flow_meter_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr,
2427 return flow_meter_aso_obj;
2431 * Create general object of type CONN_TRACK_OFFLOAD using DevX API.
2434 * Context returned from mlx5 open_device() glue function.
2436 * PD value to associate the CONN_TRACK_OFFLOAD ASO object with.
2437 * @param [in] log_obj_size
2438 * log_obj_size to allocate its power of 2 * objects
2439 * in one CONN_TRACK_OFFLOAD bulk allocation.
2442 * The DevX object created, NULL otherwise and rte_errno is set.
2444 struct mlx5_devx_obj *
2445 mlx5_devx_cmd_create_conn_track_offload_obj(void *ctx, uint32_t pd,
2446 uint32_t log_obj_size)
2448 uint32_t in[MLX5_ST_SZ_DW(create_conn_track_aso_in)] = {0};
2449 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)];
2450 struct mlx5_devx_obj *ct_aso_obj;
2453 ct_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ct_aso_obj),
2456 DRV_LOG(ERR, "Failed to allocate CONN_TRACK_OFFLOAD object.");
2460 ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, hdr);
2461 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2462 MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2463 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2464 MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD);
2465 MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range, log_obj_size);
2466 ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, conn_track_offload);
2467 MLX5_SET(conn_track_offload, ptr, conn_track_aso_access_pd, pd);
2468 ct_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2470 if (!ct_aso_obj->obj) {
2472 DRV_LOG(ERR, "Failed to create CONN_TRACK_OFFLOAD obj by using DevX.");
2473 mlx5_free(ct_aso_obj);
2476 ct_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2481 * Create general object of type GENEVE TLV option using DevX API.
2484 * Context returned from mlx5 open_device() glue function.
2486 * TLV option variable value of class
2488 * TLV option variable value of type
2490 * TLV option variable value of len
2493 * The DevX object created, NULL otherwise and rte_errno is set.
2495 struct mlx5_devx_obj *
2496 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx,
2497 uint16_t class, uint8_t type, uint8_t len)
2499 uint32_t in[MLX5_ST_SZ_DW(create_geneve_tlv_option_in)] = {0};
2500 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2501 struct mlx5_devx_obj *geneve_tlv_opt_obj = mlx5_malloc(MLX5_MEM_ZERO,
2502 sizeof(*geneve_tlv_opt_obj),
2505 if (!geneve_tlv_opt_obj) {
2506 DRV_LOG(ERR, "Failed to allocate geneve tlv option object.");
2510 void *hdr = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, hdr);
2511 void *opt = MLX5_ADDR_OF(create_geneve_tlv_option_in, in,
2513 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2514 MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2515 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2516 MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT);
2517 MLX5_SET(geneve_tlv_option, opt, option_class,
2518 rte_be_to_cpu_16(class));
2519 MLX5_SET(geneve_tlv_option, opt, option_type, type);
2520 MLX5_SET(geneve_tlv_option, opt, option_data_length, len);
2521 geneve_tlv_opt_obj->obj = mlx5_glue->devx_obj_create(ctx, in,
2522 sizeof(in), out, sizeof(out));
2523 if (!geneve_tlv_opt_obj->obj) {
2525 DRV_LOG(ERR, "Failed to create Geneve tlv option "
2527 mlx5_free(geneve_tlv_opt_obj);
2530 geneve_tlv_opt_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2531 return geneve_tlv_opt_obj;
2535 mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id)
2537 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2538 uint32_t in[MLX5_ST_SZ_DW(query_rq_in)] = {0};
2539 uint32_t out[MLX5_ST_SZ_DW(query_rq_out)] = {0};
2543 MLX5_SET(query_rq_in, in, opcode, MLX5_CMD_OP_QUERY_RQ);
2544 MLX5_SET(query_rq_in, in, rqn, ((struct ibv_wq *)wq)->wq_num);
2545 rc = mlx5_glue->devx_wq_query(wq, in, sizeof(in), out, sizeof(out));
2548 DRV_LOG(ERR, "Failed to query WQ counter set ID using DevX - "
2549 "rc = %d, errno = %d.", rc, errno);
2552 rq_ctx = MLX5_ADDR_OF(query_rq_out, out, rq_context);
2553 *counter_set_id = MLX5_GET(rqc, rq_ctx, counter_set_id);
2557 (void)counter_set_id;
2563 * Allocate queue counters via devx interface.
2566 * Context returned from mlx5 open_device() glue function.
2569 * Pointer to counter object on success, a NULL value otherwise and
2572 struct mlx5_devx_obj *
2573 mlx5_devx_cmd_queue_counter_alloc(void *ctx)
2575 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 0,
2577 uint32_t in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {0};
2578 uint32_t out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {0};
2584 MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER);
2585 dcs->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
2588 DRV_LOG(DEBUG, "Can't allocate q counter set by DevX - error "
2594 dcs->id = MLX5_GET(alloc_q_counter_out, out, counter_set_id);
2599 * Query queue counters values.
2602 * devx object of the queue counter set.
2604 * Whether hardware should clear the counters after the query or not.
2605 * @param[out] out_of_buffers
2606 * Number of dropped occurred due to lack of WQE for the associated QPs/RQs.
2609 * 0 on success, a negative value otherwise.
2612 mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear,
2613 uint32_t *out_of_buffers)
2615 uint32_t out[MLX5_ST_SZ_BYTES(query_q_counter_out)] = {0};
2616 uint32_t in[MLX5_ST_SZ_DW(query_q_counter_in)] = {0};
2619 MLX5_SET(query_q_counter_in, in, opcode,
2620 MLX5_CMD_OP_QUERY_Q_COUNTER);
2621 MLX5_SET(query_q_counter_in, in, op_mod, 0);
2622 MLX5_SET(query_q_counter_in, in, counter_set_id, dcs->id);
2623 MLX5_SET(query_q_counter_in, in, clear, !!clear);
2624 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out,
2627 DRV_LOG(ERR, "Failed to query devx q counter set - rc %d", rc);
2631 *out_of_buffers = MLX5_GET(query_q_counter_out, out, out_of_buffer);
2636 * Create general object of type DEK using DevX API.
2639 * Context returned from mlx5 open_device() glue function.
2641 * Pointer to DEK attributes structure.
2644 * The DevX object created, NULL otherwise and rte_errno is set.
2646 struct mlx5_devx_obj *
2647 mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr)
2649 uint32_t in[MLX5_ST_SZ_DW(create_dek_in)] = {0};
2650 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2651 struct mlx5_devx_obj *dek_obj = NULL;
2652 void *ptr = NULL, *key_addr = NULL;
2654 dek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dek_obj),
2656 if (dek_obj == NULL) {
2657 DRV_LOG(ERR, "Failed to allocate DEK object data");
2661 ptr = MLX5_ADDR_OF(create_dek_in, in, hdr);
2662 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2663 MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2664 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2665 MLX5_GENERAL_OBJ_TYPE_DEK);
2666 ptr = MLX5_ADDR_OF(create_dek_in, in, dek);
2667 MLX5_SET(dek, ptr, key_size, attr->key_size);
2668 MLX5_SET(dek, ptr, has_keytag, attr->has_keytag);
2669 MLX5_SET(dek, ptr, key_purpose, attr->key_purpose);
2670 MLX5_SET(dek, ptr, pd, attr->pd);
2671 MLX5_SET64(dek, ptr, opaque, attr->opaque);
2672 key_addr = MLX5_ADDR_OF(dek, ptr, key);
2673 memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE);
2674 dek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2676 if (dek_obj->obj == NULL) {
2678 DRV_LOG(ERR, "Failed to create DEK obj using DevX.");
2682 dek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2687 * Create general object of type IMPORT_KEK using DevX API.
2690 * Context returned from mlx5 open_device() glue function.
2692 * Pointer to IMPORT_KEK attributes structure.
2695 * The DevX object created, NULL otherwise and rte_errno is set.
2697 struct mlx5_devx_obj *
2698 mlx5_devx_cmd_create_import_kek_obj(void *ctx,
2699 struct mlx5_devx_import_kek_attr *attr)
2701 uint32_t in[MLX5_ST_SZ_DW(create_import_kek_in)] = {0};
2702 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2703 struct mlx5_devx_obj *import_kek_obj = NULL;
2704 void *ptr = NULL, *key_addr = NULL;
2706 import_kek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*import_kek_obj),
2708 if (import_kek_obj == NULL) {
2709 DRV_LOG(ERR, "Failed to allocate IMPORT_KEK object data");
2713 ptr = MLX5_ADDR_OF(create_import_kek_in, in, hdr);
2714 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2715 MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2716 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2717 MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK);
2718 ptr = MLX5_ADDR_OF(create_import_kek_in, in, import_kek);
2719 MLX5_SET(import_kek, ptr, key_size, attr->key_size);
2720 key_addr = MLX5_ADDR_OF(import_kek, ptr, key);
2721 memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE);
2722 import_kek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2724 if (import_kek_obj->obj == NULL) {
2726 DRV_LOG(ERR, "Failed to create IMPORT_KEK object using DevX.");
2727 mlx5_free(import_kek_obj);
2730 import_kek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2731 return import_kek_obj;
2735 * Create general object of type CREDENTIAL using DevX API.
2738 * Context returned from mlx5 open_device() glue function.
2740 * Pointer to CREDENTIAL attributes structure.
2743 * The DevX object created, NULL otherwise and rte_errno is set.
2745 struct mlx5_devx_obj *
2746 mlx5_devx_cmd_create_credential_obj(void *ctx,
2747 struct mlx5_devx_credential_attr *attr)
2749 uint32_t in[MLX5_ST_SZ_DW(create_credential_in)] = {0};
2750 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2751 struct mlx5_devx_obj *credential_obj = NULL;
2752 void *ptr = NULL, *credential_addr = NULL;
2754 credential_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*credential_obj),
2756 if (credential_obj == NULL) {
2757 DRV_LOG(ERR, "Failed to allocate CREDENTIAL object data");
2761 ptr = MLX5_ADDR_OF(create_credential_in, in, hdr);
2762 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2763 MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2764 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2765 MLX5_GENERAL_OBJ_TYPE_CREDENTIAL);
2766 ptr = MLX5_ADDR_OF(create_credential_in, in, credential);
2767 MLX5_SET(credential, ptr, credential_role, attr->credential_role);
2768 credential_addr = MLX5_ADDR_OF(credential, ptr, credential);
2769 memcpy(credential_addr, (void *)(attr->credential),
2770 MLX5_CRYPTO_CREDENTIAL_SIZE);
2771 credential_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2773 if (credential_obj->obj == NULL) {
2775 DRV_LOG(ERR, "Failed to create CREDENTIAL object using DevX.");
2776 mlx5_free(credential_obj);
2779 credential_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2780 return credential_obj;
2784 * Create general object of type CRYPTO_LOGIN using DevX API.
2787 * Context returned from mlx5 open_device() glue function.
2789 * Pointer to CRYPTO_LOGIN attributes structure.
2792 * The DevX object created, NULL otherwise and rte_errno is set.
2794 struct mlx5_devx_obj *
2795 mlx5_devx_cmd_create_crypto_login_obj(void *ctx,
2796 struct mlx5_devx_crypto_login_attr *attr)
2798 uint32_t in[MLX5_ST_SZ_DW(create_crypto_login_in)] = {0};
2799 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2800 struct mlx5_devx_obj *crypto_login_obj = NULL;
2801 void *ptr = NULL, *credential_addr = NULL;
2803 crypto_login_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*crypto_login_obj),
2805 if (crypto_login_obj == NULL) {
2806 DRV_LOG(ERR, "Failed to allocate CRYPTO_LOGIN object data");
2810 ptr = MLX5_ADDR_OF(create_crypto_login_in, in, hdr);
2811 MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2812 MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2813 MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2814 MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN);
2815 ptr = MLX5_ADDR_OF(create_crypto_login_in, in, crypto_login);
2816 MLX5_SET(crypto_login, ptr, credential_pointer,
2817 attr->credential_pointer);
2818 MLX5_SET(crypto_login, ptr, session_import_kek_ptr,
2819 attr->session_import_kek_ptr);
2820 credential_addr = MLX5_ADDR_OF(crypto_login, ptr, credential);
2821 memcpy(credential_addr, (void *)(attr->credential),
2822 MLX5_CRYPTO_CREDENTIAL_SIZE);
2823 crypto_login_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2825 if (crypto_login_obj->obj == NULL) {
2827 DRV_LOG(ERR, "Failed to create CRYPTO_LOGIN obj using DevX.");
2828 mlx5_free(crypto_login_obj);
2831 crypto_login_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2832 return crypto_login_obj;
2836 * Query LAG context.
2839 * Pointer to ibv_context, returned from mlx5dv_open_device.
2840 * @param[out] lag_ctx
2841 * Pointer to struct mlx5_devx_lag_context, to be set by the routine.
2844 * 0 on success, a negative value otherwise.
2847 mlx5_devx_cmd_query_lag(void *ctx,
2848 struct mlx5_devx_lag_context *lag_ctx)
2850 uint32_t in[MLX5_ST_SZ_DW(query_lag_in)] = {0};
2851 uint32_t out[MLX5_ST_SZ_DW(query_lag_out)] = {0};
2855 MLX5_SET(query_lag_in, in, opcode, MLX5_CMD_OP_QUERY_LAG);
2856 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
2859 lctx = MLX5_ADDR_OF(query_lag_out, out, context);
2860 lag_ctx->fdb_selection_mode = MLX5_GET(lag_context, lctx,
2861 fdb_selection_mode);
2862 lag_ctx->port_select_mode = MLX5_GET(lag_context, lctx,
2864 lag_ctx->lag_state = MLX5_GET(lag_context, lctx, lag_state);
2865 lag_ctx->tx_remap_affinity_2 = MLX5_GET(lag_context, lctx,
2866 tx_remap_affinity_2);
2867 lag_ctx->tx_remap_affinity_1 = MLX5_GET(lag_context, lctx,
2868 tx_remap_affinity_1);
2871 rc = (rc > 0) ? -rc : rc;