drivers/common/mlx5/mlx5_devx_cmds.c

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /* Copyright 2018 Mellanox Technologies, Ltd */
   3
   4 #include <unistd.h>
   5
   6 #include <rte_errno.h>
   7 #include <rte_malloc.h>
   8 #include <rte_eal_paging.h>
   9
  10 #include "mlx5_prm.h"
  11 #include "mlx5_devx_cmds.h"
  12 #include "mlx5_common_utils.h"
  13 #include "mlx5_malloc.h"
  14
  15
  16 /**
  17  * Perform read access to the registers. Reads data from register
  18  * and writes ones to the specified buffer.
  19  *
  20  * @param[in] ctx
  21  *   Context returned from mlx5 open_device() glue function.
  22  * @param[in] reg_id
  23  *   Register identifier according to the PRM.
  24  * @param[in] arg
  25  *   Register access auxiliary parameter according to the PRM.
  26  * @param[out] data
  27  *   Pointer to the buffer to store read data.
  28  * @param[in] dw_cnt
  29  *   Buffer size in double words.
  30  *
  31  * @return
  32  *   0 on success, a negative value otherwise.
  33  */
  34 int
  35 mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg,
  36                             uint32_t *data, uint32_t dw_cnt)
  37 {
  38         uint32_t in[MLX5_ST_SZ_DW(access_register_in)]   = {0};
  39         uint32_t out[MLX5_ST_SZ_DW(access_register_out) +
  40                      MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0};
  41         int status, rc;
  42
  43         MLX5_ASSERT(data && dw_cnt);
  44         MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX);
  45         if (dw_cnt  > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) {
  46                 DRV_LOG(ERR, "Not enough  buffer for register read data");
  47                 return -1;
  48         }
  49         MLX5_SET(access_register_in, in, opcode,
  50                  MLX5_CMD_OP_ACCESS_REGISTER_USER);
  51         MLX5_SET(access_register_in, in, op_mod,
  52                                         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ);
  53         MLX5_SET(access_register_in, in, register_id, reg_id);
  54         MLX5_SET(access_register_in, in, argument, arg);
  55         rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out,
  56                                          MLX5_ST_SZ_DW(access_register_out) *
  57                                          sizeof(uint32_t) + dw_cnt);
  58         if (rc)
  59                 goto error;
  60         status = MLX5_GET(access_register_out, out, status);
  61         if (status) {
  62                 int syndrome = MLX5_GET(access_register_out, out, syndrome);
  63
  64                 DRV_LOG(DEBUG, "Failed to access NIC register 0x%X, "
  65                                "status %x, syndrome = %x",
  66                                reg_id, status, syndrome);
  67                 return -1;
  68         }
  69         memcpy(data, &out[MLX5_ST_SZ_DW(access_register_out)],
  70                dw_cnt * sizeof(uint32_t));
  71         return 0;
  72 error:
  73         rc = (rc > 0) ? -rc : rc;
  74         return rc;
  75 }
  76
  77 /**
  78  * Allocate flow counters via devx interface.
  79  *
  80  * @param[in] ctx
  81  *   Context returned from mlx5 open_device() glue function.
  82  * @param dcs
  83  *   Pointer to counters properties structure to be filled by the routine.
  84  * @param bulk_n_128
  85  *   Bulk counter numbers in 128 counters units.
  86  *
  87  * @return
  88  *   Pointer to counter object on success, a negative value otherwise and
  89  *   rte_errno is set.
  90  */
  91 struct mlx5_devx_obj *
  92 mlx5_devx_cmd_flow_counter_alloc(void *ctx, uint32_t bulk_n_128)
  93 {
  94         struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs),
  95                                                 0, SOCKET_ID_ANY);
  96         uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)]   = {0};
  97         uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0};
  98
  99         if (!dcs) {
 100                 rte_errno = ENOMEM;
 101                 return NULL;
 102         }
 103         MLX5_SET(alloc_flow_counter_in, in, opcode,
 104                  MLX5_CMD_OP_ALLOC_FLOW_COUNTER);
 105         MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128);
 106         dcs->obj = mlx5_glue->devx_obj_create(ctx, in,
 107                                               sizeof(in), out, sizeof(out));
 108         if (!dcs->obj) {
 109                 DRV_LOG(ERR, "Can't allocate counters - error %d", errno);
 110                 rte_errno = errno;
 111                 mlx5_free(dcs);
 112                 return NULL;
 113         }
 114         dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id);
 115         return dcs;
 116 }
 117
 118 /**
 119  * Query flow counters values.
 120  *
 121  * @param[in] dcs
 122  *   devx object that was obtained from mlx5_devx_cmd_fc_alloc.
 123  * @param[in] clear
 124  *   Whether hardware should clear the counters after the query or not.
 125  * @param[in] n_counters
 126  *   0 in case of 1 counter to read, otherwise the counter number to read.
 127  *  @param pkts
 128  *   The number of packets that matched the flow.
 129  *  @param bytes
 130  *    The number of bytes that matched the flow.
 131  *  @param mkey
 132  *   The mkey key for batch query.
 133  *  @param addr
 134  *    The address in the mkey range for batch query.
 135  *  @param cmd_comp
 136  *   The completion object for asynchronous batch query.
 137  *  @param async_id
 138  *    The ID to be returned in the asynchronous batch query response.
 139  *
 140  * @return
 141  *   0 on success, a negative value otherwise.
 142  */
 143 int
 144 mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs,
 145                                  int clear, uint32_t n_counters,
 146                                  uint64_t *pkts, uint64_t *bytes,
 147                                  uint32_t mkey, void *addr,
 148                                  void *cmd_comp,
 149                                  uint64_t async_id)
 150 {
 151         int out_len = MLX5_ST_SZ_BYTES(query_flow_counter_out) +
 152                         MLX5_ST_SZ_BYTES(traffic_counter);
 153         uint32_t out[out_len];
 154         uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0};
 155         void *stats;
 156         int rc;
 157
 158         MLX5_SET(query_flow_counter_in, in, opcode,
 159                  MLX5_CMD_OP_QUERY_FLOW_COUNTER);
 160         MLX5_SET(query_flow_counter_in, in, op_mod, 0);
 161         MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id);
 162         MLX5_SET(query_flow_counter_in, in, clear, !!clear);
 163
 164         if (n_counters) {
 165                 MLX5_SET(query_flow_counter_in, in, num_of_counters,
 166                          n_counters);
 167                 MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1);
 168                 MLX5_SET(query_flow_counter_in, in, mkey, mkey);
 169                 MLX5_SET64(query_flow_counter_in, in, address,
 170                            (uint64_t)(uintptr_t)addr);
 171         }
 172         if (!cmd_comp)
 173                 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out,
 174                                                out_len);
 175         else
 176                 rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in),
 177                                                      out_len, async_id,
 178                                                      cmd_comp);
 179         if (rc) {
 180                 DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc);
 181                 rte_errno = rc;
 182                 return -rc;
 183         }
 184         if (!n_counters) {
 185                 stats = MLX5_ADDR_OF(query_flow_counter_out,
 186                                      out, flow_statistics);
 187                 *pkts = MLX5_GET64(traffic_counter, stats, packets);
 188                 *bytes = MLX5_GET64(traffic_counter, stats, octets);
 189         }
 190         return 0;
 191 }
 192
 193 /**
 194  * Create a new mkey.
 195  *
 196  * @param[in] ctx
 197  *   Context returned from mlx5 open_device() glue function.
 198  * @param[in] attr
 199  *   Attributes of the requested mkey.
 200  *
 201  * @return
 202  *   Pointer to Devx mkey on success, a negative value otherwise and rte_errno
 203  *   is set.
 204  */
 205 struct mlx5_devx_obj *
 206 mlx5_devx_cmd_mkey_create(void *ctx,
 207                           struct mlx5_devx_mkey_attr *attr)
 208 {
 209         struct mlx5_klm *klm_array = attr->klm_array;
 210         int klm_num = attr->klm_num;
 211         int in_size_dw = MLX5_ST_SZ_DW(create_mkey_in) +
 212                      (klm_num ? RTE_ALIGN(klm_num, 4) : 0) * MLX5_ST_SZ_DW(klm);
 213         uint32_t in[in_size_dw];
 214         uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0};
 215         void *mkc;
 216         struct mlx5_devx_obj *mkey = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mkey),
 217                                                  0, SOCKET_ID_ANY);
 218         size_t pgsize;
 219         uint32_t translation_size;
 220
 221         if (!mkey) {
 222                 rte_errno = ENOMEM;
 223                 return NULL;
 224         }
 225         memset(in, 0, in_size_dw * 4);
 226         pgsize = rte_mem_page_size();
 227         if (pgsize == (size_t)-1) {
 228                 mlx5_free(mkey);
 229                 DRV_LOG(ERR, "Failed to get page size");
 230                 rte_errno = ENOMEM;
 231                 return NULL;
 232         }
 233         MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY);
 234         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 235         if (klm_num > 0) {
 236                 int i;
 237                 uint8_t *klm = (uint8_t *)MLX5_ADDR_OF(create_mkey_in, in,
 238                                                        klm_pas_mtt);
 239                 translation_size = RTE_ALIGN(klm_num, 4);
 240                 for (i = 0; i < klm_num; i++) {
 241                         MLX5_SET(klm, klm, byte_count, klm_array[i].byte_count);
 242                         MLX5_SET(klm, klm, mkey, klm_array[i].mkey);
 243                         MLX5_SET64(klm, klm, address, klm_array[i].address);
 244                         klm += MLX5_ST_SZ_BYTES(klm);
 245                 }
 246                 for (; i < (int)translation_size; i++) {
 247                         MLX5_SET(klm, klm, mkey, 0x0);
 248                         MLX5_SET64(klm, klm, address, 0x0);
 249                         klm += MLX5_ST_SZ_BYTES(klm);
 250                 }
 251                 MLX5_SET(mkc, mkc, access_mode_1_0, attr->log_entity_size ?
 252                          MLX5_MKC_ACCESS_MODE_KLM_FBS :
 253                          MLX5_MKC_ACCESS_MODE_KLM);
 254                 MLX5_SET(mkc, mkc, log_page_size, attr->log_entity_size);
 255         } else {
 256                 translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16;
 257                 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
 258                 MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize));
 259         }
 260         MLX5_SET(create_mkey_in, in, translations_octword_actual_size,
 261                  translation_size);
 262         MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id);
 263         MLX5_SET(create_mkey_in, in, pg_access, attr->pg_access);
 264         MLX5_SET(mkc, mkc, lw, 0x1);
 265         MLX5_SET(mkc, mkc, lr, 0x1);
 266         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 267         MLX5_SET(mkc, mkc, pd, attr->pd);
 268         MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF);
 269         MLX5_SET(mkc, mkc, translations_octword_size, translation_size);
 270         MLX5_SET(mkc, mkc, relaxed_ordering_write,
 271                 attr->relaxed_ordering_write);
 272         MLX5_SET(mkc, mkc, relaxed_ordering_read,
 273                 attr->relaxed_ordering_read);
 274         MLX5_SET64(mkc, mkc, start_addr, attr->addr);
 275         MLX5_SET64(mkc, mkc, len, attr->size);
 276         mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out,
 277                                                sizeof(out));
 278         if (!mkey->obj) {
 279                 DRV_LOG(ERR, "Can't create %sdirect mkey - error %d\n",
 280                         klm_num ? "an in" : "a ", errno);
 281                 rte_errno = errno;
 282                 mlx5_free(mkey);
 283                 return NULL;
 284         }
 285         mkey->id = MLX5_GET(create_mkey_out, out, mkey_index);
 286         mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF);
 287         return mkey;
 288 }
 289
 290 /**
 291  * Get status of devx command response.
 292  * Mainly used for asynchronous commands.
 293  *
 294  * @param[in] out
 295  *   The out response buffer.
 296  *
 297  * @return
 298  *   0 on success, non-zero value otherwise.
 299  */
 300 int
 301 mlx5_devx_get_out_command_status(void *out)
 302 {
 303         int status;
 304
 305         if (!out)
 306                 return -EINVAL;
 307         status = MLX5_GET(query_flow_counter_out, out, status);
 308         if (status) {
 309                 int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome);
 310
 311                 DRV_LOG(ERR, "Bad devX status %x, syndrome = %x", status,
 312                         syndrome);
 313         }
 314         return status;
 315 }
 316
 317 /**
 318  * Destroy any object allocated by a Devx API.
 319  *
 320  * @param[in] obj
 321  *   Pointer to a general object.
 322  *
 323  * @return
 324  *   0 on success, a negative value otherwise.
 325  */
 326 int
 327 mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj)
 328 {
 329         int ret;
 330
 331         if (!obj)
 332                 return 0;
 333         ret =  mlx5_glue->devx_obj_destroy(obj->obj);
 334         mlx5_free(obj);
 335         return ret;
 336 }
 337
 338 /**
 339  * Query NIC vport context.
 340  * Fills minimal inline attribute.
 341  *
 342  * @param[in] ctx
 343  *   ibv contexts returned from mlx5dv_open_device.
 344  * @param[in] vport
 345  *   vport index
 346  * @param[out] attr
 347  *   Attributes device values.
 348  *
 349  * @return
 350  *   0 on success, a negative value otherwise.
 351  */
 352 static int
 353 mlx5_devx_cmd_query_nic_vport_context(void *ctx,
 354                                       unsigned int vport,
 355                                       struct mlx5_hca_attr *attr)
 356 {
 357         uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0};
 358         uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0};
 359         void *vctx;
 360         int status, syndrome, rc;
 361
 362         /* Query NIC vport context to determine inline mode. */
 363         MLX5_SET(query_nic_vport_context_in, in, opcode,
 364                  MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT);
 365         MLX5_SET(query_nic_vport_context_in, in, vport_number, vport);
 366         if (vport)
 367                 MLX5_SET(query_nic_vport_context_in, in, other_vport, 1);
 368         rc = mlx5_glue->devx_general_cmd(ctx,
 369                                          in, sizeof(in),
 370                                          out, sizeof(out));
 371         if (rc)
 372                 goto error;
 373         status = MLX5_GET(query_nic_vport_context_out, out, status);
 374         syndrome = MLX5_GET(query_nic_vport_context_out, out, syndrome);
 375         if (status) {
 376                 DRV_LOG(DEBUG, "Failed to query NIC vport context, "
 377                         "status %x, syndrome = %x",
 378                         status, syndrome);
 379                 return -1;
 380         }
 381         vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out,
 382                             nic_vport_context);
 383         attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx,
 384                                            min_wqe_inline_mode);
 385         return 0;
 386 error:
 387         rc = (rc > 0) ? -rc : rc;
 388         return rc;
 389 }
 390
 391 /**
 392  * Query NIC vDPA attributes.
 393  *
 394  * @param[in] ctx
 395  *   Context returned from mlx5 open_device() glue function.
 396  * @param[out] vdpa_attr
 397  *   vDPA Attributes structure to fill.
 398  */
 399 static void
 400 mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx,
 401                                   struct mlx5_hca_vdpa_attr *vdpa_attr)
 402 {
 403         uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0};
 404         uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0};
 405         void *hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 406         int status, syndrome, rc;
 407
 408         MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
 409         MLX5_SET(query_hca_cap_in, in, op_mod,
 410                  MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION |
 411                  MLX5_HCA_CAP_OPMOD_GET_CUR);
 412         rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
 413         status = MLX5_GET(query_hca_cap_out, out, status);
 414         syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
 415         if (rc || status) {
 416                 RTE_LOG(DEBUG, PMD, "Failed to query devx VDPA capabilities,"
 417                         " status %x, syndrome = %x", status, syndrome);
 418                 vdpa_attr->valid = 0;
 419         } else {
 420                 vdpa_attr->valid = 1;
 421                 vdpa_attr->desc_tunnel_offload_type =
 422                         MLX5_GET(virtio_emulation_cap, hcattr,
 423                                  desc_tunnel_offload_type);
 424                 vdpa_attr->eth_frame_offload_type =
 425                         MLX5_GET(virtio_emulation_cap, hcattr,
 426                                  eth_frame_offload_type);
 427                 vdpa_attr->virtio_version_1_0 =
 428                         MLX5_GET(virtio_emulation_cap, hcattr,
 429                                  virtio_version_1_0);
 430                 vdpa_attr->tso_ipv4 = MLX5_GET(virtio_emulation_cap, hcattr,
 431                                                tso_ipv4);
 432                 vdpa_attr->tso_ipv6 = MLX5_GET(virtio_emulation_cap, hcattr,
 433                                                tso_ipv6);
 434                 vdpa_attr->tx_csum = MLX5_GET(virtio_emulation_cap, hcattr,
 435                                               tx_csum);
 436                 vdpa_attr->rx_csum = MLX5_GET(virtio_emulation_cap, hcattr,
 437                                               rx_csum);
 438                 vdpa_attr->event_mode = MLX5_GET(virtio_emulation_cap, hcattr,
 439                                                  event_mode);
 440                 vdpa_attr->virtio_queue_type =
 441                         MLX5_GET(virtio_emulation_cap, hcattr,
 442                                  virtio_queue_type);
 443                 vdpa_attr->log_doorbell_stride =
 444                         MLX5_GET(virtio_emulation_cap, hcattr,
 445                                  log_doorbell_stride);
 446                 vdpa_attr->log_doorbell_bar_size =
 447                         MLX5_GET(virtio_emulation_cap, hcattr,
 448                                  log_doorbell_bar_size);
 449                 vdpa_attr->doorbell_bar_offset =
 450                         MLX5_GET64(virtio_emulation_cap, hcattr,
 451                                    doorbell_bar_offset);
 452                 vdpa_attr->max_num_virtio_queues =
 453                         MLX5_GET(virtio_emulation_cap, hcattr,
 454                                  max_num_virtio_queues);
 455                 vdpa_attr->umems[0].a = MLX5_GET(virtio_emulation_cap, hcattr,
 456                                                  umem_1_buffer_param_a);
 457                 vdpa_attr->umems[0].b = MLX5_GET(virtio_emulation_cap, hcattr,
 458                                                  umem_1_buffer_param_b);
 459                 vdpa_attr->umems[1].a = MLX5_GET(virtio_emulation_cap, hcattr,
 460                                                  umem_2_buffer_param_a);
 461                 vdpa_attr->umems[1].b = MLX5_GET(virtio_emulation_cap, hcattr,
 462                                                  umem_2_buffer_param_b);
 463                 vdpa_attr->umems[2].a = MLX5_GET(virtio_emulation_cap, hcattr,
 464                                                  umem_3_buffer_param_a);
 465                 vdpa_attr->umems[2].b = MLX5_GET(virtio_emulation_cap, hcattr,
 466                                                  umem_3_buffer_param_b);
 467         }
 468 }
 469
 470 int
 471 mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj,
 472                                   uint32_t ids[], uint32_t num)
 473 {
 474         uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
 475         uint32_t out[MLX5_ST_SZ_DW(create_flex_parser_out)] = {0};
 476         void *hdr = MLX5_ADDR_OF(create_flex_parser_out, in, hdr);
 477         void *flex = MLX5_ADDR_OF(create_flex_parser_out, out, flex);
 478         void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table);
 479         int ret;
 480         uint32_t idx = 0;
 481         uint32_t i;
 482
 483         if (num > MLX5_GRAPH_NODE_SAMPLE_NUM) {
 484                 rte_errno = EINVAL;
 485                 DRV_LOG(ERR, "Too many sample IDs to be fetched.");
 486                 return -rte_errno;
 487         }
 488         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
 489                  MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
 490         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
 491                  MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH);
 492         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, flex_obj->id);
 493         ret = mlx5_glue->devx_obj_query(flex_obj->obj, in, sizeof(in),
 494                                         out, sizeof(out));
 495         if (ret) {
 496                 rte_errno = ret;
 497                 DRV_LOG(ERR, "Failed to query sample IDs with object %p.",
 498                         (void *)flex_obj);
 499                 return -rte_errno;
 500         }
 501         for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) {
 502                 void *s_off = (void *)((char *)sample + i *
 503                               MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample));
 504                 uint32_t en;
 505
 506                 en = MLX5_GET(parse_graph_flow_match_sample, s_off,
 507                               flow_match_sample_en);
 508                 if (!en)
 509                         continue;
 510                 ids[idx++] = MLX5_GET(parse_graph_flow_match_sample, s_off,
 511                                   flow_match_sample_field_id);
 512         }
 513         if (num != idx) {
 514                 rte_errno = EINVAL;
 515                 DRV_LOG(ERR, "Number of sample IDs are not as expected.");
 516                 return -rte_errno;
 517         }
 518         return ret;
 519 }
 520
 521
 522 struct mlx5_devx_obj *
 523 mlx5_devx_cmd_create_flex_parser(void *ctx,
 524                               struct mlx5_devx_graph_node_attr *data)
 525 {
 526         uint32_t in[MLX5_ST_SZ_DW(create_flex_parser_in)] = {0};
 527         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
 528         void *hdr = MLX5_ADDR_OF(create_flex_parser_in, in, hdr);
 529         void *flex = MLX5_ADDR_OF(create_flex_parser_in, in, flex);
 530         void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table);
 531         void *in_arc = MLX5_ADDR_OF(parse_graph_flex, flex, input_arc);
 532         void *out_arc = MLX5_ADDR_OF(parse_graph_flex, flex, output_arc);
 533         struct mlx5_devx_obj *parse_flex_obj = mlx5_malloc
 534                      (MLX5_MEM_ZERO, sizeof(*parse_flex_obj), 0, SOCKET_ID_ANY);
 535         uint32_t i;
 536
 537         if (!parse_flex_obj) {
 538                 DRV_LOG(ERR, "Failed to allocate flex parser data.");
 539                 rte_errno = ENOMEM;
 540                 return NULL;
 541         }
 542         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
 543                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
 544         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
 545                  MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH);
 546         MLX5_SET(parse_graph_flex, flex, header_length_mode,
 547                  data->header_length_mode);
 548         MLX5_SET(parse_graph_flex, flex, header_length_base_value,
 549                  data->header_length_base_value);
 550         MLX5_SET(parse_graph_flex, flex, header_length_field_offset,
 551                  data->header_length_field_offset);
 552         MLX5_SET(parse_graph_flex, flex, header_length_field_shift,
 553                  data->header_length_field_shift);
 554         MLX5_SET(parse_graph_flex, flex, header_length_field_mask,
 555                  data->header_length_field_mask);
 556         for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) {
 557                 struct mlx5_devx_match_sample_attr *s = &data->sample[i];
 558                 void *s_off = (void *)((char *)sample + i *
 559                               MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample));
 560
 561                 if (!s->flow_match_sample_en)
 562                         continue;
 563                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 564                          flow_match_sample_en, !!s->flow_match_sample_en);
 565                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 566                          flow_match_sample_field_offset,
 567                          s->flow_match_sample_field_offset);
 568                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 569                          flow_match_sample_offset_mode,
 570                          s->flow_match_sample_offset_mode);
 571                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 572                          flow_match_sample_field_offset_mask,
 573                          s->flow_match_sample_field_offset_mask);
 574                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 575                          flow_match_sample_field_offset_shift,
 576                          s->flow_match_sample_field_offset_shift);
 577                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 578                          flow_match_sample_field_base_offset,
 579                          s->flow_match_sample_field_base_offset);
 580                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 581                          flow_match_sample_tunnel_mode,
 582                          s->flow_match_sample_tunnel_mode);
 583         }
 584         for (i = 0; i < MLX5_GRAPH_NODE_ARC_NUM; i++) {
 585                 struct mlx5_devx_graph_arc_attr *ia = &data->in[i];
 586                 struct mlx5_devx_graph_arc_attr *oa = &data->out[i];
 587                 void *in_off = (void *)((char *)in_arc + i *
 588                               MLX5_ST_SZ_BYTES(parse_graph_arc));
 589                 void *out_off = (void *)((char *)out_arc + i *
 590                               MLX5_ST_SZ_BYTES(parse_graph_arc));
 591
 592                 if (ia->arc_parse_graph_node != 0) {
 593                         MLX5_SET(parse_graph_arc, in_off,
 594                                  compare_condition_value,
 595                                  ia->compare_condition_value);
 596                         MLX5_SET(parse_graph_arc, in_off, start_inner_tunnel,
 597                                  ia->start_inner_tunnel);
 598                         MLX5_SET(parse_graph_arc, in_off, arc_parse_graph_node,
 599                                  ia->arc_parse_graph_node);
 600                         MLX5_SET(parse_graph_arc, in_off,
 601                                  parse_graph_node_handle,
 602                                  ia->parse_graph_node_handle);
 603                 }
 604                 if (oa->arc_parse_graph_node != 0) {
 605                         MLX5_SET(parse_graph_arc, out_off,
 606                                  compare_condition_value,
 607                                  oa->compare_condition_value);
 608                         MLX5_SET(parse_graph_arc, out_off, start_inner_tunnel,
 609                                  oa->start_inner_tunnel);
 610                         MLX5_SET(parse_graph_arc, out_off, arc_parse_graph_node,
 611                                  oa->arc_parse_graph_node);
 612                         MLX5_SET(parse_graph_arc, out_off,
 613                                  parse_graph_node_handle,
 614                                  oa->parse_graph_node_handle);
 615                 }
 616         }
 617         parse_flex_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
 618                                                          out, sizeof(out));
 619         if (!parse_flex_obj->obj) {
 620                 rte_errno = errno;
 621                 DRV_LOG(ERR, "Failed to create FLEX PARSE GRAPH object "
 622                         "by using DevX.");
 623                 mlx5_free(parse_flex_obj);
 624                 return NULL;
 625         }
 626         parse_flex_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
 627         return parse_flex_obj;
 628 }
 629
 630 /**
 631  * Query HCA attributes.
 632  * Using those attributes we can check on run time if the device
 633  * is having the required capabilities.
 634  *
 635  * @param[in] ctx
 636  *   Context returned from mlx5 open_device() glue function.
 637  * @param[out] attr
 638  *   Attributes device values.
 639  *
 640  * @return
 641  *   0 on success, a negative value otherwise.
 642  */
 643 int
 644 mlx5_devx_cmd_query_hca_attr(void *ctx,
 645                              struct mlx5_hca_attr *attr)
 646 {
 647         uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0};
 648         uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0};
 649         void *hcattr;
 650         int status, syndrome, rc, i;
 651
 652         MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
 653         MLX5_SET(query_hca_cap_in, in, op_mod,
 654                  MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE |
 655                  MLX5_HCA_CAP_OPMOD_GET_CUR);
 656
 657         rc = mlx5_glue->devx_general_cmd(ctx,
 658                                          in, sizeof(in), out, sizeof(out));
 659         if (rc)
 660                 goto error;
 661         status = MLX5_GET(query_hca_cap_out, out, status);
 662         syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
 663         if (status) {
 664                 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, "
 665                         "status %x, syndrome = %x",
 666                         status, syndrome);
 667                 return -1;
 668         }
 669         hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 670         attr->flow_counter_bulk_alloc_bitmap =
 671                         MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc);
 672         attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr,
 673                                             flow_counters_dump);
 674         attr->log_max_rqt_size = MLX5_GET(cmd_hca_cap, hcattr,
 675                                           log_max_rqt_size);
 676         attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager);
 677         attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin);
 678         attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr,
 679                                                 log_max_hairpin_queues);
 680         attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr,
 681                                                     log_max_hairpin_wq_data_sz);
 682         attr->log_max_hairpin_num_packets = MLX5_GET
 683                 (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz);
 684         attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id);
 685         attr->relaxed_ordering_write = MLX5_GET(cmd_hca_cap, hcattr,
 686                         relaxed_ordering_write);
 687         attr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr,
 688                         relaxed_ordering_read);
 689         attr->access_register_user = MLX5_GET(cmd_hca_cap, hcattr,
 690                         access_register_user);
 691         attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr,
 692                                           eth_net_offloads);
 693         attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt);
 694         attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr,
 695                                                flex_parser_protocols);
 696         attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos);
 697         attr->vdpa.valid = !!(MLX5_GET64(cmd_hca_cap, hcattr,
 698                                          general_obj_types) &
 699                               MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q);
 700         attr->vdpa.queue_counters_valid = !!(MLX5_GET64(cmd_hca_cap, hcattr,
 701                                                         general_obj_types) &
 702                                   MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS);
 703         attr->parse_graph_flex_node = !!(MLX5_GET64(cmd_hca_cap, hcattr,
 704                                          general_obj_types) &
 705                               MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE);
 706         attr->wqe_index_ignore = MLX5_GET(cmd_hca_cap, hcattr,
 707                                           wqe_index_ignore_cap);
 708         attr->cross_channel = MLX5_GET(cmd_hca_cap, hcattr, cd);
 709         attr->non_wire_sq = MLX5_GET(cmd_hca_cap, hcattr, non_wire_sq);
 710         attr->log_max_static_sq_wq = MLX5_GET(cmd_hca_cap, hcattr,
 711                                               log_max_static_sq_wq);
 712         attr->num_lag_ports = MLX5_GET(cmd_hca_cap, hcattr, num_lag_ports);
 713         attr->dev_freq_khz = MLX5_GET(cmd_hca_cap, hcattr,
 714                                       device_frequency_khz);
 715         attr->scatter_fcs_w_decap_disable =
 716                 MLX5_GET(cmd_hca_cap, hcattr, scatter_fcs_w_decap_disable);
 717         attr->regex = MLX5_GET(cmd_hca_cap, hcattr, regexp);
 718         attr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr,
 719                                                regexp_num_of_engines);
 720         attr->flow_hit_aso = !!(MLX5_GET64(cmd_hca_cap, hcattr,
 721                                            general_obj_types) &
 722                                 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO);
 723         if (attr->qos.sup) {
 724                 MLX5_SET(query_hca_cap_in, in, op_mod,
 725                          MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP |
 726                          MLX5_HCA_CAP_OPMOD_GET_CUR);
 727                 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in),
 728                                                  out, sizeof(out));
 729                 if (rc)
 730                         goto error;
 731                 if (status) {
 732                         DRV_LOG(DEBUG, "Failed to query devx QOS capabilities,"
 733                                 " status %x, syndrome = %x",
 734                                 status, syndrome);
 735                         return -1;
 736                 }
 737                 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 738                 attr->qos.srtcm_sup =
 739                                 MLX5_GET(qos_cap, hcattr, flow_meter_srtcm);
 740                 attr->qos.log_max_flow_meter =
 741                                 MLX5_GET(qos_cap, hcattr, log_max_flow_meter);
 742                 attr->qos.flow_meter_reg_c_ids =
 743                                 MLX5_GET(qos_cap, hcattr, flow_meter_reg_id);
 744                 attr->qos.flow_meter_reg_share =
 745                                 MLX5_GET(qos_cap, hcattr, flow_meter_reg_share);
 746                 attr->qos.packet_pacing =
 747                                 MLX5_GET(qos_cap, hcattr, packet_pacing);
 748                 attr->qos.wqe_rate_pp =
 749                                 MLX5_GET(qos_cap, hcattr, wqe_rate_pp);
 750         }
 751         if (attr->vdpa.valid)
 752                 mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa);
 753         if (!attr->eth_net_offloads)
 754                 return 0;
 755
 756         /* Query Flow Sampler Capability From FLow Table Properties Layout. */
 757         memset(in, 0, sizeof(in));
 758         memset(out, 0, sizeof(out));
 759         MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
 760         MLX5_SET(query_hca_cap_in, in, op_mod,
 761                  MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE |
 762                  MLX5_HCA_CAP_OPMOD_GET_CUR);
 763
 764         rc = mlx5_glue->devx_general_cmd(ctx,
 765                                          in, sizeof(in),
 766                                          out, sizeof(out));
 767         if (rc)
 768                 goto error;
 769         status = MLX5_GET(query_hca_cap_out, out, status);
 770         syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
 771         if (status) {
 772                 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, "
 773                         "status %x, syndrome = %x",
 774                         status, syndrome);
 775                 attr->log_max_ft_sampler_num = 0;
 776                 return -1;
 777         }
 778         hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 779         attr->log_max_ft_sampler_num =
 780                         MLX5_GET(flow_table_nic_cap,
 781                         hcattr, flow_table_properties.log_max_ft_sampler_num);
 782
 783         /* Query HCA offloads for Ethernet protocol. */
 784         memset(in, 0, sizeof(in));
 785         memset(out, 0, sizeof(out));
 786         MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
 787         MLX5_SET(query_hca_cap_in, in, op_mod,
 788                  MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS |
 789                  MLX5_HCA_CAP_OPMOD_GET_CUR);
 790
 791         rc = mlx5_glue->devx_general_cmd(ctx,
 792                                          in, sizeof(in),
 793                                          out, sizeof(out));
 794         if (rc) {
 795                 attr->eth_net_offloads = 0;
 796                 goto error;
 797         }
 798         status = MLX5_GET(query_hca_cap_out, out, status);
 799         syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
 800         if (status) {
 801                 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, "
 802                         "status %x, syndrome = %x",
 803                         status, syndrome);
 804                 attr->eth_net_offloads = 0;
 805                 return -1;
 806         }
 807         hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 808         attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps,
 809                                          hcattr, wqe_vlan_insert);
 810         attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr,
 811                                  lro_cap);
 812         attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps,
 813                                         hcattr, tunnel_lro_gre);
 814         attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps,
 815                                           hcattr, tunnel_lro_vxlan);
 816         attr->lro_max_msg_sz_mode = MLX5_GET
 817                                         (per_protocol_networking_offload_caps,
 818                                          hcattr, lro_max_msg_sz_mode);
 819         for (i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) {
 820                 attr->lro_timer_supported_periods[i] =
 821                         MLX5_GET(per_protocol_networking_offload_caps, hcattr,
 822                                  lro_timer_supported_periods[i]);
 823         }
 824         attr->lro_min_mss_size = MLX5_GET(per_protocol_networking_offload_caps,
 825                                           hcattr, lro_min_mss_size);
 826         attr->tunnel_stateless_geneve_rx =
 827                             MLX5_GET(per_protocol_networking_offload_caps,
 828                                      hcattr, tunnel_stateless_geneve_rx);
 829         attr->geneve_max_opt_len =
 830                     MLX5_GET(per_protocol_networking_offload_caps,
 831                              hcattr, max_geneve_opt_len);
 832         attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps,
 833                                          hcattr, wqe_inline_mode);
 834         attr->tunnel_stateless_gtp = MLX5_GET
 835                                         (per_protocol_networking_offload_caps,
 836                                          hcattr, tunnel_stateless_gtp);
 837         if (attr->wqe_inline_mode != MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
 838                 return 0;
 839         if (attr->eth_virt) {
 840                 rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr);
 841                 if (rc) {
 842                         attr->eth_virt = 0;
 843                         goto error;
 844                 }
 845         }
 846         return 0;
 847 error:
 848         rc = (rc > 0) ? -rc : rc;
 849         return rc;
 850 }
 851
 852 /**
 853  * Query TIS transport domain from QP verbs object using DevX API.
 854  *
 855  * @param[in] qp
 856  *   Pointer to verbs QP returned by ibv_create_qp .
 857  * @param[in] tis_num
 858  *   TIS number of TIS to query.
 859  * @param[out] tis_td
 860  *   Pointer to TIS transport domain variable, to be set by the routine.
 861  *
 862  * @return
 863  *   0 on success, a negative value otherwise.
 864  */
 865 int
 866 mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num,
 867                               uint32_t *tis_td)
 868 {
 869 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 870         uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0};
 871         uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0};
 872         int rc;
 873         void *tis_ctx;
 874
 875         MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS);
 876         MLX5_SET(query_tis_in, in, tisn, tis_num);
 877         rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out));
 878         if (rc) {
 879                 DRV_LOG(ERR, "Failed to query QP using DevX");
 880                 return -rc;
 881         };
 882         tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context);
 883         *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain);
 884         return 0;
 885 #else
 886         (void)qp;
 887         (void)tis_num;
 888         (void)tis_td;
 889         return -ENOTSUP;
 890 #endif
 891 }
 892
 893 /**
 894  * Fill WQ data for DevX API command.
 895  * Utility function for use when creating DevX objects containing a WQ.
 896  *
 897  * @param[in] wq_ctx
 898  *   Pointer to WQ context to fill with data.
 899  * @param [in] wq_attr
 900  *   Pointer to WQ attributes structure to fill in WQ context.
 901  */
 902 static void
 903 devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr)
 904 {
 905         MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type);
 906         MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature);
 907         MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode);
 908         MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave);
 909         MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge);
 910         MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size);
 911         MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset);
 912         MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm);
 913         MLX5_SET(wq, wq_ctx, pd, wq_attr->pd);
 914         MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page);
 915         MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr);
 916         MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter);
 917         MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter);
 918         MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride);
 919         MLX5_SET(wq, wq_ctx, log_wq_pg_sz, wq_attr->log_wq_pg_sz);
 920         MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz);
 921         MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid);
 922         MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid);
 923         MLX5_SET(wq, wq_ctx, log_hairpin_num_packets,
 924                  wq_attr->log_hairpin_num_packets);
 925         MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz);
 926         MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides,
 927                  wq_attr->single_wqe_log_num_of_strides);
 928         MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en);
 929         MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes,
 930                  wq_attr->single_stride_log_num_of_bytes);
 931         MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id);
 932         MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id);
 933         MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset);
 934 }
 935
 936 /**
 937  * Create RQ using DevX API.
 938  *
 939  * @param[in] ctx
 940  *   Context returned from mlx5 open_device() glue function.
 941  * @param [in] rq_attr
 942  *   Pointer to create RQ attributes structure.
 943  * @param [in] socket
 944  *   CPU socket ID for allocations.
 945  *
 946  * @return
 947  *   The DevX object created, NULL otherwise and rte_errno is set.
 948  */
 949 struct mlx5_devx_obj *
 950 mlx5_devx_cmd_create_rq(void *ctx,
 951                         struct mlx5_devx_create_rq_attr *rq_attr,
 952                         int socket)
 953 {
 954         uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0};
 955         uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0};
 956         void *rq_ctx, *wq_ctx;
 957         struct mlx5_devx_wq_attr *wq_attr;
 958         struct mlx5_devx_obj *rq = NULL;
 959
 960         rq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rq), 0, socket);
 961         if (!rq) {
 962                 DRV_LOG(ERR, "Failed to allocate RQ data");
 963                 rte_errno = ENOMEM;
 964                 return NULL;
 965         }
 966         MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ);
 967         rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx);
 968         MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky);
 969         MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en);
 970         MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);
 971         MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);
 972         MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type);
 973         MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
 974         MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en);
 975         MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin);
 976         MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index);
 977         MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn);
 978         MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
 979         MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn);
 980         wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);
 981         wq_attr = &rq_attr->wq_attr;
 982         devx_cmd_fill_wq_data(wq_ctx, wq_attr);
 983         rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
 984                                                   out, sizeof(out));
 985         if (!rq->obj) {
 986                 DRV_LOG(ERR, "Failed to create RQ using DevX");
 987                 rte_errno = errno;
 988                 mlx5_free(rq);
 989                 return NULL;
 990         }
 991         rq->id = MLX5_GET(create_rq_out, out, rqn);
 992         return rq;
 993 }
 994
 995 /**
 996  * Modify RQ using DevX API.
 997  *
 998  * @param[in] rq
 999  *   Pointer to RQ object structure.
1000  * @param [in] rq_attr
1001  *   Pointer to modify RQ attributes structure.
1002  *
1003  * @return
1004  *   0 on success, a negative errno value otherwise and rte_errno is set.
1005  */
1006 int
1007 mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,
1008                         struct mlx5_devx_modify_rq_attr *rq_attr)
1009 {
1010         uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0};
1011         uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0};
1012         void *rq_ctx, *wq_ctx;
1013         int ret;
1014
1015         MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ);
1016         MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state);
1017         MLX5_SET(modify_rq_in, in, rqn, rq->id);
1018         MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask);
1019         rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1020         MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
1021         if (rq_attr->modify_bitmask &
1022                         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS)
1023                 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);
1024         if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD)
1025                 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);
1026         if (rq_attr->modify_bitmask &
1027                         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID)
1028                 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
1029         MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq);
1030         MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca);
1031         if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) {
1032                 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);
1033                 MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm);
1034         }
1035         ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in),
1036                                          out, sizeof(out));
1037         if (ret) {
1038                 DRV_LOG(ERR, "Failed to modify RQ using DevX");
1039                 rte_errno = errno;
1040                 return -errno;
1041         }
1042         return ret;
1043 }
1044
1045 /**
1046  * Create TIR using DevX API.
1047  *
1048  * @param[in] ctx
1049  *  Context returned from mlx5 open_device() glue function.
1050  * @param [in] tir_attr
1051  *   Pointer to TIR attributes structure.
1052  *
1053  * @return
1054  *   The DevX object created, NULL otherwise and rte_errno is set.
1055  */
1056 struct mlx5_devx_obj *
1057 mlx5_devx_cmd_create_tir(void *ctx,
1058                          struct mlx5_devx_tir_attr *tir_attr)
1059 {
1060         uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
1061         uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0};
1062         void *tir_ctx, *outer, *inner, *rss_key;
1063         struct mlx5_devx_obj *tir = NULL;
1064
1065         tir = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tir), 0, SOCKET_ID_ANY);
1066         if (!tir) {
1067                 DRV_LOG(ERR, "Failed to allocate TIR data");
1068                 rte_errno = ENOMEM;
1069                 return NULL;
1070         }
1071         MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR);
1072         tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx);
1073         MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type);
1074         MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs,
1075                  tir_attr->lro_timeout_period_usecs);
1076         MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask);
1077         MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz);
1078         MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn);
1079         MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric);
1080         MLX5_SET(tirc, tir_ctx, tunneled_offload_en,
1081                  tir_attr->tunneled_offload_en);
1082         MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table);
1083         MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn);
1084         MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block);
1085         MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain);
1086         rss_key = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_toeplitz_key);
1087         memcpy(rss_key, tir_attr->rx_hash_toeplitz_key, MLX5_RSS_HASH_KEY_LEN);
1088         outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer);
1089         MLX5_SET(rx_hash_field_select, outer, l3_prot_type,
1090                  tir_attr->rx_hash_field_selector_outer.l3_prot_type);
1091         MLX5_SET(rx_hash_field_select, outer, l4_prot_type,
1092                  tir_attr->rx_hash_field_selector_outer.l4_prot_type);
1093         MLX5_SET(rx_hash_field_select, outer, selected_fields,
1094                  tir_attr->rx_hash_field_selector_outer.selected_fields);
1095         inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner);
1096         MLX5_SET(rx_hash_field_select, inner, l3_prot_type,
1097                  tir_attr->rx_hash_field_selector_inner.l3_prot_type);
1098         MLX5_SET(rx_hash_field_select, inner, l4_prot_type,
1099                  tir_attr->rx_hash_field_selector_inner.l4_prot_type);
1100         MLX5_SET(rx_hash_field_select, inner, selected_fields,
1101                  tir_attr->rx_hash_field_selector_inner.selected_fields);
1102         tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1103                                                    out, sizeof(out));
1104         if (!tir->obj) {
1105                 DRV_LOG(ERR, "Failed to create TIR using DevX");
1106                 rte_errno = errno;
1107                 mlx5_free(tir);
1108                 return NULL;
1109         }
1110         tir->id = MLX5_GET(create_tir_out, out, tirn);
1111         return tir;
1112 }
1113
1114 /**
1115  * Modify TIR using DevX API.
1116  *
1117  * @param[in] tir
1118  *   Pointer to TIR DevX object structure.
1119  * @param [in] modify_tir_attr
1120  *   Pointer to TIR modification attributes structure.
1121  *
1122  * @return
1123  *   0 on success, a negative errno value otherwise and rte_errno is set.
1124  */
1125 int
1126 mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir,
1127                          struct mlx5_devx_modify_tir_attr *modify_tir_attr)
1128 {
1129         struct mlx5_devx_tir_attr *tir_attr = &modify_tir_attr->tir;
1130         uint32_t in[MLX5_ST_SZ_DW(modify_tir_in)] = {0};
1131         uint32_t out[MLX5_ST_SZ_DW(modify_tir_out)] = {0};
1132         void *tir_ctx;
1133         int ret;
1134
1135         MLX5_SET(modify_tir_in, in, opcode, MLX5_CMD_OP_MODIFY_TIR);
1136         MLX5_SET(modify_tir_in, in, tirn, modify_tir_attr->tirn);
1137         MLX5_SET64(modify_tir_in, in, modify_bitmask,
1138                    modify_tir_attr->modify_bitmask);
1139         tir_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1140         if (modify_tir_attr->modify_bitmask &
1141                         MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO) {
1142                 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs,
1143                          tir_attr->lro_timeout_period_usecs);
1144                 MLX5_SET(tirc, tir_ctx, lro_enable_mask,
1145                          tir_attr->lro_enable_mask);
1146                 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz,
1147                          tir_attr->lro_max_msg_sz);
1148         }
1149         if (modify_tir_attr->modify_bitmask &
1150                         MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE)
1151                 MLX5_SET(tirc, tir_ctx, indirect_table,
1152                          tir_attr->indirect_table);
1153         if (modify_tir_attr->modify_bitmask &
1154                         MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH) {
1155                 int i;
1156                 void *outer, *inner;
1157
1158                 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric,
1159                          tir_attr->rx_hash_symmetric);
1160                 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn);
1161                 for (i = 0; i < 10; i++) {
1162                         MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i],
1163                                  tir_attr->rx_hash_toeplitz_key[i]);
1164                 }
1165                 outer = MLX5_ADDR_OF(tirc, tir_ctx,
1166                                      rx_hash_field_selector_outer);
1167                 MLX5_SET(rx_hash_field_select, outer, l3_prot_type,
1168                          tir_attr->rx_hash_field_selector_outer.l3_prot_type);
1169                 MLX5_SET(rx_hash_field_select, outer, l4_prot_type,
1170                          tir_attr->rx_hash_field_selector_outer.l4_prot_type);
1171                 MLX5_SET
1172                 (rx_hash_field_select, outer, selected_fields,
1173                  tir_attr->rx_hash_field_selector_outer.selected_fields);
1174                 inner = MLX5_ADDR_OF(tirc, tir_ctx,
1175                                      rx_hash_field_selector_inner);
1176                 MLX5_SET(rx_hash_field_select, inner, l3_prot_type,
1177                          tir_attr->rx_hash_field_selector_inner.l3_prot_type);
1178                 MLX5_SET(rx_hash_field_select, inner, l4_prot_type,
1179                          tir_attr->rx_hash_field_selector_inner.l4_prot_type);
1180                 MLX5_SET
1181                 (rx_hash_field_select, inner, selected_fields,
1182                  tir_attr->rx_hash_field_selector_inner.selected_fields);
1183         }
1184         if (modify_tir_attr->modify_bitmask &
1185             MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN) {
1186                 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block);
1187         }
1188         ret = mlx5_glue->devx_obj_modify(tir->obj, in, sizeof(in),
1189                                          out, sizeof(out));
1190         if (ret) {
1191                 DRV_LOG(ERR, "Failed to modify TIR using DevX");
1192                 rte_errno = errno;
1193                 return -errno;
1194         }
1195         return ret;
1196 }
1197
1198 /**
1199  * Create RQT using DevX API.
1200  *
1201  * @param[in] ctx
1202  *   Context returned from mlx5 open_device() glue function.
1203  * @param [in] rqt_attr
1204  *   Pointer to RQT attributes structure.
1205  *
1206  * @return
1207  *   The DevX object created, NULL otherwise and rte_errno is set.
1208  */
1209 struct mlx5_devx_obj *
1210 mlx5_devx_cmd_create_rqt(void *ctx,
1211                          struct mlx5_devx_rqt_attr *rqt_attr)
1212 {
1213         uint32_t *in = NULL;
1214         uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) +
1215                          rqt_attr->rqt_actual_size * sizeof(uint32_t);
1216         uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0};
1217         void *rqt_ctx;
1218         struct mlx5_devx_obj *rqt = NULL;
1219         int i;
1220
1221         in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY);
1222         if (!in) {
1223                 DRV_LOG(ERR, "Failed to allocate RQT IN data");
1224                 rte_errno = ENOMEM;
1225                 return NULL;
1226         }
1227         rqt = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt), 0, SOCKET_ID_ANY);
1228         if (!rqt) {
1229                 DRV_LOG(ERR, "Failed to allocate RQT data");
1230                 rte_errno = ENOMEM;
1231                 mlx5_free(in);
1232                 return NULL;
1233         }
1234         MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
1235         rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1236         MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type);
1237         MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size);
1238         MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size);
1239         for (i = 0; i < rqt_attr->rqt_actual_size; i++)
1240                 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]);
1241         rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out));
1242         mlx5_free(in);
1243         if (!rqt->obj) {
1244                 DRV_LOG(ERR, "Failed to create RQT using DevX");
1245                 rte_errno = errno;
1246                 mlx5_free(rqt);
1247                 return NULL;
1248         }
1249         rqt->id = MLX5_GET(create_rqt_out, out, rqtn);
1250         return rqt;
1251 }
1252
1253 /**
1254  * Modify RQT using DevX API.
1255  *
1256  * @param[in] rqt
1257  *   Pointer to RQT DevX object structure.
1258  * @param [in] rqt_attr
1259  *   Pointer to RQT attributes structure.
1260  *
1261  * @return
1262  *   0 on success, a negative errno value otherwise and rte_errno is set.
1263  */
1264 int
1265 mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt,
1266                          struct mlx5_devx_rqt_attr *rqt_attr)
1267 {
1268         uint32_t inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) +
1269                          rqt_attr->rqt_actual_size * sizeof(uint32_t);
1270         uint32_t out[MLX5_ST_SZ_DW(modify_rqt_out)] = {0};
1271         uint32_t *in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY);
1272         void *rqt_ctx;
1273         int i;
1274         int ret;
1275
1276         if (!in) {
1277                 DRV_LOG(ERR, "Failed to allocate RQT modify IN data.");
1278                 rte_errno = ENOMEM;
1279                 return -ENOMEM;
1280         }
1281         MLX5_SET(modify_rqt_in, in, opcode, MLX5_CMD_OP_MODIFY_RQT);
1282         MLX5_SET(modify_rqt_in, in, rqtn, rqt->id);
1283         MLX5_SET64(modify_rqt_in, in, modify_bitmask, 0x1);
1284         rqt_ctx = MLX5_ADDR_OF(modify_rqt_in, in, rqt_context);
1285         MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type);
1286         MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size);
1287         MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size);
1288         for (i = 0; i < rqt_attr->rqt_actual_size; i++)
1289                 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]);
1290         ret = mlx5_glue->devx_obj_modify(rqt->obj, in, inlen, out, sizeof(out));
1291         mlx5_free(in);
1292         if (ret) {
1293                 DRV_LOG(ERR, "Failed to modify RQT using DevX.");
1294                 rte_errno = errno;
1295                 return -rte_errno;
1296         }
1297         return ret;
1298 }
1299
1300 /**
1301  * Create SQ using DevX API.
1302  *
1303  * @param[in] ctx
1304  *   Context returned from mlx5 open_device() glue function.
1305  * @param [in] sq_attr
1306  *   Pointer to SQ attributes structure.
1307  * @param [in] socket
1308  *   CPU socket ID for allocations.
1309  *
1310  * @return
1311  *   The DevX object created, NULL otherwise and rte_errno is set.
1312  **/
1313 struct mlx5_devx_obj *
1314 mlx5_devx_cmd_create_sq(void *ctx,
1315                         struct mlx5_devx_create_sq_attr *sq_attr)
1316 {
1317         uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0};
1318         uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0};
1319         void *sq_ctx;
1320         void *wq_ctx;
1321         struct mlx5_devx_wq_attr *wq_attr;
1322         struct mlx5_devx_obj *sq = NULL;
1323
1324         sq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sq), 0, SOCKET_ID_ANY);
1325         if (!sq) {
1326                 DRV_LOG(ERR, "Failed to allocate SQ data");
1327                 rte_errno = ENOMEM;
1328                 return NULL;
1329         }
1330         MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ);
1331         sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx);
1332         MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky);
1333         MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master);
1334         MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre);
1335         MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en);
1336         MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe,
1337                  sq_attr->allow_multi_pkt_send_wqe);
1338         MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode,
1339                  sq_attr->min_wqe_inline_mode);
1340         MLX5_SET(sqc, sq_ctx, state, sq_attr->state);
1341         MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr);
1342         MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp);
1343         MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin);
1344         MLX5_SET(sqc, sq_ctx, non_wire, sq_attr->non_wire);
1345         MLX5_SET(sqc, sq_ctx, static_sq_wq, sq_attr->static_sq_wq);
1346         MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index);
1347         MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn);
1348         MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index,
1349                  sq_attr->packet_pacing_rate_limit_index);
1350         MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz);
1351         MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num);
1352         wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq);
1353         wq_attr = &sq_attr->wq_attr;
1354         devx_cmd_fill_wq_data(wq_ctx, wq_attr);
1355         sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1356                                              out, sizeof(out));
1357         if (!sq->obj) {
1358                 DRV_LOG(ERR, "Failed to create SQ using DevX");
1359                 rte_errno = errno;
1360                 mlx5_free(sq);
1361                 return NULL;
1362         }
1363         sq->id = MLX5_GET(create_sq_out, out, sqn);
1364         return sq;
1365 }
1366
1367 /**
1368  * Modify SQ using DevX API.
1369  *
1370  * @param[in] sq
1371  *   Pointer to SQ object structure.
1372  * @param [in] sq_attr
1373  *   Pointer to SQ attributes structure.
1374  *
1375  * @return
1376  *   0 on success, a negative errno value otherwise and rte_errno is set.
1377  */
1378 int
1379 mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq,
1380                         struct mlx5_devx_modify_sq_attr *sq_attr)
1381 {
1382         uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0};
1383         uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0};
1384         void *sq_ctx;
1385         int ret;
1386
1387         MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ);
1388         MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state);
1389         MLX5_SET(modify_sq_in, in, sqn, sq->id);
1390         sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1391         MLX5_SET(sqc, sq_ctx, state, sq_attr->state);
1392         MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq);
1393         MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca);
1394         ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in),
1395                                          out, sizeof(out));
1396         if (ret) {
1397                 DRV_LOG(ERR, "Failed to modify SQ using DevX");
1398                 rte_errno = errno;
1399                 return -rte_errno;
1400         }
1401         return ret;
1402 }
1403
1404 /**
1405  * Create TIS using DevX API.
1406  *
1407  * @param[in] ctx
1408  *   Context returned from mlx5 open_device() glue function.
1409  * @param [in] tis_attr
1410  *   Pointer to TIS attributes structure.
1411  *
1412  * @return
1413  *   The DevX object created, NULL otherwise and rte_errno is set.
1414  */
1415 struct mlx5_devx_obj *
1416 mlx5_devx_cmd_create_tis(void *ctx,
1417                          struct mlx5_devx_tis_attr *tis_attr)
1418 {
1419         uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
1420         uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0};
1421         struct mlx5_devx_obj *tis = NULL;
1422         void *tis_ctx;
1423
1424         tis = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tis), 0, SOCKET_ID_ANY);
1425         if (!tis) {
1426                 DRV_LOG(ERR, "Failed to allocate TIS object");
1427                 rte_errno = ENOMEM;
1428                 return NULL;
1429         }
1430         MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS);
1431         tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx);
1432         MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity,
1433                  tis_attr->strict_lag_tx_port_affinity);
1434         MLX5_SET(tisc, tis_ctx, lag_tx_port_affinity,
1435                  tis_attr->lag_tx_port_affinity);
1436         MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio);
1437         MLX5_SET(tisc, tis_ctx, transport_domain,
1438                  tis_attr->transport_domain);
1439         tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1440                                               out, sizeof(out));
1441         if (!tis->obj) {
1442                 DRV_LOG(ERR, "Failed to create TIS using DevX");
1443                 rte_errno = errno;
1444                 mlx5_free(tis);
1445                 return NULL;
1446         }
1447         tis->id = MLX5_GET(create_tis_out, out, tisn);
1448         return tis;
1449 }
1450
1451 /**
1452  * Create transport domain using DevX API.
1453  *
1454  * @param[in] ctx
1455  *   Context returned from mlx5 open_device() glue function.
1456  * @return
1457  *   The DevX object created, NULL otherwise and rte_errno is set.
1458  */
1459 struct mlx5_devx_obj *
1460 mlx5_devx_cmd_create_td(void *ctx)
1461 {
1462         uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0};
1463         uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0};
1464         struct mlx5_devx_obj *td = NULL;
1465
1466         td = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*td), 0, SOCKET_ID_ANY);
1467         if (!td) {
1468                 DRV_LOG(ERR, "Failed to allocate TD object");
1469                 rte_errno = ENOMEM;
1470                 return NULL;
1471         }
1472         MLX5_SET(alloc_transport_domain_in, in, opcode,
1473                  MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN);
1474         td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1475                                              out, sizeof(out));
1476         if (!td->obj) {
1477                 DRV_LOG(ERR, "Failed to create TIS using DevX");
1478                 rte_errno = errno;
1479                 mlx5_free(td);
1480                 return NULL;
1481         }
1482         td->id = MLX5_GET(alloc_transport_domain_out, out,
1483                            transport_domain);
1484         return td;
1485 }
1486
1487 /**
1488  * Dump all flows to file.
1489  *
1490  * @param[in] fdb_domain
1491  *   FDB domain.
1492  * @param[in] rx_domain
1493  *   RX domain.
1494  * @param[in] tx_domain
1495  *   TX domain.
1496  * @param[out] file
1497  *   Pointer to file stream.
1498  *
1499  * @return
1500  *   0 on success, a nagative value otherwise.
1501  */
1502 int
1503 mlx5_devx_cmd_flow_dump(void *fdb_domain __rte_unused,
1504                         void *rx_domain __rte_unused,
1505                         void *tx_domain __rte_unused, FILE *file __rte_unused)
1506 {
1507         int ret = 0;
1508
1509 #ifdef HAVE_MLX5_DR_FLOW_DUMP
1510         if (fdb_domain) {
1511                 ret = mlx5_glue->dr_dump_domain(file, fdb_domain);
1512                 if (ret)
1513                         return ret;
1514         }
1515         MLX5_ASSERT(rx_domain);
1516         ret = mlx5_glue->dr_dump_domain(file, rx_domain);
1517         if (ret)
1518                 return ret;
1519         MLX5_ASSERT(tx_domain);
1520         ret = mlx5_glue->dr_dump_domain(file, tx_domain);
1521 #else
1522         ret = ENOTSUP;
1523 #endif
1524         return -ret;
1525 }
1526
1527 /*
1528  * Create CQ using DevX API.
1529  *
1530  * @param[in] ctx
1531  *   Context returned from mlx5 open_device() glue function.
1532  * @param [in] attr
1533  *   Pointer to CQ attributes structure.
1534  *
1535  * @return
1536  *   The DevX object created, NULL otherwise and rte_errno is set.
1537  */
1538 struct mlx5_devx_obj *
1539 mlx5_devx_cmd_create_cq(void *ctx, struct mlx5_devx_cq_attr *attr)
1540 {
1541         uint32_t in[MLX5_ST_SZ_DW(create_cq_in)] = {0};
1542         uint32_t out[MLX5_ST_SZ_DW(create_cq_out)] = {0};
1543         struct mlx5_devx_obj *cq_obj = mlx5_malloc(MLX5_MEM_ZERO,
1544                                                    sizeof(*cq_obj),
1545                                                    0, SOCKET_ID_ANY);
1546         void *cqctx = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1547
1548         if (!cq_obj) {
1549                 DRV_LOG(ERR, "Failed to allocate CQ object memory.");
1550                 rte_errno = ENOMEM;
1551                 return NULL;
1552         }
1553         MLX5_SET(create_cq_in, in, opcode, MLX5_CMD_OP_CREATE_CQ);
1554         if (attr->db_umem_valid) {
1555                 MLX5_SET(cqc, cqctx, dbr_umem_valid, attr->db_umem_valid);
1556                 MLX5_SET(cqc, cqctx, dbr_umem_id, attr->db_umem_id);
1557                 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_umem_offset);
1558         } else {
1559                 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_addr);
1560         }
1561         MLX5_SET(cqc, cqctx, cqe_sz, attr->cqe_size);
1562         MLX5_SET(cqc, cqctx, cc, attr->use_first_only);
1563         MLX5_SET(cqc, cqctx, oi, attr->overrun_ignore);
1564         MLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size);
1565         MLX5_SET(cqc, cqctx, log_page_size, attr->log_page_size -
1566                  MLX5_ADAPTER_PAGE_SHIFT);
1567         MLX5_SET(cqc, cqctx, c_eqn, attr->eqn);
1568         MLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id);
1569         MLX5_SET(cqc, cqctx, cqe_comp_en, !!attr->cqe_comp_en);
1570         MLX5_SET(cqc, cqctx, mini_cqe_res_format,
1571                  attr->mini_cqe_res_format);
1572         MLX5_SET(cqc, cqctx, mini_cqe_res_format_ext,
1573                  attr->mini_cqe_res_format_ext);
1574         MLX5_SET(cqc, cqctx, cqe_sz, attr->cqe_size);
1575         if (attr->q_umem_valid) {
1576                 MLX5_SET(create_cq_in, in, cq_umem_valid, attr->q_umem_valid);
1577                 MLX5_SET(create_cq_in, in, cq_umem_id, attr->q_umem_id);
1578                 MLX5_SET64(create_cq_in, in, cq_umem_offset,
1579                            attr->q_umem_offset);
1580         }
1581         cq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
1582                                                  sizeof(out));
1583         if (!cq_obj->obj) {
1584                 rte_errno = errno;
1585                 DRV_LOG(ERR, "Failed to create CQ using DevX errno=%d.", errno);
1586                 mlx5_free(cq_obj);
1587                 return NULL;
1588         }
1589         cq_obj->id = MLX5_GET(create_cq_out, out, cqn);
1590         return cq_obj;
1591 }
1592
1593 /**
1594  * Create VIRTQ using DevX API.
1595  *
1596  * @param[in] ctx
1597  *   Context returned from mlx5 open_device() glue function.
1598  * @param [in] attr
1599  *   Pointer to VIRTQ attributes structure.
1600  *
1601  * @return
1602  *   The DevX object created, NULL otherwise and rte_errno is set.
1603  */
1604 struct mlx5_devx_obj *
1605 mlx5_devx_cmd_create_virtq(void *ctx,
1606                            struct mlx5_devx_virtq_attr *attr)
1607 {
1608         uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0};
1609         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
1610         struct mlx5_devx_obj *virtq_obj = mlx5_malloc(MLX5_MEM_ZERO,
1611                                                      sizeof(*virtq_obj),
1612                                                      0, SOCKET_ID_ANY);
1613         void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq);
1614         void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr);
1615         void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context);
1616
1617         if (!virtq_obj) {
1618                 DRV_LOG(ERR, "Failed to allocate virtq data.");
1619                 rte_errno = ENOMEM;
1620                 return NULL;
1621         }
1622         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
1623                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
1624         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
1625                  MLX5_GENERAL_OBJ_TYPE_VIRTQ);
1626         MLX5_SET16(virtio_net_q, virtq, hw_available_index,
1627                    attr->hw_available_index);
1628         MLX5_SET16(virtio_net_q, virtq, hw_used_index, attr->hw_used_index);
1629         MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4);
1630         MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6);
1631         MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum);
1632         MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum);
1633         MLX5_SET16(virtio_q, virtctx, virtio_version_1_0,
1634                    attr->virtio_version_1_0);
1635         MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode);
1636         MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id);
1637         MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr);
1638         MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr);
1639         MLX5_SET64(virtio_q, virtctx, available_addr, attr->available_addr);
1640         MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index);
1641         MLX5_SET16(virtio_q, virtctx, queue_size, attr->q_size);
1642         MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey);
1643         MLX5_SET(virtio_q, virtctx, umem_1_id, attr->umems[0].id);
1644         MLX5_SET(virtio_q, virtctx, umem_1_size, attr->umems[0].size);
1645         MLX5_SET64(virtio_q, virtctx, umem_1_offset, attr->umems[0].offset);
1646         MLX5_SET(virtio_q, virtctx, umem_2_id, attr->umems[1].id);
1647         MLX5_SET(virtio_q, virtctx, umem_2_size, attr->umems[1].size);
1648         MLX5_SET64(virtio_q, virtctx, umem_2_offset, attr->umems[1].offset);
1649         MLX5_SET(virtio_q, virtctx, umem_3_id, attr->umems[2].id);
1650         MLX5_SET(virtio_q, virtctx, umem_3_size, attr->umems[2].size);
1651         MLX5_SET64(virtio_q, virtctx, umem_3_offset, attr->umems[2].offset);
1652         MLX5_SET(virtio_q, virtctx, counter_set_id, attr->counters_obj_id);
1653         MLX5_SET(virtio_q, virtctx, pd, attr->pd);
1654         MLX5_SET(virtio_net_q, virtq, tisn_or_qpn, attr->tis_id);
1655         virtq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
1656                                                     sizeof(out));
1657         if (!virtq_obj->obj) {
1658                 rte_errno = errno;
1659                 DRV_LOG(ERR, "Failed to create VIRTQ Obj using DevX.");
1660                 mlx5_free(virtq_obj);
1661                 return NULL;
1662         }
1663         virtq_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
1664         return virtq_obj;
1665 }
1666
1667 /**
1668  * Modify VIRTQ using DevX API.
1669  *
1670  * @param[in] virtq_obj
1671  *   Pointer to virtq object structure.
1672  * @param [in] attr
1673  *   Pointer to modify virtq attributes structure.
1674  *
1675  * @return
1676  *   0 on success, a negative errno value otherwise and rte_errno is set.
1677  */
1678 int
1679 mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj,
1680                            struct mlx5_devx_virtq_attr *attr)
1681 {
1682         uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0};
1683         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
1684         void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq);
1685         void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr);
1686         void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context);
1687         int ret;
1688
1689         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
1690                  MLX5_CMD_OP_MODIFY_GENERAL_OBJECT);
1691         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
1692                  MLX5_GENERAL_OBJ_TYPE_VIRTQ);
1693         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id);
1694         MLX5_SET64(virtio_net_q, virtq, modify_field_select, attr->type);
1695         MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index);
1696         switch (attr->type) {
1697         case MLX5_VIRTQ_MODIFY_TYPE_STATE:
1698                 MLX5_SET16(virtio_net_q, virtq, state, attr->state);
1699                 break;
1700         case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS:
1701                 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_mkey,
1702                          attr->dirty_bitmap_mkey);
1703                 MLX5_SET64(virtio_net_q, virtq, dirty_bitmap_addr,
1704                          attr->dirty_bitmap_addr);
1705                 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_size,
1706                          attr->dirty_bitmap_size);
1707                 break;
1708         case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE:
1709                 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_dump_enable,
1710                          attr->dirty_bitmap_dump_enable);
1711                 break;
1712         default:
1713                 rte_errno = EINVAL;
1714                 return -rte_errno;
1715         }
1716         ret = mlx5_glue->devx_obj_modify(virtq_obj->obj, in, sizeof(in),
1717                                          out, sizeof(out));
1718         if (ret) {
1719                 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX.");
1720                 rte_errno = errno;
1721                 return -rte_errno;
1722         }
1723         return ret;
1724 }
1725
1726 /**
1727  * Query VIRTQ using DevX API.
1728  *
1729  * @param[in] virtq_obj
1730  *   Pointer to virtq object structure.
1731  * @param [in/out] attr
1732  *   Pointer to virtq attributes structure.
1733  *
1734  * @return
1735  *   0 on success, a negative errno value otherwise and rte_errno is set.
1736  */
1737 int
1738 mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj,
1739                            struct mlx5_devx_virtq_attr *attr)
1740 {
1741         uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
1742         uint32_t out[MLX5_ST_SZ_DW(query_virtq_out)] = {0};
1743         void *hdr = MLX5_ADDR_OF(query_virtq_out, in, hdr);
1744         void *virtq = MLX5_ADDR_OF(query_virtq_out, out, virtq);
1745         int ret;
1746
1747         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
1748                  MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
1749         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
1750                  MLX5_GENERAL_OBJ_TYPE_VIRTQ);
1751         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id);
1752         ret = mlx5_glue->devx_obj_query(virtq_obj->obj, in, sizeof(in),
1753                                          out, sizeof(out));
1754         if (ret) {
1755                 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX.");
1756                 rte_errno = errno;
1757                 return -errno;
1758         }
1759         attr->hw_available_index = MLX5_GET16(virtio_net_q, virtq,
1760                                               hw_available_index);
1761         attr->hw_used_index = MLX5_GET16(virtio_net_q, virtq, hw_used_index);
1762         attr->state = MLX5_GET16(virtio_net_q, virtq, state);
1763         attr->error_type = MLX5_GET16(virtio_net_q, virtq,
1764                                       virtio_q_context.error_type);
1765         return ret;
1766 }
1767
1768 /**
1769  * Create QP using DevX API.
1770  *
1771  * @param[in] ctx
1772  *   Context returned from mlx5 open_device() glue function.
1773  * @param [in] attr
1774  *   Pointer to QP attributes structure.
1775  *
1776  * @return
1777  *   The DevX object created, NULL otherwise and rte_errno is set.
1778  */
1779 struct mlx5_devx_obj *
1780 mlx5_devx_cmd_create_qp(void *ctx,
1781                         struct mlx5_devx_qp_attr *attr)
1782 {
1783         uint32_t in[MLX5_ST_SZ_DW(create_qp_in)] = {0};
1784         uint32_t out[MLX5_ST_SZ_DW(create_qp_out)] = {0};
1785         struct mlx5_devx_obj *qp_obj = mlx5_malloc(MLX5_MEM_ZERO,
1786                                                    sizeof(*qp_obj),
1787                                                    0, SOCKET_ID_ANY);
1788         void *qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1789
1790         if (!qp_obj) {
1791                 DRV_LOG(ERR, "Failed to allocate QP data.");
1792                 rte_errno = ENOMEM;
1793                 return NULL;
1794         }
1795         MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP);
1796         MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC);
1797         MLX5_SET(qpc, qpc, pd, attr->pd);
1798         if (attr->uar_index) {
1799                 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
1800                 MLX5_SET(qpc, qpc, uar_page, attr->uar_index);
1801                 MLX5_SET(qpc, qpc, log_page_size, attr->log_page_size -
1802                          MLX5_ADAPTER_PAGE_SHIFT);
1803                 if (attr->sq_size) {
1804                         MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->sq_size));
1805                         MLX5_SET(qpc, qpc, cqn_snd, attr->cqn);
1806                         MLX5_SET(qpc, qpc, log_sq_size,
1807                                  rte_log2_u32(attr->sq_size));
1808                 } else {
1809                         MLX5_SET(qpc, qpc, no_sq, 1);
1810                 }
1811                 if (attr->rq_size) {
1812                         MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->rq_size));
1813                         MLX5_SET(qpc, qpc, cqn_rcv, attr->cqn);
1814                         MLX5_SET(qpc, qpc, log_rq_stride, attr->log_rq_stride -
1815                                  MLX5_LOG_RQ_STRIDE_SHIFT);
1816                         MLX5_SET(qpc, qpc, log_rq_size,
1817                                  rte_log2_u32(attr->rq_size));
1818                         MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ);
1819                 } else {
1820                         MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ);
1821                 }
1822                 if (attr->dbr_umem_valid) {
1823                         MLX5_SET(qpc, qpc, dbr_umem_valid,
1824                                  attr->dbr_umem_valid);
1825                         MLX5_SET(qpc, qpc, dbr_umem_id, attr->dbr_umem_id);
1826                 }
1827                 MLX5_SET64(qpc, qpc, dbr_addr, attr->dbr_address);
1828                 MLX5_SET64(create_qp_in, in, wq_umem_offset,
1829                            attr->wq_umem_offset);
1830                 MLX5_SET(create_qp_in, in, wq_umem_id, attr->wq_umem_id);
1831                 MLX5_SET(create_qp_in, in, wq_umem_valid, 1);
1832         } else {
1833                 /* Special QP to be managed by FW - no SQ\RQ\CQ\UAR\DB rec. */
1834                 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ);
1835                 MLX5_SET(qpc, qpc, no_sq, 1);
1836         }
1837         qp_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
1838                                                  sizeof(out));
1839         if (!qp_obj->obj) {
1840                 rte_errno = errno;
1841                 DRV_LOG(ERR, "Failed to create QP Obj using DevX.");
1842                 mlx5_free(qp_obj);
1843                 return NULL;
1844         }
1845         qp_obj->id = MLX5_GET(create_qp_out, out, qpn);
1846         return qp_obj;
1847 }
1848
1849 /**
1850  * Modify QP using DevX API.
1851  * Currently supports only force loop-back QP.
1852  *
1853  * @param[in] qp
1854  *   Pointer to QP object structure.
1855  * @param [in] qp_st_mod_op
1856  *   The QP state modification operation.
1857  * @param [in] remote_qp_id
1858  *   The remote QP ID for MLX5_CMD_OP_INIT2RTR_QP operation.
1859  *
1860  * @return
1861  *   0 on success, a negative errno value otherwise and rte_errno is set.
1862  */
1863 int
1864 mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op,
1865                               uint32_t remote_qp_id)
1866 {
1867         union {
1868                 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)];
1869                 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)];
1870                 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)];
1871         } in;
1872         union {
1873                 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)];
1874                 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)];
1875                 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)];
1876         } out;
1877         void *qpc;
1878         int ret;
1879         unsigned int inlen;
1880         unsigned int outlen;
1881
1882         memset(&in, 0, sizeof(in));
1883         memset(&out, 0, sizeof(out));
1884         MLX5_SET(rst2init_qp_in, &in, opcode, qp_st_mod_op);
1885         switch (qp_st_mod_op) {
1886         case MLX5_CMD_OP_RST2INIT_QP:
1887                 MLX5_SET(rst2init_qp_in, &in, qpn, qp->id);
1888                 qpc = MLX5_ADDR_OF(rst2init_qp_in, &in, qpc);
1889                 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1);
1890                 MLX5_SET(qpc, qpc, rre, 1);
1891                 MLX5_SET(qpc, qpc, rwe, 1);
1892                 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
1893                 inlen = sizeof(in.rst2init);
1894                 outlen = sizeof(out.rst2init);
1895                 break;
1896         case MLX5_CMD_OP_INIT2RTR_QP:
1897                 MLX5_SET(init2rtr_qp_in, &in, qpn, qp->id);
1898                 qpc = MLX5_ADDR_OF(init2rtr_qp_in, &in, qpc);
1899                 MLX5_SET(qpc, qpc, primary_address_path.fl, 1);
1900                 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1);
1901                 MLX5_SET(qpc, qpc, mtu, 1);
1902                 MLX5_SET(qpc, qpc, log_msg_max, 30);
1903                 MLX5_SET(qpc, qpc, remote_qpn, remote_qp_id);
1904                 MLX5_SET(qpc, qpc, min_rnr_nak, 0);
1905                 inlen = sizeof(in.init2rtr);
1906                 outlen = sizeof(out.init2rtr);
1907                 break;
1908         case MLX5_CMD_OP_RTR2RTS_QP:
1909                 qpc = MLX5_ADDR_OF(rtr2rts_qp_in, &in, qpc);
1910                 MLX5_SET(rtr2rts_qp_in, &in, qpn, qp->id);
1911                 MLX5_SET(qpc, qpc, primary_address_path.ack_timeout, 14);
1912                 MLX5_SET(qpc, qpc, log_ack_req_freq, 0);
1913                 MLX5_SET(qpc, qpc, retry_count, 7);
1914                 MLX5_SET(qpc, qpc, rnr_retry, 7);
1915                 inlen = sizeof(in.rtr2rts);
1916                 outlen = sizeof(out.rtr2rts);
1917                 break;
1918         default:
1919                 DRV_LOG(ERR, "Invalid or unsupported QP modify op %u.",
1920                         qp_st_mod_op);
1921                 rte_errno = EINVAL;
1922                 return -rte_errno;
1923         }
1924         ret = mlx5_glue->devx_obj_modify(qp->obj, &in, inlen, &out, outlen);
1925         if (ret) {
1926                 DRV_LOG(ERR, "Failed to modify QP using DevX.");
1927                 rte_errno = errno;
1928                 return -rte_errno;
1929         }
1930         return ret;
1931 }
1932
1933 struct mlx5_devx_obj *
1934 mlx5_devx_cmd_create_virtio_q_counters(void *ctx)
1935 {
1936         uint32_t in[MLX5_ST_SZ_DW(create_virtio_q_counters_in)] = {0};
1937         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
1938         struct mlx5_devx_obj *couners_obj = mlx5_malloc(MLX5_MEM_ZERO,
1939                                                        sizeof(*couners_obj), 0,
1940                                                        SOCKET_ID_ANY);
1941         void *hdr = MLX5_ADDR_OF(create_virtio_q_counters_in, in, hdr);
1942
1943         if (!couners_obj) {
1944                 DRV_LOG(ERR, "Failed to allocate virtio queue counters data.");
1945                 rte_errno = ENOMEM;
1946                 return NULL;
1947         }
1948         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
1949                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
1950         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
1951                  MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS);
1952         couners_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
1953                                                       sizeof(out));
1954         if (!couners_obj->obj) {
1955                 rte_errno = errno;
1956                 DRV_LOG(ERR, "Failed to create virtio queue counters Obj using"
1957                         " DevX.");
1958                 mlx5_free(couners_obj);
1959                 return NULL;
1960         }
1961         couners_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
1962         return couners_obj;
1963 }
1964
1965 int
1966 mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj,
1967                                    struct mlx5_devx_virtio_q_couners_attr *attr)
1968 {
1969         uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
1970         uint32_t out[MLX5_ST_SZ_DW(query_virtio_q_counters_out)] = {0};
1971         void *hdr = MLX5_ADDR_OF(query_virtio_q_counters_out, in, hdr);
1972         void *virtio_q_counters = MLX5_ADDR_OF(query_virtio_q_counters_out, out,
1973                                                virtio_q_counters);
1974         int ret;
1975
1976         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
1977                  MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
1978         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
1979                  MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS);
1980         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, couners_obj->id);
1981         ret = mlx5_glue->devx_obj_query(couners_obj->obj, in, sizeof(in), out,
1982                                         sizeof(out));
1983         if (ret) {
1984                 DRV_LOG(ERR, "Failed to query virtio q counters using DevX.");
1985                 rte_errno = errno;
1986                 return -errno;
1987         }
1988         attr->received_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters,
1989                                          received_desc);
1990         attr->completed_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters,
1991                                           completed_desc);
1992         attr->error_cqes = MLX5_GET(virtio_q_counters, virtio_q_counters,
1993                                     error_cqes);
1994         attr->bad_desc_errors = MLX5_GET(virtio_q_counters, virtio_q_counters,
1995                                          bad_desc_errors);
1996         attr->exceed_max_chain = MLX5_GET(virtio_q_counters, virtio_q_counters,
1997                                           exceed_max_chain);
1998         attr->invalid_buffer = MLX5_GET(virtio_q_counters, virtio_q_counters,
1999                                         invalid_buffer);
2000         return ret;
2001 }
2002
2003 /**
2004  * Create general object of type FLOW_HIT_ASO using DevX API.
2005  *
2006  * @param[in] ctx
2007  *   Context returned from mlx5 open_device() glue function.
2008  * @param [in] pd
2009  *   PD value to associate the FLOW_HIT_ASO object with.
2010  *
2011  * @return
2012  *   The DevX object created, NULL otherwise and rte_errno is set.
2013  */
2014 struct mlx5_devx_obj *
2015 mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, uint32_t pd)
2016 {
2017         uint32_t in[MLX5_ST_SZ_DW(create_flow_hit_aso_in)] = {0};
2018         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2019         struct mlx5_devx_obj *flow_hit_aso_obj = NULL;
2020         void *ptr = NULL;
2021
2022         flow_hit_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*flow_hit_aso_obj),
2023                                        0, SOCKET_ID_ANY);
2024         if (!flow_hit_aso_obj) {
2025                 DRV_LOG(ERR, "Failed to allocate FLOW_HIT_ASO object data");
2026                 rte_errno = ENOMEM;
2027                 return NULL;
2028         }
2029         ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, hdr);
2030         MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2031                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2032         MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2033                  MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO);
2034         ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, flow_hit_aso);
2035         MLX5_SET(flow_hit_aso, ptr, access_pd, pd);
2036         flow_hit_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2037                                                            out, sizeof(out));
2038         if (!flow_hit_aso_obj->obj) {
2039                 rte_errno = errno;
2040                 DRV_LOG(ERR, "Failed to create FLOW_HIT_ASO obj using DevX.");
2041                 mlx5_free(flow_hit_aso_obj);
2042                 return NULL;
2043         }
2044         flow_hit_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2045         return flow_hit_aso_obj;
2046 }