net/ice: fix outer L4 checksum in scalar Rx
[dpdk.git] / drivers / common / mlx5 / mlx5_devx_cmds.c
1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright 2018 Mellanox Technologies, Ltd
3  */
4
5 #include <unistd.h>
6
7 #include <rte_errno.h>
8 #include <rte_malloc.h>
9 #include <rte_eal_paging.h>
10
11 #include "mlx5_prm.h"
12 #include "mlx5_devx_cmds.h"
13 #include "mlx5_common_log.h"
14 #include "mlx5_malloc.h"
15
16 static void *
17 mlx5_devx_get_hca_cap(void *ctx, uint32_t *in, uint32_t *out,
18                       int *err, uint32_t flags)
19 {
20         const size_t size_in = MLX5_ST_SZ_DW(query_hca_cap_in) * sizeof(int);
21         const size_t size_out = MLX5_ST_SZ_DW(query_hca_cap_out) * sizeof(int);
22         int status, syndrome, rc;
23
24         if (err)
25                 *err = 0;
26         memset(in, 0, size_in);
27         memset(out, 0, size_out);
28         MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
29         MLX5_SET(query_hca_cap_in, in, op_mod, flags);
30         rc = mlx5_glue->devx_general_cmd(ctx, in, size_in, out, size_out);
31         if (rc) {
32                 DRV_LOG(ERR,
33                         "Failed to query devx HCA capabilities func %#02x",
34                         flags >> 1);
35                 if (err)
36                         *err = rc > 0 ? -rc : rc;
37                 return NULL;
38         }
39         status = MLX5_GET(query_hca_cap_out, out, status);
40         syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
41         if (status) {
42                 DRV_LOG(ERR,
43                         "Failed to query devx HCA capabilities func %#02x status %x, syndrome = %x",
44                         flags >> 1, status, syndrome);
45                 if (err)
46                         *err = -1;
47                 return NULL;
48         }
49         return MLX5_ADDR_OF(query_hca_cap_out, out, capability);
50 }
51
52 /**
53  * Perform read access to the registers. Reads data from register
54  * and writes ones to the specified buffer.
55  *
56  * @param[in] ctx
57  *   Context returned from mlx5 open_device() glue function.
58  * @param[in] reg_id
59  *   Register identifier according to the PRM.
60  * @param[in] arg
61  *   Register access auxiliary parameter according to the PRM.
62  * @param[out] data
63  *   Pointer to the buffer to store read data.
64  * @param[in] dw_cnt
65  *   Buffer size in double words.
66  *
67  * @return
68  *   0 on success, a negative value otherwise.
69  */
70 int
71 mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg,
72                             uint32_t *data, uint32_t dw_cnt)
73 {
74         uint32_t in[MLX5_ST_SZ_DW(access_register_in)]   = {0};
75         uint32_t out[MLX5_ST_SZ_DW(access_register_out) +
76                      MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0};
77         int status, rc;
78
79         MLX5_ASSERT(data && dw_cnt);
80         MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX);
81         if (dw_cnt  > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) {
82                 DRV_LOG(ERR, "Not enough  buffer for register read data");
83                 return -1;
84         }
85         MLX5_SET(access_register_in, in, opcode,
86                  MLX5_CMD_OP_ACCESS_REGISTER_USER);
87         MLX5_SET(access_register_in, in, op_mod,
88                                         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ);
89         MLX5_SET(access_register_in, in, register_id, reg_id);
90         MLX5_SET(access_register_in, in, argument, arg);
91         rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out,
92                                          MLX5_ST_SZ_BYTES(access_register_out) +
93                                          sizeof(uint32_t) * dw_cnt);
94         if (rc)
95                 goto error;
96         status = MLX5_GET(access_register_out, out, status);
97         if (status) {
98                 int syndrome = MLX5_GET(access_register_out, out, syndrome);
99
100                 DRV_LOG(DEBUG, "Failed to read access NIC register 0x%X, "
101                                "status %x, syndrome = %x",
102                                reg_id, status, syndrome);
103                 return -1;
104         }
105         memcpy(data, &out[MLX5_ST_SZ_DW(access_register_out)],
106                dw_cnt * sizeof(uint32_t));
107         return 0;
108 error:
109         rc = (rc > 0) ? -rc : rc;
110         return rc;
111 }
112
113 /**
114  * Perform write access to the registers.
115  *
116  * @param[in] ctx
117  *   Context returned from mlx5 open_device() glue function.
118  * @param[in] reg_id
119  *   Register identifier according to the PRM.
120  * @param[in] arg
121  *   Register access auxiliary parameter according to the PRM.
122  * @param[out] data
123  *   Pointer to the buffer containing data to write.
124  * @param[in] dw_cnt
125  *   Buffer size in double words (32bit units).
126  *
127  * @return
128  *   0 on success, a negative value otherwise.
129  */
130 int
131 mlx5_devx_cmd_register_write(void *ctx, uint16_t reg_id, uint32_t arg,
132                              uint32_t *data, uint32_t dw_cnt)
133 {
134         uint32_t in[MLX5_ST_SZ_DW(access_register_in) +
135                     MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0};
136         uint32_t out[MLX5_ST_SZ_DW(access_register_out)] = {0};
137         int status, rc;
138         void *ptr;
139
140         MLX5_ASSERT(data && dw_cnt);
141         MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX);
142         if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) {
143                 DRV_LOG(ERR, "Data to write exceeds max size");
144                 return -1;
145         }
146         MLX5_SET(access_register_in, in, opcode,
147                  MLX5_CMD_OP_ACCESS_REGISTER_USER);
148         MLX5_SET(access_register_in, in, op_mod,
149                  MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE);
150         MLX5_SET(access_register_in, in, register_id, reg_id);
151         MLX5_SET(access_register_in, in, argument, arg);
152         ptr = MLX5_ADDR_OF(access_register_in, in, register_data);
153         memcpy(ptr, data, dw_cnt * sizeof(uint32_t));
154         rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
155
156         rc = mlx5_glue->devx_general_cmd(ctx, in,
157                                          MLX5_ST_SZ_BYTES(access_register_in) +
158                                          dw_cnt * sizeof(uint32_t),
159                                          out, sizeof(out));
160         if (rc)
161                 goto error;
162         status = MLX5_GET(access_register_out, out, status);
163         if (status) {
164                 int syndrome = MLX5_GET(access_register_out, out, syndrome);
165
166                 DRV_LOG(DEBUG, "Failed to write access NIC register 0x%X, "
167                                "status %x, syndrome = %x",
168                                reg_id, status, syndrome);
169                 return -1;
170         }
171         return 0;
172 error:
173         rc = (rc > 0) ? -rc : rc;
174         return rc;
175 }
176
177 /**
178  * Allocate flow counters via devx interface.
179  *
180  * @param[in] ctx
181  *   Context returned from mlx5 open_device() glue function.
182  * @param dcs
183  *   Pointer to counters properties structure to be filled by the routine.
184  * @param bulk_n_128
185  *   Bulk counter numbers in 128 counters units.
186  *
187  * @return
188  *   Pointer to counter object on success, a negative value otherwise and
189  *   rte_errno is set.
190  */
191 struct mlx5_devx_obj *
192 mlx5_devx_cmd_flow_counter_alloc(void *ctx, uint32_t bulk_n_128)
193 {
194         struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs),
195                                                 0, SOCKET_ID_ANY);
196         uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)]   = {0};
197         uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0};
198
199         if (!dcs) {
200                 rte_errno = ENOMEM;
201                 return NULL;
202         }
203         MLX5_SET(alloc_flow_counter_in, in, opcode,
204                  MLX5_CMD_OP_ALLOC_FLOW_COUNTER);
205         MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128);
206         dcs->obj = mlx5_glue->devx_obj_create(ctx, in,
207                                               sizeof(in), out, sizeof(out));
208         if (!dcs->obj) {
209                 DRV_LOG(ERR, "Can't allocate counters - error %d", errno);
210                 rte_errno = errno;
211                 mlx5_free(dcs);
212                 return NULL;
213         }
214         dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id);
215         return dcs;
216 }
217
218 /**
219  * Query flow counters values.
220  *
221  * @param[in] dcs
222  *   devx object that was obtained from mlx5_devx_cmd_fc_alloc.
223  * @param[in] clear
224  *   Whether hardware should clear the counters after the query or not.
225  * @param[in] n_counters
226  *   0 in case of 1 counter to read, otherwise the counter number to read.
227  *  @param pkts
228  *   The number of packets that matched the flow.
229  *  @param bytes
230  *    The number of bytes that matched the flow.
231  *  @param mkey
232  *   The mkey key for batch query.
233  *  @param addr
234  *    The address in the mkey range for batch query.
235  *  @param cmd_comp
236  *   The completion object for asynchronous batch query.
237  *  @param async_id
238  *    The ID to be returned in the asynchronous batch query response.
239  *
240  * @return
241  *   0 on success, a negative value otherwise.
242  */
243 int
244 mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs,
245                                  int clear, uint32_t n_counters,
246                                  uint64_t *pkts, uint64_t *bytes,
247                                  uint32_t mkey, void *addr,
248                                  void *cmd_comp,
249                                  uint64_t async_id)
250 {
251         int out_len = MLX5_ST_SZ_BYTES(query_flow_counter_out) +
252                         MLX5_ST_SZ_BYTES(traffic_counter);
253         uint32_t out[out_len];
254         uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0};
255         void *stats;
256         int rc;
257
258         MLX5_SET(query_flow_counter_in, in, opcode,
259                  MLX5_CMD_OP_QUERY_FLOW_COUNTER);
260         MLX5_SET(query_flow_counter_in, in, op_mod, 0);
261         MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id);
262         MLX5_SET(query_flow_counter_in, in, clear, !!clear);
263
264         if (n_counters) {
265                 MLX5_SET(query_flow_counter_in, in, num_of_counters,
266                          n_counters);
267                 MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1);
268                 MLX5_SET(query_flow_counter_in, in, mkey, mkey);
269                 MLX5_SET64(query_flow_counter_in, in, address,
270                            (uint64_t)(uintptr_t)addr);
271         }
272         if (!cmd_comp)
273                 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out,
274                                                out_len);
275         else
276                 rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in),
277                                                      out_len, async_id,
278                                                      cmd_comp);
279         if (rc) {
280                 DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc);
281                 rte_errno = rc;
282                 return -rc;
283         }
284         if (!n_counters) {
285                 stats = MLX5_ADDR_OF(query_flow_counter_out,
286                                      out, flow_statistics);
287                 *pkts = MLX5_GET64(traffic_counter, stats, packets);
288                 *bytes = MLX5_GET64(traffic_counter, stats, octets);
289         }
290         return 0;
291 }
292
293 /**
294  * Create a new mkey.
295  *
296  * @param[in] ctx
297  *   Context returned from mlx5 open_device() glue function.
298  * @param[in] attr
299  *   Attributes of the requested mkey.
300  *
301  * @return
302  *   Pointer to Devx mkey on success, a negative value otherwise and rte_errno
303  *   is set.
304  */
305 struct mlx5_devx_obj *
306 mlx5_devx_cmd_mkey_create(void *ctx,
307                           struct mlx5_devx_mkey_attr *attr)
308 {
309         struct mlx5_klm *klm_array = attr->klm_array;
310         int klm_num = attr->klm_num;
311         int in_size_dw = MLX5_ST_SZ_DW(create_mkey_in) +
312                      (klm_num ? RTE_ALIGN(klm_num, 4) : 0) * MLX5_ST_SZ_DW(klm);
313         uint32_t in[in_size_dw];
314         uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0};
315         void *mkc;
316         struct mlx5_devx_obj *mkey = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mkey),
317                                                  0, SOCKET_ID_ANY);
318         size_t pgsize;
319         uint32_t translation_size;
320
321         if (!mkey) {
322                 rte_errno = ENOMEM;
323                 return NULL;
324         }
325         memset(in, 0, in_size_dw * 4);
326         pgsize = rte_mem_page_size();
327         if (pgsize == (size_t)-1) {
328                 mlx5_free(mkey);
329                 DRV_LOG(ERR, "Failed to get page size");
330                 rte_errno = ENOMEM;
331                 return NULL;
332         }
333         MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY);
334         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
335         if (klm_num > 0) {
336                 int i;
337                 uint8_t *klm = (uint8_t *)MLX5_ADDR_OF(create_mkey_in, in,
338                                                        klm_pas_mtt);
339                 translation_size = RTE_ALIGN(klm_num, 4);
340                 for (i = 0; i < klm_num; i++) {
341                         MLX5_SET(klm, klm, byte_count, klm_array[i].byte_count);
342                         MLX5_SET(klm, klm, mkey, klm_array[i].mkey);
343                         MLX5_SET64(klm, klm, address, klm_array[i].address);
344                         klm += MLX5_ST_SZ_BYTES(klm);
345                 }
346                 for (; i < (int)translation_size; i++) {
347                         MLX5_SET(klm, klm, mkey, 0x0);
348                         MLX5_SET64(klm, klm, address, 0x0);
349                         klm += MLX5_ST_SZ_BYTES(klm);
350                 }
351                 MLX5_SET(mkc, mkc, access_mode_1_0, attr->log_entity_size ?
352                          MLX5_MKC_ACCESS_MODE_KLM_FBS :
353                          MLX5_MKC_ACCESS_MODE_KLM);
354                 MLX5_SET(mkc, mkc, log_page_size, attr->log_entity_size);
355         } else {
356                 translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16;
357                 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
358                 MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize));
359         }
360         MLX5_SET(create_mkey_in, in, translations_octword_actual_size,
361                  translation_size);
362         MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id);
363         MLX5_SET(create_mkey_in, in, pg_access, attr->pg_access);
364         MLX5_SET(mkc, mkc, lw, 0x1);
365         MLX5_SET(mkc, mkc, lr, 0x1);
366         if (attr->set_remote_rw) {
367                 MLX5_SET(mkc, mkc, rw, 0x1);
368                 MLX5_SET(mkc, mkc, rr, 0x1);
369         }
370         MLX5_SET(mkc, mkc, qpn, 0xffffff);
371         MLX5_SET(mkc, mkc, pd, attr->pd);
372         MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF);
373         MLX5_SET(mkc, mkc, umr_en, attr->umr_en);
374         MLX5_SET(mkc, mkc, translations_octword_size, translation_size);
375         MLX5_SET(mkc, mkc, relaxed_ordering_write,
376                  attr->relaxed_ordering_write);
377         MLX5_SET(mkc, mkc, relaxed_ordering_read, attr->relaxed_ordering_read);
378         MLX5_SET64(mkc, mkc, start_addr, attr->addr);
379         MLX5_SET64(mkc, mkc, len, attr->size);
380         MLX5_SET(mkc, mkc, crypto_en, attr->crypto_en);
381         if (attr->crypto_en) {
382                 MLX5_SET(mkc, mkc, bsf_en, attr->crypto_en);
383                 MLX5_SET(mkc, mkc, bsf_octword_size, 4);
384         }
385         mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out,
386                                                sizeof(out));
387         if (!mkey->obj) {
388                 DRV_LOG(ERR, "Can't create %sdirect mkey - error %d",
389                         klm_num ? "an in" : "a ", errno);
390                 rte_errno = errno;
391                 mlx5_free(mkey);
392                 return NULL;
393         }
394         mkey->id = MLX5_GET(create_mkey_out, out, mkey_index);
395         mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF);
396         return mkey;
397 }
398
399 /**
400  * Get status of devx command response.
401  * Mainly used for asynchronous commands.
402  *
403  * @param[in] out
404  *   The out response buffer.
405  *
406  * @return
407  *   0 on success, non-zero value otherwise.
408  */
409 int
410 mlx5_devx_get_out_command_status(void *out)
411 {
412         int status;
413
414         if (!out)
415                 return -EINVAL;
416         status = MLX5_GET(query_flow_counter_out, out, status);
417         if (status) {
418                 int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome);
419
420                 DRV_LOG(ERR, "Bad DevX status %x, syndrome = %x", status,
421                         syndrome);
422         }
423         return status;
424 }
425
426 /**
427  * Destroy any object allocated by a Devx API.
428  *
429  * @param[in] obj
430  *   Pointer to a general object.
431  *
432  * @return
433  *   0 on success, a negative value otherwise.
434  */
435 int
436 mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj)
437 {
438         int ret;
439
440         if (!obj)
441                 return 0;
442         ret =  mlx5_glue->devx_obj_destroy(obj->obj);
443         mlx5_free(obj);
444         return ret;
445 }
446
447 /**
448  * Query NIC vport context.
449  * Fills minimal inline attribute.
450  *
451  * @param[in] ctx
452  *   ibv contexts returned from mlx5dv_open_device.
453  * @param[in] vport
454  *   vport index
455  * @param[out] attr
456  *   Attributes device values.
457  *
458  * @return
459  *   0 on success, a negative value otherwise.
460  */
461 static int
462 mlx5_devx_cmd_query_nic_vport_context(void *ctx,
463                                       unsigned int vport,
464                                       struct mlx5_hca_attr *attr)
465 {
466         uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0};
467         uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0};
468         void *vctx;
469         int status, syndrome, rc;
470
471         /* Query NIC vport context to determine inline mode. */
472         MLX5_SET(query_nic_vport_context_in, in, opcode,
473                  MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT);
474         MLX5_SET(query_nic_vport_context_in, in, vport_number, vport);
475         if (vport)
476                 MLX5_SET(query_nic_vport_context_in, in, other_vport, 1);
477         rc = mlx5_glue->devx_general_cmd(ctx,
478                                          in, sizeof(in),
479                                          out, sizeof(out));
480         if (rc)
481                 goto error;
482         status = MLX5_GET(query_nic_vport_context_out, out, status);
483         syndrome = MLX5_GET(query_nic_vport_context_out, out, syndrome);
484         if (status) {
485                 DRV_LOG(DEBUG, "Failed to query NIC vport context, "
486                         "status %x, syndrome = %x", status, syndrome);
487                 return -1;
488         }
489         vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out,
490                             nic_vport_context);
491         attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx,
492                                            min_wqe_inline_mode);
493         return 0;
494 error:
495         rc = (rc > 0) ? -rc : rc;
496         return rc;
497 }
498
499 /**
500  * Query NIC vDPA attributes.
501  *
502  * @param[in] ctx
503  *   Context returned from mlx5 open_device() glue function.
504  * @param[out] vdpa_attr
505  *   vDPA Attributes structure to fill.
506  */
507 static void
508 mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx,
509                                   struct mlx5_hca_vdpa_attr *vdpa_attr)
510 {
511         uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)];
512         uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)];
513         void *hcattr;
514
515         hcattr = mlx5_devx_get_hca_cap(ctx, in, out, NULL,
516                         MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION |
517                         MLX5_HCA_CAP_OPMOD_GET_CUR);
518         if (!hcattr) {
519                 RTE_LOG(DEBUG, PMD, "Failed to query devx VDPA capabilities");
520                 vdpa_attr->valid = 0;
521         } else {
522                 vdpa_attr->valid = 1;
523                 vdpa_attr->desc_tunnel_offload_type =
524                         MLX5_GET(virtio_emulation_cap, hcattr,
525                                  desc_tunnel_offload_type);
526                 vdpa_attr->eth_frame_offload_type =
527                         MLX5_GET(virtio_emulation_cap, hcattr,
528                                  eth_frame_offload_type);
529                 vdpa_attr->virtio_version_1_0 =
530                         MLX5_GET(virtio_emulation_cap, hcattr,
531                                  virtio_version_1_0);
532                 vdpa_attr->tso_ipv4 = MLX5_GET(virtio_emulation_cap, hcattr,
533                                                tso_ipv4);
534                 vdpa_attr->tso_ipv6 = MLX5_GET(virtio_emulation_cap, hcattr,
535                                                tso_ipv6);
536                 vdpa_attr->tx_csum = MLX5_GET(virtio_emulation_cap, hcattr,
537                                               tx_csum);
538                 vdpa_attr->rx_csum = MLX5_GET(virtio_emulation_cap, hcattr,
539                                               rx_csum);
540                 vdpa_attr->event_mode = MLX5_GET(virtio_emulation_cap, hcattr,
541                                                  event_mode);
542                 vdpa_attr->virtio_queue_type =
543                         MLX5_GET(virtio_emulation_cap, hcattr,
544                                  virtio_queue_type);
545                 vdpa_attr->log_doorbell_stride =
546                         MLX5_GET(virtio_emulation_cap, hcattr,
547                                  log_doorbell_stride);
548                 vdpa_attr->log_doorbell_bar_size =
549                         MLX5_GET(virtio_emulation_cap, hcattr,
550                                  log_doorbell_bar_size);
551                 vdpa_attr->doorbell_bar_offset =
552                         MLX5_GET64(virtio_emulation_cap, hcattr,
553                                    doorbell_bar_offset);
554                 vdpa_attr->max_num_virtio_queues =
555                         MLX5_GET(virtio_emulation_cap, hcattr,
556                                  max_num_virtio_queues);
557                 vdpa_attr->umems[0].a = MLX5_GET(virtio_emulation_cap, hcattr,
558                                                  umem_1_buffer_param_a);
559                 vdpa_attr->umems[0].b = MLX5_GET(virtio_emulation_cap, hcattr,
560                                                  umem_1_buffer_param_b);
561                 vdpa_attr->umems[1].a = MLX5_GET(virtio_emulation_cap, hcattr,
562                                                  umem_2_buffer_param_a);
563                 vdpa_attr->umems[1].b = MLX5_GET(virtio_emulation_cap, hcattr,
564                                                  umem_2_buffer_param_b);
565                 vdpa_attr->umems[2].a = MLX5_GET(virtio_emulation_cap, hcattr,
566                                                  umem_3_buffer_param_a);
567                 vdpa_attr->umems[2].b = MLX5_GET(virtio_emulation_cap, hcattr,
568                                                  umem_3_buffer_param_b);
569         }
570 }
571
572 int
573 mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj,
574                                   uint32_t ids[], uint32_t num)
575 {
576         uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
577         uint32_t out[MLX5_ST_SZ_DW(create_flex_parser_out)] = {0};
578         void *hdr = MLX5_ADDR_OF(create_flex_parser_out, in, hdr);
579         void *flex = MLX5_ADDR_OF(create_flex_parser_out, out, flex);
580         void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table);
581         int ret;
582         uint32_t idx = 0;
583         uint32_t i;
584
585         if (num > MLX5_GRAPH_NODE_SAMPLE_NUM) {
586                 rte_errno = EINVAL;
587                 DRV_LOG(ERR, "Too many sample IDs to be fetched.");
588                 return -rte_errno;
589         }
590         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
591                  MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
592         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
593                  MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH);
594         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, flex_obj->id);
595         ret = mlx5_glue->devx_obj_query(flex_obj->obj, in, sizeof(in),
596                                         out, sizeof(out));
597         if (ret) {
598                 rte_errno = ret;
599                 DRV_LOG(ERR, "Failed to query sample IDs with object %p.",
600                         (void *)flex_obj);
601                 return -rte_errno;
602         }
603         for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) {
604                 void *s_off = (void *)((char *)sample + i *
605                               MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample));
606                 uint32_t en;
607
608                 en = MLX5_GET(parse_graph_flow_match_sample, s_off,
609                               flow_match_sample_en);
610                 if (!en)
611                         continue;
612                 ids[idx++] = MLX5_GET(parse_graph_flow_match_sample, s_off,
613                                   flow_match_sample_field_id);
614         }
615         if (num != idx) {
616                 rte_errno = EINVAL;
617                 DRV_LOG(ERR, "Number of sample IDs are not as expected.");
618                 return -rte_errno;
619         }
620         return ret;
621 }
622
623 struct mlx5_devx_obj *
624 mlx5_devx_cmd_create_flex_parser(void *ctx,
625                                  struct mlx5_devx_graph_node_attr *data)
626 {
627         uint32_t in[MLX5_ST_SZ_DW(create_flex_parser_in)] = {0};
628         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
629         void *hdr = MLX5_ADDR_OF(create_flex_parser_in, in, hdr);
630         void *flex = MLX5_ADDR_OF(create_flex_parser_in, in, flex);
631         void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table);
632         void *in_arc = MLX5_ADDR_OF(parse_graph_flex, flex, input_arc);
633         void *out_arc = MLX5_ADDR_OF(parse_graph_flex, flex, output_arc);
634         struct mlx5_devx_obj *parse_flex_obj = mlx5_malloc
635                      (MLX5_MEM_ZERO, sizeof(*parse_flex_obj), 0, SOCKET_ID_ANY);
636         uint32_t i;
637
638         if (!parse_flex_obj) {
639                 DRV_LOG(ERR, "Failed to allocate flex parser data.");
640                 rte_errno = ENOMEM;
641                 return NULL;
642         }
643         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
644                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
645         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
646                  MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH);
647         MLX5_SET(parse_graph_flex, flex, header_length_mode,
648                  data->header_length_mode);
649         MLX5_SET64(parse_graph_flex, flex, modify_field_select,
650                    data->modify_field_select);
651         MLX5_SET(parse_graph_flex, flex, header_length_base_value,
652                  data->header_length_base_value);
653         MLX5_SET(parse_graph_flex, flex, header_length_field_offset,
654                  data->header_length_field_offset);
655         MLX5_SET(parse_graph_flex, flex, header_length_field_shift,
656                  data->header_length_field_shift);
657         MLX5_SET(parse_graph_flex, flex, next_header_field_offset,
658                  data->next_header_field_offset);
659         MLX5_SET(parse_graph_flex, flex, next_header_field_size,
660                  data->next_header_field_size);
661         MLX5_SET(parse_graph_flex, flex, header_length_field_mask,
662                  data->header_length_field_mask);
663         for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) {
664                 struct mlx5_devx_match_sample_attr *s = &data->sample[i];
665                 void *s_off = (void *)((char *)sample + i *
666                               MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample));
667
668                 if (!s->flow_match_sample_en)
669                         continue;
670                 MLX5_SET(parse_graph_flow_match_sample, s_off,
671                          flow_match_sample_en, !!s->flow_match_sample_en);
672                 MLX5_SET(parse_graph_flow_match_sample, s_off,
673                          flow_match_sample_field_offset,
674                          s->flow_match_sample_field_offset);
675                 MLX5_SET(parse_graph_flow_match_sample, s_off,
676                          flow_match_sample_offset_mode,
677                          s->flow_match_sample_offset_mode);
678                 MLX5_SET(parse_graph_flow_match_sample, s_off,
679                          flow_match_sample_field_offset_mask,
680                          s->flow_match_sample_field_offset_mask);
681                 MLX5_SET(parse_graph_flow_match_sample, s_off,
682                          flow_match_sample_field_offset_shift,
683                          s->flow_match_sample_field_offset_shift);
684                 MLX5_SET(parse_graph_flow_match_sample, s_off,
685                          flow_match_sample_field_base_offset,
686                          s->flow_match_sample_field_base_offset);
687                 MLX5_SET(parse_graph_flow_match_sample, s_off,
688                          flow_match_sample_tunnel_mode,
689                          s->flow_match_sample_tunnel_mode);
690         }
691         for (i = 0; i < MLX5_GRAPH_NODE_ARC_NUM; i++) {
692                 struct mlx5_devx_graph_arc_attr *ia = &data->in[i];
693                 struct mlx5_devx_graph_arc_attr *oa = &data->out[i];
694                 void *in_off = (void *)((char *)in_arc + i *
695                               MLX5_ST_SZ_BYTES(parse_graph_arc));
696                 void *out_off = (void *)((char *)out_arc + i *
697                               MLX5_ST_SZ_BYTES(parse_graph_arc));
698
699                 if (ia->arc_parse_graph_node != 0) {
700                         MLX5_SET(parse_graph_arc, in_off,
701                                  compare_condition_value,
702                                  ia->compare_condition_value);
703                         MLX5_SET(parse_graph_arc, in_off, start_inner_tunnel,
704                                  ia->start_inner_tunnel);
705                         MLX5_SET(parse_graph_arc, in_off, arc_parse_graph_node,
706                                  ia->arc_parse_graph_node);
707                         MLX5_SET(parse_graph_arc, in_off,
708                                  parse_graph_node_handle,
709                                  ia->parse_graph_node_handle);
710                 }
711                 if (oa->arc_parse_graph_node != 0) {
712                         MLX5_SET(parse_graph_arc, out_off,
713                                  compare_condition_value,
714                                  oa->compare_condition_value);
715                         MLX5_SET(parse_graph_arc, out_off, start_inner_tunnel,
716                                  oa->start_inner_tunnel);
717                         MLX5_SET(parse_graph_arc, out_off, arc_parse_graph_node,
718                                  oa->arc_parse_graph_node);
719                         MLX5_SET(parse_graph_arc, out_off,
720                                  parse_graph_node_handle,
721                                  oa->parse_graph_node_handle);
722                 }
723         }
724         parse_flex_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
725                                                          out, sizeof(out));
726         if (!parse_flex_obj->obj) {
727                 rte_errno = errno;
728                 DRV_LOG(ERR, "Failed to create FLEX PARSE GRAPH object "
729                         "by using DevX.");
730                 mlx5_free(parse_flex_obj);
731                 return NULL;
732         }
733         parse_flex_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
734         return parse_flex_obj;
735 }
736
737 static int
738 mlx5_devx_cmd_query_hca_parse_graph_node_cap
739         (void *ctx, struct mlx5_hca_flex_attr *attr)
740 {
741         uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)];
742         uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)];
743         void *hcattr;
744         int rc;
745
746         hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
747                         MLX5_GET_HCA_CAP_OP_MOD_PARSE_GRAPH_NODE_CAP |
748                         MLX5_HCA_CAP_OPMOD_GET_CUR);
749         if (!hcattr)
750                 return rc;
751         attr->node_in = MLX5_GET(parse_graph_node_cap, hcattr, node_in);
752         attr->node_out = MLX5_GET(parse_graph_node_cap, hcattr, node_out);
753         attr->header_length_mode = MLX5_GET(parse_graph_node_cap, hcattr,
754                                             header_length_mode);
755         attr->sample_offset_mode = MLX5_GET(parse_graph_node_cap, hcattr,
756                                             sample_offset_mode);
757         attr->max_num_arc_in = MLX5_GET(parse_graph_node_cap, hcattr,
758                                         max_num_arc_in);
759         attr->max_num_arc_out = MLX5_GET(parse_graph_node_cap, hcattr,
760                                          max_num_arc_out);
761         attr->max_num_sample = MLX5_GET(parse_graph_node_cap, hcattr,
762                                         max_num_sample);
763         attr->sample_id_in_out = MLX5_GET(parse_graph_node_cap, hcattr,
764                                           sample_id_in_out);
765         attr->max_base_header_length = MLX5_GET(parse_graph_node_cap, hcattr,
766                                                 max_base_header_length);
767         attr->max_sample_base_offset = MLX5_GET(parse_graph_node_cap, hcattr,
768                                                 max_sample_base_offset);
769         attr->max_next_header_offset = MLX5_GET(parse_graph_node_cap, hcattr,
770                                                 max_next_header_offset);
771         attr->header_length_mask_width = MLX5_GET(parse_graph_node_cap, hcattr,
772                                                   header_length_mask_width);
773         /* Get the max supported samples from HCA CAP 2 */
774         hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
775                         MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 |
776                         MLX5_HCA_CAP_OPMOD_GET_CUR);
777         if (!hcattr)
778                 return rc;
779         attr->max_num_prog_sample =
780                 MLX5_GET(cmd_hca_cap_2, hcattr, max_num_prog_sample_field);
781         return 0;
782 }
783
784 static int
785 mlx5_devx_query_pkt_integrity_match(void *hcattr)
786 {
787         return MLX5_GET(flow_table_nic_cap, hcattr,
788                         ft_field_support_2_nic_receive.inner_l3_ok) &&
789                MLX5_GET(flow_table_nic_cap, hcattr,
790                         ft_field_support_2_nic_receive.inner_l4_ok) &&
791                MLX5_GET(flow_table_nic_cap, hcattr,
792                         ft_field_support_2_nic_receive.outer_l3_ok) &&
793                MLX5_GET(flow_table_nic_cap, hcattr,
794                         ft_field_support_2_nic_receive.outer_l4_ok) &&
795                MLX5_GET(flow_table_nic_cap, hcattr,
796                         ft_field_support_2_nic_receive
797                                 .inner_ipv4_checksum_ok) &&
798                MLX5_GET(flow_table_nic_cap, hcattr,
799                         ft_field_support_2_nic_receive.inner_l4_checksum_ok) &&
800                MLX5_GET(flow_table_nic_cap, hcattr,
801                         ft_field_support_2_nic_receive
802                                 .outer_ipv4_checksum_ok) &&
803                MLX5_GET(flow_table_nic_cap, hcattr,
804                         ft_field_support_2_nic_receive.outer_l4_checksum_ok);
805 }
806
807 /**
808  * Query HCA attributes.
809  * Using those attributes we can check on run time if the device
810  * is having the required capabilities.
811  *
812  * @param[in] ctx
813  *   Context returned from mlx5 open_device() glue function.
814  * @param[out] attr
815  *   Attributes device values.
816  *
817  * @return
818  *   0 on success, a negative value otherwise.
819  */
820 int
821 mlx5_devx_cmd_query_hca_attr(void *ctx,
822                              struct mlx5_hca_attr *attr)
823 {
824         uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0};
825         uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0};
826         bool hca_cap_2_sup;
827         uint64_t general_obj_types_supported = 0;
828         void *hcattr;
829         int rc, i;
830
831         hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
832                         MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE |
833                         MLX5_HCA_CAP_OPMOD_GET_CUR);
834         if (!hcattr)
835                 return rc;
836         hca_cap_2_sup = MLX5_GET(cmd_hca_cap, hcattr, hca_cap_2);
837         attr->max_wqe_sz_sq = MLX5_GET(cmd_hca_cap, hcattr, max_wqe_sz_sq);
838         attr->flow_counter_bulk_alloc_bitmap =
839                         MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc);
840         attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr,
841                                             flow_counters_dump);
842         attr->log_max_rmp = MLX5_GET(cmd_hca_cap, hcattr, log_max_rmp);
843         attr->mem_rq_rmp = MLX5_GET(cmd_hca_cap, hcattr, mem_rq_rmp);
844         attr->log_max_rqt_size = MLX5_GET(cmd_hca_cap, hcattr,
845                                           log_max_rqt_size);
846         attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager);
847         attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin);
848         attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr,
849                                                 log_max_hairpin_queues);
850         attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr,
851                                                     log_max_hairpin_wq_data_sz);
852         attr->log_max_hairpin_num_packets = MLX5_GET
853                 (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz);
854         attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id);
855         attr->relaxed_ordering_write = MLX5_GET(cmd_hca_cap, hcattr,
856                                                 relaxed_ordering_write);
857         attr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr,
858                                                relaxed_ordering_read);
859         attr->access_register_user = MLX5_GET(cmd_hca_cap, hcattr,
860                                               access_register_user);
861         attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr,
862                                           eth_net_offloads);
863         attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt);
864         attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr,
865                                                flex_parser_protocols);
866         attr->max_geneve_tlv_options = MLX5_GET(cmd_hca_cap, hcattr,
867                         max_geneve_tlv_options);
868         attr->max_geneve_tlv_option_data_len = MLX5_GET(cmd_hca_cap, hcattr,
869                         max_geneve_tlv_option_data_len);
870         attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos);
871         attr->qos.flow_meter_aso_sup = !!(MLX5_GET64(cmd_hca_cap, hcattr,
872                                          general_obj_types) &
873                               MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO);
874         attr->vdpa.valid = !!(MLX5_GET64(cmd_hca_cap, hcattr,
875                                          general_obj_types) &
876                               MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q);
877         attr->vdpa.queue_counters_valid = !!(MLX5_GET64(cmd_hca_cap, hcattr,
878                                                         general_obj_types) &
879                                   MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS);
880         attr->parse_graph_flex_node = !!(MLX5_GET64(cmd_hca_cap, hcattr,
881                                          general_obj_types) &
882                               MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE);
883         attr->wqe_index_ignore = MLX5_GET(cmd_hca_cap, hcattr,
884                                           wqe_index_ignore_cap);
885         attr->cross_channel = MLX5_GET(cmd_hca_cap, hcattr, cd);
886         attr->non_wire_sq = MLX5_GET(cmd_hca_cap, hcattr, non_wire_sq);
887         attr->log_max_static_sq_wq = MLX5_GET(cmd_hca_cap, hcattr,
888                                               log_max_static_sq_wq);
889         attr->num_lag_ports = MLX5_GET(cmd_hca_cap, hcattr, num_lag_ports);
890         attr->dev_freq_khz = MLX5_GET(cmd_hca_cap, hcattr,
891                                       device_frequency_khz);
892         attr->scatter_fcs_w_decap_disable =
893                 MLX5_GET(cmd_hca_cap, hcattr, scatter_fcs_w_decap_disable);
894         attr->roce = MLX5_GET(cmd_hca_cap, hcattr, roce);
895         attr->rq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, rq_ts_format);
896         attr->sq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, sq_ts_format);
897         attr->steering_format_version =
898                 MLX5_GET(cmd_hca_cap, hcattr, steering_format_version);
899         attr->regexp_params = MLX5_GET(cmd_hca_cap, hcattr, regexp_params);
900         attr->regexp_version = MLX5_GET(cmd_hca_cap, hcattr, regexp_version);
901         attr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr,
902                                                regexp_num_of_engines);
903         /* Read the general_obj_types bitmap and extract the relevant bits. */
904         general_obj_types_supported = MLX5_GET64(cmd_hca_cap, hcattr,
905                                                  general_obj_types);
906         attr->vdpa.valid = !!(general_obj_types_supported &
907                               MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q);
908         attr->vdpa.queue_counters_valid =
909                         !!(general_obj_types_supported &
910                            MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS);
911         attr->parse_graph_flex_node =
912                         !!(general_obj_types_supported &
913                            MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE);
914         attr->flow_hit_aso = !!(general_obj_types_supported &
915                                 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO);
916         attr->geneve_tlv_opt = !!(general_obj_types_supported &
917                                   MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT);
918         attr->dek = !!(general_obj_types_supported &
919                        MLX5_GENERAL_OBJ_TYPES_CAP_DEK);
920         attr->import_kek = !!(general_obj_types_supported &
921                               MLX5_GENERAL_OBJ_TYPES_CAP_IMPORT_KEK);
922         attr->credential = !!(general_obj_types_supported &
923                               MLX5_GENERAL_OBJ_TYPES_CAP_CREDENTIAL);
924         attr->crypto_login = !!(general_obj_types_supported &
925                                 MLX5_GENERAL_OBJ_TYPES_CAP_CRYPTO_LOGIN);
926         /* Add reading of other GENERAL_OBJ_TYPES_CAP bits above this line. */
927         attr->log_max_cq = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq);
928         attr->log_max_qp = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp);
929         attr->log_max_cq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq_sz);
930         attr->log_max_qp_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp_sz);
931         attr->log_max_mrw_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_mrw_sz);
932         attr->log_max_pd = MLX5_GET(cmd_hca_cap, hcattr, log_max_pd);
933         attr->log_max_srq = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq);
934         attr->log_max_srq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq_sz);
935         attr->reg_c_preserve =
936                 MLX5_GET(cmd_hca_cap, hcattr, reg_c_preserve);
937         attr->mmo_regex_qp_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_qp);
938         attr->mmo_regex_sq_en = MLX5_GET(cmd_hca_cap, hcattr, regexp_mmo_sq);
939         attr->mmo_dma_sq_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_sq);
940         attr->mmo_compress_sq_en = MLX5_GET(cmd_hca_cap, hcattr,
941                         compress_mmo_sq);
942         attr->mmo_decompress_sq_en = MLX5_GET(cmd_hca_cap, hcattr,
943                         decompress_mmo_sq);
944         attr->mmo_dma_qp_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_qp);
945         attr->mmo_compress_qp_en = MLX5_GET(cmd_hca_cap, hcattr,
946                         compress_mmo_qp);
947         attr->mmo_decompress_qp_en = MLX5_GET(cmd_hca_cap, hcattr,
948                         decompress_mmo_qp);
949         attr->compress_min_block_size = MLX5_GET(cmd_hca_cap, hcattr,
950                                                  compress_min_block_size);
951         attr->log_max_mmo_dma = MLX5_GET(cmd_hca_cap, hcattr, log_dma_mmo_size);
952         attr->log_max_mmo_compress = MLX5_GET(cmd_hca_cap, hcattr,
953                                               log_compress_mmo_size);
954         attr->log_max_mmo_decompress = MLX5_GET(cmd_hca_cap, hcattr,
955                                                 log_decompress_mmo_size);
956         attr->cqe_compression = MLX5_GET(cmd_hca_cap, hcattr, cqe_compression);
957         attr->mini_cqe_resp_flow_tag = MLX5_GET(cmd_hca_cap, hcattr,
958                                                 mini_cqe_resp_flow_tag);
959         attr->mini_cqe_resp_l3_l4_tag = MLX5_GET(cmd_hca_cap, hcattr,
960                                                  mini_cqe_resp_l3_l4_tag);
961         attr->umr_indirect_mkey_disabled =
962                 MLX5_GET(cmd_hca_cap, hcattr, umr_indirect_mkey_disabled);
963         attr->umr_modify_entity_size_disabled =
964                 MLX5_GET(cmd_hca_cap, hcattr, umr_modify_entity_size_disabled);
965         attr->wait_on_time = MLX5_GET(cmd_hca_cap, hcattr, wait_on_time);
966         attr->crypto = MLX5_GET(cmd_hca_cap, hcattr, crypto);
967         attr->ct_offload = !!(MLX5_GET64(cmd_hca_cap, hcattr,
968                                          general_obj_types) &
969                               MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD);
970         attr->rq_delay_drop = MLX5_GET(cmd_hca_cap, hcattr, rq_delay_drop);
971         if (attr->crypto) {
972                 attr->aes_xts = MLX5_GET(cmd_hca_cap, hcattr, aes_xts);
973                 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
974                                 MLX5_GET_HCA_CAP_OP_MOD_CRYPTO |
975                                 MLX5_HCA_CAP_OPMOD_GET_CUR);
976                 if (!hcattr)
977                         return -1;
978                 attr->crypto_wrapped_import_method = !!(MLX5_GET(crypto_caps,
979                                                 hcattr, wrapped_import_method)
980                                                 & 1 << 2);
981         }
982         if (hca_cap_2_sup) {
983                 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
984                                 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 |
985                                 MLX5_HCA_CAP_OPMOD_GET_CUR);
986                 if (!hcattr) {
987                         DRV_LOG(DEBUG,
988                                 "Failed to query DevX HCA capabilities 2.");
989                         return rc;
990                 }
991                 attr->log_min_stride_wqe_sz = MLX5_GET(cmd_hca_cap_2, hcattr,
992                                                        log_min_stride_wqe_sz);
993         }
994         if (attr->log_min_stride_wqe_sz == 0)
995                 attr->log_min_stride_wqe_sz = MLX5_MPRQ_LOG_MIN_STRIDE_WQE_SIZE;
996         if (attr->qos.sup) {
997                 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
998                                 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP |
999                                 MLX5_HCA_CAP_OPMOD_GET_CUR);
1000                 if (!hcattr) {
1001                         DRV_LOG(DEBUG, "Failed to query devx QOS capabilities");
1002                         return rc;
1003                 }
1004                 attr->qos.flow_meter_old =
1005                                 MLX5_GET(qos_cap, hcattr, flow_meter_old);
1006                 attr->qos.log_max_flow_meter =
1007                                 MLX5_GET(qos_cap, hcattr, log_max_flow_meter);
1008                 attr->qos.flow_meter_reg_c_ids =
1009                                 MLX5_GET(qos_cap, hcattr, flow_meter_reg_id);
1010                 attr->qos.flow_meter =
1011                                 MLX5_GET(qos_cap, hcattr, flow_meter);
1012                 attr->qos.packet_pacing =
1013                                 MLX5_GET(qos_cap, hcattr, packet_pacing);
1014                 attr->qos.wqe_rate_pp =
1015                                 MLX5_GET(qos_cap, hcattr, wqe_rate_pp);
1016                 if (attr->qos.flow_meter_aso_sup) {
1017                         attr->qos.log_meter_aso_granularity =
1018                                 MLX5_GET(qos_cap, hcattr,
1019                                         log_meter_aso_granularity);
1020                         attr->qos.log_meter_aso_max_alloc =
1021                                 MLX5_GET(qos_cap, hcattr,
1022                                         log_meter_aso_max_alloc);
1023                         attr->qos.log_max_num_meter_aso =
1024                                 MLX5_GET(qos_cap, hcattr,
1025                                         log_max_num_meter_aso);
1026                 }
1027         }
1028         /*
1029          * Flex item support needs max_num_prog_sample_field
1030          * from the Capabilities 2 table for PARSE_GRAPH_NODE
1031          */
1032         if (attr->parse_graph_flex_node) {
1033                 rc = mlx5_devx_cmd_query_hca_parse_graph_node_cap
1034                         (ctx, &attr->flex);
1035                 if (rc)
1036                         return -1;
1037         }
1038         if (attr->vdpa.valid)
1039                 mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa);
1040         if (!attr->eth_net_offloads)
1041                 return 0;
1042         /* Query Flow Sampler Capability From FLow Table Properties Layout. */
1043         hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1044                         MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE |
1045                         MLX5_HCA_CAP_OPMOD_GET_CUR);
1046         if (!hcattr) {
1047                 attr->log_max_ft_sampler_num = 0;
1048                 return rc;
1049         }
1050         attr->log_max_ft_sampler_num = MLX5_GET
1051                 (flow_table_nic_cap, hcattr,
1052                  flow_table_properties_nic_receive.log_max_ft_sampler_num);
1053         attr->flow.tunnel_header_0_1 = MLX5_GET
1054                 (flow_table_nic_cap, hcattr,
1055                  ft_field_support_2_nic_receive.tunnel_header_0_1);
1056         attr->flow.tunnel_header_2_3 = MLX5_GET
1057                 (flow_table_nic_cap, hcattr,
1058                  ft_field_support_2_nic_receive.tunnel_header_2_3);
1059         attr->pkt_integrity_match = mlx5_devx_query_pkt_integrity_match(hcattr);
1060         attr->inner_ipv4_ihl = MLX5_GET
1061                 (flow_table_nic_cap, hcattr,
1062                  ft_field_support_2_nic_receive.inner_ipv4_ihl);
1063         attr->outer_ipv4_ihl = MLX5_GET
1064                 (flow_table_nic_cap, hcattr,
1065                  ft_field_support_2_nic_receive.outer_ipv4_ihl);
1066         /* Query HCA offloads for Ethernet protocol. */
1067         hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1068                         MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS |
1069                         MLX5_HCA_CAP_OPMOD_GET_CUR);
1070         if (!hcattr) {
1071                 attr->eth_net_offloads = 0;
1072                 return rc;
1073         }
1074         attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps,
1075                                          hcattr, wqe_vlan_insert);
1076         attr->csum_cap = MLX5_GET(per_protocol_networking_offload_caps,
1077                                          hcattr, csum_cap);
1078         attr->vlan_cap = MLX5_GET(per_protocol_networking_offload_caps,
1079                                          hcattr, vlan_cap);
1080         attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr,
1081                                  lro_cap);
1082         attr->max_lso_cap = MLX5_GET(per_protocol_networking_offload_caps,
1083                                  hcattr, max_lso_cap);
1084         attr->scatter_fcs = MLX5_GET(per_protocol_networking_offload_caps,
1085                                  hcattr, scatter_fcs);
1086         attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps,
1087                                         hcattr, tunnel_lro_gre);
1088         attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps,
1089                                           hcattr, tunnel_lro_vxlan);
1090         attr->swp = MLX5_GET(per_protocol_networking_offload_caps,
1091                                           hcattr, swp);
1092         attr->tunnel_stateless_gre =
1093                                 MLX5_GET(per_protocol_networking_offload_caps,
1094                                           hcattr, tunnel_stateless_gre);
1095         attr->tunnel_stateless_vxlan =
1096                                 MLX5_GET(per_protocol_networking_offload_caps,
1097                                           hcattr, tunnel_stateless_vxlan);
1098         attr->swp_csum = MLX5_GET(per_protocol_networking_offload_caps,
1099                                           hcattr, swp_csum);
1100         attr->swp_lso = MLX5_GET(per_protocol_networking_offload_caps,
1101                                           hcattr, swp_lso);
1102         attr->lro_max_msg_sz_mode = MLX5_GET
1103                                         (per_protocol_networking_offload_caps,
1104                                          hcattr, lro_max_msg_sz_mode);
1105         for (i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) {
1106                 attr->lro_timer_supported_periods[i] =
1107                         MLX5_GET(per_protocol_networking_offload_caps, hcattr,
1108                                  lro_timer_supported_periods[i]);
1109         }
1110         attr->lro_min_mss_size = MLX5_GET(per_protocol_networking_offload_caps,
1111                                           hcattr, lro_min_mss_size);
1112         attr->tunnel_stateless_geneve_rx =
1113                             MLX5_GET(per_protocol_networking_offload_caps,
1114                                      hcattr, tunnel_stateless_geneve_rx);
1115         attr->geneve_max_opt_len =
1116                     MLX5_GET(per_protocol_networking_offload_caps,
1117                              hcattr, max_geneve_opt_len);
1118         attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps,
1119                                          hcattr, wqe_inline_mode);
1120         attr->tunnel_stateless_gtp = MLX5_GET
1121                                         (per_protocol_networking_offload_caps,
1122                                          hcattr, tunnel_stateless_gtp);
1123         attr->rss_ind_tbl_cap = MLX5_GET
1124                                         (per_protocol_networking_offload_caps,
1125                                          hcattr, rss_ind_tbl_cap);
1126         /* Query HCA attribute for ROCE. */
1127         if (attr->roce) {
1128                 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1129                                 MLX5_GET_HCA_CAP_OP_MOD_ROCE |
1130                                 MLX5_HCA_CAP_OPMOD_GET_CUR);
1131                 if (!hcattr) {
1132                         DRV_LOG(DEBUG,
1133                                 "Failed to query devx HCA ROCE capabilities");
1134                         return rc;
1135                 }
1136                 attr->qp_ts_format = MLX5_GET(roce_caps, hcattr, qp_ts_format);
1137         }
1138         if (attr->eth_virt &&
1139             attr->wqe_inline_mode == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT) {
1140                 rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr);
1141                 if (rc) {
1142                         attr->eth_virt = 0;
1143                         goto error;
1144                 }
1145         }
1146         if (attr->eswitch_manager) {
1147                 hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
1148                                 MLX5_SET_HCA_CAP_OP_MOD_ESW |
1149                                 MLX5_HCA_CAP_OPMOD_GET_CUR);
1150                 if (!hcattr)
1151                         return rc;
1152                 attr->esw_mgr_vport_id_valid =
1153                         MLX5_GET(esw_cap, hcattr,
1154                                  esw_manager_vport_number_valid);
1155                 attr->esw_mgr_vport_id =
1156                         MLX5_GET(esw_cap, hcattr, esw_manager_vport_number);
1157         }
1158         return 0;
1159 error:
1160         rc = (rc > 0) ? -rc : rc;
1161         return rc;
1162 }
1163
1164 /**
1165  * Query TIS transport domain from QP verbs object using DevX API.
1166  *
1167  * @param[in] qp
1168  *   Pointer to verbs QP returned by ibv_create_qp .
1169  * @param[in] tis_num
1170  *   TIS number of TIS to query.
1171  * @param[out] tis_td
1172  *   Pointer to TIS transport domain variable, to be set by the routine.
1173  *
1174  * @return
1175  *   0 on success, a negative value otherwise.
1176  */
1177 int
1178 mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num,
1179                               uint32_t *tis_td)
1180 {
1181 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
1182         uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0};
1183         uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0};
1184         int rc;
1185         void *tis_ctx;
1186
1187         MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS);
1188         MLX5_SET(query_tis_in, in, tisn, tis_num);
1189         rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out));
1190         if (rc) {
1191                 DRV_LOG(ERR, "Failed to query QP using DevX");
1192                 return -rc;
1193         };
1194         tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context);
1195         *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain);
1196         return 0;
1197 #else
1198         (void)qp;
1199         (void)tis_num;
1200         (void)tis_td;
1201         return -ENOTSUP;
1202 #endif
1203 }
1204
1205 /**
1206  * Fill WQ data for DevX API command.
1207  * Utility function for use when creating DevX objects containing a WQ.
1208  *
1209  * @param[in] wq_ctx
1210  *   Pointer to WQ context to fill with data.
1211  * @param [in] wq_attr
1212  *   Pointer to WQ attributes structure to fill in WQ context.
1213  */
1214 static void
1215 devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr)
1216 {
1217         MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type);
1218         MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature);
1219         MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode);
1220         MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave);
1221         MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge);
1222         MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size);
1223         MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset);
1224         MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm);
1225         MLX5_SET(wq, wq_ctx, pd, wq_attr->pd);
1226         MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page);
1227         MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr);
1228         MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter);
1229         MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter);
1230         MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride);
1231         if (wq_attr->log_wq_pg_sz > MLX5_ADAPTER_PAGE_SHIFT)
1232                 MLX5_SET(wq, wq_ctx, log_wq_pg_sz,
1233                          wq_attr->log_wq_pg_sz - MLX5_ADAPTER_PAGE_SHIFT);
1234         MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz);
1235         MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid);
1236         MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid);
1237         MLX5_SET(wq, wq_ctx, log_hairpin_num_packets,
1238                  wq_attr->log_hairpin_num_packets);
1239         MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz);
1240         MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides,
1241                  wq_attr->single_wqe_log_num_of_strides);
1242         MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en);
1243         MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes,
1244                  wq_attr->single_stride_log_num_of_bytes);
1245         MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id);
1246         MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id);
1247         MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset);
1248 }
1249
1250 /**
1251  * Create RQ using DevX API.
1252  *
1253  * @param[in] ctx
1254  *   Context returned from mlx5 open_device() glue function.
1255  * @param [in] rq_attr
1256  *   Pointer to create RQ attributes structure.
1257  * @param [in] socket
1258  *   CPU socket ID for allocations.
1259  *
1260  * @return
1261  *   The DevX object created, NULL otherwise and rte_errno is set.
1262  */
1263 struct mlx5_devx_obj *
1264 mlx5_devx_cmd_create_rq(void *ctx,
1265                         struct mlx5_devx_create_rq_attr *rq_attr,
1266                         int socket)
1267 {
1268         uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0};
1269         uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0};
1270         void *rq_ctx, *wq_ctx;
1271         struct mlx5_devx_wq_attr *wq_attr;
1272         struct mlx5_devx_obj *rq = NULL;
1273
1274         rq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rq), 0, socket);
1275         if (!rq) {
1276                 DRV_LOG(ERR, "Failed to allocate RQ data");
1277                 rte_errno = ENOMEM;
1278                 return NULL;
1279         }
1280         MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ);
1281         rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx);
1282         MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky);
1283         MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en);
1284         MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);
1285         MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);
1286         MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type);
1287         MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
1288         MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en);
1289         MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin);
1290         MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index);
1291         MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn);
1292         MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
1293         MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn);
1294         MLX5_SET(sqc, rq_ctx, ts_format, rq_attr->ts_format);
1295         wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);
1296         wq_attr = &rq_attr->wq_attr;
1297         devx_cmd_fill_wq_data(wq_ctx, wq_attr);
1298         rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1299                                                   out, sizeof(out));
1300         if (!rq->obj) {
1301                 DRV_LOG(ERR, "Failed to create RQ using DevX");
1302                 rte_errno = errno;
1303                 mlx5_free(rq);
1304                 return NULL;
1305         }
1306         rq->id = MLX5_GET(create_rq_out, out, rqn);
1307         return rq;
1308 }
1309
1310 /**
1311  * Modify RQ using DevX API.
1312  *
1313  * @param[in] rq
1314  *   Pointer to RQ object structure.
1315  * @param [in] rq_attr
1316  *   Pointer to modify RQ attributes structure.
1317  *
1318  * @return
1319  *   0 on success, a negative errno value otherwise and rte_errno is set.
1320  */
1321 int
1322 mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,
1323                         struct mlx5_devx_modify_rq_attr *rq_attr)
1324 {
1325         uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0};
1326         uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0};
1327         void *rq_ctx, *wq_ctx;
1328         int ret;
1329
1330         MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ);
1331         MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state);
1332         MLX5_SET(modify_rq_in, in, rqn, rq->id);
1333         MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask);
1334         rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1335         MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
1336         if (rq_attr->modify_bitmask &
1337                         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS)
1338                 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);
1339         if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD)
1340                 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);
1341         if (rq_attr->modify_bitmask &
1342                         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID)
1343                 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
1344         MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq);
1345         MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca);
1346         if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) {
1347                 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);
1348                 MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm);
1349         }
1350         ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in),
1351                                          out, sizeof(out));
1352         if (ret) {
1353                 DRV_LOG(ERR, "Failed to modify RQ using DevX");
1354                 rte_errno = errno;
1355                 return -errno;
1356         }
1357         return ret;
1358 }
1359
1360 /**
1361  * Create RMP using DevX API.
1362  *
1363  * @param[in] ctx
1364  *   Context returned from mlx5 open_device() glue function.
1365  * @param [in] rmp_attr
1366  *   Pointer to create RMP attributes structure.
1367  * @param [in] socket
1368  *   CPU socket ID for allocations.
1369  *
1370  * @return
1371  *   The DevX object created, NULL otherwise and rte_errno is set.
1372  */
1373 struct mlx5_devx_obj *
1374 mlx5_devx_cmd_create_rmp(void *ctx,
1375                          struct mlx5_devx_create_rmp_attr *rmp_attr,
1376                          int socket)
1377 {
1378         uint32_t in[MLX5_ST_SZ_DW(create_rmp_in)] = {0};
1379         uint32_t out[MLX5_ST_SZ_DW(create_rmp_out)] = {0};
1380         void *rmp_ctx, *wq_ctx;
1381         struct mlx5_devx_wq_attr *wq_attr;
1382         struct mlx5_devx_obj *rmp = NULL;
1383
1384         rmp = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rmp), 0, socket);
1385         if (!rmp) {
1386                 DRV_LOG(ERR, "Failed to allocate RMP data");
1387                 rte_errno = ENOMEM;
1388                 return NULL;
1389         }
1390         MLX5_SET(create_rmp_in, in, opcode, MLX5_CMD_OP_CREATE_RMP);
1391         rmp_ctx = MLX5_ADDR_OF(create_rmp_in, in, ctx);
1392         MLX5_SET(rmpc, rmp_ctx, state, rmp_attr->state);
1393         MLX5_SET(rmpc, rmp_ctx, basic_cyclic_rcv_wqe,
1394                  rmp_attr->basic_cyclic_rcv_wqe);
1395         wq_ctx = MLX5_ADDR_OF(rmpc, rmp_ctx, wq);
1396         wq_attr = &rmp_attr->wq_attr;
1397         devx_cmd_fill_wq_data(wq_ctx, wq_attr);
1398         rmp->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
1399                                               sizeof(out));
1400         if (!rmp->obj) {
1401                 DRV_LOG(ERR, "Failed to create RMP using DevX");
1402                 rte_errno = errno;
1403                 mlx5_free(rmp);
1404                 return NULL;
1405         }
1406         rmp->id = MLX5_GET(create_rmp_out, out, rmpn);
1407         return rmp;
1408 }
1409
1410 /*
1411  * Create TIR using DevX API.
1412  *
1413  * @param[in] ctx
1414  *  Context returned from mlx5 open_device() glue function.
1415  * @param [in] tir_attr
1416  *   Pointer to TIR attributes structure.
1417  *
1418  * @return
1419  *   The DevX object created, NULL otherwise and rte_errno is set.
1420  */
1421 struct mlx5_devx_obj *
1422 mlx5_devx_cmd_create_tir(void *ctx,
1423                          struct mlx5_devx_tir_attr *tir_attr)
1424 {
1425         uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
1426         uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0};
1427         void *tir_ctx, *outer, *inner, *rss_key;
1428         struct mlx5_devx_obj *tir = NULL;
1429
1430         tir = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tir), 0, SOCKET_ID_ANY);
1431         if (!tir) {
1432                 DRV_LOG(ERR, "Failed to allocate TIR data");
1433                 rte_errno = ENOMEM;
1434                 return NULL;
1435         }
1436         MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR);
1437         tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx);
1438         MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type);
1439         MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs,
1440                  tir_attr->lro_timeout_period_usecs);
1441         MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask);
1442         MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz);
1443         MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn);
1444         MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric);
1445         MLX5_SET(tirc, tir_ctx, tunneled_offload_en,
1446                  tir_attr->tunneled_offload_en);
1447         MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table);
1448         MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn);
1449         MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block);
1450         MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain);
1451         rss_key = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_toeplitz_key);
1452         memcpy(rss_key, tir_attr->rx_hash_toeplitz_key, MLX5_RSS_HASH_KEY_LEN);
1453         outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer);
1454         MLX5_SET(rx_hash_field_select, outer, l3_prot_type,
1455                  tir_attr->rx_hash_field_selector_outer.l3_prot_type);
1456         MLX5_SET(rx_hash_field_select, outer, l4_prot_type,
1457                  tir_attr->rx_hash_field_selector_outer.l4_prot_type);
1458         MLX5_SET(rx_hash_field_select, outer, selected_fields,
1459                  tir_attr->rx_hash_field_selector_outer.selected_fields);
1460         inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner);
1461         MLX5_SET(rx_hash_field_select, inner, l3_prot_type,
1462                  tir_attr->rx_hash_field_selector_inner.l3_prot_type);
1463         MLX5_SET(rx_hash_field_select, inner, l4_prot_type,
1464                  tir_attr->rx_hash_field_selector_inner.l4_prot_type);
1465         MLX5_SET(rx_hash_field_select, inner, selected_fields,
1466                  tir_attr->rx_hash_field_selector_inner.selected_fields);
1467         tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1468                                                    out, sizeof(out));
1469         if (!tir->obj) {
1470                 DRV_LOG(ERR, "Failed to create TIR using DevX");
1471                 rte_errno = errno;
1472                 mlx5_free(tir);
1473                 return NULL;
1474         }
1475         tir->id = MLX5_GET(create_tir_out, out, tirn);
1476         return tir;
1477 }
1478
1479 /**
1480  * Modify TIR using DevX API.
1481  *
1482  * @param[in] tir
1483  *   Pointer to TIR DevX object structure.
1484  * @param [in] modify_tir_attr
1485  *   Pointer to TIR modification attributes structure.
1486  *
1487  * @return
1488  *   0 on success, a negative errno value otherwise and rte_errno is set.
1489  */
1490 int
1491 mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir,
1492                          struct mlx5_devx_modify_tir_attr *modify_tir_attr)
1493 {
1494         struct mlx5_devx_tir_attr *tir_attr = &modify_tir_attr->tir;
1495         uint32_t in[MLX5_ST_SZ_DW(modify_tir_in)] = {0};
1496         uint32_t out[MLX5_ST_SZ_DW(modify_tir_out)] = {0};
1497         void *tir_ctx;
1498         int ret;
1499
1500         MLX5_SET(modify_tir_in, in, opcode, MLX5_CMD_OP_MODIFY_TIR);
1501         MLX5_SET(modify_tir_in, in, tirn, modify_tir_attr->tirn);
1502         MLX5_SET64(modify_tir_in, in, modify_bitmask,
1503                    modify_tir_attr->modify_bitmask);
1504         tir_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1505         if (modify_tir_attr->modify_bitmask &
1506                         MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO) {
1507                 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs,
1508                          tir_attr->lro_timeout_period_usecs);
1509                 MLX5_SET(tirc, tir_ctx, lro_enable_mask,
1510                          tir_attr->lro_enable_mask);
1511                 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz,
1512                          tir_attr->lro_max_msg_sz);
1513         }
1514         if (modify_tir_attr->modify_bitmask &
1515                         MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE)
1516                 MLX5_SET(tirc, tir_ctx, indirect_table,
1517                          tir_attr->indirect_table);
1518         if (modify_tir_attr->modify_bitmask &
1519                         MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH) {
1520                 int i;
1521                 void *outer, *inner;
1522
1523                 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric,
1524                          tir_attr->rx_hash_symmetric);
1525                 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn);
1526                 for (i = 0; i < 10; i++) {
1527                         MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i],
1528                                  tir_attr->rx_hash_toeplitz_key[i]);
1529                 }
1530                 outer = MLX5_ADDR_OF(tirc, tir_ctx,
1531                                      rx_hash_field_selector_outer);
1532                 MLX5_SET(rx_hash_field_select, outer, l3_prot_type,
1533                          tir_attr->rx_hash_field_selector_outer.l3_prot_type);
1534                 MLX5_SET(rx_hash_field_select, outer, l4_prot_type,
1535                          tir_attr->rx_hash_field_selector_outer.l4_prot_type);
1536                 MLX5_SET
1537                 (rx_hash_field_select, outer, selected_fields,
1538                  tir_attr->rx_hash_field_selector_outer.selected_fields);
1539                 inner = MLX5_ADDR_OF(tirc, tir_ctx,
1540                                      rx_hash_field_selector_inner);
1541                 MLX5_SET(rx_hash_field_select, inner, l3_prot_type,
1542                          tir_attr->rx_hash_field_selector_inner.l3_prot_type);
1543                 MLX5_SET(rx_hash_field_select, inner, l4_prot_type,
1544                          tir_attr->rx_hash_field_selector_inner.l4_prot_type);
1545                 MLX5_SET
1546                 (rx_hash_field_select, inner, selected_fields,
1547                  tir_attr->rx_hash_field_selector_inner.selected_fields);
1548         }
1549         if (modify_tir_attr->modify_bitmask &
1550             MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN) {
1551                 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block);
1552         }
1553         ret = mlx5_glue->devx_obj_modify(tir->obj, in, sizeof(in),
1554                                          out, sizeof(out));
1555         if (ret) {
1556                 DRV_LOG(ERR, "Failed to modify TIR using DevX");
1557                 rte_errno = errno;
1558                 return -errno;
1559         }
1560         return ret;
1561 }
1562
1563 /**
1564  * Create RQT using DevX API.
1565  *
1566  * @param[in] ctx
1567  *   Context returned from mlx5 open_device() glue function.
1568  * @param [in] rqt_attr
1569  *   Pointer to RQT attributes structure.
1570  *
1571  * @return
1572  *   The DevX object created, NULL otherwise and rte_errno is set.
1573  */
1574 struct mlx5_devx_obj *
1575 mlx5_devx_cmd_create_rqt(void *ctx,
1576                          struct mlx5_devx_rqt_attr *rqt_attr)
1577 {
1578         uint32_t *in = NULL;
1579         uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) +
1580                          rqt_attr->rqt_actual_size * sizeof(uint32_t);
1581         uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0};
1582         void *rqt_ctx;
1583         struct mlx5_devx_obj *rqt = NULL;
1584         int i;
1585
1586         in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY);
1587         if (!in) {
1588                 DRV_LOG(ERR, "Failed to allocate RQT IN data");
1589                 rte_errno = ENOMEM;
1590                 return NULL;
1591         }
1592         rqt = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt), 0, SOCKET_ID_ANY);
1593         if (!rqt) {
1594                 DRV_LOG(ERR, "Failed to allocate RQT data");
1595                 rte_errno = ENOMEM;
1596                 mlx5_free(in);
1597                 return NULL;
1598         }
1599         MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
1600         rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1601         MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type);
1602         MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size);
1603         MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size);
1604         for (i = 0; i < rqt_attr->rqt_actual_size; i++)
1605                 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]);
1606         rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out));
1607         mlx5_free(in);
1608         if (!rqt->obj) {
1609                 DRV_LOG(ERR, "Failed to create RQT using DevX");
1610                 rte_errno = errno;
1611                 mlx5_free(rqt);
1612                 return NULL;
1613         }
1614         rqt->id = MLX5_GET(create_rqt_out, out, rqtn);
1615         return rqt;
1616 }
1617
1618 /**
1619  * Modify RQT using DevX API.
1620  *
1621  * @param[in] rqt
1622  *   Pointer to RQT DevX object structure.
1623  * @param [in] rqt_attr
1624  *   Pointer to RQT attributes structure.
1625  *
1626  * @return
1627  *   0 on success, a negative errno value otherwise and rte_errno is set.
1628  */
1629 int
1630 mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt,
1631                          struct mlx5_devx_rqt_attr *rqt_attr)
1632 {
1633         uint32_t inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) +
1634                          rqt_attr->rqt_actual_size * sizeof(uint32_t);
1635         uint32_t out[MLX5_ST_SZ_DW(modify_rqt_out)] = {0};
1636         uint32_t *in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY);
1637         void *rqt_ctx;
1638         int i;
1639         int ret;
1640
1641         if (!in) {
1642                 DRV_LOG(ERR, "Failed to allocate RQT modify IN data.");
1643                 rte_errno = ENOMEM;
1644                 return -ENOMEM;
1645         }
1646         MLX5_SET(modify_rqt_in, in, opcode, MLX5_CMD_OP_MODIFY_RQT);
1647         MLX5_SET(modify_rqt_in, in, rqtn, rqt->id);
1648         MLX5_SET64(modify_rqt_in, in, modify_bitmask, 0x1);
1649         rqt_ctx = MLX5_ADDR_OF(modify_rqt_in, in, rqt_context);
1650         MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type);
1651         MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size);
1652         MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size);
1653         for (i = 0; i < rqt_attr->rqt_actual_size; i++)
1654                 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]);
1655         ret = mlx5_glue->devx_obj_modify(rqt->obj, in, inlen, out, sizeof(out));
1656         mlx5_free(in);
1657         if (ret) {
1658                 DRV_LOG(ERR, "Failed to modify RQT using DevX.");
1659                 rte_errno = errno;
1660                 return -rte_errno;
1661         }
1662         return ret;
1663 }
1664
1665 /**
1666  * Create SQ using DevX API.
1667  *
1668  * @param[in] ctx
1669  *   Context returned from mlx5 open_device() glue function.
1670  * @param [in] sq_attr
1671  *   Pointer to SQ attributes structure.
1672  * @param [in] socket
1673  *   CPU socket ID for allocations.
1674  *
1675  * @return
1676  *   The DevX object created, NULL otherwise and rte_errno is set.
1677  **/
1678 struct mlx5_devx_obj *
1679 mlx5_devx_cmd_create_sq(void *ctx,
1680                         struct mlx5_devx_create_sq_attr *sq_attr)
1681 {
1682         uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0};
1683         uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0};
1684         void *sq_ctx;
1685         void *wq_ctx;
1686         struct mlx5_devx_wq_attr *wq_attr;
1687         struct mlx5_devx_obj *sq = NULL;
1688
1689         sq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sq), 0, SOCKET_ID_ANY);
1690         if (!sq) {
1691                 DRV_LOG(ERR, "Failed to allocate SQ data");
1692                 rte_errno = ENOMEM;
1693                 return NULL;
1694         }
1695         MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ);
1696         sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx);
1697         MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky);
1698         MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master);
1699         MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre);
1700         MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en);
1701         MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe,
1702                  sq_attr->allow_multi_pkt_send_wqe);
1703         MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode,
1704                  sq_attr->min_wqe_inline_mode);
1705         MLX5_SET(sqc, sq_ctx, state, sq_attr->state);
1706         MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr);
1707         MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp);
1708         MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin);
1709         MLX5_SET(sqc, sq_ctx, non_wire, sq_attr->non_wire);
1710         MLX5_SET(sqc, sq_ctx, static_sq_wq, sq_attr->static_sq_wq);
1711         MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index);
1712         MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn);
1713         MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index,
1714                  sq_attr->packet_pacing_rate_limit_index);
1715         MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz);
1716         MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num);
1717         MLX5_SET(sqc, sq_ctx, ts_format, sq_attr->ts_format);
1718         wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq);
1719         wq_attr = &sq_attr->wq_attr;
1720         devx_cmd_fill_wq_data(wq_ctx, wq_attr);
1721         sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1722                                              out, sizeof(out));
1723         if (!sq->obj) {
1724                 DRV_LOG(ERR, "Failed to create SQ using DevX");
1725                 rte_errno = errno;
1726                 mlx5_free(sq);
1727                 return NULL;
1728         }
1729         sq->id = MLX5_GET(create_sq_out, out, sqn);
1730         return sq;
1731 }
1732
1733 /**
1734  * Modify SQ using DevX API.
1735  *
1736  * @param[in] sq
1737  *   Pointer to SQ object structure.
1738  * @param [in] sq_attr
1739  *   Pointer to SQ attributes structure.
1740  *
1741  * @return
1742  *   0 on success, a negative errno value otherwise and rte_errno is set.
1743  */
1744 int
1745 mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq,
1746                         struct mlx5_devx_modify_sq_attr *sq_attr)
1747 {
1748         uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0};
1749         uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0};
1750         void *sq_ctx;
1751         int ret;
1752
1753         MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ);
1754         MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state);
1755         MLX5_SET(modify_sq_in, in, sqn, sq->id);
1756         sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1757         MLX5_SET(sqc, sq_ctx, state, sq_attr->state);
1758         MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq);
1759         MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca);
1760         ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in),
1761                                          out, sizeof(out));
1762         if (ret) {
1763                 DRV_LOG(ERR, "Failed to modify SQ using DevX");
1764                 rte_errno = errno;
1765                 return -rte_errno;
1766         }
1767         return ret;
1768 }
1769
1770 /**
1771  * Create TIS using DevX API.
1772  *
1773  * @param[in] ctx
1774  *   Context returned from mlx5 open_device() glue function.
1775  * @param [in] tis_attr
1776  *   Pointer to TIS attributes structure.
1777  *
1778  * @return
1779  *   The DevX object created, NULL otherwise and rte_errno is set.
1780  */
1781 struct mlx5_devx_obj *
1782 mlx5_devx_cmd_create_tis(void *ctx,
1783                          struct mlx5_devx_tis_attr *tis_attr)
1784 {
1785         uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
1786         uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0};
1787         struct mlx5_devx_obj *tis = NULL;
1788         void *tis_ctx;
1789
1790         tis = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tis), 0, SOCKET_ID_ANY);
1791         if (!tis) {
1792                 DRV_LOG(ERR, "Failed to allocate TIS object");
1793                 rte_errno = ENOMEM;
1794                 return NULL;
1795         }
1796         MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS);
1797         tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx);
1798         MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity,
1799                  tis_attr->strict_lag_tx_port_affinity);
1800         MLX5_SET(tisc, tis_ctx, lag_tx_port_affinity,
1801                  tis_attr->lag_tx_port_affinity);
1802         MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio);
1803         MLX5_SET(tisc, tis_ctx, transport_domain,
1804                  tis_attr->transport_domain);
1805         tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1806                                               out, sizeof(out));
1807         if (!tis->obj) {
1808                 DRV_LOG(ERR, "Failed to create TIS using DevX");
1809                 rte_errno = errno;
1810                 mlx5_free(tis);
1811                 return NULL;
1812         }
1813         tis->id = MLX5_GET(create_tis_out, out, tisn);
1814         return tis;
1815 }
1816
1817 /**
1818  * Create transport domain using DevX API.
1819  *
1820  * @param[in] ctx
1821  *   Context returned from mlx5 open_device() glue function.
1822  * @return
1823  *   The DevX object created, NULL otherwise and rte_errno is set.
1824  */
1825 struct mlx5_devx_obj *
1826 mlx5_devx_cmd_create_td(void *ctx)
1827 {
1828         uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0};
1829         uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0};
1830         struct mlx5_devx_obj *td = NULL;
1831
1832         td = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*td), 0, SOCKET_ID_ANY);
1833         if (!td) {
1834                 DRV_LOG(ERR, "Failed to allocate TD object");
1835                 rte_errno = ENOMEM;
1836                 return NULL;
1837         }
1838         MLX5_SET(alloc_transport_domain_in, in, opcode,
1839                  MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN);
1840         td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1841                                              out, sizeof(out));
1842         if (!td->obj) {
1843                 DRV_LOG(ERR, "Failed to create TIS using DevX");
1844                 rte_errno = errno;
1845                 mlx5_free(td);
1846                 return NULL;
1847         }
1848         td->id = MLX5_GET(alloc_transport_domain_out, out,
1849                            transport_domain);
1850         return td;
1851 }
1852
1853 /**
1854  * Dump all flows to file.
1855  *
1856  * @param[in] fdb_domain
1857  *   FDB domain.
1858  * @param[in] rx_domain
1859  *   RX domain.
1860  * @param[in] tx_domain
1861  *   TX domain.
1862  * @param[out] file
1863  *   Pointer to file stream.
1864  *
1865  * @return
1866  *   0 on success, a negative value otherwise.
1867  */
1868 int
1869 mlx5_devx_cmd_flow_dump(void *fdb_domain __rte_unused,
1870                         void *rx_domain __rte_unused,
1871                         void *tx_domain __rte_unused, FILE *file __rte_unused)
1872 {
1873         int ret = 0;
1874
1875 #ifdef HAVE_MLX5_DR_FLOW_DUMP
1876         if (fdb_domain) {
1877                 ret = mlx5_glue->dr_dump_domain(file, fdb_domain);
1878                 if (ret)
1879                         return ret;
1880         }
1881         MLX5_ASSERT(rx_domain);
1882         ret = mlx5_glue->dr_dump_domain(file, rx_domain);
1883         if (ret)
1884                 return ret;
1885         MLX5_ASSERT(tx_domain);
1886         ret = mlx5_glue->dr_dump_domain(file, tx_domain);
1887 #else
1888         ret = ENOTSUP;
1889 #endif
1890         return -ret;
1891 }
1892
1893 int
1894 mlx5_devx_cmd_flow_single_dump(void *rule_info __rte_unused,
1895                         FILE *file __rte_unused)
1896 {
1897         int ret = 0;
1898 #ifdef HAVE_MLX5_DR_FLOW_DUMP_RULE
1899         if (rule_info)
1900                 ret = mlx5_glue->dr_dump_rule(file, rule_info);
1901 #else
1902         ret = ENOTSUP;
1903 #endif
1904         return -ret;
1905 }
1906
1907 /*
1908  * Create CQ using DevX API.
1909  *
1910  * @param[in] ctx
1911  *   Context returned from mlx5 open_device() glue function.
1912  * @param [in] attr
1913  *   Pointer to CQ attributes structure.
1914  *
1915  * @return
1916  *   The DevX object created, NULL otherwise and rte_errno is set.
1917  */
1918 struct mlx5_devx_obj *
1919 mlx5_devx_cmd_create_cq(void *ctx, struct mlx5_devx_cq_attr *attr)
1920 {
1921         uint32_t in[MLX5_ST_SZ_DW(create_cq_in)] = {0};
1922         uint32_t out[MLX5_ST_SZ_DW(create_cq_out)] = {0};
1923         struct mlx5_devx_obj *cq_obj = mlx5_malloc(MLX5_MEM_ZERO,
1924                                                    sizeof(*cq_obj),
1925                                                    0, SOCKET_ID_ANY);
1926         void *cqctx = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1927
1928         if (!cq_obj) {
1929                 DRV_LOG(ERR, "Failed to allocate CQ object memory.");
1930                 rte_errno = ENOMEM;
1931                 return NULL;
1932         }
1933         MLX5_SET(create_cq_in, in, opcode, MLX5_CMD_OP_CREATE_CQ);
1934         if (attr->db_umem_valid) {
1935                 MLX5_SET(cqc, cqctx, dbr_umem_valid, attr->db_umem_valid);
1936                 MLX5_SET(cqc, cqctx, dbr_umem_id, attr->db_umem_id);
1937                 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_umem_offset);
1938         } else {
1939                 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_addr);
1940         }
1941         MLX5_SET(cqc, cqctx, cqe_sz, (RTE_CACHE_LINE_SIZE == 128) ?
1942                                      MLX5_CQE_SIZE_128B : MLX5_CQE_SIZE_64B);
1943         MLX5_SET(cqc, cqctx, cc, attr->use_first_only);
1944         MLX5_SET(cqc, cqctx, oi, attr->overrun_ignore);
1945         MLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size);
1946         if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT)
1947                 MLX5_SET(cqc, cqctx, log_page_size,
1948                          attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT);
1949         MLX5_SET(cqc, cqctx, c_eqn, attr->eqn);
1950         MLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id);
1951         MLX5_SET(cqc, cqctx, cqe_comp_en, !!attr->cqe_comp_en);
1952         MLX5_SET(cqc, cqctx, mini_cqe_res_format, attr->mini_cqe_res_format);
1953         MLX5_SET(cqc, cqctx, mini_cqe_res_format_ext,
1954                  attr->mini_cqe_res_format_ext);
1955         if (attr->q_umem_valid) {
1956                 MLX5_SET(create_cq_in, in, cq_umem_valid, attr->q_umem_valid);
1957                 MLX5_SET(create_cq_in, in, cq_umem_id, attr->q_umem_id);
1958                 MLX5_SET64(create_cq_in, in, cq_umem_offset,
1959                            attr->q_umem_offset);
1960         }
1961         cq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
1962                                                  sizeof(out));
1963         if (!cq_obj->obj) {
1964                 rte_errno = errno;
1965                 DRV_LOG(ERR, "Failed to create CQ using DevX errno=%d.", errno);
1966                 mlx5_free(cq_obj);
1967                 return NULL;
1968         }
1969         cq_obj->id = MLX5_GET(create_cq_out, out, cqn);
1970         return cq_obj;
1971 }
1972
1973 /**
1974  * Create VIRTQ using DevX API.
1975  *
1976  * @param[in] ctx
1977  *   Context returned from mlx5 open_device() glue function.
1978  * @param [in] attr
1979  *   Pointer to VIRTQ attributes structure.
1980  *
1981  * @return
1982  *   The DevX object created, NULL otherwise and rte_errno is set.
1983  */
1984 struct mlx5_devx_obj *
1985 mlx5_devx_cmd_create_virtq(void *ctx,
1986                            struct mlx5_devx_virtq_attr *attr)
1987 {
1988         uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0};
1989         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
1990         struct mlx5_devx_obj *virtq_obj = mlx5_malloc(MLX5_MEM_ZERO,
1991                                                      sizeof(*virtq_obj),
1992                                                      0, SOCKET_ID_ANY);
1993         void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq);
1994         void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr);
1995         void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context);
1996
1997         if (!virtq_obj) {
1998                 DRV_LOG(ERR, "Failed to allocate virtq data.");
1999                 rte_errno = ENOMEM;
2000                 return NULL;
2001         }
2002         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2003                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2004         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2005                  MLX5_GENERAL_OBJ_TYPE_VIRTQ);
2006         MLX5_SET16(virtio_net_q, virtq, hw_available_index,
2007                    attr->hw_available_index);
2008         MLX5_SET16(virtio_net_q, virtq, hw_used_index, attr->hw_used_index);
2009         MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4);
2010         MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6);
2011         MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum);
2012         MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum);
2013         MLX5_SET16(virtio_q, virtctx, virtio_version_1_0,
2014                    attr->virtio_version_1_0);
2015         MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode);
2016         MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id);
2017         MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr);
2018         MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr);
2019         MLX5_SET64(virtio_q, virtctx, available_addr, attr->available_addr);
2020         MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index);
2021         MLX5_SET16(virtio_q, virtctx, queue_size, attr->q_size);
2022         MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey);
2023         MLX5_SET(virtio_q, virtctx, umem_1_id, attr->umems[0].id);
2024         MLX5_SET(virtio_q, virtctx, umem_1_size, attr->umems[0].size);
2025         MLX5_SET64(virtio_q, virtctx, umem_1_offset, attr->umems[0].offset);
2026         MLX5_SET(virtio_q, virtctx, umem_2_id, attr->umems[1].id);
2027         MLX5_SET(virtio_q, virtctx, umem_2_size, attr->umems[1].size);
2028         MLX5_SET64(virtio_q, virtctx, umem_2_offset, attr->umems[1].offset);
2029         MLX5_SET(virtio_q, virtctx, umem_3_id, attr->umems[2].id);
2030         MLX5_SET(virtio_q, virtctx, umem_3_size, attr->umems[2].size);
2031         MLX5_SET64(virtio_q, virtctx, umem_3_offset, attr->umems[2].offset);
2032         MLX5_SET(virtio_q, virtctx, counter_set_id, attr->counters_obj_id);
2033         MLX5_SET(virtio_q, virtctx, pd, attr->pd);
2034         MLX5_SET(virtio_q, virtctx, queue_period_mode, attr->hw_latency_mode);
2035         MLX5_SET(virtio_q, virtctx, queue_period_us, attr->hw_max_latency_us);
2036         MLX5_SET(virtio_q, virtctx, queue_max_count, attr->hw_max_pending_comp);
2037         MLX5_SET(virtio_net_q, virtq, tisn_or_qpn, attr->tis_id);
2038         virtq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
2039                                                     sizeof(out));
2040         if (!virtq_obj->obj) {
2041                 rte_errno = errno;
2042                 DRV_LOG(ERR, "Failed to create VIRTQ Obj using DevX.");
2043                 mlx5_free(virtq_obj);
2044                 return NULL;
2045         }
2046         virtq_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2047         return virtq_obj;
2048 }
2049
2050 /**
2051  * Modify VIRTQ using DevX API.
2052  *
2053  * @param[in] virtq_obj
2054  *   Pointer to virtq object structure.
2055  * @param [in] attr
2056  *   Pointer to modify virtq attributes structure.
2057  *
2058  * @return
2059  *   0 on success, a negative errno value otherwise and rte_errno is set.
2060  */
2061 int
2062 mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj,
2063                            struct mlx5_devx_virtq_attr *attr)
2064 {
2065         uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0};
2066         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2067         void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq);
2068         void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr);
2069         void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context);
2070         int ret;
2071
2072         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2073                  MLX5_CMD_OP_MODIFY_GENERAL_OBJECT);
2074         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2075                  MLX5_GENERAL_OBJ_TYPE_VIRTQ);
2076         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id);
2077         MLX5_SET64(virtio_net_q, virtq, modify_field_select, attr->type);
2078         MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index);
2079         switch (attr->type) {
2080         case MLX5_VIRTQ_MODIFY_TYPE_STATE:
2081                 MLX5_SET16(virtio_net_q, virtq, state, attr->state);
2082                 break;
2083         case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS:
2084                 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_mkey,
2085                          attr->dirty_bitmap_mkey);
2086                 MLX5_SET64(virtio_net_q, virtq, dirty_bitmap_addr,
2087                          attr->dirty_bitmap_addr);
2088                 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_size,
2089                          attr->dirty_bitmap_size);
2090                 break;
2091         case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE:
2092                 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_dump_enable,
2093                          attr->dirty_bitmap_dump_enable);
2094                 break;
2095         default:
2096                 rte_errno = EINVAL;
2097                 return -rte_errno;
2098         }
2099         ret = mlx5_glue->devx_obj_modify(virtq_obj->obj, in, sizeof(in),
2100                                          out, sizeof(out));
2101         if (ret) {
2102                 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX.");
2103                 rte_errno = errno;
2104                 return -rte_errno;
2105         }
2106         return ret;
2107 }
2108
2109 /**
2110  * Query VIRTQ using DevX API.
2111  *
2112  * @param[in] virtq_obj
2113  *   Pointer to virtq object structure.
2114  * @param [in/out] attr
2115  *   Pointer to virtq attributes structure.
2116  *
2117  * @return
2118  *   0 on success, a negative errno value otherwise and rte_errno is set.
2119  */
2120 int
2121 mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj,
2122                            struct mlx5_devx_virtq_attr *attr)
2123 {
2124         uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
2125         uint32_t out[MLX5_ST_SZ_DW(query_virtq_out)] = {0};
2126         void *hdr = MLX5_ADDR_OF(query_virtq_out, in, hdr);
2127         void *virtq = MLX5_ADDR_OF(query_virtq_out, out, virtq);
2128         int ret;
2129
2130         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2131                  MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
2132         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2133                  MLX5_GENERAL_OBJ_TYPE_VIRTQ);
2134         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id);
2135         ret = mlx5_glue->devx_obj_query(virtq_obj->obj, in, sizeof(in),
2136                                          out, sizeof(out));
2137         if (ret) {
2138                 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX.");
2139                 rte_errno = errno;
2140                 return -errno;
2141         }
2142         attr->hw_available_index = MLX5_GET16(virtio_net_q, virtq,
2143                                               hw_available_index);
2144         attr->hw_used_index = MLX5_GET16(virtio_net_q, virtq, hw_used_index);
2145         attr->state = MLX5_GET16(virtio_net_q, virtq, state);
2146         attr->error_type = MLX5_GET16(virtio_net_q, virtq,
2147                                       virtio_q_context.error_type);
2148         return ret;
2149 }
2150
2151 /**
2152  * Create QP using DevX API.
2153  *
2154  * @param[in] ctx
2155  *   Context returned from mlx5 open_device() glue function.
2156  * @param [in] attr
2157  *   Pointer to QP attributes structure.
2158  *
2159  * @return
2160  *   The DevX object created, NULL otherwise and rte_errno is set.
2161  */
2162 struct mlx5_devx_obj *
2163 mlx5_devx_cmd_create_qp(void *ctx,
2164                         struct mlx5_devx_qp_attr *attr)
2165 {
2166         uint32_t in[MLX5_ST_SZ_DW(create_qp_in)] = {0};
2167         uint32_t out[MLX5_ST_SZ_DW(create_qp_out)] = {0};
2168         struct mlx5_devx_obj *qp_obj = mlx5_malloc(MLX5_MEM_ZERO,
2169                                                    sizeof(*qp_obj),
2170                                                    0, SOCKET_ID_ANY);
2171         void *qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
2172
2173         if (!qp_obj) {
2174                 DRV_LOG(ERR, "Failed to allocate QP data.");
2175                 rte_errno = ENOMEM;
2176                 return NULL;
2177         }
2178         MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP);
2179         MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC);
2180         MLX5_SET(qpc, qpc, pd, attr->pd);
2181         MLX5_SET(qpc, qpc, ts_format, attr->ts_format);
2182         MLX5_SET(qpc, qpc, user_index, attr->user_index);
2183         if (attr->uar_index) {
2184                 if (attr->mmo) {
2185                         void *qpc_ext_and_pas_list = MLX5_ADDR_OF(create_qp_in,
2186                                 in, qpc_extension_and_pas_list);
2187                         void *qpc_ext = MLX5_ADDR_OF(qpc_extension_and_pas_list,
2188                                 qpc_ext_and_pas_list, qpc_data_extension);
2189
2190                         MLX5_SET(create_qp_in, in, qpc_ext, 1);
2191                         MLX5_SET(qpc_extension, qpc_ext, mmo, 1);
2192                 }
2193                 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
2194                 MLX5_SET(qpc, qpc, uar_page, attr->uar_index);
2195                 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT)
2196                         MLX5_SET(qpc, qpc, log_page_size,
2197                                  attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT);
2198                 if (attr->num_of_send_wqbbs) {
2199                         MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->num_of_send_wqbbs));
2200                         MLX5_SET(qpc, qpc, cqn_snd, attr->cqn);
2201                         MLX5_SET(qpc, qpc, log_sq_size,
2202                                  rte_log2_u32(attr->num_of_send_wqbbs));
2203                 } else {
2204                         MLX5_SET(qpc, qpc, no_sq, 1);
2205                 }
2206                 if (attr->num_of_receive_wqes) {
2207                         MLX5_ASSERT(RTE_IS_POWER_OF_2(
2208                                         attr->num_of_receive_wqes));
2209                         MLX5_SET(qpc, qpc, cqn_rcv, attr->cqn);
2210                         MLX5_SET(qpc, qpc, log_rq_stride, attr->log_rq_stride -
2211                                  MLX5_LOG_RQ_STRIDE_SHIFT);
2212                         MLX5_SET(qpc, qpc, log_rq_size,
2213                                  rte_log2_u32(attr->num_of_receive_wqes));
2214                         MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ);
2215                 } else {
2216                         MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ);
2217                 }
2218                 if (attr->dbr_umem_valid) {
2219                         MLX5_SET(qpc, qpc, dbr_umem_valid,
2220                                  attr->dbr_umem_valid);
2221                         MLX5_SET(qpc, qpc, dbr_umem_id, attr->dbr_umem_id);
2222                 }
2223                 MLX5_SET64(qpc, qpc, dbr_addr, attr->dbr_address);
2224                 MLX5_SET64(create_qp_in, in, wq_umem_offset,
2225                            attr->wq_umem_offset);
2226                 MLX5_SET(create_qp_in, in, wq_umem_id, attr->wq_umem_id);
2227                 MLX5_SET(create_qp_in, in, wq_umem_valid, 1);
2228         } else {
2229                 /* Special QP to be managed by FW - no SQ\RQ\CQ\UAR\DB rec. */
2230                 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ);
2231                 MLX5_SET(qpc, qpc, no_sq, 1);
2232         }
2233         qp_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
2234                                                  sizeof(out));
2235         if (!qp_obj->obj) {
2236                 rte_errno = errno;
2237                 DRV_LOG(ERR, "Failed to create QP Obj using DevX.");
2238                 mlx5_free(qp_obj);
2239                 return NULL;
2240         }
2241         qp_obj->id = MLX5_GET(create_qp_out, out, qpn);
2242         return qp_obj;
2243 }
2244
2245 /**
2246  * Modify QP using DevX API.
2247  * Currently supports only force loop-back QP.
2248  *
2249  * @param[in] qp
2250  *   Pointer to QP object structure.
2251  * @param [in] qp_st_mod_op
2252  *   The QP state modification operation.
2253  * @param [in] remote_qp_id
2254  *   The remote QP ID for MLX5_CMD_OP_INIT2RTR_QP operation.
2255  *
2256  * @return
2257  *   0 on success, a negative errno value otherwise and rte_errno is set.
2258  */
2259 int
2260 mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op,
2261                               uint32_t remote_qp_id)
2262 {
2263         union {
2264                 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)];
2265                 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)];
2266                 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)];
2267         } in;
2268         union {
2269                 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)];
2270                 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)];
2271                 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)];
2272         } out;
2273         void *qpc;
2274         int ret;
2275         unsigned int inlen;
2276         unsigned int outlen;
2277
2278         memset(&in, 0, sizeof(in));
2279         memset(&out, 0, sizeof(out));
2280         MLX5_SET(rst2init_qp_in, &in, opcode, qp_st_mod_op);
2281         switch (qp_st_mod_op) {
2282         case MLX5_CMD_OP_RST2INIT_QP:
2283                 MLX5_SET(rst2init_qp_in, &in, qpn, qp->id);
2284                 qpc = MLX5_ADDR_OF(rst2init_qp_in, &in, qpc);
2285                 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1);
2286                 MLX5_SET(qpc, qpc, rre, 1);
2287                 MLX5_SET(qpc, qpc, rwe, 1);
2288                 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
2289                 inlen = sizeof(in.rst2init);
2290                 outlen = sizeof(out.rst2init);
2291                 break;
2292         case MLX5_CMD_OP_INIT2RTR_QP:
2293                 MLX5_SET(init2rtr_qp_in, &in, qpn, qp->id);
2294                 qpc = MLX5_ADDR_OF(init2rtr_qp_in, &in, qpc);
2295                 MLX5_SET(qpc, qpc, primary_address_path.fl, 1);
2296                 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1);
2297                 MLX5_SET(qpc, qpc, mtu, 1);
2298                 MLX5_SET(qpc, qpc, log_msg_max, 30);
2299                 MLX5_SET(qpc, qpc, remote_qpn, remote_qp_id);
2300                 MLX5_SET(qpc, qpc, min_rnr_nak, 0);
2301                 inlen = sizeof(in.init2rtr);
2302                 outlen = sizeof(out.init2rtr);
2303                 break;
2304         case MLX5_CMD_OP_RTR2RTS_QP:
2305                 qpc = MLX5_ADDR_OF(rtr2rts_qp_in, &in, qpc);
2306                 MLX5_SET(rtr2rts_qp_in, &in, qpn, qp->id);
2307                 MLX5_SET(qpc, qpc, primary_address_path.ack_timeout, 16);
2308                 MLX5_SET(qpc, qpc, log_ack_req_freq, 0);
2309                 MLX5_SET(qpc, qpc, retry_count, 7);
2310                 MLX5_SET(qpc, qpc, rnr_retry, 7);
2311                 inlen = sizeof(in.rtr2rts);
2312                 outlen = sizeof(out.rtr2rts);
2313                 break;
2314         default:
2315                 DRV_LOG(ERR, "Invalid or unsupported QP modify op %u.",
2316                         qp_st_mod_op);
2317                 rte_errno = EINVAL;
2318                 return -rte_errno;
2319         }
2320         ret = mlx5_glue->devx_obj_modify(qp->obj, &in, inlen, &out, outlen);
2321         if (ret) {
2322                 DRV_LOG(ERR, "Failed to modify QP using DevX.");
2323                 rte_errno = errno;
2324                 return -rte_errno;
2325         }
2326         return ret;
2327 }
2328
2329 struct mlx5_devx_obj *
2330 mlx5_devx_cmd_create_virtio_q_counters(void *ctx)
2331 {
2332         uint32_t in[MLX5_ST_SZ_DW(create_virtio_q_counters_in)] = {0};
2333         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2334         struct mlx5_devx_obj *couners_obj = mlx5_malloc(MLX5_MEM_ZERO,
2335                                                        sizeof(*couners_obj), 0,
2336                                                        SOCKET_ID_ANY);
2337         void *hdr = MLX5_ADDR_OF(create_virtio_q_counters_in, in, hdr);
2338
2339         if (!couners_obj) {
2340                 DRV_LOG(ERR, "Failed to allocate virtio queue counters data.");
2341                 rte_errno = ENOMEM;
2342                 return NULL;
2343         }
2344         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2345                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2346         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2347                  MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS);
2348         couners_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
2349                                                       sizeof(out));
2350         if (!couners_obj->obj) {
2351                 rte_errno = errno;
2352                 DRV_LOG(ERR, "Failed to create virtio queue counters Obj using"
2353                         " DevX.");
2354                 mlx5_free(couners_obj);
2355                 return NULL;
2356         }
2357         couners_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2358         return couners_obj;
2359 }
2360
2361 int
2362 mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj,
2363                                    struct mlx5_devx_virtio_q_couners_attr *attr)
2364 {
2365         uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
2366         uint32_t out[MLX5_ST_SZ_DW(query_virtio_q_counters_out)] = {0};
2367         void *hdr = MLX5_ADDR_OF(query_virtio_q_counters_out, in, hdr);
2368         void *virtio_q_counters = MLX5_ADDR_OF(query_virtio_q_counters_out, out,
2369                                                virtio_q_counters);
2370         int ret;
2371
2372         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2373                  MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
2374         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2375                  MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS);
2376         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, couners_obj->id);
2377         ret = mlx5_glue->devx_obj_query(couners_obj->obj, in, sizeof(in), out,
2378                                         sizeof(out));
2379         if (ret) {
2380                 DRV_LOG(ERR, "Failed to query virtio q counters using DevX.");
2381                 rte_errno = errno;
2382                 return -errno;
2383         }
2384         attr->received_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters,
2385                                          received_desc);
2386         attr->completed_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters,
2387                                           completed_desc);
2388         attr->error_cqes = MLX5_GET(virtio_q_counters, virtio_q_counters,
2389                                     error_cqes);
2390         attr->bad_desc_errors = MLX5_GET(virtio_q_counters, virtio_q_counters,
2391                                          bad_desc_errors);
2392         attr->exceed_max_chain = MLX5_GET(virtio_q_counters, virtio_q_counters,
2393                                           exceed_max_chain);
2394         attr->invalid_buffer = MLX5_GET(virtio_q_counters, virtio_q_counters,
2395                                         invalid_buffer);
2396         return ret;
2397 }
2398
2399 /**
2400  * Create general object of type FLOW_HIT_ASO using DevX API.
2401  *
2402  * @param[in] ctx
2403  *   Context returned from mlx5 open_device() glue function.
2404  * @param [in] pd
2405  *   PD value to associate the FLOW_HIT_ASO object with.
2406  *
2407  * @return
2408  *   The DevX object created, NULL otherwise and rte_errno is set.
2409  */
2410 struct mlx5_devx_obj *
2411 mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, uint32_t pd)
2412 {
2413         uint32_t in[MLX5_ST_SZ_DW(create_flow_hit_aso_in)] = {0};
2414         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2415         struct mlx5_devx_obj *flow_hit_aso_obj = NULL;
2416         void *ptr = NULL;
2417
2418         flow_hit_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*flow_hit_aso_obj),
2419                                        0, SOCKET_ID_ANY);
2420         if (!flow_hit_aso_obj) {
2421                 DRV_LOG(ERR, "Failed to allocate FLOW_HIT_ASO object data");
2422                 rte_errno = ENOMEM;
2423                 return NULL;
2424         }
2425         ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, hdr);
2426         MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2427                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2428         MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2429                  MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO);
2430         ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, flow_hit_aso);
2431         MLX5_SET(flow_hit_aso, ptr, access_pd, pd);
2432         flow_hit_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2433                                                            out, sizeof(out));
2434         if (!flow_hit_aso_obj->obj) {
2435                 rte_errno = errno;
2436                 DRV_LOG(ERR, "Failed to create FLOW_HIT_ASO obj using DevX.");
2437                 mlx5_free(flow_hit_aso_obj);
2438                 return NULL;
2439         }
2440         flow_hit_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2441         return flow_hit_aso_obj;
2442 }
2443
2444 /*
2445  * Create PD using DevX API.
2446  *
2447  * @param[in] ctx
2448  *   Context returned from mlx5 open_device() glue function.
2449  *
2450  * @return
2451  *   The DevX object created, NULL otherwise and rte_errno is set.
2452  */
2453 struct mlx5_devx_obj *
2454 mlx5_devx_cmd_alloc_pd(void *ctx)
2455 {
2456         struct mlx5_devx_obj *ppd =
2457                 mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ppd), 0, SOCKET_ID_ANY);
2458         u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {0};
2459         u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {0};
2460
2461         if (!ppd) {
2462                 DRV_LOG(ERR, "Failed to allocate PD data.");
2463                 rte_errno = ENOMEM;
2464                 return NULL;
2465         }
2466         MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD);
2467         ppd->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2468                                 out, sizeof(out));
2469         if (!ppd->obj) {
2470                 mlx5_free(ppd);
2471                 DRV_LOG(ERR, "Failed to allocate PD Obj using DevX.");
2472                 rte_errno = errno;
2473                 return NULL;
2474         }
2475         ppd->id = MLX5_GET(alloc_pd_out, out, pd);
2476         return ppd;
2477 }
2478
2479 /**
2480  * Create general object of type FLOW_METER_ASO using DevX API.
2481  *
2482  * @param[in] ctx
2483  *   Context returned from mlx5 open_device() glue function.
2484  * @param [in] pd
2485  *   PD value to associate the FLOW_METER_ASO object with.
2486  * @param [in] log_obj_size
2487  *   log_obj_size define to allocate number of 2 * meters
2488  *   in one FLOW_METER_ASO object.
2489  *
2490  * @return
2491  *   The DevX object created, NULL otherwise and rte_errno is set.
2492  */
2493 struct mlx5_devx_obj *
2494 mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx, uint32_t pd,
2495                                                 uint32_t log_obj_size)
2496 {
2497         uint32_t in[MLX5_ST_SZ_DW(create_flow_meter_aso_in)] = {0};
2498         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)];
2499         struct mlx5_devx_obj *flow_meter_aso_obj;
2500         void *ptr;
2501
2502         flow_meter_aso_obj = mlx5_malloc(MLX5_MEM_ZERO,
2503                                                 sizeof(*flow_meter_aso_obj),
2504                                                 0, SOCKET_ID_ANY);
2505         if (!flow_meter_aso_obj) {
2506                 DRV_LOG(ERR, "Failed to allocate FLOW_METER_ASO object data");
2507                 rte_errno = ENOMEM;
2508                 return NULL;
2509         }
2510         ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, hdr);
2511         MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2512                 MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2513         MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2514                 MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO);
2515         MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range,
2516                 log_obj_size);
2517         ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, flow_meter_aso);
2518         MLX5_SET(flow_meter_aso, ptr, access_pd, pd);
2519         flow_meter_aso_obj->obj = mlx5_glue->devx_obj_create(
2520                                                         ctx, in, sizeof(in),
2521                                                         out, sizeof(out));
2522         if (!flow_meter_aso_obj->obj) {
2523                 rte_errno = errno;
2524                 DRV_LOG(ERR, "Failed to create FLOW_METER_ASO obj using DevX.");
2525                 mlx5_free(flow_meter_aso_obj);
2526                 return NULL;
2527         }
2528         flow_meter_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr,
2529                                                                 out, obj_id);
2530         return flow_meter_aso_obj;
2531 }
2532
2533 /*
2534  * Create general object of type CONN_TRACK_OFFLOAD using DevX API.
2535  *
2536  * @param[in] ctx
2537  *   Context returned from mlx5 open_device() glue function.
2538  * @param [in] pd
2539  *   PD value to associate the CONN_TRACK_OFFLOAD ASO object with.
2540  * @param [in] log_obj_size
2541  *   log_obj_size to allocate its power of 2 * objects
2542  *   in one CONN_TRACK_OFFLOAD bulk allocation.
2543  *
2544  * @return
2545  *   The DevX object created, NULL otherwise and rte_errno is set.
2546  */
2547 struct mlx5_devx_obj *
2548 mlx5_devx_cmd_create_conn_track_offload_obj(void *ctx, uint32_t pd,
2549                                             uint32_t log_obj_size)
2550 {
2551         uint32_t in[MLX5_ST_SZ_DW(create_conn_track_aso_in)] = {0};
2552         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)];
2553         struct mlx5_devx_obj *ct_aso_obj;
2554         void *ptr;
2555
2556         ct_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ct_aso_obj),
2557                                  0, SOCKET_ID_ANY);
2558         if (!ct_aso_obj) {
2559                 DRV_LOG(ERR, "Failed to allocate CONN_TRACK_OFFLOAD object.");
2560                 rte_errno = ENOMEM;
2561                 return NULL;
2562         }
2563         ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, hdr);
2564         MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2565                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2566         MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2567                  MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD);
2568         MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range, log_obj_size);
2569         ptr = MLX5_ADDR_OF(create_conn_track_aso_in, in, conn_track_offload);
2570         MLX5_SET(conn_track_offload, ptr, conn_track_aso_access_pd, pd);
2571         ct_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2572                                                      out, sizeof(out));
2573         if (!ct_aso_obj->obj) {
2574                 rte_errno = errno;
2575                 DRV_LOG(ERR, "Failed to create CONN_TRACK_OFFLOAD obj by using DevX.");
2576                 mlx5_free(ct_aso_obj);
2577                 return NULL;
2578         }
2579         ct_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2580         return ct_aso_obj;
2581 }
2582
2583 /**
2584  * Create general object of type GENEVE TLV option using DevX API.
2585  *
2586  * @param[in] ctx
2587  *   Context returned from mlx5 open_device() glue function.
2588  * @param [in] class
2589  *   TLV option variable value of class
2590  * @param [in] type
2591  *   TLV option variable value of type
2592  * @param [in] len
2593  *   TLV option variable value of len
2594  *
2595  * @return
2596  *   The DevX object created, NULL otherwise and rte_errno is set.
2597  */
2598 struct mlx5_devx_obj *
2599 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx,
2600                 uint16_t class, uint8_t type, uint8_t len)
2601 {
2602         uint32_t in[MLX5_ST_SZ_DW(create_geneve_tlv_option_in)] = {0};
2603         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2604         struct mlx5_devx_obj *geneve_tlv_opt_obj = mlx5_malloc(MLX5_MEM_ZERO,
2605                                                    sizeof(*geneve_tlv_opt_obj),
2606                                                    0, SOCKET_ID_ANY);
2607
2608         if (!geneve_tlv_opt_obj) {
2609                 DRV_LOG(ERR, "Failed to allocate geneve tlv option object.");
2610                 rte_errno = ENOMEM;
2611                 return NULL;
2612         }
2613         void *hdr = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, hdr);
2614         void *opt = MLX5_ADDR_OF(create_geneve_tlv_option_in, in,
2615                         geneve_tlv_opt);
2616         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2617                         MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2618         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2619                  MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT);
2620         MLX5_SET(geneve_tlv_option, opt, option_class,
2621                         rte_be_to_cpu_16(class));
2622         MLX5_SET(geneve_tlv_option, opt, option_type, type);
2623         MLX5_SET(geneve_tlv_option, opt, option_data_length, len);
2624         geneve_tlv_opt_obj->obj = mlx5_glue->devx_obj_create(ctx, in,
2625                                         sizeof(in), out, sizeof(out));
2626         if (!geneve_tlv_opt_obj->obj) {
2627                 rte_errno = errno;
2628                 DRV_LOG(ERR, "Failed to create Geneve tlv option "
2629                                 "Obj using DevX.");
2630                 mlx5_free(geneve_tlv_opt_obj);
2631                 return NULL;
2632         }
2633         geneve_tlv_opt_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2634         return geneve_tlv_opt_obj;
2635 }
2636
2637 int
2638 mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id)
2639 {
2640 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2641         uint32_t in[MLX5_ST_SZ_DW(query_rq_in)] = {0};
2642         uint32_t out[MLX5_ST_SZ_DW(query_rq_out)] = {0};
2643         int rc;
2644         void *rq_ctx;
2645
2646         MLX5_SET(query_rq_in, in, opcode, MLX5_CMD_OP_QUERY_RQ);
2647         MLX5_SET(query_rq_in, in, rqn, ((struct ibv_wq *)wq)->wq_num);
2648         rc = mlx5_glue->devx_wq_query(wq, in, sizeof(in), out, sizeof(out));
2649         if (rc) {
2650                 rte_errno = errno;
2651                 DRV_LOG(ERR, "Failed to query WQ counter set ID using DevX - "
2652                         "rc = %d, errno = %d.", rc, errno);
2653                 return -rc;
2654         };
2655         rq_ctx = MLX5_ADDR_OF(query_rq_out, out, rq_context);
2656         *counter_set_id = MLX5_GET(rqc, rq_ctx, counter_set_id);
2657         return 0;
2658 #else
2659         (void)wq;
2660         (void)counter_set_id;
2661         return -ENOTSUP;
2662 #endif
2663 }
2664
2665 /*
2666  * Allocate queue counters via devx interface.
2667  *
2668  * @param[in] ctx
2669  *   Context returned from mlx5 open_device() glue function.
2670  *
2671  * @return
2672  *   Pointer to counter object on success, a NULL value otherwise and
2673  *   rte_errno is set.
2674  */
2675 struct mlx5_devx_obj *
2676 mlx5_devx_cmd_queue_counter_alloc(void *ctx)
2677 {
2678         struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 0,
2679                                                 SOCKET_ID_ANY);
2680         uint32_t in[MLX5_ST_SZ_DW(alloc_q_counter_in)]   = {0};
2681         uint32_t out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {0};
2682
2683         if (!dcs) {
2684                 rte_errno = ENOMEM;
2685                 return NULL;
2686         }
2687         MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER);
2688         dcs->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
2689                                               sizeof(out));
2690         if (!dcs->obj) {
2691                 DRV_LOG(DEBUG, "Can't allocate q counter set by DevX - error "
2692                         "%d.", errno);
2693                 rte_errno = errno;
2694                 mlx5_free(dcs);
2695                 return NULL;
2696         }
2697         dcs->id = MLX5_GET(alloc_q_counter_out, out, counter_set_id);
2698         return dcs;
2699 }
2700
2701 /**
2702  * Query queue counters values.
2703  *
2704  * @param[in] dcs
2705  *   devx object of the queue counter set.
2706  * @param[in] clear
2707  *   Whether hardware should clear the counters after the query or not.
2708  *  @param[out] out_of_buffers
2709  *   Number of dropped occurred due to lack of WQE for the associated QPs/RQs.
2710  *
2711  * @return
2712  *   0 on success, a negative value otherwise.
2713  */
2714 int
2715 mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear,
2716                                   uint32_t *out_of_buffers)
2717 {
2718         uint32_t out[MLX5_ST_SZ_BYTES(query_q_counter_out)] = {0};
2719         uint32_t in[MLX5_ST_SZ_DW(query_q_counter_in)] = {0};
2720         int rc;
2721
2722         MLX5_SET(query_q_counter_in, in, opcode,
2723                  MLX5_CMD_OP_QUERY_Q_COUNTER);
2724         MLX5_SET(query_q_counter_in, in, op_mod, 0);
2725         MLX5_SET(query_q_counter_in, in, counter_set_id, dcs->id);
2726         MLX5_SET(query_q_counter_in, in, clear, !!clear);
2727         rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out,
2728                                        sizeof(out));
2729         if (rc) {
2730                 DRV_LOG(ERR, "Failed to query devx q counter set - rc %d", rc);
2731                 rte_errno = rc;
2732                 return -rc;
2733         }
2734         *out_of_buffers = MLX5_GET(query_q_counter_out, out, out_of_buffer);
2735         return 0;
2736 }
2737
2738 /**
2739  * Create general object of type DEK using DevX API.
2740  *
2741  * @param[in] ctx
2742  *   Context returned from mlx5 open_device() glue function.
2743  * @param [in] attr
2744  *   Pointer to DEK attributes structure.
2745  *
2746  * @return
2747  *   The DevX object created, NULL otherwise and rte_errno is set.
2748  */
2749 struct mlx5_devx_obj *
2750 mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr)
2751 {
2752         uint32_t in[MLX5_ST_SZ_DW(create_dek_in)] = {0};
2753         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2754         struct mlx5_devx_obj *dek_obj = NULL;
2755         void *ptr = NULL, *key_addr = NULL;
2756
2757         dek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dek_obj),
2758                               0, SOCKET_ID_ANY);
2759         if (dek_obj == NULL) {
2760                 DRV_LOG(ERR, "Failed to allocate DEK object data");
2761                 rte_errno = ENOMEM;
2762                 return NULL;
2763         }
2764         ptr = MLX5_ADDR_OF(create_dek_in, in, hdr);
2765         MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2766                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2767         MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2768                  MLX5_GENERAL_OBJ_TYPE_DEK);
2769         ptr = MLX5_ADDR_OF(create_dek_in, in, dek);
2770         MLX5_SET(dek, ptr, key_size, attr->key_size);
2771         MLX5_SET(dek, ptr, has_keytag, attr->has_keytag);
2772         MLX5_SET(dek, ptr, key_purpose, attr->key_purpose);
2773         MLX5_SET(dek, ptr, pd, attr->pd);
2774         MLX5_SET64(dek, ptr, opaque, attr->opaque);
2775         key_addr = MLX5_ADDR_OF(dek, ptr, key);
2776         memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE);
2777         dek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2778                                                   out, sizeof(out));
2779         if (dek_obj->obj == NULL) {
2780                 rte_errno = errno;
2781                 DRV_LOG(ERR, "Failed to create DEK obj using DevX.");
2782                 mlx5_free(dek_obj);
2783                 return NULL;
2784         }
2785         dek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2786         return dek_obj;
2787 }
2788
2789 /**
2790  * Create general object of type IMPORT_KEK using DevX API.
2791  *
2792  * @param[in] ctx
2793  *   Context returned from mlx5 open_device() glue function.
2794  * @param [in] attr
2795  *   Pointer to IMPORT_KEK attributes structure.
2796  *
2797  * @return
2798  *   The DevX object created, NULL otherwise and rte_errno is set.
2799  */
2800 struct mlx5_devx_obj *
2801 mlx5_devx_cmd_create_import_kek_obj(void *ctx,
2802                                     struct mlx5_devx_import_kek_attr *attr)
2803 {
2804         uint32_t in[MLX5_ST_SZ_DW(create_import_kek_in)] = {0};
2805         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2806         struct mlx5_devx_obj *import_kek_obj = NULL;
2807         void *ptr = NULL, *key_addr = NULL;
2808
2809         import_kek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*import_kek_obj),
2810                                      0, SOCKET_ID_ANY);
2811         if (import_kek_obj == NULL) {
2812                 DRV_LOG(ERR, "Failed to allocate IMPORT_KEK object data");
2813                 rte_errno = ENOMEM;
2814                 return NULL;
2815         }
2816         ptr = MLX5_ADDR_OF(create_import_kek_in, in, hdr);
2817         MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2818                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2819         MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2820                  MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK);
2821         ptr = MLX5_ADDR_OF(create_import_kek_in, in, import_kek);
2822         MLX5_SET(import_kek, ptr, key_size, attr->key_size);
2823         key_addr = MLX5_ADDR_OF(import_kek, ptr, key);
2824         memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE);
2825         import_kek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2826                                                          out, sizeof(out));
2827         if (import_kek_obj->obj == NULL) {
2828                 rte_errno = errno;
2829                 DRV_LOG(ERR, "Failed to create IMPORT_KEK object using DevX.");
2830                 mlx5_free(import_kek_obj);
2831                 return NULL;
2832         }
2833         import_kek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2834         return import_kek_obj;
2835 }
2836
2837 /**
2838  * Create general object of type CREDENTIAL using DevX API.
2839  *
2840  * @param[in] ctx
2841  *   Context returned from mlx5 open_device() glue function.
2842  * @param [in] attr
2843  *   Pointer to CREDENTIAL attributes structure.
2844  *
2845  * @return
2846  *   The DevX object created, NULL otherwise and rte_errno is set.
2847  */
2848 struct mlx5_devx_obj *
2849 mlx5_devx_cmd_create_credential_obj(void *ctx,
2850                                     struct mlx5_devx_credential_attr *attr)
2851 {
2852         uint32_t in[MLX5_ST_SZ_DW(create_credential_in)] = {0};
2853         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2854         struct mlx5_devx_obj *credential_obj = NULL;
2855         void *ptr = NULL, *credential_addr = NULL;
2856
2857         credential_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*credential_obj),
2858                                      0, SOCKET_ID_ANY);
2859         if (credential_obj == NULL) {
2860                 DRV_LOG(ERR, "Failed to allocate CREDENTIAL object data");
2861                 rte_errno = ENOMEM;
2862                 return NULL;
2863         }
2864         ptr = MLX5_ADDR_OF(create_credential_in, in, hdr);
2865         MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2866                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2867         MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2868                  MLX5_GENERAL_OBJ_TYPE_CREDENTIAL);
2869         ptr = MLX5_ADDR_OF(create_credential_in, in, credential);
2870         MLX5_SET(credential, ptr, credential_role, attr->credential_role);
2871         credential_addr = MLX5_ADDR_OF(credential, ptr, credential);
2872         memcpy(credential_addr, (void *)(attr->credential),
2873                MLX5_CRYPTO_CREDENTIAL_SIZE);
2874         credential_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2875                                                          out, sizeof(out));
2876         if (credential_obj->obj == NULL) {
2877                 rte_errno = errno;
2878                 DRV_LOG(ERR, "Failed to create CREDENTIAL object using DevX.");
2879                 mlx5_free(credential_obj);
2880                 return NULL;
2881         }
2882         credential_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2883         return credential_obj;
2884 }
2885
2886 /**
2887  * Create general object of type CRYPTO_LOGIN using DevX API.
2888  *
2889  * @param[in] ctx
2890  *   Context returned from mlx5 open_device() glue function.
2891  * @param [in] attr
2892  *   Pointer to CRYPTO_LOGIN attributes structure.
2893  *
2894  * @return
2895  *   The DevX object created, NULL otherwise and rte_errno is set.
2896  */
2897 struct mlx5_devx_obj *
2898 mlx5_devx_cmd_create_crypto_login_obj(void *ctx,
2899                                       struct mlx5_devx_crypto_login_attr *attr)
2900 {
2901         uint32_t in[MLX5_ST_SZ_DW(create_crypto_login_in)] = {0};
2902         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2903         struct mlx5_devx_obj *crypto_login_obj = NULL;
2904         void *ptr = NULL, *credential_addr = NULL;
2905
2906         crypto_login_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*crypto_login_obj),
2907                                        0, SOCKET_ID_ANY);
2908         if (crypto_login_obj == NULL) {
2909                 DRV_LOG(ERR, "Failed to allocate CRYPTO_LOGIN object data");
2910                 rte_errno = ENOMEM;
2911                 return NULL;
2912         }
2913         ptr = MLX5_ADDR_OF(create_crypto_login_in, in, hdr);
2914         MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2915                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2916         MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2917                  MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN);
2918         ptr = MLX5_ADDR_OF(create_crypto_login_in, in, crypto_login);
2919         MLX5_SET(crypto_login, ptr, credential_pointer,
2920                  attr->credential_pointer);
2921         MLX5_SET(crypto_login, ptr, session_import_kek_ptr,
2922                  attr->session_import_kek_ptr);
2923         credential_addr = MLX5_ADDR_OF(crypto_login, ptr, credential);
2924         memcpy(credential_addr, (void *)(attr->credential),
2925                MLX5_CRYPTO_CREDENTIAL_SIZE);
2926         crypto_login_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2927                                                            out, sizeof(out));
2928         if (crypto_login_obj->obj == NULL) {
2929                 rte_errno = errno;
2930                 DRV_LOG(ERR, "Failed to create CRYPTO_LOGIN obj using DevX.");
2931                 mlx5_free(crypto_login_obj);
2932                 return NULL;
2933         }
2934         crypto_login_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2935         return crypto_login_obj;
2936 }
2937
2938 /**
2939  * Query LAG context.
2940  *
2941  * @param[in] ctx
2942  *   Pointer to ibv_context, returned from mlx5dv_open_device.
2943  * @param[out] lag_ctx
2944  *   Pointer to struct mlx5_devx_lag_context, to be set by the routine.
2945  *
2946  * @return
2947  *   0 on success, a negative value otherwise.
2948  */
2949 int
2950 mlx5_devx_cmd_query_lag(void *ctx,
2951                         struct mlx5_devx_lag_context *lag_ctx)
2952 {
2953         uint32_t in[MLX5_ST_SZ_DW(query_lag_in)] = {0};
2954         uint32_t out[MLX5_ST_SZ_DW(query_lag_out)] = {0};
2955         void *lctx;
2956         int rc;
2957
2958         MLX5_SET(query_lag_in, in, opcode, MLX5_CMD_OP_QUERY_LAG);
2959         rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
2960         if (rc)
2961                 goto error;
2962         lctx = MLX5_ADDR_OF(query_lag_out, out, context);
2963         lag_ctx->fdb_selection_mode = MLX5_GET(lag_context, lctx,
2964                                                fdb_selection_mode);
2965         lag_ctx->port_select_mode = MLX5_GET(lag_context, lctx,
2966                                                port_select_mode);
2967         lag_ctx->lag_state = MLX5_GET(lag_context, lctx, lag_state);
2968         lag_ctx->tx_remap_affinity_2 = MLX5_GET(lag_context, lctx,
2969                                                 tx_remap_affinity_2);
2970         lag_ctx->tx_remap_affinity_1 = MLX5_GET(lag_context, lctx,
2971                                                 tx_remap_affinity_1);
2972         return 0;
2973 error:
2974         rc = (rc > 0) ? -rc : rc;
2975         return rc;
2976 }